Triple-mode redundant clock synchronization device, method, electronic device and storage medium

Abstract

The present invention discloses a triple-module redundant clock synchronization device, method, electronic device and storage medium. The device includes three clock modules, each of which includes a master clock counting unit and an MCU; any one of the three clock modules is used to send synchronization protocol frames to the other two clock modules respectively; any one of the three MCUs is used to determine whether the clock module in which it is located is the master clock module according to the synchronization protocol frames sent by the other two clock modules, if not, to determine the priority of the synchronization protocol frames sent by the other two clock modules, and synchronize the count value of the master clock counting unit in the clock module in which it is located to the count value of the master clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority. When the original master clock module fails and its authority is downgraded, the present invention can determine a new master clock module, perform clock synchronization on the slave clock module, and improve the clock synchronization stability in the triple-module redundant system.

Description

Technical Field

[0001] The present invention relates to the field of computer industrial control systems, and in particular to a triple-module redundant clock synchronization device, method, electronic device and storage medium. Background Art

[0002] Industrial control systems based on microcomputer technology have been widely used in the field of industrial control, and are also widely used in safety-critical fields such as thermal power, nuclear power, coal, petroleum, and chemical industry. In these safety-critical fields, higher requirements are placed on the reliability of control systems, and redundancy technology is generally used to achieve higher reliability. Considering the balance between reliability and cost, most systems use dual-mode redundancy technology; while industrial control systems used in core safety-critical fields use triple-mode redundancy technology. Triple-mode redundancy technology involves more complex data interaction and fault handling mechanisms.

[0003] The three synchronization modules in the triple-module redundant system can be three identical components or three identical computers. The core of the triple-module redundant system is the synchronous operation of the three synchronization modules, and the core of the synchronous operation of the three synchronization modules is the clock synchronization of the three synchronization modules.

[0004] In a triple-module redundant system, one of the three synchronization modules is often required to be the master module with the highest authority, and then synchronize the clock of the slave module to the clock of the master module to ensure the clock synchronization of the three synchronization modules. The master module is generally pre-set by the system, but when the master module fails and the authority is downgraded, if the system does not determine a new master module, it will cause clock synchronization errors. Summary of the invention

[0005] The technical problem to be solved by the present invention is to overcome the defect that clock synchronization in a triple-module redundant system in the prior art is prone to errors, and to provide a triple-redundant clock synchronization device, method, electronic device and storage medium.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] The present invention provides a triple-module redundant clock synchronization device, the triple-module redundant clock synchronization device comprising a first clock module, a second clock module and a third clock module, wherein the first clock module comprises a first master clock counting unit and a first MCU, the second clock module comprises a second master clock counting unit and a second MCU, and the third clock module comprises a third master clock counting unit and a third MCU;

[0008] Any one of the first clock module, the second clock module and the third clock module is respectively connected to the other two clock modules for communication;

[0009] Any one of the first clock module, the second clock module and the third clock module is used to send synchronization protocol frames to the other two clock modules respectively;

[0010] Any one of the first MCU, the second MCU and the third MCU is used to determine whether the clock module in which it is located is the main clock module based on the synchronization protocol frames sent by the other two clock modules. If not, it determines the priority of the synchronization protocol frames sent by the other two clock modules, and synchronizes the count value of the main clock counting unit in its clock module to the count value of the main clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority.

[0011] Preferably, the first clock module further includes a first interface unit, the second clock module further includes a second interface unit, and the third clock module further includes a third interface unit;

[0012] Any one of the first master clock counting unit, the second master clock counting unit and the third master clock counting unit is respectively connected to the interface unit in the clock module where the first master clock counting unit is located;

[0013] Any one of the first interface unit, the second interface unit and the third interface unit is respectively connected to the other two interface units for communication;

[0014] Any one of the first MCU, the second MCU and the third MCU is respectively connected to the interface unit and the main clock counting unit in the clock module where the first MCU is located;

[0015] Any one of the first master clock counting unit, the second master clock counting unit and the third master clock counting unit is used to send a synchronization pulse to the interface unit in the clock module where it is located at a preset frequency, and re-count after sending the synchronization pulse;

[0016] Any one of the first interface unit, the second interface unit and the third interface unit is used to generate a corresponding synchronization protocol frame according to the received synchronization pulse, and send the generated synchronization protocol frame to the other two interface units;

[0017] Any one of the first interface unit, the second interface unit and the third interface unit is further used to send the received synchronization protocol frame to the MCU in the clock module where the first interface unit is located.

[0018] Preferably, the first clock module further includes a first slave clock counting unit and a second slave clock counting unit, the second clock module further includes a third slave clock counting unit and a fourth slave clock counting unit, and the third clock module further includes a fifth slave clock counting unit and a sixth slave clock counting unit;

[0019] Any one of the first interface unit, the second interface unit and the third interface unit is also respectively connected to two slave clock counting units in the clock module in which it is located;

[0020] Any one of the first interface unit, the second interface unit and the third interface unit is also used to generate two corresponding synchronization signals according to the two received synchronization protocol frames, and send the two synchronization signals to the two slave clock counting units in the clock module where it is located, so that the two slave clock counting units recount from the pre-designed values.

[0021] Preferably, any one of the first MCU, the second MCU and the third MCU is also communicatively connected with two slave clock counting units in the clock module in which it is located;

[0022] The step of synchronizing the count value of the master clock counting unit in the clock module where the master clock counting unit is located to the count value of the master clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority includes:

[0023] Read the count value of the main clock counting unit in the clock module where it is located;

[0024] When the count value of the master clock counting unit reaches a preset value, reading the count value of a target slave clock counting unit as an update value, wherein the target slave clock counting unit is a slave clock counting unit that receives a synchronization signal generated according to the synchronization protocol frame with a higher priority;

[0025] The main clock counting unit is controlled to re-count from the updated value.

[0026] Preferably, the synchronization protocol frame generated by the first interface unit includes a first clock module quality level code and a first clock module priority code, the synchronization protocol frame generated by the second interface unit includes a second clock module quality level code and a second clock module priority code, and the synchronization protocol frame generated by the third interface unit includes a third clock module quality level code and a third clock module priority code;

[0027] The step of judging whether the clock module in which the clock module is located is the master clock module according to the synchronization protocol frames sent by the other two clock modules comprises:

[0028] Determine whether the clock module quality level code of the clock module in which the clock module is located is greater than the clock module quality level codes in the synchronization protocol frames sent by the other two clock modules at the same time. If so, determine that the clock module in which the clock module is located is the master clock module;

[0029] If not, determine whether the module quality level code of the clock module in which it is located is less than any of the clock module quality level codes in the synchronization protocol frame sent by the other two clock modules. If it is less than, determine that the clock module in which it is located is a slave clock module;

[0030] If it is not less than, determine whether the clock module quality level code of the clock module itself and the clock module quality level codes in the synchronization protocol frames sent by the other two clock modules are equal at the same time; if they are equal, determine whether the clock module priority code of the clock module itself is greater than any one of the clock module priority codes in the synchronization protocol frames sent by the other two clock modules; if it is greater, determine that the clock module itself is the master clock module; if it is not greater, determine that the clock module itself is the slave clock module;

[0031] If they are not equal, determine whether the clock module priority code of the clock module in which the user is located is greater than the clock module priority code in the synchronization protocol frame sent by the target clock module, wherein the target clock module is a clock module in which the clock module quality level code of the other two clock modules is equal to the clock module quality level code of the clock module in which the user is located; if it is greater, determine that the clock module in which the user is located is the master clock module;

[0032] If it is not greater, it is determined that the clock module in which it is located is a slave clock module.

[0033] Preferably, the step of determining the priority of the synchronization protocol frames sent by the other two clock modules comprises:

[0034] Determine whether the size of the clock module quality level code in the synchronization protocol frame sent by one of the other two clock modules is greater than the size of the clock module quality level code in the synchronization protocol frame sent by the other of the other two clock modules, and if so, determine that the synchronization protocol frame sent by the former has a higher priority;

[0035] If not, determine whether the size of the clock module priority code in the synchronization protocol frame sent by one of the other two clock modules is greater than the size of the clock module priority code in the synchronization protocol frame sent by the other of the other two clock modules. If so, determine that the synchronization protocol frame sent by the former has a higher priority.

[0036] The present invention also provides a triple-module redundant clock synchronization method, which is applied to the triple-module redundant clock synchronization device as described above, and the triple-module redundant clock synchronization method includes:

[0037] Sending synchronization protocol frames to the other two clock modules respectively through any one of the first clock module, the second clock module and the third clock module;

[0038] Any one of the first MCU, the second MCU and the third MCU determines whether the clock module in which it is located is the main clock module based on the synchronization protocol frames sent by the other two clock modules. If not, it determines the priority of the synchronization protocol frames sent by the other two clock modules, and synchronizes the count value of the main clock counting unit in its own clock module to the count value of the main clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority.

[0039] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the aforementioned triple-module redundant clock synchronization method when executing the computer program.

[0040] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the aforementioned triple-module redundant clock synchronization method is implemented.

[0041] The positive and progressive effect of the present invention is that when the original master clock module fails and causes authority degradation, the present invention can determine a new master clock module and synchronize the clock of the slave clock module, thereby improving the stability of clock synchronization in the triple-module redundant system. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a module diagram of a triple-module redundant clock synchronization device according to Embodiment 1 of the present invention.

[0043] Figure 2 This is the first flow chart of the MCU function of embodiment 1 of the present invention.

[0044] Figure 3 This is the second flow chart of the MCU function of embodiment 1 of the present invention.

[0045] Figure 4 This is the third flow chart of the MCU function of embodiment 1 of the present invention.

[0046] Figure 5 This is a flow chart of a triple-module redundant clock synchronization method according to Embodiment 2 of the present invention.

[0047] Figure 6 This is a schematic diagram of the structure of an electronic device according to Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0048] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0049] Example 1

[0050] This embodiment provides a triple-mode redundant clock synchronization device, such as Figure 1 As shown, the triple-module redundant clock synchronization device includes a first clock module 1, a second clock module 2 and a third clock module 3, wherein the first clock module 1 includes a first master clock counting unit 11 and a first MCU12, the second clock module 2 includes a second master clock counting unit 21 and a second MCU22, and the third clock module 3 includes a third master clock counting unit 31 and a third MCU32.

[0051] Any one of the first clock module 1 , the second clock module 2 and the third clock module 3 is respectively connected to the other two clock modules for communication.

[0052] Any one of the first clock module 1 , the second clock module 2 and the third clock module 3 is used to send a synchronization protocol frame to the other two clock modules respectively.

[0053] Any one of the first MCU12, the second MCU22 and the third MCU32 is used to determine whether the clock module in which it is located is the main clock module based on the synchronization protocol frames sent by the other two clock modules. If not, it determines the priority of the synchronization protocol frames sent by the other two clock modules, and synchronizes the count value of the main clock counting unit in its own clock module to the count value of the main clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority.

[0054] like Figure 1 As shown, the first clock module 1 also includes a first interface unit 13, the second clock module 2 also includes a second interface unit 23, and the third clock module 3 also includes a third interface unit 33. In this embodiment, the interface in the interface unit is a UART (Universal Asynchronous Receiver / Transmitter) interface, and the communication between the interface units can use CRC (Cyclic Redundancy Check) verification to eliminate communication errors and help improve anti-interference capabilities. With the changes in actual requirements in specific applications, the physical link between the interface units in this embodiment can use RS-485, LVDS (Low-Voltage Differential Signaling) or RS-422 interfaces, etc.

[0055] Any one of the first master clock counting unit 11 , the second master clock counting unit 21 and the third master clock counting unit 31 is respectively connected to the interface unit in the clock module where it is located.

[0056] Any one of the first interface unit 13, the second interface unit 23 and the third interface unit 33 is communicatively connected with the other two interface units respectively.

[0057] Any one of the first MCU 12 , the second MCU 22 and the third MCU 32 is respectively connected to the interface unit and the main clock counting unit in the clock module where it is located.

[0058] Any one of the first master clock counting unit 11, the second master clock counting unit 21 and the third master clock counting unit 31 is used to send synchronization pulses to the interface unit in the clock module where it is located at a preset frequency, and recount after sending the synchronization pulse. Specifically, in this embodiment, the first master clock counting unit 11, the second master clock counting unit 21 and the third master clock counting unit 31 are of the same model, which can be a 32-bit incremental counter, and the preset frequency of sending the synchronization pulse can be 1000hz. When the count value of the counter is greater than the count value corresponding to 1ms, the count value of the counter will be automatically cleared and recounted, so the counter will continue to run and generate accurate millisecond timing.

[0059] Any one of the first interface unit 13, the second interface unit 23 and the third interface unit 33 is used to generate a corresponding synchronization protocol frame according to the received synchronization pulse, and send the generated synchronization protocol frame to the other two interface units.

[0060] Any one of the first interface unit 13, the second interface unit 23 and the third interface unit 33 is further used to send the received synchronization protocol frame to the MCU in the clock module where the first interface unit 13, the second interface unit 23 and the third interface unit 33 are located.

[0061] like Figure 1 As shown, the first clock module 1 further includes a first slave clock counting unit 14 and a second slave clock counting unit 15 , the second clock module 2 further includes a third slave clock counting unit 24 and a fourth slave clock counting unit 25 , and the third clock module 3 further includes a fifth slave clock counting unit 34 and a sixth slave clock counting unit 35 .

[0062] Any one of the first interface unit 13 , the second interface unit 23 and the third interface unit 33 is also respectively connected to two slave clock counting units in the clock module where it is located.

[0063] Any one of the first interface unit 13, the second interface unit 23 and the third interface unit 33 is also used to generate two corresponding synchronization signals according to the two received synchronization protocol frames, and send the two synchronization signals to the two slave clock counting units in the clock module where it is located, so that the two slave clock counting units re-count from the pre-designed values. Specifically, in this embodiment, the first slave clock counting unit 14, the second slave clock counting unit 15, the third slave clock counting unit 24, the fourth slave clock counting unit 25, the fifth slave clock counting unit 34, and the sixth slave clock counting unit 35 are of the same model, and can also be a 32-bit incremental counter. When the slave clock counting unit receives a synchronization signal, the counter will be reset and restart counting. If the synchronization signal has not been received, the counter will count to hexadecimal FFFFFFFF and stop counting. At this time, the value of the counter is hexadecimal FFFFFFFF. After receiving the synchronization signal, the slave clock counting unit starts counting again from the pre-designed value in order to correct the delay between the sending of the synchronization pulse from the master clock counting unit and the receipt of the synchronization signal by the slave clock counting unit. This delay is known and can be corrected to obtain an accurate synchronized clock.

[0064] like Figure 1 As shown, any one of the first MCU 12 , the second MCU 22 and the third MCU 32 is also communicatively connected with two slave clock counting units in the clock module where the first MCU 12 , the second MCU 22 and the third MCU 32 are located.

[0065] like Figure 2 As shown, specifically, in this embodiment, the step of synchronizing the count value of the main clock counting unit in the clock module in which any one of the first MCU12, the second MCU22 and the third MCU32 is located to the count value of the main clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority includes:

[0066] S101, reading the count value of the main clock counting unit in the clock module where the main clock counting unit is located.

[0067] S102 . When the count value of the master clock counting unit reaches a preset value, read the count value of the target slave clock counting unit as an update value. The target slave clock counting unit is a slave clock counting unit that receives a synchronization signal generated according to a synchronization protocol frame with a higher priority.

[0068] S103, controlling the main clock counting unit to re-count from the updated value.

[0069] Specifically, in this embodiment, the synchronization protocol frame generated by the first interface unit includes the first clock module quality level code and the first clock module priority code, the synchronization protocol frame generated by the second interface unit includes the second clock module quality level code and the second clock module priority code, and the synchronization protocol frame generated by the third interface unit includes the third clock module quality level code and the third clock module priority code. In this embodiment, the clock module quality level code is predefined inside the clock module according to the fault analysis of the specific clock module function, and is used to evaluate the reliability of the clock module. The clock module priority code is determined according to the unit address of each clock module and is pre-assigned to the three clock modules. The existence of the clock module priority code can try to avoid the situation where the clock module quality level codes of different modules are the same, and it is not known which clock module is determined to be the main clock module, and a snatch event occurs, resulting in a long decision time.

[0070] like Figure 3 As shown, specifically, in this embodiment, the step of any one of the first MCU12, the second MCU22 and the third MCU32 determining whether the clock module in which it is located is the main clock module according to the synchronization protocol frame sent by the other two clock modules includes:

[0071] S201, determine whether the clock module quality level code of the clock module in which the clock module is located is greater than the clock module quality level codes in the synchronization protocol frames sent by the other two clock modules; if so, execute S202, if not, execute S203.

[0072] S202: Determine that the clock module in which the clock is located is a master clock module.

[0073] S203, determine whether the module quality level code of the clock module in which the clock module is located is smaller than any of the clock module quality level codes in the synchronization protocol frames sent by the other two clock modules; if it is smaller, execute S204; if not, execute S205.

[0074] S204: Determine that the clock module in which the clock module is located is a slave clock module.

[0075] S205, determine whether the clock module quality level code of the clock module in which the clock module is located is equal to the clock module quality level codes in the synchronization protocol frames sent by the other two clock modules at the same time; if they are equal, execute S206, if not equal, execute S207.

[0076] S206, determine whether the clock module priority code of the clock module in which the clock module is located is greater than any of the clock module priority codes in the synchronization protocol frames sent by the other two clock modules; if greater, execute S202; if not greater, execute S204.

[0077] S207. Determine whether the clock module priority code of the clock module in which the device is located is greater than the clock module priority code in the synchronization protocol frame sent by the target clock module, wherein the target clock module is a clock module in which the clock module quality level code of the other two clock modules is equal to the clock module quality level code of the clock module in which the device is located; if greater, execute S202; if not greater, execute S204.

[0078] Specifically, in this embodiment, any one of the first master clock counting unit 11, the second master clock counting unit 21, and the third master clock counting unit 31 is connected to a master snapshot register and a master MAX register. The master snapshot register can be used to read the current count value of the corresponding master clock counting unit. The master MAX register can be used to store the maximum value of the count value of the corresponding master clock counting unit when the synchronization pulse is sent.

[0079] Specifically, in this embodiment, any one of the first slave clock counting unit 14, the second slave clock counting unit 15, the third slave clock counting unit 24, the fourth slave clock counting unit 25, the fifth slave clock counting unit 34, and the sixth slave clock counting unit 35 is respectively connected to a slave snapshot register and a slave MAX register for communication. The slave snapshot register can be used to read the current count value of the corresponding slave clock counting unit, and the slave MAX register can be used to save the maximum value of the count value of the corresponding slave clock counting unit when receiving the synchronization clock.

[0080] The number of bits of the register in this embodiment matches the number of bits of the master clock counting unit and the slave clock counting unit in this embodiment. When the master clock counting unit in this embodiment is a 32-bit up-counter, the master snapshot register and the master MAX register are also 32-bit registers. When the slave clock counting unit in this embodiment is a 32-bit up-counter, the slave snapshot register and the slave MAX register are also 32-bit registers.

[0081] Specifically, in the present embodiment, any one of the first MCU12, the second MCU22 and the third MCU32 can judge the working state of the main clock counting unit in the clock module where it is located by reading the values ​​of the main snapshot register and the main MAX register in the clock module where it is located. When the main clock counting unit sends out a synchronization pulse, it will simultaneously send a millisecond pulse to the MCU located in the same clock module. After receiving the millisecond pulse, the MCU will read the values ​​of the main snapshot register and the main MAX register located in the same clock module at this time. When the difference between the value of the main snapshot register and the value of the main MAX register is within a preset range, it is determined that the working state of the main clock counting unit is normal. When the difference between the value of the main snapshot register and the value of the main MAX register is not within the preset range, it is determined that the working state of the main clock counting unit is abnormal.

[0082] Specifically, in the present embodiment, any one of the first MCU12, the second MCU22 and the third MCU32 can judge whether the working status of the other two clock modules is normal by reading the values ​​of the slave snapshot register and the slave MAX register of the clock module in which it is located. If it is judged that the working status of a clock module is abnormal, the synchronization protocol frame sent by the clock module is ignored in this cycle and the next cycle is waited. Taking the first MCU12 as an example, after the first slave clock counting unit 14 receives the synchronization signal, the first MCU12 will read the values ​​of the slave snapshot register and the slave MAX register that are connected to the first slave clock counting unit 14 at this time. When the difference between the value of the slave snapshot register and the value of the slave MAX register is within the preset range, it is determined that the working status of the target master clock counting unit is normal. When the difference between the value of the slave snapshot register and the value of the slave MAX register is not within the preset range, it is determined that the working status of the clock module that is connected to the first slave clock counting unit 14 is abnormal, and may be disturbed to cause communication errors.

[0083] like Figure 4 As shown, specifically, in this embodiment, the step of any one of the first MCU12, the second MCU22 and the third MCU32 determining the priority of the synchronization protocol frame sent by the other two clock modules includes:

[0084] S301. Determine whether the size of the clock module quality level code in the synchronization protocol frame sent by one of the other two clock modules is greater than the size of the clock module quality level code in the synchronization protocol frame sent by the other of the other two clock modules; if so, execute S302; if not, execute S303.

[0085] S302: Determine that the priority of the synchronization protocol frame sent by the former is higher.

[0086] S303, determine whether the size of the clock module priority code in the synchronization protocol frame sent by one of the other two clock modules is greater than the size of the clock module priority code in the synchronization protocol frame sent by the other of the other two clock modules; if so, execute S302.

[0087] This embodiment provides a triple-module redundant clock synchronization device, which can determine a new master clock module and synchronize the slave clock modules when the original master clock module fails and causes authority degradation, thereby improving the stability of clock synchronization in the triple-module redundant system.

[0088] Example 2

[0089] This embodiment provides a triple-module redundant clock synchronization method, which is applied to the triple-module redundant clock synchronization device in Embodiment 1, such as Figure 5 As shown, the triple-module redundant clock synchronization method includes:

[0090] S401 . Send a synchronization protocol frame to the other two clock modules through any one of the first clock module, the second clock module and the third clock module.

[0091] S402 , using any one of the first MCU, the second MCU and the third MCU to determine whether the clock module in which it is located is the main clock module according to the synchronization protocol frames sent by the other two clock modules; if not, executing S403 .

[0092] S403: Determine the priorities of the synchronization protocol frames sent by the other two clock modules, and synchronize the count value of the master clock counting unit in the clock module where the master clock counting unit is located to the count value of the master clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority.

[0093] This embodiment provides a triple-module redundant clock synchronization method. When the original master clock module fails and causes authority degradation, the method can determine a new master clock module and synchronize the clock of the slave clock module, thereby improving the stability of clock synchronization in the triple-module redundant system.

[0094] Example 3

[0095] Figure 6 This is a schematic diagram of the structure of an electronic device provided in Embodiment 3 of the present invention, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the triple-module redundant clock synchronization method of Embodiment 2 is implemented when the processor executes the computer program. Figure 6 The electronic device 40 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0096] The electronic device 40 may be in the form of a general-purpose computing device, for example, it may be a server device. The components of the electronic device 40 may include, but are not limited to: at least one processor 41, at least one memory 42, and a bus 43 connecting different system components (including the memory 42 and the processor 41).

[0097] The bus 43 includes a data bus, an address bus, and a control bus.

[0098] The memory 42 may include a volatile memory, such as a random access memory (RAM) 421 and / or a cache memory 422 , and may further include a read-only memory (ROM) 423 .

[0099] The memory 42 may also include a program / utility 425 having a set (at least one) of program modules 424, such program modules 424 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0100] The processor 41 executes various functional applications and data processing by running the computer program stored in the memory 42, such as the triple-module redundant clock synchronization method of embodiment 2 of the present invention.

[0101] The electronic device 40 may also communicate with one or more external devices 44 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 45. Furthermore, the model-generated device 40 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 36. As shown, the network adapter 46 communicates with other modules of the model-generated device 40 via a bus 43. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the model-generated device 40, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (RAID) systems, tape drives, and data backup storage systems.

[0102] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to an embodiment of the present invention, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0103] Example 4

[0104] The present invention also provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, the triple-module redundant clock synchronization method of the aforementioned embodiment 2 is implemented.

[0105] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0106] In a possible implementation manner, the present invention may also be implemented in the form of a program product, which includes a program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the triple-module redundant clock synchronization method of embodiment 2.

[0107] The program code for executing the present invention may be written in any combination of one or more programming languages, and may be executed entirely on a user device, partially on a user device, as an independent software package, partially on a user device and partially on a remote device, or entirely on a remote device.

[0108] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A triple-mode redundant clock synchronization device, characterized in that: The triple-module redundant clock synchronization device includes a first clock module, a second clock module and a third clock module, wherein the first clock module includes a first master clock counting unit and a first MCU, the second clock module includes a second master clock counting unit and a second MCU, and the third clock module includes a third master clock counting unit and a third MCU; Any one of the first clock module, the second clock module and the third clock module is respectively connected to the other two clock modules for communication; Any one of the first clock module, the second clock module and the third clock module is used to send synchronization protocol frames to the other two clock modules respectively; Any one of the first MCU, the second MCU and the third MCU is used to determine whether the clock module in which it is located is the master clock module according to the synchronization protocol frames sent by the other two clock modules, and if not, determine the priority of the synchronization protocol frames sent by the other two clock modules, and synchronize the count value of the master clock counting unit in the clock module in which it is located to the count value of the master clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority; The first clock module further includes a first interface unit, the second clock module further includes a second interface unit, and the third clock module further includes a third interface unit; The first clock module further includes a first slave clock counting unit and a second slave clock counting unit, the second clock module further includes a third slave clock counting unit and a fourth slave clock counting unit, and the third clock module further includes a fifth slave clock counting unit and a sixth slave clock counting unit; Any one of the first interface unit, the second interface unit and the third interface unit is also respectively connected to two slave clock counting units in the clock module where the first interface unit is located; Any one of the first interface unit, the second interface unit and the third interface unit is further used to generate two corresponding synchronization signals according to the two received synchronization protocol frames, and send the two synchronization signals to two slave clock counting units in the clock module where the two slave clock counting units are located, so that the two slave clock counting units re-count from the pre-designed values; The pre-designed value is used to correct the delay between the master clock counting unit sending a synchronization pulse and the slave clock counting unit receiving a synchronization signal.

2. The triple-mode redundant clock synchronization device according to claim 1, characterized in that: Any one of the first master clock counting unit, the second master clock counting unit and the third master clock counting unit is respectively connected to the interface unit in the clock module where the first master clock counting unit is located; Any one of the first interface unit, the second interface unit and the third interface unit is respectively connected to the other two interface units for communication; Any one of the first MCU, the second MCU and the third MCU is respectively connected to the interface unit and the main clock counting unit in the clock module where the first MCU is located; Any one of the first master clock counting unit, the second master clock counting unit and the third master clock counting unit is used to send a synchronization pulse to the interface unit in the clock module where it is located at a preset frequency, and re-count after sending the synchronization pulse; Any one of the first interface unit, the second interface unit and the third interface unit is used to generate a corresponding synchronization protocol frame according to the received synchronization pulse, and send the generated synchronization protocol frame to the other two interface units; Any one of the first interface unit, the second interface unit and the third interface unit is further used to send the received synchronization protocol frame to the MCU in the clock module where the first interface unit is located.

3. The triple-mode redundant clock synchronization device according to claim 1, characterized in that: Any one of the first MCU, the second MCU and the third MCU is also communicatively connected with two slave clock counting units in the clock module in which it is located; The step of synchronizing the count value of the master clock counting unit in the clock module where the master clock counting unit is located to the count value of the master clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority includes: Read the count value of the main clock counting unit in the clock module where it is located; When the count value of the master clock counting unit reaches a preset value, reading the count value of a target slave clock counting unit as an update value, wherein the target slave clock counting unit is a slave clock counting unit that receives a synchronization signal generated according to the synchronization protocol frame with a higher priority; The main clock counting unit is controlled to re-count from the updated value.

4. The triple-mode redundant clock synchronization device according to claim 1, characterized in that: The synchronization protocol frame generated by the first interface unit includes a first clock module quality level code and a first clock module priority code, the synchronization protocol frame generated by the second interface unit includes a second clock module quality level code and a second clock module priority code, and the synchronization protocol frame generated by the third interface unit includes a third clock module quality level code and a third clock module priority code; The step of judging whether the clock module in which the clock module is located is the master clock module according to the synchronization protocol frames sent by the other two clock modules comprises: Determine whether the clock module quality level code of the clock module in which the clock module is located is greater than the clock module quality level codes in the synchronization protocol frames sent by the other two clock modules at the same time. If so, determine that the clock module in which the clock module is located is the master clock module; If not, determine whether the module quality level code of the clock module in which it is located is less than any of the clock module quality level codes in the synchronization protocol frame sent by the other two clock modules. If it is less than, determine that the clock module in which it is located is a slave clock module; If it is not less than, determine whether the clock module quality level code of the clock module itself and the clock module quality level codes in the synchronization protocol frames sent by the other two clock modules are equal at the same time; if they are equal, determine whether the clock module priority code of the clock module itself is greater than any one of the clock module priority codes in the synchronization protocol frames sent by the other two clock modules; if it is greater, determine that the clock module itself is the master clock module; if it is not greater, determine that the clock module itself is the slave clock module; If they are not equal, determine whether the clock module priority code of the clock module in which the user is located is greater than the clock module priority code in the synchronization protocol frame sent by the target clock module, wherein the target clock module is a clock module in which the clock module quality level code of the other two clock modules is equal to the clock module quality level code of the clock module in which the user is located; if it is greater, determine that the clock module in which the user is located is the master clock module; If it is not greater, it is determined that the clock module in which it is located is a slave clock module.

5. The triple-mode redundant clock synchronization device according to claim 4, characterized in that: The step of determining the priorities of the synchronization protocol frames sent by the other two clock modules comprises: Determine whether the size of the clock module quality level code in the synchronization protocol frame sent by one of the other two clock modules is greater than the size of the clock module quality level code in the synchronization protocol frame sent by the other of the other two clock modules, and if so, determine that the synchronization protocol frame sent by the former has a higher priority; If not, determine whether the size of the clock module priority code in the synchronization protocol frame sent by one of the other two clock modules is greater than the size of the clock module priority code in the synchronization protocol frame sent by the other of the other two clock modules. If so, determine that the synchronization protocol frame sent by the former has a higher priority.

6. A triple-module redundant clock synchronization method, characterized in that: The triple-module redundant clock synchronization method is applied to the triple-module redundant clock synchronization device according to any one of claims 1 to 5, and the triple-module redundant clock synchronization method includes: Sending synchronization protocol frames to the other two clock modules respectively through any one of the first clock module, the second clock module and the third clock module; Any one of the first MCU, the second MCU and the third MCU determines whether the clock module in which it is located is the main clock module based on the synchronization protocol frames sent by the other two clock modules. If not, it determines the priority of the synchronization protocol frames sent by the other two clock modules, and synchronizes the count value of the main clock counting unit in its own clock module to the count value of the main clock counting unit in the clock module that sends the synchronization protocol frame with a higher priority.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the triple-module redundant clock synchronization method according to claim 6 is implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the triple-module redundant clock synchronization method of claim 6 is implemented.

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