Semiconductor memory device and system

Abstract

An embodiment of the present application provides a semiconductor memory device and system capable of high-speed operation. The semiconductor device of the embodiment includes: a memory cell array; and a control circuit configured to receive a first instruction for performing a read operation and first address information (ADD2) that specifies one or more bit line groups (BLGs), read first data (Dout) from the memory cell array via the one or more BLGs without passing through a bit line not included in the one or more BLGs based on the first instruction, and output the first data.

Description

[0001] [Related Applications]

[0002] This application enjoys priority to Japanese Patent Application No. 2021-118962 (filed on July 19, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation relates to a semiconductor memory device and system. Background Technology

[0004] As a semiconductor memory device, NAND flash memory is the most well-known. Summary of the Invention

[0005] One embodiment of the present invention provides a semiconductor memory device and system capable of high-speed operation.

[0006] The semiconductor memory device of the embodiment includes: a memory cell array; and a control circuit configured to receive a first instruction for performing a read operation and first address information specifying one or more bit line groups, and according to the first instruction, read first data from the memory cell array via the one or more bit line groups without via bit lines not included in the one or more bit line groups, and output the first data. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system including the semiconductor memory device of the first embodiment.

[0008] Figure 2 This is a block diagram illustrating an example of the configuration of the semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a diagram illustrating an example of the circuit configuration of the memory cell array of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 This is a cross-sectional view showing a portion of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the first embodiment.

[0011] Figure 5 This is a diagram illustrating an example of the threshold voltage distribution formed by the memory cell transistors of the semiconductor memory device of the first embodiment.

[0012] Figure 6 This is a diagram illustrating the formation of a threshold voltage distribution that reduces the bit error rate when the semiconductor memory device of the first embodiment performs a read operation.

[0013] Figure 7 This is a diagram illustrating an example of the setting of the threshold voltage of each group selection transistor in a certain string group, which schematically shows a portion of the cross-sectional structure of the memory cell array of the semiconductor memory device of the first embodiment.

[0014] Figure 8 This is a graph showing a table that displays the threshold voltage settings of each group select transistor (GCT) in the string.

[0015] Figure 9 This is a diagram showing a table that displays how many bit line groups can be formed by the number of group selection word lines of a certain block of the memory cell array of the semiconductor memory device according to the first embodiment.

[0016] Figure 10 This is a block diagram illustrating an example of the configuration of the sense amplifier module of the semiconductor memory device according to the first embodiment.

[0017] Figure 11 This is a diagram illustrating an example of the configuration of the driver assembly and line decoder module of the semiconductor memory device according to the first embodiment.

[0018] Figure 12 This is a diagram illustrating an example of the configuration of a driver circuit and a voltage transmission circuit in the semiconductor memory device of the first embodiment.

[0019] Figure 13 This is a diagram illustrating an example of a timing diagram, which shows the time variation of the voltages applied to various wirings of the selection block when the semiconductor memory device of the first embodiment performs a write operation.

[0020] Figure 14 This is a diagram illustrating an example of a timing diagram, which shows the timing changes of the instruction set and various other signals for a certain read operation performed by the semiconductor memory device of the first embodiment.

[0021] Figure 15 This is a diagram illustrating an example of a table used by the memory controller of the first embodiment when generating an instruction set to cause the semiconductor memory device to perform a read operation.

[0022] Figure 16 This diagram is used to conceptually illustrate the reading of data from multiple blocks performed by the semiconductor memory device of the first embodiment.

[0023] Figure 17 This is an example of a timing diagram showing the time variation of voltages applied to various wirings of a selected block when the semiconductor memory device of the first embodiment performs the read operation.

[0024] Figure 18 This diagram illustrates the application of voltage to the select word lines of each group when the semiconductor memory device of the first embodiment reads data from a block in units of a bit line group.

[0025] Figure 19 This is a diagram illustrating an example of the configuration of the driver assembly and line decoder module of the semiconductor memory device in the first variation of the first embodiment.

[0026] Figure 20 This is a diagram illustrating an example of the configuration of a driver circuit and two voltage transmission circuits in a semiconductor memory device according to a first variation of the first embodiment.

[0027] Figure 21 This is a diagram illustrating an example of the configuration of the driver assembly and line decoder module of the semiconductor memory device in the second variation of the first embodiment.

[0028] Figure 22 This is a diagram showing an example of a table displaying the threshold voltage settings of each group selection transistor in a string of a semiconductor memory device according to the second embodiment.

[0029] Figure 23 This is a diagram showing a table that displays how many bit line groups can be formed by the number of group selection word lines of a certain block of the memory cell array of the semiconductor memory device according to the second embodiment. Detailed Implementation

[0030] The embodiments will now be described with reference to the drawings. In the following description, constituent elements having the same function and structure are marked with common reference symbols. When distinguishing multiple constituent elements with common reference symbols, a subscript is used to differentiate them. When it is not necessary to distinguish multiple constituent elements, only the common reference symbol is used without a subscript.

[0031] Each functional block can be implemented using either hardware or software, or a combination of both. Furthermore, the functional blocks do not necessarily need to be distinguished as described below. For example, some functions may be executed by functional blocks different from those illustrated. Moreover, the illustrated functional blocks may be divided into more subdivided functional sub-blocks. Additionally, the names of the functional blocks and constituent elements in the following description are for convenience and do not limit the structure or operation of the functional blocks and constituent elements.

[0032] <First Embodiment>

[0033] Hereinafter, the semiconductor memory device 1 of the first embodiment will be described.

[0034] [Example of composition]

[0035] (1) Memory System

[0036] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system 3 including the semiconductor memory device 1 of the first embodiment.

[0037] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2, and is controlled by the host device 4. The memory system 3 may be, for example, an SD (Secure Digital) SD card. TM(touch memory，触摸式存储器) Memory cards like memory cards, or SSDs (Solid State Drives), etc.

[0038] Semiconductor memory device 1 is controlled by memory controller 2. Memory controller 2 receives host instructions from host device 4 and controls semiconductor memory device 1 according to the host instructions. Through this control, various actions are performed, such as writing data to the memory cell array of semiconductor memory device 1 (hereinafter referred to as write action) and reading data from the memory cell array of semiconductor memory device 1 (hereinafter referred to as read action).

[0039] The memory controller 2 includes a host interface circuit 21, a CPU (Central Processing Unit) 22, RAM (Random Access Memory) 23, ROM (Read Only Memory) 24, a memory interface circuit 25, and an ECC (Error Check and Correction) circuit 26. The memory controller 2 is configured, for example, as a SoC (System-on-a-Chip).

[0040] The host interface circuit 21 is connected to the host device 4 via a host interface and is responsible for communication between the memory controller 2 and the host device 4. For example, the host interface circuit 21 receives host commands sent from the host device 4 to the memory controller 2.

[0041] ROM 24 stores firmware (program). RAM 23 can store this firmware and use it as a working area for CPU 22. The firmware stored in ROM 24 and loaded into RAM 23 is executed by CPU 22. Thus, memory controller 2 performs various operations including write and read operations, and performs part of the functions of host interface circuit 21 and memory interface circuit 25.

[0042] RAM 23, for example, temporarily stores data and functions as a buffer and cache memory. The portion of RAM 23 that functions as a buffer will be described as data buffer 231. Data buffer 231 receives write data sent from host device 4 via host interface circuit 21 and temporarily stores the write data. Data buffer 231 also temporarily stores read data sent to host device 4 via host interface circuit 21. Data buffer 231 can be either volatile or non-volatile memory.

[0043] The memory interface circuit 25 is connected to the semiconductor memory device 1 via the memory interface and is responsible for communication between the memory controller 2 and the semiconductor memory device 1. The memory interface transmits, for example, the chip enable signal bCE, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal bWE, the read enable signal bRE, the write protection signal bWP, the ready / busy signal bR / B, and signals DQ<0> to DQ<7>. Hereinafter, signals DQ<0> to DQ<7> will be referred to as signals DQ<7:0>. The memory interface can further transmit the signal SBG. For example, the signal SBG can be transmitted using a different signal line than that used in the transmission of signal DQ<7:0>. For example, the signal SBG can be received by the semiconductor memory device 1 via an external terminal of the semiconductor memory device 1 that is different from the external terminal used to receive signal DQ<7:0>.

[0044] The memory interface circuit 25 generates an instruction set, for example, based on host instructions from the host device 4, and sends the instruction set to the semiconductor memory device 1 via the signal DQ<7:0>. The instruction set may include, for example, instruction CMD and address information ADD1. In addition to instruction CMD and address information ADD1, the instruction set may also include write data DAT. The memory interface circuit 25 can generate address information ADD2 based on the host instructions and send address information ADD2 to the semiconductor memory device 1 via the signal SBG. Address information ADD2 is, for example, address information used in conjunction with address information ADD1 during a read operation. On the other hand, the memory interface circuit 25 receives read data DAT sent from the semiconductor memory device 1 via the signal DQ<7:0>. In this specification, for ease of reference, both the write data and the read data sent and received by the memory interface circuit 25 are referred to by the reference numeral DAT. Hereinafter, write data and read data will also be collectively referred to as data DAT.

[0045] ECC circuit 26 receives the write data stored in data buffer 231. ECC circuit 26 adds an error correction code to the write data. The write data marked with this error correction code is the write data DAT. ECC circuit 26 supplies the write data DAT to, for example, data buffer 231 or memory interface circuit 25.

[0046] ECC circuit 26 receives read data DAT sent from semiconductor memory device 1 via memory interface circuit 25. ECC circuit 26 determines whether there is an error in the read data DAT based on the error correction code. If an error is found in the read data DAT, ECC circuit 26 performs error correction processing on the read data DAT based on the error correction code. ECC circuit 26 supplies the error-corrected read data to, for example, a data buffer 231.

[0047] (2) Semiconductor memory devices

[0048] Figure 2 This is a block diagram illustrating an example of the configuration of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 of the first embodiment is, for example, a NAND flash memory capable of non-volatile data storage.

[0049] The semiconductor memory device 1 includes a memory cell array 10, a sense amplifier module 11, a line decoder module 12, an input / output circuit 13, a register 14, a logic control circuit 15, a sequencer 16, a ready / busy control circuit 17, a voltage generation circuit 18, and a driver assembly 19.

[0050] The memory cell array 10 comprises blocks BLK0 to BLK(n-1) (where n is an integer greater than or equal to 1). Each block BLK contains multiple non-volatile memory cells associated with bit lines and word lines, serving as, for example, data erasure units. In the semiconductor memory device 1, for example, SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Three-Level Cell), or QLC (Quad-Level Cell) methods can be applied. In SLC, 1 bit of data is stored in each memory cell; in MLC, 2 bits of data are stored in each memory cell; in TLC, 3 bits of data are stored in each memory cell; and in QLC, 4 bits of data are stored in each memory cell. Alternatively, 5 or more bits of data can be stored in each memory cell.

[0051] Input / output circuit 13 controls the input and output of signals DQ<7:0> between itself and memory controller 2. Signals DQ<7:0> include, for example, instruction CMD, data DAT, address information ADD1, and status information STS. Instruction CMD includes, for example, instructions to cause semiconductor memory device 1 to perform processing corresponding to host instructions from host device 4. Address information ADD1 includes, for example, column address and row address. Row address includes, for example, block address, page address, string address, and plane address. Plane address may also be included in block address. Status information STS includes, for example, information about the results of write and read operations performed in semiconductor memory device 1.

[0052] More specifically, the input / output circuit 13 includes an input circuit and an output circuit, which perform the following processing: The input circuit receives write data DAT, address information ADD1, and instruction CMD from the memory controller 2 via the signal DQ<7:0>. The input circuit transmits the write data DAT to the sense amplifier module 11 and transmits the address information ADD1 and instruction CMD to the register 14. The output circuit receives status information STS from the register 14 and read data DAT from the sense amplifier module 11. The output circuit sends the status information STS and read data DAT to the memory controller 2 via the signal DQ<7:0>. Here, the input / output circuit 13 and the sense amplifier module 11 are connected via a data bus. The data bus includes, for example, eight data lines IO0 to IO7 corresponding to each signal DQ0 to DQ7. Furthermore, the number of data lines IO is not limited to eight; for example, it can be 16 or 32, and can be arbitrarily set.

[0053] The input / output circuit 13 then controls the input of the signal SBG from the memory controller 2. More specifically, the input circuit receives address information ADD2 from the memory controller 2 via the signal SBG. This input circuit then transmits the address information ADD2 to register 14.

[0054] Register 14 includes status register 141, address register 142, and instruction register 143.

[0055] Status register 141 stores status information STS and transmits the status information STS to input / output circuit 13 according to the instructions of sequencer 16.

[0056] Address register 142 stores the address information ADD1 transmitted from input / output circuit 13 and transmits this address information ADD1 to sequencer 16. Address register 142 transmits the column address in address information ADD1 to sense amplifier module 11 and the row address in address information ADD1 to row decoder module 12. Address register 142, for example, transmits the row address to driver assembly 19.

[0057] Address register 142 then stores the address information ADD2 transmitted from input / output circuit 13 and transmits the address information ADD2 to sequencer 16. Address register 142 then transmits the address information ADD2 to driver assembly 19 and sense amplifier module 11, for example.

[0058] Furthermore, in this specification, when it is described that address register 142 transmits any address information to a component and the component operates according to the address information, address register 142 may not necessarily transmit the address information to the component. Instead, for example, sequencer 16, which receives the address information, may control the operation of the component according to the address information.

[0059] The instruction register 143 stores the instruction CMD transmitted from the input / output circuit 13 and transmits the instruction CMD to the sequencer 16.

[0060] The logic control circuit 15 receives signals from the memory controller 2, such as chip enable signal bCE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal bWE, read enable signal bRE, and write protection signal bWP. The logic control circuit 15 controls the input / output circuit 13 and the sequencer 16 based on these signals.

[0061] The chip enable signal bCE is used to start the semiconductor memory device 1. The instruction latch enable signal CLE is used to notify the input / output circuit 13 of the period for sending the instruction CMD via the signal DQ<7:0> input to the semiconductor memory device 1. The address latch enable signal ALE is used to notify the input / output circuit 13 of the period for sending the address information ADD1 via the signal DQ<7:0> input to the semiconductor memory device 1. The write enable signal bWE and the read enable signal bRE are used to enable the input / output circuit 13 to input and output the signal DQ<7:0>, respectively. The write protection signal bWP is used to prevent writing data to the semiconductor memory device 1 and to prevent erasing data from the semiconductor memory device 1.

[0062] The sequencer 16 receives the instruction CMD and address information ADD1 from register 14, and controls the operation of the entire semiconductor memory device 1 according to the instruction CMD and address information ADD1. The sequencer 16 then receives address information ADD2 from address register 142. The sequencer 16 can also control the operation of the entire semiconductor memory device 1 according to the address information ADD2. The sequencer 16 controls, for example, the sense amplifier module 11, the line decoder module 12, the voltage generation circuit 18, and the driver assembly 19, to perform various operations such as write operations and read operations.

[0063] Sequencer 16 generates status information STS and sends the status information STS to status register 141.

[0064] The ready / busy control circuit 17 generates a ready / busy signal bR / B according to the control of the sequencer 16, and sends the ready / busy signal bR / B to the memory controller 2. The ready / busy signal bR / B is used to notify the memory controller 2 whether the semiconductor memory device 1 is in a ready state or a busy state. In the ready state, the semiconductor memory device 1 accepts instructions from the memory controller 2. In the busy state, the semiconductor memory device 1 does not accept instructions from the memory controller 2, such as those for performing operations accompanied by access to the memory cell array 10.

[0065] The voltage generation circuit 18 generates various voltages according to the control of the sequencer 16 and supplies the generated voltages to the driver assembly 19.

[0066] Driver component 19 receives a row address from address register 142, for example, and decodes the row address. Based on the decoding result, driver component 19 supplies various voltages used in various operations, such as voltages supplied by voltage generation circuit 18, to memory cell array 10, sense amplifier module 11, and row decoder module 12. Driver component 19 further receives address information ADD2 from address register 142, for example, and decodes the address information ADD2. Driver component 19 may also supply the various voltages based on the decoding result of address information ADD2.

[0067] The sensing amplifier module 11 receives the column address from the address register 142 and decodes the column address. Based on the decoding result, the sensing amplifier module 11 performs the data DAT transfer operation between the memory controller 2 and the memory cell array 10. That is, the sensing amplifier module 11 receives the write data DAT from the memory controller 2 via the input / output circuit 13 and transmits the write data DAT to the memory cell array 10. In addition, the sensing amplifier module 11 reads the read data DAT from the memory cells in the memory cell array 10 and outputs the read data DAT to the memory controller 2 via the input / output circuit 13. The sensing amplifier module 11 then receives, for example, address information ADD2 from the address register 142 and decodes the address information ADD2. The sensing amplifier module 11 can also read the read data DAT and transmit the read data to the input / output circuit 13 based on the decoding result of the address information ADD2.

[0068] The row decoder module 12 receives the row address from the address register 142 and decodes the row address. Based on the decoding result, the row decoder module 12 selects a specific block BLK (hereinafter also referred to as the selected block BLK(sel)) from the blocks BLK of the memory cell array 10 as the object to perform various operations such as read and write operations. The row decoder module 12 can transmit the voltage supplied from the driver component 19 to the selected block BLK(sel). The row decoder module 12 can also select multiple blocks BLK based on the decoding result, and voltage can be transmitted to each of the selected blocks BLK(sel) through the row decoder module 12.

[0069] The combination of the memory cell array 10, the sense amplifier module 11, and the line decoder module 12 described herein constitutes a planar PB. The semiconductor memory device 1, for example, includes multiple planar PBs, each having the same configuration as the described planar PB.

[0070] (3) Memory cell array

[0071] Figure 3 This section illustrates an example of the circuit configuration of the memory cell array 10 of the semiconductor memory device 1 according to the first embodiment. As an example of the circuit configuration of the memory cell array 10, an example of the circuit configuration of blocks BLK0 and BLK1 included in the memory cell array 10 is shown.

[0072] The following explanation focuses on the circuit configuration of a single block BLK. The same explanation applies to either block BLK0 or BLK1. The same explanation also applies to each of the other blocks BLK contained in the memory cell array 10.

[0073] This block BLK, for example, contains four string groups SU0 to SU3. Each string group SU contains multiple NAND strings NS. These multiple NAND strings NS are established in a one-to-one correspondence with m bit lines BL0, BL1, ..., and BL(m-1) (where m is an integer greater than or equal to 1). Each NAND string NS is connected to the corresponding bit line BL, and for example contains 96 cell transistors CT0 to CT95, and select transistors ST1 and ST2. Each cell transistor CT contains a control gate (hereinafter also referred to as the gate) and a charge storage layer. Each cell transistor CT can non-volatilely store data as a memory cell. In this specification, the cell transistors CT that function as memory cells are referred to as memory cell transistors. Each select transistor ST1 and ST2 is used to select the NAND string NS containing the select transistor ST1 and ST2 during various operations.

[0074] The drain of the select transistor ST1 of each NAND string NS is connected to the corresponding bit line BL. Unit transistors CT0 to CT95 are connected in series between the source of select transistor ST1 and the drain of select transistor ST2. More specifically, the source of select transistor ST1 is connected to the drain of unit transistor CT95, the source of unit transistor CT95 is connected to the drain of unit transistor CT94, the source of unit transistor CT94 is connected to the drain of unit transistor CT93, ..., the source of unit transistor CT1 is connected to the drain of unit transistor CT0, and the source of unit transistor CT0 is connected to the drain of select transistor ST2. The source of select transistor ST2 is connected to the source line SL.

[0075] The selection transistors ST1 and ST2, the unit transistors CT0 to CT95, and the wiring connected to their gates are described using integers j and k. Figure 3 In the example, the following statement holds true for each instance where j is an integer from 0 to 3, and also for each instance where k is an integer from 0 to 95.

[0076] The gates of the select transistors ST1 of each NAND string NS contained in string group SUj are commonly connected to the select gate line SGDj. The gates of the select transistors ST2 of each NAND string NS contained in block BLK are commonly connected to the select gate line SGS. The gates of the cell transistors CTk of each NAND string NS contained in block BLK are commonly connected to the word line WLk. These select gate lines SGD and SGS and the word line WL are provided, for example, in each block.

[0077] Each bit line BL is connected to the drain of the selection transistor ST1 that establishes the corresponding NAND string NS in each string group SU of the block BLK. These bit lines BL are connected in the same manner, for example, in different blocks BLK of the memory cell array 10, thus being shared among blocks BLK. The bit line BL is provided, for example, in each plane PB. In this case, the same bit line BL is not shared among blocks BLK in different planes PB, for example, as described above.

[0078] The source line SL is commonly connected to the source of the select transistor ST2 of each NAND string NS contained in the block BLK, thus being shared among the string groups SU of the block BLK. This source line SL is also connected in the same manner, for example, in different blocks BLK, thus being shared among the blocks BLK.

[0079] A collection of cell transistors CT that are connected to a word line WL in a serial group SU is called a cell group CU. For example, when each cell transistor CT in a cell group CU functions as a memory cell, the collection of 1-bit data stored in each cell transistor CT is called a "page of data". For example, when multiple bits of data are stored in each memory cell using methods such as MLC, multiple such "pages of data" can be stored in a cell group CU.

[0080] The circuit configuration of the memory cell array 10 has been described above, but the circuit configuration of the memory cell array 10 is not limited to the above configuration. For example, the number of string groups SU contained in each block BLK can be designed to be any number. The number of cell transistors CT and select transistors ST1 and ST2 contained in each NAND string NS can be designed to be any number. The number of word lines WL and select gate lines SGD and SGS can be changed according to the number of cell transistors CT and select transistors ST1 and ST2 in the NAND string NS, respectively.

[0081] This specification describes the use of a charge storage layer to store data in each unit transistor CT, but the configuration of each unit transistor CT is not limited to this. For example, each unit transistor CT may also use a floating gate instead of a charge storage layer to store data.

[0082] Figure 4 This is a cross-sectional view showing a portion of the cross-sectional structure of the memory cell array 10 of the semiconductor memory device 1 according to the first embodiment. Figure 4 Interlayer insulators are omitted in the example. For Figure 4 The reference symbol GWL shown will be mentioned in the explanation of the diagrams later.

[0083] Conductors 41, 42, and 49, memory pillar 43, and contact plug 48 constitute part of the structure of memory cell array 10.

[0084] Semiconductor memory device 1 includes a semiconductor substrate 40. Here, two directions parallel to, for example, mutually orthogonal to, the surface of the semiconductor substrate 40 are defined as the first direction D1 and the second direction D2. The direction intersecting the surface and forming the memory cell array 10 with the surface as a reference is defined as the third direction D3. The third direction D3 is described as a direction orthogonal to the first direction D1 and the second direction D2, but it is not limited to this. Hereinafter, the third direction D3 will be referred to as "up" and the direction opposite to the third direction D3 will be referred to as "down," but this terminology is merely for convenience and is, for example, unrelated to the direction of gravity.

[0085] A conductor 41 is disposed above the semiconductor substrate 40, separated by an insulator. The conductor 41 functions as a source line SL. Above the conductor 41, multiple layers of conductors 42 are sequentially deposited, separated from adjacent conductors by insulators. Figure 4 In the stack, there are 98 conductive layers 42, which function as select gate line SGS, word line WL0, word line WL1, word line WL2, ..., word line WL95 and a certain select gate line SGD from bottom to top.

[0086] A memory pillar 43 is disposed within the multilayer conductor 42. The memory pillar 43 extends, for example, in the D3 direction. The memory pillar 43 has a configuration in which a tunnel insulating layer 45, a charge storage layer 46, and a block insulating layer 47 are sequentially disposed on the side of a pillar-shaped semiconductor 44. The lower end of the semiconductor 44 reaches the conductor 41. The portion of the memory pillar 43 that intersects with a conductor 42 functions as a unit transistor CT, a select transistor ST1, or a select transistor ST2. Figure 4 In the middle, from bottom to top, there are sections that function as select transistor ST2, unit transistor CT0, unit transistor CT1, unit transistor CT2, ..., unit transistor CT95, and select transistor ST1. Select transistor ST2, unit transistors CT0 to CT95, and select transistor ST1 are contained within a certain NAND string NS. Semiconductor 44 functions as a current path for the NAND string NS, becoming a region that provides channels for forming each unit transistor CT.

[0087] The upper end of semiconductor 44 is connected to conductor 49 via contact plug 48. Conductor 49 extends, for example, in a first direction D1 and functions as a bit line BL. Furthermore, conductor LI is provided on conductor 41. Conductor LI extends, for example, in a second direction D2 and a third direction D3 and functions as a source line contact. Conductor LI has, for example, a line shape along the second direction D2. A string group SU is, for example, arranged between the two conductors LI.

[0088] (4) Threshold voltage of memory cell transistors

[0089] If the voltage applied to the gate of a transistor CT is increased, the transistor CT switches from an off state to an on state. The off state is a state where no path for current to flow through the transistor CT is formed, and the on state is a state where this path is formed. The voltage at which the transistor CT switches precisely from the off state to the on state is called the threshold voltage of the transistor CT. The threshold voltage is sometimes negative.

[0090] Reference Figure 5 This will be explained in relation to the threshold voltage of each cell transistor CT that functions as a memory cell.

[0091] Figure 5 express Figure 3 The following is an example of the threshold voltage distribution, data allocation, readout voltage, and verification voltage of the memory cell array 10 shown, where each cell transistor CT stores 3 bits of data in a TLC manner.

[0092] The unit transistor CT stores the 3-bit data based on a threshold voltage. The write operation involves a programming operation, which raises the threshold voltage of the unit transistor CT by injecting electrons into its charge storage layer.

[0093] Figure 5 This is a rough example of a graph plotting the number of unit transistors (CTs) with a threshold voltage of a certain value as a variable, representing one of eight threshold voltage distributions resulting from controlling that threshold voltage. The horizontal axis represents the threshold voltage Vth value of the unit transistor CT. The vertical axis represents the number of unit transistors CT.

[0094] Eight threshold voltage distributions are established, corresponding to states such as "Er", "A", "B", "C", "D", "E", "F", and "G". The threshold voltage of the unit transistor CT determines which of these states it is in. The threshold voltage of the unit transistor CT increases in the order it is in the "Er", "A", "B", "C", "D", "E", "F", and "G" states. For example, the state "Er" is assigned "111" ("upper order / middle order / lower order"), the state "A" is assigned "110", the state "B" is assigned "100", the state "C" is assigned "000", the state "D" is assigned "010", the state "E" is assigned "011", the state "F" is assigned "001", and the state "G" is assigned "101". The data assigned to each state is the data stored in the unit transistor CT that is in that state.

[0095] During the write operation, a verification operation is performed to confirm whether the threshold voltage of the cell transistor CT has reached the target voltage. The verification voltage used in this verification operation is set. Specifically, the verification voltage VVA is set corresponding to state "A", VVB to state "B", VVC to state "C", VVD to state "D", VVE to state "E", VVF to state "F", and VVG to state "G".

[0096] The case where a verification voltage VVA is applied to the gate of a certain cell transistor CT will be explained. If the cell transistor CT is in the ON state, it is clear that the threshold voltage of the cell transistor CT has not reached the target voltage. On the other hand, if the cell transistor CT is in the OFF state, it is clear that the threshold voltage of the cell transistor CT has reached the target voltage. Thus, it is possible to confirm, for example, the result of a write operation of "110" data, whether the threshold voltage of the cell transistor CT to be written has reached the target voltage. The same applies to other verification voltages.

[0097] During the readout operation, the state of the unit transistor CT is determined. The readout voltage used in the readout operation is set. Specifically, the readout voltage VRA is set to correspond to state "A", VRB to correspond to state "B", VRC to correspond to state "C", VRD to correspond to state "D", VRE to correspond to state "E", VRF to correspond to state "F", and VRG to correspond to state "G".

[0098] The case where the readout voltage VRA is applied to the gate of a certain unit transistor CT will be explained. If the unit transistor CT is in the ON state, it is clear that the unit transistor CT is in the "Er" state. On the other hand, if the unit transistor CT is in the OFF state, it is clear that the unit transistor CT is in any of the following states: "A", "B", "C", "D", "E", "F", and "G". Therefore, it can be determined that the unit transistor CT is in the "Er" state, or in any of the following states: "A", "B", "C", "D", "E", "F", and "G". The same applies to other readout voltages.

[0099] Before the readout operation is performed, some of the electrons stored in the charge storage layer of the single-cell transistor (CT) leak out over time, causing the threshold voltage of the CT to sometimes decrease. To address this decrease in threshold voltage, each readout voltage is set lower than the verification voltage, which is set to correspond to the same state as the readout voltage. That is, readout voltage VRA is lower than verification voltage VVA, readout voltage VRB is lower than verification voltage VVB, readout voltage VRC is lower than verification voltage VVC, readout voltage VRD is lower than verification voltage VVD, readout voltage VRE is lower than verification voltage VVE, readout voltage VRF is lower than verification voltage VVF, and readout voltage VRG is lower than verification voltage VVG.

[0100] Furthermore, the read-through voltage VREAD is set in a manner that is always higher than the threshold voltage of the unit transistor CT in the highest "G" state. When the read-through voltage VREAD is applied to the gate of a unit transistor CT, the unit transistor CT becomes ON regardless of the data stored.

[0101] Furthermore, the number of bits of data stored in a single unit transistor CT as described above, and the data allocation for the threshold voltage distribution, are merely examples and are not limited to this.

[0102] Figure 6This is a diagram illustrating the formation of a threshold voltage distribution that reduces the bit error rate (BER) when the semiconductor memory device 1 of the first embodiment performs a read operation. Figure 6 express Figure 3 The diagram shows an example of the threshold voltage distribution, readout voltage, and verification voltage of each transistor CT in the memory cell array 10 when storing 4 bits of data in QLC mode.

[0103] Figure 6 and Figure 5 The same approximate representation is an example of a graph obtained by plotting the number of unit transistors (CTs) with a threshold voltage of a certain value as a variable, as a reference. Figure 5 An example of 16 threshold voltage distributions resulting from the same control exerted by the programmer.

[0104] Sixteen threshold voltage distributions are established, for example, corresponding to states "Er", "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", "n", and "o". The threshold voltage of the unit transistor CT is used to distinguish which of these states the unit transistor CT is in. The threshold voltage of the unit transistor CT increases in the order of "Er", "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", "n", and "o".

[0105] Establish correspondences with these states, and with references Figure 5 The description states that the verification voltages used are set in the same manner. Specifically, the voltages are set in ascending order of voltage: Vva, Vvb, Vvc, Vvd, Vve, Vvf, Vvg, Vvh, Vvi, Vvj, Vvk, Vvl, Vvm, Vvn, and Vvo.

[0106] Establish correspondences with these states, and with references Figure 5 The author sets the readout voltages used in the same way. Specifically, the voltages are set in ascending order of voltage: Vra, Vrb, Vrc, Vrd, Vre, Vrf, Vrg, Vrh, Vri, Vrj, Vrk, Vrl, Vrm, Vrn, and Vro.

[0107] Each readout voltage is lower than the verification voltage, which is set to correspond to a state with the same readout voltage. (Refer to...) Figure 5 The readout voltage VREAD is always higher than the threshold voltage of the unit transistor CT when it is in its highest "o" state.

[0108] The control function for performing a write operation using QLC method is explained when the semiconductor memory device 1 performs a write operation using TLC method.

[0109] In the QLC writing operation, programming and verification operations can be performed by setting the threshold voltage of each transistor CT to any of the following voltages: Vvb, Vvd, Vvf, Vvh, Vvj, Vvl, and Vvn.

[0110] When the semiconductor memory device 1 receives an instruction from the memory controller 2 to perform a TLC-mode write operation, it performs a QLC-mode write operation instead of a TLC-mode write operation, for example. Specifically, the control described below applies to this write operation.

[0111] Instead of controlling the threshold voltage of the unit transistor CT to reach voltage VVA in a TLC manner, control is performed to bring that threshold voltage to voltage Vvb in a QLC manner. As a result, although... Figure 6 The threshold voltage distribution shown is for state "b", but this threshold voltage distribution is considered as the threshold voltage distribution for state "A".

[0112] Instead of controlling the threshold voltage of the unit transistor CT to reach voltage VVB in a TLC manner, control is performed to bring that threshold voltage to voltage Vvd in a QLC manner. As a result, although... Figure 6 The threshold voltage distribution shown is for the "d" state, but this threshold voltage distribution is considered as the threshold voltage distribution for the "B" state.

[0113] Instead of controlling the threshold voltage of the unit transistor CT to reach voltage VVC in a TLC manner, control is performed to achieve voltage Vvf in a QLC manner. As a result, although... Figure 6 The threshold voltage distribution shown is for the “f” state, but this threshold voltage distribution is considered as the threshold voltage distribution for the “C” state.

[0114] Instead of controlling the threshold voltage of the unit transistor CT to reach voltage VVD in a TLC manner, control is performed to achieve voltage Vvh in a QLC manner. As a result, although... Figure 6The threshold voltage distribution shown is for the “h” state, but this threshold voltage distribution is considered as the threshold voltage distribution for the “D” state.

[0115] Instead of controlling the threshold voltage of the unit transistor CT to reach voltage VVE in a TLC manner, control is performed to bring that threshold voltage to voltage Vvj in a QLC manner. As a result, although... Figure 6 The threshold voltage distribution for state "j" is shown, but this threshold voltage distribution is considered as the threshold voltage distribution for state "E".

[0116] Instead of controlling the threshold voltage of the unit transistor CT to reach voltage VVF in a TLC manner, control is performed to bring that threshold voltage to voltage Vvl in a QLC manner. As a result, although... Figure 6 The threshold voltage distribution shown is for the "l" state, but this threshold voltage distribution is considered as the threshold voltage distribution for the "F" state.

[0117] Instead of controlling the threshold voltage of the unit transistor CT to reach voltage VVG in a TLC manner, control is performed to bring that threshold voltage to voltage Vvn in a QLC manner. As a result, although... Figure 6 The threshold voltage distribution shown is for the “n” state, but this threshold voltage distribution is considered as the threshold voltage distribution for the “G” state.

[0118] Although not in Figure 5 and Figure 6 The various curves are shown, but the threshold voltage distribution of a certain state sometimes partially overlaps with the threshold voltage distribution of adjacent states on the curve.

[0119] When the semiconductor memory device 1 performs a write operation in TLC mode and utilizes QLC mode control, compared to the case where QLC mode control is not utilized, the ratio of the overlapping portion of each of the eight threshold voltage distributions on the graph with adjacent threshold voltage distributions is smaller. This means that when the semiconductor memory device 1 reads out the data written in this way during a read operation, the bit error rate is reduced.

[0120] In the above description, regarding the case where each cell transistor CT of the memory cell array 10 stores 3 bits of data using TLC (Time Limited Carrier) method, it was explained that the semiconductor memory device 1 can utilize QLC (Quick Limited Carrier) control to reduce the bit error rate during read operations. The semiconductor memory device 1 can also utilize other controls that allow each memory cell to store data with a larger number of bits than the QLC method. Thus, the semiconductor memory device 1 can utilize the control used to store data with a larger number of bits than the desired data number for each cell transistor CT of the memory cell array 10 to perform write operations.

[0121] (5) Group selection transistor

[0122] The following explanation will refer to each cell transistor CT in the NAND string NS connected to a certain bit line BL as the cell transistor CT connected to that bit line BL.

[0123] Figure 3 The bit lines BL0 to BL(m-1) shown are each included in any of a plurality of bit line groups BLG. Each bit line group BLG is, for example, composed of a plurality of bit lines BL. The number of bit lines BL constituting a bit line group BLG may be the same or different among all bit line group BLGs. For convenience, the term bit line group BLG is used in this specification, but there may also be bit line group BLGs composed of a single bit line BL. These bit line group BLGs are, for example, referred to... Figure 2 The plane PB described is defined in units.

[0124] Semiconductor memory device 1 is capable of performing operations in units of bit line groups (BLGs). Figure 2 The read operation is performed on a block BLK of the plane PB shown. The following explains that the semiconductor memory device 1 can perform a read operation on a unit of bit line groups (BLGs) when any block BLK of the plane PB is targeted. The following explanation uses one block BLK of the plane PB as an example. The following explanation also applies to other blocks BLK of the plane PB.

[0125] By setting the threshold voltage of each cell transistor CT connected to the multiple word lines WL associated with the block BLK, readout operations can be performed in units of bit line groups BLG. Hereinafter, the word lines WL will be referred to as group select word lines GWL, and the cell transistor CT will be referred to as group select transistors GCT.

[0126] Figure 7 This diagram illustrates an example of setting the threshold voltage of each group selection transistor (GCT) in a string group SU of the block BLK shown in the figure below. The figure schematically shows a portion of the cross-sectional structure of the memory cell array 10 of the semiconductor memory device 1 according to the first embodiment. Hereinafter, this string group SU is used as an example for explanation, but the following explanation also applies to other string groups SU in the block BLK. Hereinafter, the case where bit lines BL0 to BL(m-1) constitute 32 bit line groups BLG is used as an example for explanation, but the number of bit line groups BLG constituted by bit lines BL0 to BL(m-1) is not limited to 32.

[0127] For example, word line WL95 functions as group selection word line GWL0, word line WL94 functions as group selection word line GWL1, word line WL93 functions as group selection word line GWL2, ..., word line WL65 functions as group selection word line GWL30, and word line WL64 functions as group selection word line GWL31.

[0128] For each bit line BL0 to BL(m-1), the unit transistors CT95, CT94, CT93, ..., and CT64, which are connected to the group select word lines GWL0 to GWL31 respectively, function as group select transistors GCT. More specifically, unit transistor CT95 functions as group select transistor GCT0, unit transistor CT94 functions as group select transistor GCT1, unit transistor CT93 functions as group select transistor GCT2, ..., unit transistor CT65 functions as group select transistor GCT30, and unit transistor CT64 functions as group select transistor GCT31. Figure 7 In the diagram, the unit transistor CT, which functions as the group selection transistor GCT, is enclosed in a box marked with the symbol GCTG for reference.

[0129] Figure 7 In the example, p bit lines BL0, BL1, ..., and BL(p-1) constitute bit line group BLG0, q bit lines BLp, BL(p+1), ..., and BL(p+q-1) constitute bit line group BLG1, ..., and r bit lines BL(mr), BL(m-r+1), ..., and BL(m-1) constitute bit line group BLG31. Furthermore, each of p, q, and r is an integer greater than or equal to 1, and the sum of p, q, and r is less than m. Since bit lines BL0 to BL(m-1) constitute these bit line groups BLG0 to BLG31, the threshold voltage of the selector transistor (GCT) for each group is explained below.

[0130] First, the threshold voltage of each group selector transistor (GCT) is lower than voltage VL, or higher than voltage VL but lower than voltage VH. Voltage VL can also be the same as any readout voltage, such as voltage VRA. If voltage VL is the same as any readout voltage, voltage VH can also be the same as any readout voltage higher than the readout voltage that is the same as voltage VL. Alternatively, voltage VH can also be the same as voltage VREAD.

[0131] The following explains how, when the threshold voltage of the group selection transistor (GCT) is lower than the voltage VL, the threshold voltage of the GCT is classified as type "0", and how, when the threshold voltage of the GCT is higher than the voltage VL but lower than the voltage VH, the threshold voltage of the GCT is classified as type "1".

[0132] Figure 7In the example, for each bit line BL, the number of group selection transistors GCT0 to GCT31 connected to that bit line BL that are classified as type "1" with a threshold voltage is one. This threshold voltage of each group selection transistor GCT is compared with, for example, a reference... Figure 5 The programming actions described are controlled in the same way.

[0133] For each bit line BL0, BL1, ..., BL(p-1) constituting the bit line group BLG0, the group selection transistor GCT associated with the bit line BL satisfies the following condition: Among the threshold voltages of the group selection transistor GCTs connected to the bit line BL, the threshold voltage of transistor GCT0 is classified as type "1", and the threshold voltages of the other transistor GCTs are classified as type "0".

[0134] For each bit line BLp, BL(p+1), ..., BL(p+q-1) constituting bit line group BLG1, the group selection transistor GCT associated with the bit line BL satisfies the following condition: Among the threshold voltages of the group selection transistor GCTs connected to the bit line BL, the threshold voltage of transistor GCT1 is classified as type "1", and the threshold voltages of the other transistor GCTs are classified as type "0".

[0135] Similarly, for each bit line BL constituting bit line group BLG2, among the threshold voltages of the group selection transistor GCT connected to that bit line BL, only the threshold voltage of transistor GCT2 is classified as type "1". Furthermore, for each bit line BL constituting bit line group BLG3, among the threshold voltages of the group selection transistor GCT connected to that bit line BL, only the threshold voltage of transistor GCT3 is classified as type "1". The same applies below.

[0136] Finally, for each bit line BL(mr), BL(m-r+1), ..., BL(m-1) constituting bit line group BLG31, the group selection transistor GCT associated with the bit line BL satisfies the following condition: The threshold voltage of transistor GCT31 is classified as type "1" among the threshold voltages of the group selection transistors GCT31 connected to the bit line BL, while the threshold voltages of the other transistors GCT are classified as type "0".

[0137] The above describes how each unit transistor CT95, CT94, CT93, ..., and CT64, connected to each bit line BL0 to BL(m-1), functions as a group selection transistor (GCT). The remaining unit transistors CT0, CT1, ..., and CT63 connected to the bit line BL function as memory cell transistors (MCTs). Hereinafter, each unit transistor CT0 will be referred to as memory cell transistor MCT0, each unit transistor CT1 as memory cell transistor MCT1, ..., and each unit transistor CT63 as memory cell transistor MCT63. Figure 7 In the diagram, the memory cell transistor CT, which functions as the memory cell transistor MCT, is enclosed in a box marked with the symbol MCTG for reference.

[0138] Figure 7 In the example, the word lines WL related to the BLK in this block, which function as group selection word lines GWL, are selected sequentially starting from the word lines WL located on the bit line BL side. Also, Figure 4 As shown, the group select word line GWL is located between the word line WL and the bit line BL, which function as the group select word line GWL. Therefore, the group select word line GWL can be used to control whether the sense amplifier module 11 can access the memory cell transistor MCT connected to the word line WL via the bit line BL.

[0139] Figure 7 In the example, multiple bit lines BL that constitute the same bit line group BLG are shown to be adjacent to each other, but the bit lines BL that constitute the same bit line group BLG do not necessarily have to be adjacent to each other.

[0140] Figure 8 Show a list of references Figure 7 The table describes the threshold voltage settings for each group selector transistor (GCT).

[0141] The table shows the threshold voltage settings of the group selection transistors (GCTs) associated with the bit lines BL that constitute the bit line group BLG. More specifically, for each bit line BL that constitutes the bit line group BLG, the table shows the threshold voltage settings of the group selection transistors (GCTs) connected to that bit line BL. 0 and 1 in the table represent the threshold voltage classified as type "0" and the threshold voltage classified as type "1," respectively.

[0142] Next, it explains how many bit line groups BLG can be formed from bit lines BL0 to BL(m-1) based on the number of word lines WL used as group selection word lines GWL in a certain block BLK-related word line WL.

[0143] Figure 7 and Figure 8In the example, for each bit line BL constituting a bit line group BLG, among the threshold voltages of the group selection transistor GCT connected to that bit line BL, the threshold voltage of the transistor GCT connected only to a certain group selection word line GWL is classified as type "1". This holds true for any bit line group BLG, but if the bit line group BLG is different, the group selection word line GWL will also be different. Thus, Figure 7 and Figure 8 In the example, the bit line group BLG is established in a one-to-one correspondence with the group select word line GWL. Figure 7 and Figure 8 In the example, the corresponding number of bit line groups (BLGs) can be constructed in such a way. That is, the number of bit line groups (BLGs) that can be constructed to select one word from 32 group select word lines (GWLs).

[0144] Figure 9 The table shows a list of the number of group select word lines GWL associated with a certain block BLK of the memory cell array 10 of the semiconductor memory device 1 according to the first embodiment, and how many bit line groups BLG can be formed by bit lines BL0 to BL(m-1).

[0145] This shows that it is possible to construct a select word line GWL from the group to be used with Figure 7 The same method is used to select one bit line group BLG, so the same number of bit line groups BLG as the number of group select word lines GWL can be formed.

[0146] The table shows that when the number of group select word lines (GWLs) is 32, 32 bit line groups (BLGs) can be formed. This corresponds to... Figure 7 and Figure 8 Example.

[0147] (6) Sensing amplifier module

[0148] Figure 10 This is a block diagram illustrating an example of the configuration of the sense amplifier module 11 in the semiconductor memory device 1 of the first embodiment. The configuration of the sense amplifier module 11 described below is merely an example, and various configurations can be applied as the sense amplifier module 11.

[0149] The sensing amplifier module 11 includes, for example, m sensing amplifier groups SAU0 to SAU(m-1). Each of the m sensing amplifier groups SAU0 to SAU(m-1) is respectively established in a one-to-one correspondence with m bit lines BL0 to BL(m-1).

[0150] Each sense amplifier group (SAU) includes, for example, a sense amplifier circuit (SA) and latch circuits (ADL, BDL, CDL, and XDL). The number of latch circuits in each sense amplifier group (SAU) is, for example, based on the number of bits of data stored in each memory cell transistor (MCT). The sense amplifier circuit (SA) and the latch circuits (ADL, BDL, CDL, and XDL) will be described with reference to a specific sense amplifier group (SAU).

[0151] The sense amplifier circuit SA is connected to the bit line BL corresponding to the sense amplifier group SAU. The sense amplifier circuit SA, as well as the latch circuits ADL, BDL, CDL, and XDL, are all connected to the bus DBUS.

[0152] During the write operation, the sense amplifier circuit SA applies a voltage to the bit line BL. During the read operation, the sense amplifier circuit SA reads the data stored in the memory cell transistor MCT by sensing the current flowing through the bit line BL or changes in the potential of the bit line BL. During the read operation, for example, a control signal STB is supplied to the sense amplifier circuit SA via the sequencer 16. The sense amplifier circuit SA determines the data at the timing of the control signal STB activation and outputs the data to the bus DBUS.

[0153] The latching circuits ADL, BDL, and CDL receive data via the DBUS bus and temporarily store the received data.

[0154] The latch circuit XDL is connected to a bus XBUS. The latch circuit XDL is connected to the input / output circuit 13 via the bus XBUS.

[0155] The latch circuit XDL enables the reception and transmission of data between the sense amplifier group SAU and the input / output circuit 13. During a write operation, a bit of data received by the semiconductor memory device 1 from the memory controller 2 is first stored in the latch circuit XDL, and then transmitted to latch circuits ADL, BDL, and CDL, and the sense amplifier circuit SA. During a read operation, data in latch circuits ADL, BDL, and CDL, or the sense amplifier circuit SA, is first transmitted and stored in the latch circuit XDL, and then transmitted to the input / output circuit 13 before being output to the outside of the semiconductor memory device 1. Thus, the latch circuit XDL functions as a cache memory for the semiconductor memory device 1, connected in series between the input / output circuit 13 and the sense amplifier circuit SA.

[0156] During the readout operation, for example, data read from multiple memory cell transistors (MCTs) via multiple bit lines (BLs) is transmitted and stored in multiple latch circuits (XDLs), and then output to the outside of the semiconductor memory device 1 after being transmitted to the input / output circuit 13.

[0157] (7) Driver components and line decoder module

[0158] Figure 11 This illustrates an example of the configuration of the driver assembly 19 and the line decoder module 12 of the semiconductor memory device 1 according to the first embodiment.

[0159] Driver assembly 19 includes driver circuits DC0, DC1, DC2, ..., and DC(n-1). Line decoder module 12 includes voltage transmission circuits TC0, TC1, TC2, ..., and TC(n-1).

[0160] Driver circuits DC0, DC1, DC2, ..., and DC(n-1) are respectively established in a one-to-one correspondence with voltage transmission circuits TC0, TC1, TC2, ..., and TC(n-1) in the aforementioned order. Voltage transmission circuits TC0, TC1, TC2, ..., and TC(n-1) are respectively established in a one-to-one correspondence with blocks BLK0, BLK1, BLK2, ..., and BLK(n-1) in the aforementioned order. Driver circuits DC0, DC1, DC2, ..., and DC(n-1) are respectively established in a one-to-one correspondence with blocks BLK0, BLK1, BLK2, ..., and BLK(n-1) in the aforementioned order.

[0161] Each driver circuit DC is connected, for example, to 96 wirings CG0 to CG95, 4 wirings CXD0 to CXD3, and wiring CXS. These wirings CG0 to CG95, CXD0 to CXD3, and CXS are connected to a voltage transmission circuit TC that corresponds to the driver circuit DC. Groups of these wirings CG0 to CG95, CXD0 to CXD3, and CXS are, for example, provided in each driver circuit DC.

[0162] Each voltage transmission circuit TC, for example, is related to the reference. Figure 3 The 96 word lines WL0 to WL95, 4 select gate lines SGD0 to SGD3, and select gate line SGS are described. These word lines WL0 to WL95, and the select gate lines SGD0 to SGD3 and SGS, are positioned between the unit transistor CT or select transistor ST in the block BLK corresponding to the voltage transfer circuit TC, serving as a reference. Figure 3In the described connection relationships, the word lines WL0 to WL95, and the select gate lines SGD0 to SGD3 and SGS, are respectively established in a one-to-one correspondence with the wirings CG0 to CG95, CXD0 to CXD3, and CXS connected to the voltage transmission circuit TC in the described order. The group of word lines WL0 to WL95 and select gate lines SGD0 to SGD3 and SGS is, for example, provided in each voltage transmission circuit TC, i.e., in each block BLK.

[0163] The voltage generation circuit 18 generates various voltages used in the read operation, such as VCGRV and VREAD, and supplies the generated voltages to the driver assembly 19. Voltage VCGRV is a reference voltage. Figure 5 The term refers to the collective verification voltage or readout voltage. The voltage generation circuit 18 then generates voltages VH and VL, and supplies VH and VL to the driver assembly 19. In addition to these voltages supplied from the voltage generation circuit 18, the driver assembly 19 is also supplied with voltages such as VSS. Voltage VSS is a reference voltage.

[0164] Each driver circuit DC transmits a specific voltage from the voltage supplied to the driver assembly 19 to the wirings CG0-CG95, CXD0-CXD3, and CXS connected to the driver circuit DC, for example, based on the block address, page address, and serial address. During read operations, each driver circuit DC can also perform this transmission based on the address information ADD2.

[0165] The voltage transmission circuit TC, corresponding to the driver circuit DC, can electrically connect the wirings CG0-CG95, CXD0-CXD3, and CXS to the word lines WL0-WL95 and the select gate lines SGD0-SGD3 and SGS, respectively, which are connected to the voltage transmission circuit TC, to establish corresponding wirings. Through this electrical connection, the voltage transmitted to the wirings CG0-CG95, CXD0-CXD3, and CXS is transmitted to the word lines WL0-WL95 and the select gate lines SGD0-SGD3 and SGS, respectively, and then to the block BLK corresponding to the voltage transmission circuit TC.

[0166] Figure 12 This section illustrates an example of the configuration of the driver circuit DC0 and voltage transmission circuit TC0 of the semiconductor memory device 1 according to the first embodiment. Hereinafter, the driver circuit DC0 and voltage transmission circuit TC0 will be described, but the same description applies to other driver circuits DC and voltage transmission circuits TC corresponding to those driver circuits DC.

[0167] The driver circuit DC0 includes, for example, drivers CGdrv0, CGdrv1, ..., CGdrv95, CXDdrv0, CXDdrv1, CXDdrv2, CXDdrv3, ​​and CXSdrv.

[0168] For reference Figure 11 The connection between the driver circuit DC0 and the wiring CG0~CG95, CXD0~CXD3, and CXS is explained in more detail.

[0169] Driver CGdrv0 is connected to wiring CG0, driver CGdrv1 is connected to wiring CG1, driver CGdrv2 is connected to wiring CG2, ..., driver CGdrv95 is connected to wiring CG95. Driver CXDdrv0 is connected to wiring CXD0, driver CXDdrv1 is connected to wiring CXD1, driver CXDdrv2 is connected to wiring CXD2, driver CXDdrv3 is connected to wiring CXD3. Driver CXSdrv is connected to wiring CXS.

[0170] The wiring in the connection of each driver CGdrv0~CGdrv95, CXDdrv0~CXDdrv3, ​​and CXSdrv pairs CG0~CG95, CXD0~CXD3, and CXS transmits a certain voltage from the voltage supplied to the driver assembly 19.

[0171] The voltage transmission circuit TC0 includes the block decoder BD0 and the transistor group TG0. The transistor group TG0 includes transistors TWTr0, TWTr1, ..., TWTr95, TDTr0, TDTr1, TDTr2, TDTr3, and TSTr. These transistors are, for example, field-effect transistors (FETs) such as n-channel MOS (Metal Oxide Semiconductor) transistors.

[0172] The output of the block decoder BD0 is connected to the gate of each transistor TWTr0, TWTr1, ..., TWTr95, TDTr0, TDTr1, TDTr2, TDTr3, and TSTr.

[0173] Terminal 1 of transistor TWTr0 is connected to wiring CG0, and terminal 2 of transistor TWTr0 is connected to word line WL0. Terminal 1 of transistor TWTr1 is connected to wiring CG1, and terminal 2 of transistor TWTr1 is connected to word line WL1. The same applies below; terminal 1 of transistor TWTr95 is connected to wiring CG95, and terminal 2 of transistor TWTr95 is connected to word line WL95.

[0174] Terminal 1 of transistor TTr0 is connected to wiring CXD0, and terminal 2 of transistor TTr0 is connected to the select gate line SGD0. Terminal 1 of transistor TTr1 is connected to wiring CXD1, and terminal 2 of transistor TTr1 is connected to the select gate line SGD1. The same applies below; terminal 1 of transistor TTr3 is connected to wiring CXD3, and terminal 2 of transistor TTr3 is connected to the select gate line SGD3.

[0175] Terminal 1 of transistor TTr is connected to wiring CXS, and terminal 2 of transistor TTr is connected to the select gate line SGS.

[0176] Block decoder BD0 decodes the block address. When the block address matches the block address assigned to block BLK0, block decoder BD0 increases the voltage level output from its output terminal, establishing a correspondence between block BLK0 and the voltage transmission circuit TC0 containing block decoder BD0. Consequently, transistors TWTr0, TWTr1, ..., TWTr95, TDTr0, TDTr1, TDTr2, TDTr3, and TSTr, whose gates are respectively connected to this output terminal, become ON. Thus, as shown in the reference... Figure 11 As explained, wiring CG0~CG95, CXD0~CXD3, and CXS are electrically connected to word lines WL0~WL95 and select gate lines SGD0~SGD3 and SGS, respectively.

[0177] [Action Example]

[0178] The following describes in detail several examples of actions in which the memory controller 2 sends a set of instructions to the semiconductor memory device 1, and the semiconductor memory device 1 performs actions according to the set of instructions.

[0179] In the following description, the memory cell transistor MT, which is the object to be written to or read from, is referred to as the select memory cell transistor MCT. The select memory cell transistor MCT is contained in the select block BLK(sel) mentioned above. The word line WL in the word line WL associated with the select block BLK(sel) that is connected to the select memory cell transistor MCT is called the select word line WL(sel), and the other word lines WL are called the non-select word lines WL(usel). The string group SU containing the select memory cell transistor MCT is called the string group SU(sel). The select gate line SGD associated with the string group SU(sel) in the select gate line SGD associated with the select block BLK(sel) is called the select select gate line SGD(sel), and the other select gate lines SGD are called the non-select select gate line SGD(usel).

[0180] (1) Write action

[0181] Figure 13 This is an example of a timing diagram showing the time variation of the voltage applied to various lines related to the select block BLK(sel) during a write operation performed by the semiconductor memory device 1 in the first embodiment. The write operation described below is merely an example, and the write operation in this embodiment is not limited to this. In the following description, when describing the voltage applied to a certain line, unless it is explicitly stated that other voltages are subsequently applied to that line, it is assumed that the voltage is continuously applied to that line.

[0182] For example, by using the sequencer 16 to control the voltage generation circuit 18, the driver assembly 19, and the line decoder module 12, the voltage applied to the word line WL and the select gate lines SGD and SGS, as described below, can be achieved. For example, by using the sequencer 16 to control the voltage generation circuit 18 and the driver assembly 19, the voltage applied to the source line SL can be achieved. For example, by using the sequencer 16 to control the voltage generation circuit 18 and the sense amplifier module 11, the voltage applied to the bit line BL can be achieved.

[0183] The following explanation focuses on controlling the voltage applied to a single non-select word line WL(usel). This is because the voltages applied to the other non-select word lines WL(usel) are controlled in the same manner. The same logic applies to controlling the voltage applied to a single non-select gate line SGD(usel). Similarly, the same logic applies to controlling the voltage applied to a single group select word line GWL. Furthermore, the same logic applies to controlling the voltage applied to a single bit line BL.

[0184] Figure 13 Before the write operation of the example begins, voltage VSS is applied to word lines WL(sel), WL(usel), and GWL, select gate lines SGD(sel), SGD(usel), and SGS, bit line BL, and source line SL, respectively.

[0185] First, perform the programming actions. Specifically, as follows.

[0186] The control described below will be implemented at time T00.

[0187] When the threshold voltage of the select memory cell transistor (MCT) connected to the bit line BL is increased through a programming operation, the voltage applied to the bit line BL is maintained at voltage VSS. On the other hand, when the threshold voltage is not increased through this programming operation, the voltage applied to the bit line BL is increased from voltage VSS to voltage VBL1.

[0188] The voltage applied to the source line SL is changed from voltage VSS to voltage VCELSRC1. Voltage VCELSRC1 is a reference voltage different from voltage VSS. The voltage applied to the select gate line SGD(sel) is increased from voltage VSS to voltage VSGD1.

[0189] Subsequently, at time T01, the voltage applied to the select gate line SGD(sel) is reduced from voltage VSGD1 to voltage VSGD2. Voltage VSGD2 is higher than voltage VSS and lower than voltage VBL1. Voltage VSGD2 is such that when voltage VSS is applied to bit line BL, the select transistor ST1 connected to bit line BL is in the ON state, and when voltage VBL1 is applied to bit line BL, the select transistor ST1 is in the OFF state. Additionally, applying voltage VSGD1 to the select gate line SGD(sel) may, for example, shorten the time before the potential of the select gate line SGD(sel), which is stabilized by voltage VSS, is stabilized by voltage VSGD2. Alternatively, voltage VSGD2 may be applied to the select gate line SGD(sel) without applying voltage VSGD1.

[0190] After the potential of the wiring to which the voltage is applied stabilizes, the control described below is performed. Additionally, since a voltage VSS is applied to the select gate line SGS, the select transistor ST2 connected to that bit line BL is in the off state.

[0191] At time T02, the voltage applied to the select word line WL(sel) is increased from voltage VSS to voltage VPGM, and the voltages applied to the non-select word line WL(usel) and the group select word line GWL are increased from voltage VSS to voltage VPASS, respectively. Voltage VPASS is lower than voltage VPGM. Voltage VPGM is used to inject electrons into the charge storage layer of the select memory cell transistor MCT to raise the threshold voltage of the select memory cell transistor MCT. Voltage VPASS is a voltage high enough that, in the NAND string NS including the select transistor ST1 in the on state, it turns on the memory cell transistor MCT connected to the non-select word line WL(sel) to which voltage VPASS is applied, but suppresses programming of the memory cell transistor MCT. Furthermore, voltage VPASS is a voltage high enough that, in the NAND string NS including the select transistor ST1 in the off state, it raises the potential of the channel through coupling to a level that suppresses the rise in the threshold voltage of the select memory cell transistor MCT caused by the applied voltage VPGM.

[0192] Subsequently, at time T03, the voltages applied to the bit line BL, source line SL, select gate line SGD(sel), select word line WL(sel), non-select word line WL(usel), and group select word line GWL are changed to voltage VSS.

[0193] The programming action is performed in this way, followed by the verification action. Specifically, it is as follows.

[0194] The control described below will be implemented at time T04.

[0195] The voltages applied to the select gate line SGD(sel) and select gate line SGS are increased from voltage VSS to voltage VSG, respectively. The voltage applied to the select word line WL(sel) is changed from voltage VSS to voltage VCGRV. The voltages applied to the non-select word line WL(usel) and group select word line GWL are increased from voltage VSS to voltage VREAD, respectively. Voltage VSG is the voltage at which the select transistor ST is turned on when its gate is applied. Voltage VCGRV is a reference voltage. Figure 5 The verification voltages described are any one of VVA, VVB, VVC, VVD, VVE, VVF, and VVG.

[0196] After the potential of the wiring with the applied voltage stabilizes, the control described below is performed. At time T05, the voltage applied to the bit line BL is increased from voltage VSS to voltage VBL2, and the voltage applied to the source line is changed from voltage VSS to voltage VCELSRC2. Voltage VBL2 is, for example, the voltage that allows read current to flow through the bit line BL when the select memory cell transistor MCT connected to the bit line BL is in the ON state. Voltage VCELSRC2 is a reference voltage different from voltage VSS. Voltage VCELSRC2 may also be different from voltage VCELSRC1.

[0197] After the potential of the wiring with the applied voltage stabilizes, the sensing amplifier circuit SA connected to the bit line BL senses, for example, the current on the bit line BL. This confirms the result of the programming operation, such as whether the threshold voltage of the select memory cell transistor MCT connected to the bit line BL has reached the target voltage.

[0198] Subsequently, at time T06, the voltages applied to bit line BL, source line SL, select gate line SGD(sel), select gate line SGS, select word line WL(sel), non-select word line WL(usel), and group select word line GWL are changed to voltage VSS.

[0199] The verification action follows the programming action. This combination of programming and verification actions can be repeated during the write action. Figure 13 The diagram also shows the time variation of the voltage applied to the wiring during the final verification operation. Specifically, it is as follows.

[0200] The control described below will be implemented at time T07.

[0201] The voltages applied to the select gate line SGD(sel) and select gate line SGS are increased from voltage VSS to voltage VSG, respectively. The voltage applied to the select word line WL(sel) is changed from voltage VSS to voltage VCGRV. The voltages applied to the non-select word line WL(usel) and group select word line GWL are increased from voltage VSS to voltage VREAD, respectively. This voltage VCGRV may also be different from the voltage VCGRV used at time T04 described above.

[0202] After the potential of the wiring with the applied voltage stabilizes, the control described below is performed. At time T08, the voltage applied to the bit line BL is increased from voltage VSS to voltage VBL2, and the voltage applied to the source line is changed from voltage VSS to voltage VCELSRC2.

[0203] After the potential of the wiring with the applied voltage stabilizes, the sensing amplifier circuit SA connected to the bit line BL senses, for example, the current on the bit line BL. This confirms the result of the programming operation, such as whether the threshold voltage of the select memory cell transistor MCT connected to the bit line BL has reached the target voltage.

[0204] Subsequently, at time T09, the voltages applied to the bit line BL, source line SL, select gate line SGD(sel), select gate line SGS, select word line WL(sel), non-select word line WL(usel), and group select word line GWL are changed to voltage VSS.

[0205] The above description relates to the write operation performed by the semiconductor memory device 1 of the first embodiment. (Refer to...) Figure 7 As explained, the threshold voltages of each group select transistor (GCT) are classified as type "0" or type "1," thus allowing the same write operation to be used. When the threshold voltage of a particular GCT is raised, the voltage applied to the group select word line GWL, which is connected to the gate of that GCT, is controlled in the same manner as described for the select word line WL(sel). The control of the voltages applied to the other lines is the same as the write operation described above.

[0206] (2) Read out the action

[0207] The semiconductor memory device 1 of the first embodiment is capable of performing operations in units of bit line groups (BLGs). Figure 2The block BLK(sel) of the plane PB shown is the read operation for the target. More specifically, the semiconductor memory device 1 can select, for example, one bit line group BLG from a plurality of bit line groups BLG, and read the data stored in the memory cell transistor MCT connected to that bit line group BLG in the block BLK(sel). Hereinafter, the selected bit line group BLG is labeled with the symbol BLG(sel).

[0208] (2-1) Instruction Sequence

[0209] Figure 14 The following timing diagram illustrates an example of the timing changes of the instruction set and various other signals related to a read operation performed by the semiconductor memory device 1 of the first embodiment. Hereinafter, for ease of reference, the previously described read data DAT will be referred to as read data Dout. In the following description, when the term "level" is used in relation to a signal, unless specifically mentioned otherwise, the voltage level of that signal is referred to. In the following description, when a signal is described as having a certain level, unless explicitly stated that subsequent control to change that signal to another level will be applied, the signal will remain at the described level.

[0210] During the period when the semiconductor memory device 1 is in the ready state, it sends the ready / busy signal bR / B to the memory controller 2 at the H level. On the other hand, during the period when the semiconductor memory device 1 is in the busy state, it sends the ready / busy signal bR / B to the memory controller 2 at the L level.

[0211] For example, during the period when the memory controller 2 of the semiconductor memory device 1 sends the ready / busy signal bR / B to the memory controller 2 at the H level, that is, during the period when the semiconductor memory device 1 is in the ready state, the memory controller 2 operates in the following manner.

[0212] The memory controller 2 generates an instruction set to instruct the semiconductor memory device 1 to perform a read operation, and sends the instruction set to the semiconductor memory device 1 via the signal DQ<7:0>. This instruction set includes the instruction "00h", address information ADD1, and the instruction "30h". The memory controller 2 then generates address information ADD2 and sends it to the semiconductor memory device 1 via the signal SBG. Upon receiving the instruction set and address information ADD2, the semiconductor memory device 1 begins the read operation. More specifically, the details are as follows.

[0213] The memory controller 2 generates the instruction "00h" and sends it to the semiconductor memory device 1. The instruction "00h" is used to cause the semiconductor memory device 1 to perform a read operation. The logic control circuit 15 enables the input / output circuit 13 to fetch the instruction "00h" and transfer it to the instruction register 143.

[0214] Subsequently, the memory controller 2 generates, for example, 5-cycle address information ADD1 and sends this address information ADD1 to the semiconductor memory device 1. This address information ADD1 includes, for example, a column address and a row address. The row address includes a block address and a plane address. The block address specifies the block BLK(sel)_1 to be read. The plane address specifies the plane PB to be read. The column address, for example, specifies multiple latch circuits XDL at the start of the read operation. The address information ADD1 is not limited to 5 cycles and can be address information of any number of cycles. The plane PB specified for the plane address is... Figure 2 The case of plane PB will be explained below. In plane PB, as shown in the example... Figure 7 As explained, a bit line group BLG is defined. This line address also includes the page address of the specified word line WL(sel) and the string address of the specified string group SU(sel). The logic control circuit 15 enables the input / output circuit 13 to fetch the address information ADD1 and transfer the address information ADD1 to the address register 142.

[0215] The memory controller 2 generates address information ADD2 and sends it to the semiconductor memory device 1 via signal SBG. This address information ADD2 is associated with the address information ADD1. For example, address information ADD2 specifies a bit group BLG(sel)_1. For example, the logic control circuit 15 enables the input / output circuit 13 to fetch address information ADD2 and transfer it to the address register 142. This control by the logic control circuit 15 can also be based on any timing control signal sent from the memory controller 2 and received by the logic control circuit 15. This timing control signal can also be synchronized with the write enable signal bWE, for example. Figure 14 The address information ADD1 and the corresponding address information ADD2 are shown to be sent by the memory controller 2 during the same period, but the period for sending address information ADD2 is not limited to this. In this specification, address information ADD2 is sent via one signal SBG, but address information ADD2 can also be sent via multiple signals. Address information ADD2 can also be address information of any number of cycles.

[0216] The memory controller 2 can generate and send the combination of address information ADD1 and address information ADD2 multiple times. Figure 14 The following indicates that address information ADD1 is generated and sent s times, and address information ADD2 is also generated and sent s times. The instruction set contains address information ADD1 s times. The following explains the case where address information ADD1 and address information ADD2 are generated and sent s times each, but it is also possible to generate and send address information ADD1 and address information ADD2 only once. Figure 14 In this context, address information ADD1 is shown for each transmission, but it can also be considered as address information obtained by summarizing the address information ADD1 from the first transmission, the address information ADD1 from the second transmission, ..., and the address information ADD1 from the sth transmission. The same applies to address information ADD2.

[0217] The second address information ADD1 specifies another block BLK(sel)_2 as the target of the read operation. The third address information ADD1 specifies another block BLK(sel)_3 as the target of the read operation. The same applies below; the s-th address information ADD1 specifies yet another block BLK(sel)_s as the target of the read operation. Thus, in any given instance, the address information ADD1 specifies a different block BLK than the address information ADD1 specifies in other instances.

[0218] Furthermore, the plane address of each instance of address information ADD1 shares a common plane PB with the plane addresses of other instances of address information ADD1. The following explains the designation of the common plane PB. The page address of each instance of address information ADD1 can be a word line WL shared with the word line WL specified by the page addresses of other instances of address information ADD1, or it can be a different word line WL. The string address of each instance of address information ADD1 can be a string group SU shared with the string group SU specified by the string addresses of other instances of address information ADD1, or it can be a different string group SU.

[0219] The second address information ADD2 specifies a bit line group BLG(sel)_2, which is different from the bit line group specified in the first address information ADD2. The third address information ADD2 specifies another bit line group BLG(sel)_3. The same applies below; the s-th address information ADD2 specifies yet another bit line group BLG(sel)_s. Thus, in any given instance, the address information ADD2 specifies a bit line group BLG that is different from the bit line groups specified in all other instances of ADD2.

[0220] The address information ADD1 and ADD2 sent in this way are taken into the input / output circuit 13 and transmitted to the address register 142 as described above.

[0221] Subsequently, the memory controller 2 generates the instruction "30h" and sends it to the semiconductor memory device 1. Instruction "30h" is used to instruct the semiconductor memory device 1 to perform a read operation based on the address information ADD1 received after receiving instruction "00h". The logic control circuit 15 enables the input / output circuit 13 to fetch instruction "00h" and transfer it to the instruction register 143.

[0222] Upon receiving the instruction "30h", sequencer 16 causes logic control circuit 15 to send a ready / busy signal bR / B at an L level to memory controller 2. As a result, memory controller 2 is notified that semiconductor memory device 1 is in a busy state. Upon receiving the instruction "30h", sequencer 16 controls voltage generation circuit 18, driver assembly 19, sense amplifier module 11, and line decoder module 12 to begin readout operations.

[0223] In this read operation, the memory cell transistor MCT connected to the bit line BL of the bit line group BLG(sel) specified by the address information ADD2, which is associated with the address information ADD1, in each block BLK(sel) of the address information ADD1, can become the object of the read operation. More specific details are as follows.

[0224] The memory cell transistor MCT in block BLK(sel)_1, connected to bit line BL of bit line group BLG(sel)_1, can be the object of a read operation. Furthermore, the memory cell transistor MCT in block BLK(sel)_2, connected to bit line BL of bit line group BLG(sel)_2, can be the object of a read operation. Furthermore, the memory cell transistor MCT in block BLK(sel)_3, connected to bit line BL of bit line group BLG(sel)_3, can be the object of a read operation. Similarly, the memory cell transistor MCT in block BLK(sel)_s, connected to bit line BL of bit line group BLG(sel)_s, can also be the object of a read operation.

[0225] The data Dout read out by this readout action is transmitted to the latch circuit XDL of the sense amplifier module 11. Subsequently, the sequencer 16 causes the ready / busy control circuit 17 to send the ready / busy signal bR / B at a high level to the memory controller 2. Thus, the memory controller 2 is notified that the semiconductor memory device 1 is in a ready state.

[0226] The memory controller 2 generates an instruction set containing the instruction "05h", address information ADD1, and instruction "E0h" based on the received ready / busy signal bR / B indicating that the semiconductor memory device 1 is in a ready state, and sends this instruction set to the semiconductor memory device 1 via the signal DQ<7:0>. The semiconductor memory device 1 receives this instruction set. The instructions "05h" and "E0h" are used to cause the semiconductor memory device 1 to output the read data transferred to the latch circuit XDL through the read operation to the memory controller 2. The sequencer 16, based on the received instruction "E0h", causes the semiconductor memory device 1 to output the data Dout transferred to the latch circuit XDL through the read operation to the memory controller 2. However, it is not mandatory to use the aforementioned instruction "05h", address information ADD1, and instruction "E0h". In this case, the semiconductor memory device 1 may, for example, use the triggering of the read enable signal bRE sent from the memory controller 2 as a trigger to output the data Dout to the memory controller 2.

[0227] In this description, the semiconductor memory device 1 receives address information ADD2 of a specified bit line group BLG from the memory controller 2 via the signal SBG. However, this embodiment is not limited to this. The instruction set sent by the memory controller 2 via the signal DQ<7:0> to cause the semiconductor memory device 1 to perform a read operation may also include address information of the specified bit line group BLG. Furthermore, it is also possible to... Figure 14 Before the instruction set shown, a prefix instruction is sent indicating that the memory controller 2 will send the address information ADD2 to the semiconductor memory device 1.

[0228] Figure 15 This is an example of a table used by the memory controller 2 to generate a set of instructions for causing the semiconductor storage device 1 to perform a read operation.

[0229] The table is as follows Figure 15 The table shown illustrates the logical and physical addresses in a corresponding manner, used for logical address to physical address translation. This table is also known as a logical-to-physical translation table.

[0230] The memory controller 2 receives a host instruction from the host device 4, for example. The host instruction contains a logical address, or information corresponding to the logical address.

[0231] Upon receiving a host instruction to perform a write operation, the memory controller 2 generates address information within the instruction set for the write operation, for example, based on a physical address. This physical address specifies a plane PB, a block BLK, a string group SU, a word line WL, and multiple latching circuits XDL at the starting point of the operation. Based on this address information, the write operation is performed page-by-page via bit lines BL0 to BL(m-1) through the semiconductor memory device 1. The memory controller 2 writes the logical address associated with the received host instruction and the physical address into a logic-to-physical translation table stored in RAM 23 in a correspondence-establishing manner. This generates the logic-to-physical translation table used during read operations.

[0232] Upon receiving a host instruction to perform a read operation, memory controller 2 refers to the logical-physical translation table (LPT) to obtain the logical address associated with the received host instruction and establish the corresponding physical address. Memory controller 2 generates address information ADD1, for example, based on this physical address. Address information ADD1 specifies, for example, the same plane PB, block BLK, serial group SU, word line WL, and multiple latch circuits XDL as the physical address specifyer. That is, address information ADD1 specifies the region to be read on a page-by-page basis. Memory controller 2 generates an instruction set for performing the read operation, containing address information ADD1, based on the host instruction. Memory controller 2 can then generate address information ADD2, without referring to the LPT, based on the host instruction. Address information ADD2 specifies, for example, a bit group BLG in the execution unit of the read operation.

[0233] (2-2) Parallel reading from multiple blocks

[0234] Figure 16 It is used to conceptually illustrate the reference. Figure 14 This describes a graph of multiple blocks BLK(sel) reading data Dout. Figure 16 In order to facilitate reference, the number of bit lines BL that make up each bit line group BLG is set to 4.

[0235] Figure 16 The following examples illustrate this: Figure 14 In the example, block BLK(sel)_1 and bit line group BLG(sel)_1 are block BLK1 and bit line group BLG1, respectively. Figure 14 In the example, block BLK(sel)_2 and bit line group BLG(sel)_2 are block BLK3 and bit line group BLG4, respectively. Figure 14 In the example, block BLK(sel)_3 and bit line group BLG(sel)_3 are block BLK5 and bit line group BLG3, respectively, ... Figure 14In the example, block BLK(sel)_s and bit line group BLG(sel)_s are block BLK6 and bit line group BLG5, respectively.

[0236] The driver circuit DC and voltage transmission circuit TC corresponding to the block BLK specified by the block address of each address information ADD1 operate as follows: The driver circuit DC supplies various voltages to the voltage transmission circuit TC based, for example, the page address and string address in the address information ADD1, and the address information ADD2 associated with the address information ADD1. The voltage transmission circuit TC then transmits the supplied voltages to the block BLK according to the block address. Figure 16 In the example, driver circuit DC1 and voltage transmission circuit TC1, driver circuit DC3 and voltage transmission circuit TC3, driver circuit DC5 and voltage transmission circuit TC5, and driver circuit DC6 and voltage transmission circuit TC6 operate in this manner. The sense amplifier module 11, for example, enables the corresponding sense amplifier group SAU to be established for each bit line BL of the bit line group BLG(sel) specified by the address information ADD2. The sense amplifier module 11 uses the enabled sense amplifier group SAU to read data from each block BLK(sel) in the following manner.

[0237] Data is read from block BLK1 via bit line BL of bit line group BLG1, data is read from block BLK3 via bit line BL of bit line group BLG4, data is read from block BLK5 via bit line BL of bit line group BLG3, ..., data is read from block BLK6 via bit line BL of bit line group BLG5.

[0238] Thus, data is read from different blocks BLK(sel) via the bit lines of different bit line groups BLG(sel), so the sensing amplifier module 11 can read data from these blocks BLK(sel) in parallel.

[0239] The sense amplifier module 11 transmits the data read from the effective sense amplifier group SAU via the data bus to the input / output circuit 13, and outputs it to the memory controller 2 via the input / output circuit 13. The size of this data is, for example, proportional to the number of effective sense amplifier groups SAU. That is, the size of this data is proportional to the number of bit lines constituting the bit line group BLG(sel).

[0240] (2-3) Timing Diagram

[0241] The description explains that during the read operation, data can be read in parallel from each of multiple blocks BLK(sel) in units of bit line groups BLG. The following explanation focuses on reading data from a specific block BLK(sel) within that block in units of a specific bit line group BLG(sel).

[0242] Figure 17 The following timing diagram illustrates an example of the time variation of the voltage applied to various wirings related to the selected block BLK(sel) when the semiconductor memory device 1 of the first embodiment performs the read operation. The read operation described below is merely an example, and the read operation of this embodiment is not limited to this.

[0243] In the following description, the group select word line GWL related to the selected block BLK(sel) will be referred to as follows.

[0244] For reference Figure 7 As explained, for each bit line BL constituting the bit line group BLG(sel), a group selection transistor GCT1 with a threshold voltage classified as type "1" is connected to that bit line BL. The group selection word lines GWL connected to these group selection transistors GCT1 with threshold voltages classified as type "1" are called group selection word lines GWL(sel), and the other group selection word lines GWL are called group selection word lines GWL(usel). See reference... Figure 8 As explained, the group select word line GWL(sel) is the group select word line GWL corresponding to the bit line group BLG(sel).

[0245] The following is in relation to Figure 13 For the same reasoning, the control of the voltage applied to a certain non-select word line WL(usel) is explained for the non-select select gate line SGD(usel), the control of the voltage applied to a certain non-select select gate line SGD(usel), the control of the voltage applied to a certain group select word line GWL(usel), and the control of the voltage applied to a certain bit line BL are also explained for the non-select select gate line SGD(usel).

[0246] exist Figure 17 Before the read operation of the example begins, voltage VSS is applied to word lines WL(sel), WL(usel), GWL(sel), and GWL(usel), select gate lines SGD(sel), SGD(usel), and SGS, bit line BL, and source line SL, respectively.

[0247] The control described below will be implemented at time T10.

[0248] The voltages applied to the select gate lines SGD(sel) and SGS are increased from voltage VSS to voltage VSG, respectively. The voltage applied to the select word line WL(sel) is changed from voltage VSS to voltage VCGRV. The voltage applied to the non-select word line WL(usel) is increased from voltage VSS to voltage VREAD.

[0249] Change the voltage applied to the group select word line GWL(sel) from voltage VSS to voltage VH. Change the voltage applied to the group select word line GWL(usel) from voltage VSS to voltage VL. Figure 17 In the example, voltage VL is higher than voltage VSS.

[0250] Subsequently, at time T11, the voltage applied to the bit line BL is increased from voltage VSS to voltage VBL2, and the voltage applied to the source line SL is changed from voltage VSS to voltage VCELSRC2.

[0251] After the potential of the wiring under such applied voltage stabilizes, for each bit line BL of the bit line group BLG(sel), the sense amplifier circuit SA connected to that bit line BL senses, for example, the current flowing through that bit line BL. This can be achieved by turning on each group selection transistor GCT connected to that bit line BL. Based on the sensing of this current, the sense amplifier circuit SA reads out the data stored in the selection memory cell transistor MCT connected to that bit line BL.

[0252] Subsequently, at time T12, the voltages applied to the bit line BL, source line SL, select gate line SGD(sel), select gate line SGS, select word line WL(sel), non-select word line WL(usel), group select word line GWL(sel), and group select word line GWL(usel) are changed to voltage VSS.

[0253] Figure 18 This diagram illustrates the application of voltages to the select word lines GWL associated with block BLK(sel) when reading data from block BLK(sel) in units of bit line group BLG1. Figure 18 In the example, the threshold voltage of each group selector transistor GCT is as follows: Figure 7 The settings are shown.

[0254] For each bit line BL constituting bit line group BLG1, among the threshold voltages of the group selection transistors GCT connected to that bit line BL, only the threshold voltage of transistor GCT1 is classified as type "1", while the threshold voltages of the other transistors GCT are classified as type "0". Therefore, the group selection word line GWL1 connected to transistor GCT1 is the group selection word line GWL(sel), and the other group selection word lines GWL are group selection word lines GWL(usel). Thus, in Figure 17 For example, from time T11 to time T12, a voltage VH is applied to the group select word line GWL1, and a voltage VL is applied to the other group select word lines GWL. For example, the bit line group BLG1 is specified according to the address information ADD2, and the application of this voltage to various lines is controlled.

[0255] The following explanation focuses on a specific bit line BL in bit line group BLG1, but the explanation also applies to other bit lines BL in bit line group BLG1.

[0256] When a voltage is applied to each group select word line GWL as described above, a voltage higher than the threshold voltage is applied to the gate of each group select transistor GCT connected to that bit line BL in the following manner: For the gate of transistor GCT1, which has a threshold voltage classified as type "1", a voltage VH higher than that threshold voltage is applied via group select word line GWL1. For the gates of other transistors GCT, which have threshold voltages classified as type "0", a voltage VL higher than these threshold voltages is applied via the other group select word lines GWL, respectively.

[0257] Therefore, all group selection transistors (GCTs) connected to the bit line BL are turned on. As a result, the sense amplifier circuit (SA) connected to the bit line BL can read the data stored in the select memory cell transistor (MCT) by sensing the current flowing through the bit line BL.

[0258] On the other hand, the other bit line groups (BLG) are as follows. The following explanation uses a bit line BL from bit line group BLG0 as an example. The same explanation applies to the other bit lines BL of bit line groups other than BLG1.

[0259] As described above, when a voltage is applied to each group select word line GWL, a voltage VL is applied to the gate of the group select transistor GCT0, which is connected to the bit line BL, via the group select word line GWL0. The threshold voltage of the group select transistor GCT0 is classified as type "1", which is higher than the voltage VL.

[0260] Therefore, the group selection transistor GCT0 is in the off state. As a result, even if the memory cell transistor MCT connected to the bit line BL and the select word line WL(sel) is turned on, the on state of the memory cell transistor MCT will not affect the current flowing through the bit line BL.

[0261] In this way, data can be read from the block BLK(sel) in units of bit line groups BLG1. This data reading does not affect the current flowing through the individual lines BL of other bit line groups BLG. This means that the semiconductor memory device 1 can read data from other blocks BLK in units of different bit line groups BLG. Therefore, as referred to... Figure 14 and Figure 16 As explained, the semiconductor memory device 1 can read data in parallel from multiple blocks BLK via different bit line groups BLG.

[0262] The example described above illustrates the case where data is read in parallel from multiple blocks BLK(sel) of the same plane PB. However, as mentioned above, data can also be read from a single block BLK(sel) via a single bit line group BLG.

[0263] The example described above illustrates the case of reading data from a single block BLK(sel) via a single bit line group BLG. However, data can also be read from a single block BLK(sel) via any number of bit line groups BLG.

[0264] For example, Figure 18 The example illustrates the case where data is read from a block BLK(sel) in units of bit lines BLG0 and BLG1. (Refer to...) Figure 14 The description defines the address information ADD2 associated with the address information ADD1 that specifies the block BLK(sel), specifying, for example, bit line groups BLG0 and BLG1.

[0265] For each bit line BL constituting bit line group BLG0, among the threshold voltages of the group selection transistors GCT connected to that bit line BL, only the threshold voltage of transistor GCT0 is classified as type "1". The group selection word line GWL0 connected to these transistors GCT0 is designated as group selection word line GWL(sel). Furthermore, for each bit line BL constituting bit line group BLG1, among the threshold voltages of the group selection transistors GCT connected to that bit line BL, only the threshold voltage of transistor GCT1 is classified as type "1". The group selection word line GWL1 connected to these transistors GCT1 is also designated as group selection word line GWL(sel). The remaining group selection word lines GWL are designated as group selection word line GWL(usel).

[0266] and Figure 18Similar to the previous example, a voltage VH is applied to the group select word lines GWL0 and GWL1, which are group select word lines GWL(sel). On the other hand, a voltage VL is applied to the other group select word lines GWL. Thus, data can be read from this block BLK(sel) via bit line groups BLG0 and BLG1. Data can also be read from other blocks BLK(sel) that can be read in parallel, in units of one or more bit line groups BLG that do not include either bit line groups BLG0 or BLG1.

[0267] [Effect]

[0268] The memory cell array 10 of the semiconductor memory device 1 of the first embodiment has bit lines BL0 to BL(m-1) that are included in any of the multiple bit line groups BLG.

[0269] Figure 7 and Figure 8 In the example, for each bit line BL constituting a bit line group BLG, the threshold voltage of the group selection transistor GCT connected to that bit line BL is as follows: The threshold voltage of the group selection transistor GCT connected to a group selection word line GWL is classified as type "1". The threshold voltages of the group selection transistor GCTs connected to other group selection word lines GWL are classified as type "0". This applies to any bit line group BLG, but if the bit line group BLG is different, the group selection word line GWL will also be different.

[0270] Semiconductor memory device 1 is capable of reading data stored in a select memory cell transistor (MCT) connected to a bit line group (BLG) during a read operation targeting a certain block (BLK(sel)). More specifically, the following applies.

[0271] Figure 17 In the example, from time T11 to time T12, the semiconductor memory device 1 applies voltages to each group select word line GWL associated with the block BLK(sel) in the following manner: The semiconductor memory device 1 applies voltage VH to the group select word line GWL(sel) and voltage VL to the other group select word lines GWL(usel).

[0272] For each bit line BL constituting the bit line group BLG(sel), the group selection transistor GCT connected to the bit line BL is connected to any group selection word line GWL in the following manner: Group selection transistor GCTs with a threshold voltage classified as type "1" are connected to the group selection word line GWL(sel). Group selection transistor GCTs with a threshold voltage classified as type "0" are connected to the group selection word line GWL(usel).

[0273] As described above, when a voltage is applied to each group select word line GWL, a voltage is applied to the gate of each group select transistor GCT connected to that bit line BL in the following manner: For the gate of the transistor GCT classified as type "1" with a threshold voltage, a voltage VH higher than that threshold voltage is applied via the group select word line GWL(sel). For the gates of the other transistor GCTs classified as type "0" with a threshold voltage, a voltage VL higher than these threshold voltages is supplied via the other group select word lines GWL(usel). As a result, all group select transistors GCT connected to that bit line BL are turned on. Consequently, the sense amplifier circuit SA connected to that bit line BL can, for example, read out the data stored in the select memory cell transistor MCT by sensing the current flowing through that bit line BL.

[0274] On the other hand, the individual lines of the other line groups BLG are as follows.

[0275] When a voltage is applied to each group select word line GWL as described above, a voltage VL lower than the threshold voltage is applied to the gate of the group select transistor GCT, which is classified as type "1" and connected to the bit line BL, via the group select word line GWL(usel). As a result, the group select transistor GCT becomes off. Consequently, even if the memory cell transistor MCT connected to the bit line BL and the select word line WL(sel) becomes on, the on state of the memory cell transistor MCT will not affect the current flowing through the bit line BL.

[0276] Thus, semiconductor memory device 1 can perform read operations targeting the block BLK(sel) on a unit basis, using bit line groups (BLG). See reference... Figure 9 As explained, the number of bit line groups BLGs that can be used as group selection word lines GWL in the word line WL associated with the block BLK(sel) is the same as the number of bit line groups BLGs. If more bit line groups BLGs are constructed, each bit line group BLG can be composed of fewer bit lines BL. When each bit line group BLG is composed of fewer bit lines BL, the read operation is performed in units of fewer bit lines BL, and smaller data is read through this read operation.

[0277] Therefore, according to the semiconductor memory device 1 of the first embodiment, when the required data size is small, data can be read in units of the required data size without reading out excess data. This enables data to be accessed in units of, for example, tens of bits as required in graphics databases, etc. For example, when reading data containing excess data, excess data is also transmitted between the semiconductor memory device and the memory controller, thereby causing a delay in the transmission of the required data, and furthermore, a portion of the memory interface between the semiconductor memory device and the memory controller may be occupied. According to the semiconductor memory device 1 of the first embodiment, data can be read in units of the required data size, so the transmission of the required data will not cause a delay, and furthermore, a portion of the memory interface will not be occupied. The data reading can be achieved by a simple control, that is, applying a voltage VH to only one group select word line GWL of the block BLK(sel) associated with the block to be read, and applying a voltage VL to the other group select word lines GWL.

[0278] As described above, reading data from a certain block BLK(sel) in units of a certain bit line group BLG(sel) will not affect the current flowing through each bit line BL in other bit line groups BLG. This means that semiconductor memory device 1 can read data from other blocks BLK in units of other bit line groups BLG. Therefore, as referred to Figure 14 and Figure 16 As explained, the semiconductor memory device 1 can read data in parallel from multiple blocks BLK via different bit line groups BLG.

[0279] Therefore, the semiconductor memory device 1 according to the first embodiment can improve the access speed for random reads, thereby improving the efficiency of moving the required data. Thus, it is unnecessary for the semiconductor memory device to temporarily read and sort the data before writing it back to the database in order to improve the efficiency of moving the data stored in the database. Such rewriting would lead to degradation of the characteristics and access performance of the semiconductor memory device. Therefore, according to the semiconductor memory device 1, such degradation of characteristics and access performance can be prevented.

[0280] Furthermore, when the semiconductor memory device 1 receives an instruction to perform a write operation in TLC mode, as referred to Figure 6 As explained, write operations can be performed using QLC control. Therefore, the ratio of the overlapping portions of each threshold voltage distribution with adjacent threshold voltage distributions on the graph is smaller compared to the case where QLC control is not used. Consequently, the bit error rate is reduced when the semiconductor memory device 1 performs a read operation.

[0281] For example, when a semiconductor memory device maintains the ratio of error correction codes in the data DAT and performs read operations in units of fewer bit lines BL, the frequency of read operations increases, thereby increasing the frequency of error correction processing failures using the ECC circuit. Consequently, the frequency of retry reads by the semiconductor memory device also increases. However, according to the semiconductor memory device 1 of the first embodiment, the bit error rate is reduced as described above, thus reducing the frequency of error correction processing failures. Therefore, according to the semiconductor memory device 1, even when the semiconductor memory device 1 maintains the ratio of error correction codes in the data DAT and performs read operations in units of fewer bit lines BL, the frequency of retry reads can be maintained without increasing.

[0282] Furthermore, the description will focus on the memory controller 2 of the first embodiment. The memory controller 2 generates an instruction set for performing the read operation in the semiconductor memory device 1 and sends this instruction set to the semiconductor memory device 1. The semiconductor memory device 1 performs the read operation according to this instruction set. The memory controller 2, for example, refers to a host instruction received from the host device 4. Figure 15 The address information ADD1 contained in the instruction set is generated based on the logical-physical translation table shown. Address information ADD1, for example, specifies the plane PB, block BLK, serial group SU, word line WL, and multiple latch circuits XDL. That is, address information ADD1 specifies the region to be read in the same page unit as during a write operation. On the other hand, the memory controller 2 generates address information ADD2 based on the host instruction without referring to the logical-physical translation table. Address information ADD2, for example, specifies a bit group BLG of the unit executing the read operation. The semiconductor memory device 1 also performs the read operation based on address information ADD2, in units of that bit group BLG.

[0283] Thus, the memory controller 2 generates address information ADD2 for a bit line group (BLG) specifying the execution unit of the read operation without referring to a logical-physical translation table. For example, if the information representing the bit line group (BLG) is also obtained according to a logical-physical translation table, the capacity of the logical-physical translation table increases, and therefore, the time required for the memory controller to generate the address information for the read operation increases. However, according to the memory controller 2 of the first embodiment, as described above, the information representing the bit line group (BLG) is generated without referring to a logical-physical translation table. Therefore, the capacity of the logical-physical translation table is prevented from increasing, and the time required for the memory controller 2 to generate the address information for the read operation does not increase.

[0284] [Example of variation]

[0285] (1) Example of the first variation

[0286] The configuration of the driver component 19 and the line decoder module 12 is not limited to the reference. Figure 11 and Figure 12 The structure described herein. Other examples are described below. The following is for reference only. Figure 11 and Figure 12 The explanation focuses on different aspects of the speaker.

[0287] Figure 19 This is an example of the configuration of the driver assembly 19 and the line decoder module 12 of the semiconductor memory device 1, which represents a first variation of the first embodiment.

[0288] Driver assembly 19 includes driver circuits DC0 and DC2. Driver circuit DC0 is connected to voltage transmission circuits TC0 and TC1. Driver circuit DC2 is connected to voltage transmission circuits TC2 and TC3.

[0289] Figure 20 This section illustrates an example of the configuration of the driver circuit DC0 and voltage transmission circuits TC0 and TC1 in the semiconductor memory device 1 of the first embodiment, representing a first variation of the first embodiment. Hereinafter, the driver circuit DC0 and voltage transmission circuits TC0 and TC1 will be described, but the same description applies to, for example, the driver circuit DC2 and voltage transmission circuits TC2 and TC3.

[0290] The driver circuit DC0 and the voltage transmission circuit TC0 are as follows: Figure 12 As explained, the connections are via wiring CG0-CG95, CXD0-CXD3, and CXS. The voltage transmission circuit TC0 and block BLK0 are as described in the reference. Figure 12 As explained, the connection is made via word lines WL0 to WL95 and select gate lines SGD0 to SGD3 and SGS.

[0291] Voltage transmission circuit TC1 as referenced Figure 12As described, it has the same configuration as the voltage transmission circuit TC0. More specifically, the voltage transmission circuit TC1 includes a block decoder BD1 and a transistor group TG1. The transistor group TG1 includes transistors TWTr0, TWTr1, ..., TWTr95, TDTr0, TDTr1, TDTr2, TDTr3, and TTr. The output of the block decoder BD1 is connected to the gates of each of the transistors TWTr0, TWTr1, ..., TWTr95, TDTr0, TDTr1, TDTr2, TDTr3, and TTr in the transistor group TG1. The connection relationship between the driver circuit DC0 and the voltage transmission circuit TC1 will be explained below, focusing on each transistor in the transistor group TG1. The voltage transmission circuit TC1 is connected to various wiring connected to the driver circuit DC0 in the following manner. Furthermore, the connection relationship between the voltage transmission circuit TC1 and the block BLK1 is as follows, and reference... Figure 12 The same explanation applies to the connection between the voltage transmission circuit TC0 and the block BLK0.

[0292] Terminal 1 of transistor TWTr0 is connected to wiring CG0. Terminal 1 of transistor TWTr1 is connected to wiring CG1. The same applies below; terminal 1 of transistor TWTr95 is connected to wiring CG95. Terminal 1 of transistor TDTr0 is connected to wiring CXD0. Terminal 1 of transistor TDTr1 is connected to wiring CXD1. The same applies below; terminal 1 of transistor TDTr3 is connected to wiring CXD3. Terminal 1 of transistor TSTr is connected to wiring CXS.

[0293] When the block address in address information ADD1 specifies either block BLK0 or BLK1, driver circuit DC0 transmits a voltage from the voltage supplied to driver assembly 19 to each wiring CG0-CG95, CXD0-CXD3, and CXS connected to driver circuit DC, for example, based on the page address and string address in address information ADD1. Driver circuit DC0 may also perform this transmission based on address information ADD2 during read operations.

[0294] Each voltage transmission circuit TC0 and TC1 can electrically connect the wiring CG0~CG95, CXD0~CXD3, and CXS to the word lines WL0~WL95 and the select gate lines SGD0~SGD3 and SGS connected to the voltage transmission circuit TC, respectively, to establish corresponding wiring. This electrical connection is as follows: Figure 12As explained, this is based on the decoding result of the block address by the block decoder BD contained in the voltage transmission circuits TC0 and TC1. Through this electrical connection, the voltage transmitted to the wirings CG0-CG95, CXD0-CXD3, and CXS by the driver circuit DC0 is respectively transmitted to one of the blocks BLK0 and BLK1.

[0295] Figure 19 and Figure 20 In the example, semiconductor memory device 1 can also perform read operations targeting each block BLK, with bit line group (BLG) as the unit. Figure 19 and Figure 20 In the example, such as referring to Figure 16 As explained, the semiconductor memory device 1 can read data in parallel from any block BLK in blocks BLK0 and BLK1, and from any block BLK in blocks BLK2 and BLK3. Figure 19 and Figure 20 In this example, multiple blocks BLK that do not read data in parallel are each connected to the same driver circuit DC via a voltage transmission circuit TC. According to the first variation of the first embodiment, the semiconductor memory device 1 can reduce the circuit size by reducing the number of driver circuits DC in this way.

[0296] (2) Second variation example

[0297] In the above, the semiconductor memory device 1 can also be executed in units of bit line groups (BLGs). Figure 2 The read operation targeting any block BLK in the plane PB shown has been described. Hereinafter, the case where the semiconductor memory device 1 performs a read operation targeting a block BLK in the plane PB without using bit line groups BLG as units will be described.

[0298] Figure 21 This is an example of the configuration of the driver assembly 19 and the line decoder module 12 of the semiconductor memory device 1, which represents a second variation of the first embodiment.

[0299] Driver assembly 19 includes driver circuits DC0, DC1, DC2, ..., and DCs (s is an integer greater than or equal to 1 and less than n). Line decoder module 12 and... Figure 11 The example is the same, including voltage transmission circuits TC0, TC1, TC2, ..., and TC(n-1). Voltage transmission circuits TC0, TC1, TC2, ..., and TC(n-1) are respectively established in a one-to-one correspondence with blocks BLK0, BLK1, BLK2, ..., and BLK(n-1) in the order described.

[0300] The following is for reference Figure 11 and Figure 12The explanation focuses on different aspects of the speaker.

[0301] Driver circuit DCs and reference Figure 19 and Figure 20 The same applies to the voltage transfer circuits TCs, TC(s+1), TC(s+2), ..., and TC(n-1). Each voltage transfer circuit TC is described in reference... Figure 11 As explained, the block BLK is connected to and corresponds to the voltage transmission circuit TC.

[0302] For each block BLK in blocks BLK0, BLK1, BLK2, ..., and BLK(s-1), refer to... Figure 7 The explanation given is valid.

[0303] For each block BLK in blocks BLKs, BLK(s+1), BLK(s+2), ..., and BLK(n-1), the following statement holds true. The word lines WL associated with this block BLK are not considered as references. Figure 7 The group select word line GWL is used as described, and the cell transistors CT in this block BLK are not used as group select transistors GCT.

[0304] Figure 21 In the example, the semiconductor memory device 1 can perform a read operation targeting each block BLK0 to BLK(s-1) in units of bit line groups BLG, and thus can read data from multiple blocks BLK in parallel. Figure 21 In, with Figure 16 The example similarly illustrates the case of reading data in parallel from multiple block BLKs in these block BLKs.

[0305] Figure 21 In the example, for each block BLKs~BLK(n-1), a readout operation targeting that block BLK is performed on a page-by-page basis via bit lines BL0~BL(m-1). During this readout operation, for example, the sense amplifier group SAU corresponding to each bit line BL0~BL(m-1) is activated.

[0306] In addition, for blocks BLK0 to BLK(s-1) that are read out in units of bit line groups BLG, as explained in the first variation example, multiple blocks BLK that do not read out data in parallel can also be connected to the same driver circuit DC via voltage transmission circuit TC.

[0307] <Second Implementation>

[0308] Hereinafter, the semiconductor memory device 1a according to the second embodiment will be described.

[0309] The symbol 1a is used to distinguish it from the semiconductor memory device 1a of the first embodiment, but the configuration of the semiconductor memory device 1a is the same as that of the semiconductor memory device 1 of the first embodiment, except for the aspects described below.

[0310] Semiconductor memory device 1a is the same as semiconductor memory device 1 in the first embodiment, and is capable of performing operations in units of bit line groups (BLGs). Figure 2 The read operation targets a certain block BLK of the plane PB shown. Hereinafter, the following explanation will address the following situation: Similar to the semiconductor memory device 1 of the first embodiment, semiconductor memory device 1a can also perform read operations on a unit of bit line groups (BLGs) when targeting any block BLK of the plane PB. Hereinafter, the explanation will be given using one block BLK of the plane PB as an example. The following explanation applies to other blocks BLK of the plane PB. Figure 7 Similarly, by setting the threshold voltage of each group select transistor (GCT) connected to the multiple group select word lines (GWL) associated with the block BLK, readout operations can be performed in units of bit line groups (BLG).

[0311] Figure 22 This table shows an example of the threshold voltage settings of each group selection transistor (GCT) in a certain string group SU of the semiconductor memory device 1a of the second embodiment BLK. Hereinafter, this string group SU will be used as an example for explanation; the following explanation also applies to other string groups SU of the same BLK. Hereinafter, the case where bit lines BL0 to BL(m-1) constitute 35 bit line groups BLG will be used as an example for explanation, but the number of bit line groups BLG formed by bit lines BL0 to BL(m-1) is not limited to 35.

[0312] and Figure 7 Similar to the previous example, the group selection word lines GWL0 to GWL6 are defined. Furthermore, with... Figure 7 Similar to the previous example, for each bit line BL0 to BL(m-1), the group selection transistors GCT0 to GCT6 in the unit transistor CT connected to that bit line BL are defined.

[0313] In the table, with Figure 8 Similar to the table, for each bit line group BLG, the threshold voltage settings of the group selection transistors GCT associated with the bit line BL constituting the bit line group BLG are shown.

[0314] For each bit line BL constituting bit line group BLG0, the group selection transistor GCT associated with that bit line BL satisfies the following condition: among the threshold voltages of the group selection transistor GCT connected to that bit line BL, the threshold voltages of transistors GCT0, GCT1, and GCT2 are classified as type "1", and the threshold voltages of the other transistors GCT3 to GCT6 are classified as type "0".

[0315] Similarly, for each bit line BL constituting bit line group BLG1, the threshold voltages of the group selection transistors GCT connected to that bit line BL, specifically transistors GCT0, GCT1, and GCT3, are classified as type "1". Furthermore, for each bit line BL constituting bit line group BLG2, the threshold voltages of the group selection transistors GCT connected to that bit line BL, specifically transistors GCT0, GCT1, and GCT4, are classified as type "1". Furthermore, for each bit line BL constituting bit line group BLG3, the threshold voltages of the group selection transistors GCT connected to that bit line BL, specifically transistors GCT0, GCT1, and GCT5, are classified as type "1". Furthermore, for each bit line BL constituting bit line group BLG4, the threshold voltages of the group selection transistors GCT connected to that bit line BL, specifically transistors GCT0, GCT1, and GCT6, are classified as type "1". The same applies below. Figure 22 The table is shown.

[0316] The above explains that for each bit line BL0 to BL(m-1), seven of the cell transistors CT connected to the bit line BL function as group selection transistors (GCTs). The remaining cell transistors CT connected to the bit line BL function as memory cell transistors (MCTs).

[0317] Next, we will explain how many bit line groups BLG can be formed by the bit lines BL0 to BL(m-1) based on the number of word lines WL used as group selection word lines GWL in the word lines WL related to a certain block BLK.

[0318] Figure 22 In the example, for each bit line BL constituting a bit line group BLG, the threshold voltages of the group selection transistors GCTs connected to that bit line BL are classified as type "1" for the group selection transistors GCTs connected to three group selection word lines GWL respectively, and the threshold voltages of the other transistors GCTs are classified as type "0". This holds true for any bit line group BLG, but if the bit line group BLG is different, the combination of the three group selection word lines GWL will also be different. Thus, Figure 22 In the example, the bit line group BLG is paired with the three group select word lines GWL in a one-to-one correspondence. Figure 22In the example, the corresponding number of bit line groups (BLGs) can be constructed in such a way. That is, the number of bit line groups (BLGs) that can be constructed to select 3 words from 7 group selection word lines (GWLs).

[0319] Thus, if 2t (t is an integer greater than or equal to 1) word lines WL related to a certain block BLK are used as group selection word lines GWL, consider the following quantities as the number of bit line groups BLG that can be formed by bit lines BL0 to BL(m-1). In the following explanation, the total number of combinations of selecting i words from h distinct words will be used. h Represented as C i i is an integer greater than or equal to 1, and h is an integer greater than or equal to i.

[0320] The number of ways to select one word line from 2t groups and choose 1 from GWL is: 2t C1, the number of combinations of selecting 2 word lines from 2t groups (GWL) is: 2t C2, the number of combinations of selecting 3 word lines from 2t groups (GWL) is: 2t C3, similarly, has a quantity of 2t C4 2t C5 2t C6 2t C7、····

[0321] The largest of these quantities is 2t C t That is, if 2t word lines WL related to a certain block BLK are used as group selection word lines GWL, then the bit lines BL0 to BL(m-1) can constitute a maximum of 2t C t Individual line group BLG.

[0322] Similarly, if (2t+1) word lines WL related to a certain block BLK are used as group selection word lines GWL, consider the following number as the number of bit line groups BLG that can be formed by bit lines BL0~BL(m-1).

[0323] The number of ways to select 1 word line from (2t+1) groups using the GGL method is: 2t+1 C1, the number of combinations of selecting 2 word lines from (2t+1) groups using the GWL is: 2t+1 C2, the number of combinations of selecting 3 word lines from (2t+1) groups using the GWL is: 2t+1 C3, similarly, has a quantity of 2t+1 C4 2t+1 C5 2t+1 C6 2t+1 C7、····

[0324] The largest of these quantities is 2t+1 C t and 2t+1 C t+1 That is, if (2t+1) word lines WL related to a certain block BLK are used as group selection word lines GWL, then the bit lines BL0~BL(m-1) can constitute a maximum of 2t+1 C t and 2t+ 1C t+1 Individual line group BLG.

[0325] Figure 23 The table shows the number of group select word lines GWL associated with a certain block BLK of the memory cell array 10 of the semiconductor memory device 1a according to the second embodiment, and how many bit line groups BLG can be formed by bit lines BL0 to BL(m-1).

[0326] When the number of group selection word lines (GWLs) is 2t, the number of bit line groups (BLGs) that can be constructed from the 2t group selection word lines (GWLs) and select t words is represented by the number of combinations. Therefore, it indicates that the number of combinations that can be constructed is... 2t C t Individual line group BLG.

[0327] When the number of group selection word lines (GWLs) is (2t+1), the number of bit line groups (BLGs) that can be constructed from the (2t+1) group selection word lines (GWLs) is expressed as: Therefore, it represents the number of ways to construct... 2t+1 C t Individual line group BLG.

[0328] The table shows that with 7 group select word lines (GWL), 35 bit line groups (BLG) can be formed. This corresponds to... Figure 22 Example.

[0329] Next, the operation of the semiconductor memory device 1a is the same as that of the semiconductor memory device 1 in the first embodiment, except for the aspects described below.

[0330] Reference Figure 22 The description of reading data from block BLK in units of bit line group BLG is based on a reference. Figure 17 The method described is as follows. In the semiconductor memory device 1a of the second embodiment, there are three group select word lines GWL(sel) associated with the block BLK(sel). The combination of these three group select word lines GWL(sel) is as described in the reference. Figure 22 The description refers to the combination of three group select word lines GWL corresponding to the bit line group BLG(sel).

[0331] The application of voltage to the select word lines GWL associated with each group of BLK(sel) when reading data from the block BLK(sel) in units of bit line group BLG1 is explained.

[0332] Group select word lines GWL0, GWL1, and GWL3 are group select word lines GWL(sel). On the other hand, other group select word lines GWL are group select word lines GWL(usel). Therefore, in Figure 17 In the example, from time T11 to time T12, voltage VH is applied to group select word lines GWL0, GWL1, and GWL3, and voltage VL is applied to other group select word lines GWL.

[0333] The following explanation focuses on a specific bit line BL in bit line group BLG1, but the explanation also applies to other bit lines BL in bit line group BLG1.

[0334] When a voltage is applied to the group select word line GWL as described above, the gates of each group select transistor GCT connected to the bit line BL are voltaged as follows: For the gates of transistors GCT0, GCT1, and GCT3, which have a threshold voltage classified as type "1", a voltage VH higher than these threshold voltages is applied via the group select word lines GWL0, GWL1, and GWL3, respectively. For the gates of other transistors GCT, which have a threshold voltage classified as type "0", a voltage VL higher than these threshold voltages is applied via the other group select word lines GWL, respectively.

[0335] Therefore, all group selection transistors (GCTs) connected to the bit line BL are turned on. As a result, the sense amplifier circuit SA connected to the bit line BL can read the data stored in the select memory cell transistor (MCT) by sensing the current flowing through the bit line BL.

[0336] On the other hand, the same applies to other bit line groups (BLG). The following explanation uses a bit line BL from bit line group BLG0 as an example. The same explanation applies to other bit lines BL from bit line groups other than BLG1.

[0337] When a voltage is applied to the group select word line GWL as described above, a voltage VL is applied to the gate of the group select transistor GCT2, which is connected to the bit line BL, via the group select word line GWL2. The threshold voltage of the group select transistor GCT2 is classified as type "1", which is higher than the voltage VL.

[0338] Therefore, the group selection transistor GCT2 is in the off state. As a result, even if the memory cell transistor MCT connected to the bit line BL and the select word line WL(sel) is turned on, the on state of the memory cell transistor MCT will not affect the current flowing through the bit line BL.

[0339] In this way, data can be read from the block BLK(sel) in units of bit line groups BLG1. This data reading does not affect the current flowing through the bit lines BL in other bit line groups BLG. This means that the semiconductor memory device 1a can read data from other blocks BLK in units of other bit line groups BLG. Therefore, as referred to... Figure 14 and Figure 16 As explained, the semiconductor memory device 1a can read data in parallel from multiple blocks BLK via different bit line groups BLG.

[0340] According to the semiconductor memory device 1a of the second embodiment, as described for the semiconductor memory device 1 of the first embodiment, data can be read out in units of the required data size, and the efficiency of moving the required data can be improved. The semiconductor memory device 1a of the second embodiment also exhibits the following effects.

[0341] In the semiconductor memory device 1 of the first embodiment, as referred to Figure 7 As explained, in order to form 32 bit line groups BLG by bit lines BL0 to BL(m-1), 32 word lines WL in the word lines WL related to a certain block BLK are used as group selection word lines GWL. In contrast, in the semiconductor memory device 1a of the second embodiment, as referred to... Figure 22 As explained, in order to form 35 bit line groups BLG from bit lines BL0 to BL(m-1), 7 word lines WL related to a certain block BLK are used as group selection word lines GWL. That is, in semiconductor memory device 1a, with... Figure 7 The example uses fewer group select word lines (GWL) but constitutes a larger number of bit line groups (BLG).

[0342] Therefore, according to the semiconductor memory device 1a of the second embodiment, compared with the semiconductor memory device 1 of the first embodiment, by providing the same number of bit line groups BLG in a certain plane PB, data can be read out in units of the same size, and the number of unit transistors CT used as memory unit transistors MCT can be increased.

[0343] <Other Implementation Methods>

[0344] In this specification, "connection" means electrical connection, which may include other components in between.

[0345] In this specification, expressions such as "same," "consistent," "certain," and "maintain" are used because they acknowledge and include the possibility of design-related errors when implementing the technology described in the embodiments. The same applies when the term "substantially" is used repeatedly in these expressions, such as as "substantially the same." Furthermore, the expression "apply or supply a voltage" is used because it encompasses both controlling the application or supply of that voltage and actually applying or supplying it. Moreover, applying or supplying a voltage may, for example, include applying or supplying a voltage of 0V.

[0346] Several embodiments have been described herein, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention as described in the claims and its equivalents.

[0347] [Explanation of Symbols]

[0348] 1. Semiconductor memory device

[0349] 10 Memory Cell Array

[0350] 11 Sensing Amplifier Module

[0351] 12-line decoder module

[0352] 13 Input / Output Circuits

[0353] 14 Registers

[0354] 141 Status Register

[0355] 142 Address Register

[0356] 143 Instruction Register

[0357] 15. Logic Control Circuit

[0358] 16 Sequencers

[0359] 17 Ready / Busy Control Circuit

[0360] 18 Voltage Generation Circuit

[0361] 19. Driver Components

[0362] 2. Memory controller

[0363] 21 Host Interface Circuit

[0364] 22 CPU

[0365] 23 RAM

[0366] 231 Data Buffer

[0367] 24 ROM

[0368] 25. Memory Interface Circuit

[0369] 26 ECC Circuit

[0370] 3. Memory System

[0371] 4. Main unit

[0372] 40 Semiconductor substrate

[0373] 41, 42, 49 Conductors

[0374] 43 memory cylinders

[0375] 44 Semiconductors

[0376] 45 Tunnel insulation layer

[0377] 46 Charge storage layer

[0378] 47 Block Insulation Layer

[0379] 48 Contact plug

[0380] PB plane

[0381] BLK Block

[0382] SU Serial Group

[0383] NS NAND string

[0384] CU unit group

[0385] BL bitline

[0386] WL lettering

[0387] SGD, SGS Select Gate Line

[0388] SL source line

[0389] CT unit transistor

[0390] ST Select Transistor

[0391] LI conductor

[0392] BLG bitline group

[0393] GWL group select word line

[0394] GCT group selection transistor

[0395] MCT memory cell transistor

[0396] SAU Sensing Amplifier Group

[0397] SA Sensing Amplifier Circuit

[0398] XDL, ADL, BDL, CDL latch circuits

[0399] DBUS, XBUS buses

[0400] DC driver circuit

[0401] TC voltage transmission circuit

[0402] CG, CXD, CXS wiring

[0403] BD Block Decoder

[0404] TG transistor group

[0405] TDTr, TWTr, TTr transistors

[0406] CXDdrv, CGdrv, CXSdrv drivers.

Claims

1. A semiconductor memory device comprising: Memory cell array; and The control circuit is configured to receive a first instruction for performing a read operation and first address information specifying one or more bit line groups; according to the first instruction, read first data from the memory cell array via the one or more bit line groups, without via bit lines not included in the one or more bit line groups, and output the first data; wherein The control circuit is further configured to perform the following control during the write operation: the control is used to store data in each memory cell that is larger than the number of bits of data stored in each memory cell of the write target in the memory cell array.

2. The semiconductor memory device according to claim 1, wherein The first address information is received via an external terminal that is different from the external terminal used in receiving the first instruction.

3. The semiconductor memory device according to claim 1, wherein... The size of the first data is based on the number of bit lines contained in the one or more bit line groups.

4. The semiconductor memory device according to claim 1, wherein The control circuit is then configured to receive the second address information. The first data is read out based on the second address information.

5. The semiconductor memory device according to claim 1, wherein... The memory cell array comprises a first block and a second block on the same plane. The first data includes the second data read from the first block and the third data read from the second block.

6. The semiconductor memory device according to claim 5, wherein The control circuit is further configured to receive second address information specifying the first block and the second block. The first data is read out based on the second address information.

7. The semiconductor memory device according to claim 5, wherein The one or more bit line groups include a first bit line group and a second bit line group. The second data is read out via the first bit group without passing through the second bit group, and the third data is read out via the second bit group without passing through the first bit group.

8. The semiconductor memory device according to claim 5, wherein The period during which the second data is read overlaps at least partially with the period during which the third data is read.

9. The semiconductor memory device according to claim 5, wherein The control circuit includes: The first driver circuit supplies voltage to the first block for operation targeting the first block; and The second driver circuit supplies voltage to the second block for operation targeting the second block during the period when the first driver circuit supplies voltage to the first block.

10. The semiconductor memory device according to claim 1, wherein The memory cell array includes a first block. The semiconductor memory device further includes a first word line, a second word line, a third word line, and a fourth word line associated with the first block. The control circuit is further configured to read second data from the first block according to the first instruction, while applying a first voltage to the first word line, applying a second voltage higher than the first voltage to the second word line, applying a third voltage to the third word line, and applying a fourth voltage higher than the third voltage to the fourth word line. The second data is included in the first data.

11. The semiconductor memory device of claim 10, wherein... The second voltage is lower than the fourth voltage.

12. The semiconductor memory device according to claim 1, wherein The memory cell array includes a first block. The semiconductor memory device further includes multiple word lines associated with the first block and corresponding to multiple bit line groups, each established in a one-to-one manner. The first address information specifies the first bit group. The control circuit is further configured to, according to the first instruction, apply a first voltage to a first word line corresponding to the first bit line group among the plurality of word lines, and apply a second voltage different from the first voltage to the word lines other than the first word line among the plurality of word lines, while reading second data from the first block. The second data is included in the first data.

13. The semiconductor memory device according to claim 12, wherein The second data is read from the first block via the first bit line group, but not via bit lines not included in the first bit line group.

14. The semiconductor memory device according to claim 1, wherein The memory cell array includes a first block. The semiconductor memory device further includes multiple word lines associated with the first block and corresponding to multiple bit line groups, each established in a one-to-one manner. The first address information specifies the first bit group and the second bit group. The control circuit is further configured to, according to the first instruction, apply a first voltage to the first word line corresponding to the first bit line group and the second word line corresponding to the second bit line group among the plurality of word lines, and apply a second voltage lower than the first voltage to the word lines other than the first word line and the second word line among the plurality of word lines, while reading second data from the first block. The second data is included in the first data.

15. The semiconductor memory device of claim 14, wherein... The second data is read from the first block via the first bit line group and the second bit line group, without via bit lines not included in either the first bit line group or the second bit line group.

16. The semiconductor memory device according to claim 1, wherein The memory cell array includes a first block. The semiconductor memory device further includes multiple word lines corresponding to the multiple bit line groups associated with the first block. Each of the plurality of bit line groups corresponds to a number of word lines that is half the number of word lines in the plurality of word lines, or a number of word lines that is closest to that half number. For each bit line group among the plurality of bit line groups, the combination of word lines corresponding to that bit line group is different from the combination of word lines corresponding to other bit line groups among the plurality of bit line groups. The first address information specifies the first bit group. The control circuit is further configured to, according to the first instruction, apply a first voltage to the word lines that correspond to the first bit line group among the plurality of word lines, and apply a second voltage different from the first voltage to the word lines that do not correspond to the first bit line group among the plurality of word lines, while reading second data from the first block. The second data is included in the first data.

17. The semiconductor memory device of claim 16, wherein... The second data is read from the first block via the first bit line group, but not via bit lines not included in the first bit line group.

18. A system having: The semiconductor memory device according to claim 1; and The controller is configured to send the first instruction and the first address information to the semiconductor memory device, and to receive the first data.

19. The system of claim 18, wherein The controller is further configured to generate second address information based on a table for converting logical addresses to physical addresses, and send the second address information to the semiconductor memory device. The control circuit is then configured to receive the second address information. The first data is read out and then based on the second address information. The first address information is generated by the controller without relying on the table.

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