Preparation method of pin limiter based on silicon-based pin diode and pin limiter

Abstract

The application provides a preparation method of a PIN limiter based on a silicon-based PIN diode and the PIN limiter, and the method comprises the following steps: preparing a multistage PN junction on a silicon wafer substrate to obtain an N+ layer, a plurality of P+ layers and a plurality of I layer regions; preparing an upper electrode on the upper surface of each P+ layer; preparing a lower electrode on the lower surface of the N+ layer; preparing a first passivation layer on the upper surface of the N+ layer; etching a plurality of grooves to the N+ layer on the upper surface of the first passivation layer to prepare a plurality of ground pads based on the plurality of grooves; preparing an insulating dielectric layer on the upper surface of the first passivation layer; performing windowing on the upper surface of the insulating dielectric layer to form a plurality of openings; preparing a preset peripheral circuit on the upper surface of the insulating dielectric layer; and performing gold plating treatment in the plurality of openings to electrically connect the plurality of upper electrodes and the plurality of ground pads with the preset peripheral circuit. The single-chip preparation method is adopted, so that the prepared PIN limiter based on the silicon-based PIN diode is small in size and high in integration.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for fabricating a PIN limiter based on a silicon-based PIN diode and the PIN limiter itself. Background Technology

[0002] High-power microwaves, due to their high power and high frequency, cause significant interference and damage to electronic equipment, making the need for protection against high-power microwaves increasingly urgent.

[0003] PIN limiters are used for high-power microwave protection of electronic devices. Traditional PIN limiters using GaAs-based PIN diodes encounter bottlenecks in power handling. Silicon-based PIN diodes have high thermal conductivity and high voltage withstand capability; however, traditional silicon-based PIN diode-based PIN limiters use hybrid integration processes, resulting in large sizes and low integration density, which does not meet the miniaturization and high integration requirements of electronic devices. Therefore, there is an urgent need for a monolithic fabrication method for silicon-based PIN diode-based PIN limiters to reduce their size and improve their integration density. Summary of the Invention

[0004] This application provides a method for fabricating a PIN limiter based on a silicon-based PIN diode and a PIN limiter, which adopts a monolithic fabrication method to make the fabricated PIN limiter based on a silicon-based PIN diode small in size and highly integrated.

[0005] This application is achieved through the following technical solution:

[0006] In a first aspect, embodiments of this application provide a method for fabricating a PIN limiter based on a silicon-based PIN diode, comprising: fabricating a multi-level PN junction on a silicon wafer substrate to obtain an N+ layer, multiple P+ layers, and multiple I-layer regions corresponding to the multiple P+ layers; wherein each level of PN junction includes at least one PN junction; the multi-level PN junctions share a single N+ layer; the I-layer regions are located between the N+ layer and the P+ layer; fabricating an upper electrode on the upper surface of each P+ layer; thinning the lower surface of the N+ layer to a predetermined thickness and fabricating a lower electrode on the lower surface of the N+ layer; and fabricating multiple I-layer regions, multiple P+ layers, and multiple upper electrodes on the upper surface of the N+ layer. A first passivation layer is prepared in the region; multiple grooves are etched on the upper surface of the first passivation layer to the N+ layer, and multiple ground pads are prepared based on the multiple grooves; an insulating dielectric layer is prepared on the upper surface of the first passivation layer, covering the first passivation layer, multiple ground pads, multiple P+ layers, and multiple upper electrodes; a windowing process is performed at a predetermined position on the upper surface of the insulating dielectric layer to form multiple openings; the predetermined position is a position perpendicular to the multiple upper electrodes and multiple ground pads; a predetermined peripheral circuit is prepared on the upper surface of the insulating dielectric layer, and gold plating is performed in the multiple openings to electrically connect the multiple upper electrodes and multiple ground pads to the predetermined peripheral circuit.

[0007] In one possible implementation of the first aspect, a multi-level PN junction is fabricated on a silicon wafer substrate to obtain an N+ layer, multiple P+ layers, and multiple I-layer regions corresponding to the multiple P+ layers, comprising: performing N+ doping on the lower surface of the silicon wafer substrate to form an N+ layer; performing multiple P+ doping at different positions on the upper surface of the silicon wafer substrate to form multiple P+ layers with a first preset diameter; an I-layer is formed between the P+ layer and the N+ layer; the I-layer is etched to retain multiple I-layer regions under the multiple P+ layers, and the diameter of each I-layer region is a second preset diameter; the first preset diameter is larger than the second preset diameter.

[0008] In one possible implementation of the first aspect, an upper electrode is prepared on the upper surface of each P+ layer; the lower surface of the N+ layer is thinned to a preset thickness, and a lower electrode is prepared on the lower surface of the N+ layer, comprising: performing gold plating on the upper surface of each P+ layer to form an upper electrode; the corresponding first gold plating thickness is 1 to 5 μm; thinning the lower surface of the N+ layer to a preset thickness, and performing gold plating on the lower surface of the N+ layer to form a lower electrode; the corresponding second gold plating thickness is 0.8 to 3 μm.

[0009] In one possible implementation of the first aspect, multiple grounding pads are prepared based on multiple grooves, including: performing gold plating in the multiple grooves to form multiple grounding pads; the corresponding third gold plating thickness is 1 to 5 μm.

[0010] In one possible implementation of the first aspect, a windowing process is performed at a predetermined position on the upper surface of the insulating dielectric layer to form a plurality of openings, including: etching to the upper electrode or ground pad at the predetermined position on the upper surface of the insulating dielectric layer to form a plurality of openings.

[0011] In one possible implementation of the first aspect, the method for fabricating a PIN limiter based on a silicon-based PIN diode further includes: fabricating a second passivation layer on the upper surface of a preset peripheral circuit.

[0012] Secondly, embodiments of this application provide a PIN limiter, obtained by applying the fabrication method of a silicon-based PIN diode-based PIN limiter as described in any of the first aspects; the PIN limiter includes: a multi-level PN junction, the multi-level PN junction including an N+ layer of a predetermined thickness, multiple I-layer regions of a second predetermined diameter, and multiple P+ layers of a first predetermined diameter; multiple I-layer regions are disposed on the upper surface of the N+ layer and correspond to the multiple P+ layers respectively; multiple P+ layers are respectively disposed on the upper surface of the multiple I-layer regions; multiple upper electrodes are respectively disposed on the upper surface of the multiple P+ layers; and a lower electrode is disposed on the lower surface of the N+ layer. The structure includes: a first passivation layer disposed on the upper surface of the N+ layer, excluding the regions of multiple I layers, multiple P+ layers, and multiple upper electrodes; multiple ground pads, with multiple grooves etched into the N+ layer on the upper surface of the first passivation layer, each ground pad disposed in one of the grooves; an insulating dielectric layer disposed on the upper surface of the first passivation layer, covering the first passivation layer, multiple ground pads, multiple P+ layers, and multiple upper electrodes; multiple openings disposed at predetermined positions on the upper surface of the insulating dielectric layer, the predetermined positions being positions perpendicular to the multiple upper electrodes and multiple ground pads; and a predetermined peripheral circuit disposed on the upper surface of the insulating dielectric layer.

[0013] In conjunction with the second aspect, in some possible implementations, the PIN limiter further includes: a second passivation layer disposed on the upper surface of a preset peripheral circuit; the thickness of the second passivation layer is 0.5 to 2 μm.

[0014] In conjunction with the second aspect, in some possible implementations, the preset thickness is 100 μm, the thickness of the I layer region is 7–10 μm, the thickness of the first passivation layer is 0.5–2 μm, and the thickness of the insulating dielectric layer is 10 ± 1 μm.

[0015] In conjunction with the second aspect, in some possible implementations, the first preset diameter is larger than the second preset diameter; the first preset diameter is 50-100 μm, the diameter of the upper electrode is 5-50 μm, the diameter of the groove is 5-50 μm, and the diameter of the opening is 5-50 μm.

[0016] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0017] The beneficial effects of the embodiments in this application compared with the prior art are:

[0018] The method for fabricating a silicon-based PIN diode-based PIN limiter provided in this application adopts a monolithic fabrication approach. By fabricating multi-level PN junctions, upper and lower electrodes, ground pads, insulating dielectric layers, and preset peripheral circuits on the same silicon wafer substrate, and by performing windowing and gold plating, the upper electrode and ground pads can be electrically connected to the preset peripheral circuits, thereby obtaining a silicon-based PIN diode-based PIN limiter. This method can reduce the size of the PIN limiter, improve its integration, and the fabrication method is simple and easy to implement.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a cross-sectional view of a PIN limiter provided in an embodiment of this application;

[0022] Figure 2 This is a top view of multiple P+ layers, multiple upper electrodes, and multiple ground pads provided in an embodiment of this application;

[0023] Figure 3 This is a schematic flowchart of a method for fabricating a PIN limiter based on a silicon-based PIN diode according to an embodiment of this application;

[0024] Figure 4 This is a cross-sectional view of a PIN limiter after the grounding pad is fabricated, according to an embodiment of this application.

[0025] Figure 5 This is a cross-sectional view of a PIN limiter after the hole has been prepared, according to an embodiment of this application. Detailed Implementation

[0026] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0027] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0028] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0029] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0030] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0032] Furthermore, the term "multiple" mentioned in the embodiments of this application should be interpreted as two or more.

[0033] Figure 1 This is a cross-sectional view of a PIN limiter provided in an embodiment of this application. Figure 2 This is a top view of multiple P+ layers, multiple top electrodes, and multiple ground pads provided in an embodiment of this application. (See attached image.) Figure 1 As shown, this PIN limiter is obtained using a method for fabricating a PIN limiter based on a silicon-based PIN diode, including:

[0034] A multi-level PN junction includes an N+ layer 1 of a preset thickness, multiple I-layer regions 2 of a second preset diameter, and multiple P+ layers 3 of a first preset diameter; the multiple I-layer regions 2 are disposed on the upper surface of the N+ layer 1 and correspond to the multiple P+ layers 3 respectively; the multiple P+ layers 3 are disposed on the upper surface of the multiple I-layer regions 2 respectively.

[0035] Multiple upper electrodes 4 are respectively disposed on the upper surface of multiple P+ layers 3.

[0036] The lower electrode 5 is disposed on the lower surface of the N+ layer 1.

[0037] The first passivation layer 6 is disposed on the upper surface of the N+ layer 1, excluding the regions of multiple I layer regions 2, multiple P+ layers 3 and multiple upper electrodes 4.

[0038] Multiple grounding pads 7, and multiple grooves are etched on the upper surface of the first passivation layer 6 to the N+ layer 1, with each grounding pad 7 disposed in each groove.

[0039] An insulating dielectric layer 8 is disposed on the upper surface of the first passivation layer 6, covering the first passivation layer 6, multiple grounding pads 7, multiple P+ layers 3, and multiple upper electrodes 4. Multiple openings are provided at predetermined positions on the upper surface of the insulating dielectric layer 8, the predetermined positions being positions perpendicular to the multiple upper electrodes 4 and the multiple grounding pads 7.

[0040] The pre-set peripheral circuit 9 is located on the upper surface of the insulating dielectric layer 8.

[0041] Each PN junction level includes at least one PN junction, and multiple PN junction levels share an N+ layer 1. The first preset diameter is larger than the second preset diameter, and based on... Figure 1 and Figure 2 As shown, the projection area of ​​layer P+3 in the vertical direction includes the projection area of ​​layer I region 2 in the vertical direction.

[0042] Optionally, the above-described method for fabricating a silicon-based PIN diode-based PIN limiter can be any of the methods described in the later embodiments of this application for fabricating a silicon-based PIN diode-based PIN limiter.

[0043] For example, the preset thickness is 100 μm, the thickness of layer 2 is 7–10 μm, the thickness of the first passivation layer 6 is 0.5–2 μm, and the thickness of the insulating dielectric layer 8 is 10 ± 1 μm. The preset diameter is 50–100 μm, the diameter of the upper electrode 4 is 5–50 μm, the diameter of the groove is 5–50 μm, and the diameter of the opening is 5–50 μm.

[0044] Optionally, the PIN limiter may also include: a second passivation layer (not shown) disposed on the upper surface of the preset peripheral circuit 9; the thickness of the second passivation layer is 0.5 to 2 μm.

[0045] It should be noted that there are no specific limitations on the thickness and diameter mentioned above, and they can be set according to specific needs.

[0046] The following combination Figure 1 The fabrication method of the silicon-based PIN diode-based PIN limiter according to the embodiments of this application will be described in detail.

[0047] Figure 3 This is a schematic flowchart illustrating a method for fabricating a PIN limiter based on a silicon-based PIN diode according to an embodiment of this application. (Refer to...) Figure 3 The method is described in detail below:

[0048] Step 101: Prepare a multi-level PN junction on a silicon wafer substrate to obtain an N+ layer, multiple P+ layers, and multiple I-layer regions corresponding to the multiple P+ layers.

[0049] Each PN junction includes at least one PN junction, and multiple PN junctions share an N+ layer. The I layer region is located between the N+ layer and the P+ layer.

[0050] In one possible implementation, step 101 may specifically include:

[0051] N+ doping is performed on the lower surface of a silicon wafer substrate to form an N+ layer.

[0052] Multiple P+ doping is performed at different locations on the upper surface of a silicon wafer substrate to form multiple P+ layers with a first predetermined diameter.

[0053] The space between the P+ layer and the N+ layer is the I layer. The I layer is etched to preserve multiple I layer regions under multiple P+ layers. The diameter of each I layer region is a second preset diameter, and the first preset diameter is larger than the second preset diameter.

[0054] For example, N+ doping is performed on the lower surface of a silicon wafer substrate using carrier injection to obtain an N+ layer, and P+ doping is performed at different positions on the upper surface of the silicon wafer substrate using carrier injection to obtain multiple P+ layers. The carriers injected during P+ doping and N+ doping are different, and the lifetime of the carriers is less than or equal to 100 ns.

[0055] Between the P+ layer and the N+ layer lies the I layer, which is the undoped region. The I layer is etched to retain multiple I-layer regions beneath the multiple P+ layers, thereby reducing the junction capacitance of the final fabricated PN junction. The aforementioned N+ layer, multiple P+ layers, and the corresponding I-layer regions constitute multiple PN junctions. These multiple PN junctions can be divided into multi-level PN junctions based on the position of the P+ layers, with each level including at least one PN junction, which can be configured according to specific needs. For example, a two-stage PIN limiter includes two levels of PN junctions, where the first level can have three PN junctions and the second level can have one PN junction.

[0056] Optionally, a silicon wafer substrate with high thermal conductivity can be used to prepare the PN junction, so that the prepared PN junction has good heat dissipation characteristics.

[0057] For example, the first preset diameter of the P+ layer can be 50 to 100 μm, which is larger than the second preset diameter of the I layer region. The thickness of the I layer can be 7 to 10 μm, that is, the thickness of the I layer region can be 7 to 10 μm.

[0058] Step 102: Prepare an upper electrode on the upper surface of each P+ layer; thin the lower surface of the N+ layer to a preset thickness, and prepare a lower electrode on the lower surface of the N+ layer.

[0059] In one possible implementation, step 102 may specifically include:

[0060] Gold plating is performed on the upper surface of each P+ layer to form the upper electrode. The corresponding first gold plating thickness is 1–5 μm.

[0061] The lower surface of the N+ layer is thinned to a predetermined thickness, and then gold plating is performed on the lower surface of the N+ layer to form the lower electrode. The corresponding second gold plating thickness is 0.8–3 μm.

[0062] For example, the diameter of the upper electrode can be 5–50 μm. The preset thickness can be 100 μm. Thinning the N+ layer can reduce the forward voltage drop of the prepared PN junction and increase the current density.

[0063] Step 103: Prepare a first passivation layer on the upper surface of the N+ layer, excluding the regions of multiple I layers, multiple P+ layers, and multiple upper electrodes; etch multiple grooves to the N+ layer on the upper surface of the first passivation layer, and prepare multiple grounding pads based on the multiple grooves.

[0064] Figure 4 This is a cross-sectional view of a PIN limiter after fabrication of a grounding pad, according to an embodiment of this application. (Refer to...) Figure 4 Optionally, a first passivation layer 6 can be prepared on the upper surface of the N+ layer 1, excluding the regions of multiple I-layers 2, multiple P+ layers 3 and multiple upper electrodes 4, by means of thermal oxidation growth or chemical deposition for protection. The thickness of the first passivation layer 6 can be 0.5 to 2 μm.

[0065] For example, etching is performed on the upper surface of the first passivation layer 6 until the N+ layer 1 is exposed, and then etching is stopped to form multiple grooves. The multiple grooves can be evenly distributed around the multi-level PN junction, or they can be positioned as needed, and the diameter of each groove can be 5 to 50 μm.

[0066] Optionally, step 103, which involves preparing multiple grounding pads based on multiple grooves, may specifically include: performing gold plating within the multiple grooves to form multiple grounding pads. The corresponding third gold plating thickness is 1–5 μm.

[0067] For example, gold plating is performed in the above-mentioned multiple grooves to form multiple grounding pads 7, wherein the diameter of each grounding pad 7 is larger than the diameter of the corresponding groove to facilitate subsequent use.

[0068] Step 104: Prepare an insulating dielectric layer on the upper surface of the first passivation layer, and perform windowing treatment at a predetermined position on the upper surface of the insulating dielectric layer to form multiple openings.

[0069] The insulating dielectric layer covers the first passivation layer, multiple ground pads, multiple P+ layers, and multiple upper electrodes. The preset positions are those perpendicular to the multiple upper electrodes and multiple ground pads.

[0070] Figure 5 This is a cross-sectional view of a PIN limiter after the aperture has been fabricated, according to an embodiment of this application. (Refer to...) Figure 5 Optionally, an insulating dielectric layer 8 is prepared on the upper surface of the first passivation layer 6 using methods such as spin coating, impregnation, or casting to prevent contact between metal conductors, i.e., to prevent contact between the N+ layer 1 or multiple P+ layers 3 and the preset peripheral circuit, ensuring that no phase-to-ground or phase-to-phase breakdown short circuit occurs. The insulating dielectric layer 8 can be a PI dielectric or other material, and its thickness is 10±1μm.

[0071] For example, step 104, which involves creating a window at a predetermined position on the upper surface of the insulating dielectric layer to form multiple openings, may specifically include etching to the upper electrode or ground pad at a predetermined position on the upper surface of the insulating dielectric layer to form multiple openings.

[0072] Optionally, etching is performed on the upper surface of the insulating dielectric layer 8 at positions perpendicular to the multiple upper electrodes 4 and multiple ground pads 7 until the upper electrodes 4 or ground pads 7 are exposed, and then etching is stopped to form multiple openings, i.e., each opening corresponds to one upper electrode 4 or ground pad 7, and the diameter of each opening is 5 to 50 μm.

[0073] Step 105: Prepare a preset peripheral circuit on the upper surface of the insulating dielectric layer, and perform gold plating in multiple openings so that multiple upper electrodes and multiple grounding pads are electrically connected to the preset peripheral circuit.

[0074] Optionally, a preset peripheral circuit can be fabricated on the upper surface of the insulating dielectric layer using methods such as electroplating or photolithography. The preset peripheral circuit can be set as needed and is not specifically limited here. For example, if a PIN limiter needs to be fabricated in this embodiment, the preset peripheral circuit is a limiter circuit. If a switch monolithic microwave integrated circuit (referred to as a switch MMIC) needs to be fabricated, the preset peripheral circuit is a corresponding switch circuit.

[0075] For example, gold plating is performed in the above-mentioned multiple openings, and the corresponding fourth gold plating thickness can be 1 to 5 μm, so that multiple upper electrodes and multiple grounding pads are electrically connected to the preset peripheral circuit through the gold plating in the multiple openings.

[0076] In one possible implementation, the method for fabricating a PIN limiter based on a silicon-based PIN diode may further include: fabricating a second passivation layer on the upper surface of a preset peripheral circuit.

[0077] Optionally, a second passivation layer can be prepared on the upper surface of the preset peripheral circuit for protection by means of thermal oxidation growth or chemical deposition, wherein the thickness of the second passivation layer is 0.5 to 2 μm.

[0078] In practical applications, an 8-inch silicon wafer substrate is used, allowing for the fabrication of multiple monolithic silicon-based PIN diode-based PIN limiters on the same substrate. The silicon wafer substrate is then diced as needed, for example, according to chip dimensions, ultimately resulting in multiple independent PIN limiters. The PIN limiter fabricated using the silicon-based PIN diode-based PIN limiter fabrication method provided in this application is one-tenth the size of a conventional silicon-based PIN diode-based PIN limiter fabricated using hybrid integration processes, thus reducing the size and increasing the integration density of the PIN limiter. Furthermore, compared to conventional PIN limiters using GaAs-based PIN diodes, its power handling capability is increased by 5 to 10 times.

[0079] The method for fabricating a silicon-based PIN diode-based PIN limiter provided in this application adopts a monolithic fabrication approach. By fabricating multi-level PN junctions, upper and lower electrodes, ground pads, insulating dielectric layers, and preset peripheral circuits on the same silicon wafer substrate, and by performing windowing and gold plating, the upper electrode and ground pads can be electrically connected to the preset peripheral circuits, thereby obtaining a silicon-based PIN diode-based PIN limiter. This method can reduce the size of the PIN limiter, improve its integration, and the fabrication method is simple and easy to implement.

[0080] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0081] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of fabricating a PIN limiter based on a silicon-based PIN diode, characterized in that, include: A multi-level PN junction is fabricated on a silicon wafer substrate to obtain an N+ layer, multiple P+ layers, and multiple I-layer regions corresponding to the multiple P+ layers; wherein each level of PN junction includes at least one PN junction; the multi-level PN junctions share a single N+ layer; and the I-layer regions are located between the N+ layer and the P+ layer. An upper electrode is fabricated on the upper surface of each P+ layer; the lower surface of the N+ layer is thinned to a preset thickness, and a lower electrode is fabricated on the lower surface of the N+ layer. A first passivation layer is prepared on the upper surface of the N+ layer, excluding the regions of the plurality of I layers, the plurality of P+ layers, and the regions of the plurality of upper electrodes; a plurality of grooves are etched on the upper surface of the first passivation layer to the upper surface of the N+ layer, and a plurality of grounding pads are prepared based on the plurality of grooves; An insulating dielectric layer is prepared on the upper surface of the first passivation layer, the insulating dielectric layer covering the first passivation layer, the plurality of ground pads, the plurality of P+ layers and the plurality of upper electrodes; a windowing process is performed at a predetermined position on the upper surface of the insulating dielectric layer to form a plurality of openings; the predetermined position is the position on the upper surface of the insulating dielectric layer that is perpendicular to the plurality of upper electrodes and the plurality of ground pads. A preset peripheral circuit is prepared on the upper surface of the insulating dielectric layer, and gold plating is performed in the plurality of openings so that the plurality of upper electrodes and the plurality of grounding pads are electrically connected to the preset peripheral circuit.

2. The method for fabricating a PIN limiter based on a silicon-based PIN diode according to claim 1, characterized in that, The process of fabricating a multi-level PN junction on a silicon wafer substrate to obtain an N+ layer, multiple P+ layers, and multiple I-layer regions corresponding to the multiple P+ layers includes: N+ doping is performed on the lower surface of a silicon wafer substrate to form an N+ layer; Multiple P+ doping is performed at different locations on the upper surface of the silicon wafer substrate to form multiple P+ layers with a first predetermined diameter; The space between the P+ layer and the N+ layer is an I layer. The I layer is etched to retain multiple I layer regions under the multiple P+ layers. The diameter of each I layer region is a second preset diameter. The first preset diameter is larger than the second preset diameter.

3. The method for fabricating a PIN limiter based on a silicon-based PIN diode according to claim 1, characterized in that, An upper electrode is prepared on the upper surface of each of the P+ layers; Thinning the lower surface of the N+ layer to a predetermined thickness and fabricating a lower electrode on the lower surface of the N+ layer includes: Gold plating is performed on the upper surface of each P+ layer to form an upper electrode; the corresponding first gold plating thickness is 1~5μm. The lower surface of the N+ layer is thinned to a preset thickness, and gold plating is performed on the lower surface of the N+ layer to form a lower electrode; the corresponding second gold plating thickness is 0.8~3μm.

4. The method for fabricating a PIN limiter based on a silicon-based PIN diode according to claim 1, characterized in that, The process of fabricating multiple grounding pads based on the multiple grooves includes: Gold plating is performed in the multiple grooves to form multiple grounding pads; the corresponding third gold plating thickness is 1~5μm.

5. The method for fabricating a PIN limiter based on a silicon-based PIN diode according to claim 1, characterized in that, The step involves creating multiple openings at predetermined positions on the upper surface of the insulating dielectric layer, including: Multiple openings are formed by etching at a predetermined position on the upper surface of the insulating dielectric layer onto the upper surface of the upper electrode or the upper surface of the grounding pad.

6. The method for fabricating a PIN limiter based on a silicon-based PIN diode according to claim 1, characterized in that, Also includes: A second passivation layer is prepared on the upper surface of the preset peripheral circuit.

7. A PIN limiter, characterized in that, The PIN limiter is obtained by applying the fabrication method of the silicon-based PIN diode as described in any one of claims 1 to 6; the PIN limiter comprises: A multi-level PN junction includes an N+ layer of a predetermined thickness, multiple I-layer regions of a second predetermined diameter, and multiple P+ layers of a first predetermined diameter; the multiple I-layer regions are disposed on the upper surface of the N+ layer and correspond to the multiple P+ layers respectively; the multiple P+ layers are respectively disposed on the upper surface of the multiple I-layer regions. Multiple upper electrodes are respectively disposed on the upper surface of the multiple P+ layers; The lower electrode is disposed on the lower surface of the N+ layer; The first passivation layer is disposed on the upper surface of the N+ layer, excluding the regions of the plurality of I layers, the regions of the plurality of P+ layers, and the regions of the plurality of upper electrodes; Multiple grounding pads are provided, and multiple grooves are etched from the upper surface of the first passivation layer to the upper surface of the N+ layer, with each grounding pad being disposed in each groove. An insulating dielectric layer is disposed on the upper surface of the first passivation layer, covering the first passivation layer, the plurality of ground pads, the plurality of P+ layers, and the plurality of upper electrodes; a plurality of openings are provided at a predetermined position on the upper surface of the insulating dielectric layer, the predetermined position being a position on the upper surface of the insulating dielectric layer that is perpendicular to the plurality of upper electrodes and the plurality of ground pads; A pre-set peripheral circuit is disposed on the upper surface of the insulating dielectric layer.

8. The PIN limiter according to claim 7, characterized in that, Also includes: A second passivation layer is disposed on the upper surface of the preset peripheral circuit; The thickness of the second passivation layer is 0.5~2μm.

9. The PIN limiter according to claim 7, characterized in that, The preset thickness is 100 μm, the thickness of the I layer region is 7~10 μm, the thickness of the first passivation layer is 0.5~2 μm, and the thickness of the insulating dielectric layer is 10±1 μm.

10. The PIN limiter according to claim 7, characterized in that, The first preset diameter is larger than the second preset diameter; the first preset diameter is 50~100μm, the diameter of the upper electrode is 5~50μm, the diameter of the groove is 5~50μm, and the diameter of the opening is 5~50μm.

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