A semiconductor structure manufacturing method, a semiconductor structure and a memory

Abstract

The application provides a semiconductor structure manufacturing method, a semiconductor structure and a memory. The semiconductor structure manufacturing method comprises the following steps: providing a substrate, the substrate comprising a first surface and a second surface opposite to each other; forming a first dielectric layer on the first surface of the substrate, wherein a semiconductor device is formed in the first dielectric layer; forming a first trench extending into the substrate on the first dielectric layer; forming a first barrier layer on the first dielectric layer, the first barrier layer covering the inner wall of the first trench and the surface of the first dielectric layer, wherein the first barrier layer is connected with the semiconductor device; forming a second trench corresponding to the first trench on the second surface of the substrate, wherein the first barrier layer serves as a stop layer when the second trench is formed; and forming a second barrier layer on the substrate, the second barrier layer covering the second surface and the inner wall of the second trench, wherein the second barrier layer is connected with the first barrier layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink and the interconnection density of devices continues to increase. Traditional two-dimensional packaging can no longer meet the needs of the industry. Therefore, stacked packaging based on through silicon via (TSV) vertical interconnection has become the mainstream direction of packaging technology development due to its key technological advantages of short-distance interconnection and high-density integration.

[0003] TSV (Through-Video) technology involves creating vertical vias between different device structures using methods such as etching or laser drilling, and then depositing conductive materials within these vias through electroplating to form conductive pillars, thus achieving electrical interconnection. Currently, TSV processes mainly use TSV middle or TSV last processes to form TSV structures, requiring a large area to be reserved for the TSV, resulting in significant waste.

[0004] Therefore, how to solve the above problems has become an urgent issue for those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a method for fabricating a semiconductor structure, a semiconductor structure, and a memory, which can solve the above-mentioned problems.

[0006] To address the aforementioned problems, according to one aspect of this application, a method for fabricating a semiconductor structure is provided, comprising:

[0007] A substrate is provided, the substrate comprising opposing first and second surfaces;

[0008] A first dielectric layer is formed on the first surface of the substrate, wherein a semiconductor device is formed within the first dielectric layer;

[0009] A first trench extending into the substrate is formed on the first dielectric layer;

[0010] A first barrier layer is formed on the first dielectric layer, the first barrier layer covering the inner wall of the first trench and the surface of the first dielectric layer, wherein the first barrier layer is connected to the semiconductor device;

[0011] A second trench corresponding to the first trench is formed on the second surface of the substrate, wherein the first barrier layer serves as a stop layer when the second trench is formed;

[0012] A second barrier layer is formed on the substrate, the second barrier layer covering the second surface and the inner wall of the second trench, wherein the second barrier layer is connected to the first barrier layer.

[0013] In some embodiments, forming a first trench extending into the substrate on the first dielectric layer includes:

[0014] A first mask pattern is formed on the first dielectric layer;

[0015] The first dielectric layer is etched using the first mask pattern to form the first trench extending from the first dielectric layer into the substrate.

[0016] In some embodiments, forming a first mask pattern on the first dielectric layer includes:

[0017] A first hard mask layer is formed on the first dielectric layer;

[0018] The first mask pattern is formed on the first hard mask layer.

[0019] In some embodiments, after etching the first dielectric layer using the first mask pattern to form the first trench extending from the first dielectric layer into the substrate, the method further includes:

[0020] A second hard mask layer is formed covering the first mask pattern and the first trench;

[0021] A patterned photoresist layer is formed on the second hard mask layer;

[0022] The pattern of the photoresist layer is transferred to the first dielectric layer using a dry etching process.

[0023] In some embodiments, after transferring the pattern of the photoresist layer to the first dielectric layer using a dry etching process, the method further includes:

[0024] The hard mask and photoresist on the first dielectric layer are removed using a wet cleaning process.

[0025] In some embodiments, after forming the first barrier layer on the first dielectric layer, the method further includes:

[0026] A first metal layer is formed to cover the first barrier layer.

[0027] In some embodiments, before forming a second trench corresponding to the first trench on the second surface of the substrate, the method further includes:

[0028] The second surface side of the substrate is thinned.

[0029] In some embodiments, forming a second trench corresponding to the first trench on the second surface of the substrate includes:

[0030] A second mask pattern is formed on the second surface of the substrate;

[0031] The substrate is etched using the second mask pattern to form the second trench that stops at the first barrier layer.

[0032] In some embodiments, forming a second mask pattern on the second surface of the substrate includes:

[0033] A third hard mask layer is formed on the second surface of the substrate;

[0034] The third hard mask layer is processed using an exposure process to form the second mask pattern.

[0035] In some embodiments, prior to forming the second barrier layer on the substrate, the method further includes:

[0036] A second dielectric layer is formed on the substrate, the second dielectric layer covering the second surface and the inner wall of the second trench.

[0037] In some embodiments, after forming the second dielectric layer on the substrate, the method further includes:

[0038] The second dielectric layer formed at the bottom of the second trench is removed by an etching process.

[0039] In some embodiments, after forming the second barrier layer on the substrate, the method further includes:

[0040] A second metal layer is formed to cover the second barrier layer.

[0041] In some embodiments, there are multiple first trenches and multiple second trenches, and the multiple second trenches and multiple first trenches are arranged in a one-to-one correspondence.

[0042] In some embodiments, the cross-section of the second trench is wedge-shaped, and the opening size of the second trench gradually decreases along the direction from the second surface to the first surface.

[0043] According to a second aspect of this application, this application provides a semiconductor structure comprising:

[0044] A substrate, the substrate comprising opposing first and second surfaces;

[0045] A first dielectric layer is formed on the first surface of the substrate, and a semiconductor device is formed within the first dielectric layer; wherein the semiconductor structure includes a first trench formed on the first dielectric layer extending into the substrate;

[0046] A first barrier layer is formed on the first dielectric layer, covering the inner wall of the first trench and the surface of the first dielectric layer, and the first barrier layer is connected to the semiconductor device; wherein the semiconductor structure includes a second trench formed on the second surface of the substrate corresponding to the first trench, and the first barrier layer serves as a stop layer when the second trench is formed.

[0047] A second barrier layer covers the second surface and the inner wall of the second trench, wherein the second barrier layer is connected to the first barrier layer.

[0048] In some embodiments, the system further includes a first metal layer, the first metal layer being formed to cover the first barrier layer.

[0049] In some embodiments, the system further includes a second dielectric layer that covers the second surface and the inner wall of the second trench.

[0050] In some embodiments, the system further includes a second metal layer, the second metal layer being formed to cover the second barrier layer.

[0051] In some embodiments, there are multiple first trenches and multiple second trenches, and the multiple second trenches and multiple first trenches are arranged in a one-to-one correspondence.

[0052] According to a third aspect of this application, this application provides a memory including the semiconductor structure described above.

[0053] The above-mentioned technical solution of this application has the following beneficial technical effects:

[0054] In the formation method of the technical solution of this application, on the one hand, the TSV process flow is optimized. By using the TSV first process to form a first trench and a second trench on two opposite surfaces of the substrate (or wafer), the problem of excessive wafer fabrication area and high cost caused by both fabricating semiconductor devices on the same surface of the wafer and reserving TSV fabrication area can be solved. By forming a second trench on the second surface of the substrate, the number of first trenches on the first surface of the substrate can be reduced, effectively controlling the wafer manufacturing area and saving semiconductor manufacturing costs. On the other hand, by making full use of the two opposite surfaces of the substrate, a 3D TSV structure composed of the first trench and the second trench is formed. The second barrier layer in the second trench and the first barrier layer in the first trench are interconnected with each other, realizing the 3D architecture of the internal subsystem of the system-on-a-chip. The subsystem interconnection is more flexible and the interconnection lines are shorter, thereby improving semiconductor performance. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0057] Figures 2-12 This is a schematic diagram illustrating the structure presented in the flowchart of a semiconductor structure fabrication method according to an exemplary embodiment.

[0058] Figure label:

[0059] 10. Substrate; 20. First dielectric layer; 30. First hard mask layer; 40. First trench; 50. Second hard mask layer; 60. Photoresist layer; 70. First barrier layer; 80. First metal layer; 90. Third hard mask layer; 100. Second trench; 110. Second dielectric layer; 120. Second barrier layer; 130. Second metal layer; 11. First surface; 12. Second surface; 21. Capacitor structure; 22. First metal plug; 23. Second metal plug; 24. Device; 25. Trench isolation. Detailed Implementation

[0060] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0062] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0063] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink and the interconnection density of devices continues to increase. Traditional two-dimensional packaging can no longer meet the needs of the industry. Therefore, stacked packaging based on through silicon via (TSV) vertical interconnection has become the mainstream direction of packaging technology development due to its key technological advantages of short-distance interconnection and high-density integration.

[0064] TSV (Through-Video) technology involves creating vertical vias between different device structures using methods such as etching or laser drilling, and then depositing conductive materials within these vias through electroplating to form conductive pillars, thus achieving electrical interconnection. Currently, TSV processes mainly use TSV middle or TSV last processes to form TSV structures, requiring a large area to be reserved for the TSV, resulting in significant waste.

[0065] In some embodiments, due to the high cost of silicon-on-insulator (SiI), which is at least ten times more expensive than bulk silicon, the traditional method of fabricating semiconductor devices only on the front side of SiI is wasteful. Furthermore, manufacturing a system-on-a-chip (SoC) on a single plane results in a large construction area, and each subsystem can only utilize one process node, failing to fully utilize the surface area of ​​SiI, leading to high manufacturing costs and inflexible interconnection between subsystems within the system. Therefore, designing a powerful SoC that can fabricate semiconductor devices on both the front and back sides of SiI has become a problem for those skilled in the art.

[0066] like Figure 1 As shown, this application provides a method for fabricating a semiconductor structure, including: S110, providing a substrate, the substrate including a first surface and a second surface opposite to each other;

[0067] S120. A first dielectric layer is formed on a first surface of a substrate, wherein a semiconductor device is formed within the first dielectric layer;

[0068] S130, A first trench extending into the substrate is formed on the first dielectric layer;

[0069] S140. A first barrier layer is formed on the first dielectric layer, the first barrier layer covering the inner wall of the first trench and the surface of the first dielectric layer, wherein the first barrier layer is connected to the semiconductor device.

[0070] S150. A second trench corresponding to the first trench is formed on the second surface of the substrate, wherein the first barrier layer serves as a stop layer when the second trench is formed.

[0071] S160. A second barrier layer is formed on the substrate, the second barrier layer covering the inner wall of the second surface and the second trench, wherein the second barrier layer is connected to the first barrier layer.

[0072] In this embodiment, on the one hand, the TSV process flow is optimized. By using the TSV first process to form a first trench and a second trench on two opposite surfaces of the substrate (or wafer), the problem of excessive wafer fabrication area and high cost caused by both fabricating semiconductor devices on the same surface of the wafer and reserving TSV fabrication area can be solved. By forming a second trench on the second surface of the substrate, the number of first trenches on the first surface of the substrate can be reduced, effectively controlling the wafer manufacturing area and saving semiconductor manufacturing costs. On the other hand, by making full use of the two opposite surfaces of the substrate, a 3D TSV structure composed of the first trench and the second trench is formed. The second barrier layer in the second trench and the first barrier layer in the first trench are interconnected with each other, realizing the 3D architecture of the internal subsystem of the system-on-a-chip. The subsystem interconnection is more flexible and the interconnection lines are shorter, improving semiconductor performance.

[0073] Specifically, Figures 2-7 This application provides schematic diagrams of the structures presented in steps S110-S140 of the semiconductor structure fabrication method according to embodiments of the present application. (Refer to...) Figures 2-7 This is a cross-sectional view of a semiconductor structure in the manufacturing process. The figure shows a substrate 10, a first dielectric layer 20 formed on the substrate 10, a first surface 11 and a second surface 12 of the substrate 10, and a first trench 40 formed thereon.

[0074] The substrate 10 can be any substrate 10 available in the prior art, and the structure and material of the substrate 10 can be adapted as needed. For example, the material of the substrate 10 can be one or any combination of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, silicon on insulator (SOI), or germanium on insulator (GOI).

[0075] In some embodiments, reference Figure 7 In step 120, a first dielectric layer 20 is formed on the first surface 11 of the substrate 10, wherein a semiconductor device is formed within the first dielectric layer 20. For example... Figures 2 to 12 As shown, the semiconductor device includes a capacitor structure 21, a first metal plug 22, a second metal plug 23, a device 24, and a trench isolation 25. The capacitor structure 21 is formed on the first surface 11 of the substrate 10. The first metal plug 22 is connected to the capacitor structure 21, and the exposed top surface of the first metal plug 22 is covered by a first barrier layer 70. The trench isolation 25 is formed within the substrate 10. The device 24 is formed on the first surface 11 of the substrate 10. The second metal plug 23 is connected to the device 24, and the exposed top surface of the second metal plug 23 is covered by the first barrier layer 70. The material of the first dielectric layer 20 can be at least one of SiN (silicon nitride), SiO2 (silicon oxide), SiON (silicon oxynitride), and BARC (bottom anti-reflective layer). Figure 7 In this application, a semiconductor device is formed on the first surface 11 of the substrate 10. The first dielectric layer 20 is formed on the first surface 11 of the substrate 10 using a deposition process. The first dielectric layer 20 is formed to cover the semiconductor device, which includes, but is not limited to, NMOS devices, PMOS devices, CMOS devices, resistors, capacitors or inductors.

[0076] In some embodiments, reference Figures 2 to 12In step S130, a first trench 40 extending into the substrate 10 is formed on the first dielectric layer 20, wherein the first trench 40 is formed on the substrate 10 using a TSV first process. As can be seen from the above figures, this application utilizes a TSV first process to process the surface of the first dielectric layer 20 facing away from the substrate 10 to form a first trench 40 that penetrates the first dielectric layer 20 and extends into the substrate 10. The first trench 40 is formed between adjacent semiconductor devices.

[0077] In some embodiments, reference Figure 7 In step S140, a first barrier layer 70 is formed on the first dielectric layer 20. The first barrier layer 70 covers the inner wall of the first trench 40 and the surface of the first dielectric layer 20, wherein the first barrier layer 70 is connected to the semiconductor device. It should be understood that in some embodiments, the first barrier layer 70 is a metal interconnect layer. (Continue to refer to...) Figure 7 A plurality of trenches are formed on the first dielectric layer 20, including a first trench 40. A trench is formed on the top of each semiconductor device to expose the surface of the semiconductor device. A first barrier layer 70 is formed to cover the surface of the first dielectric layer 20 and is connected to the exposed surface of each semiconductor device.

[0078] In some embodiments, step S130, forming a first trench 40 extending into the substrate 10 on the first dielectric layer 20, includes:

[0079] S131. A first mask pattern is formed on the first dielectric layer 20;

[0080] refer to Figure 2 As shown, the first mask pattern is formed on the surface of the first dielectric layer 20 away from the substrate 10.

[0081] S132. The first dielectric layer 20 is etched using the first mask pattern to form a first trench 40 extending from the first dielectric layer 20 into the substrate 10.

[0082] Continue to refer to Figure 2 As shown, the first mask pattern defines an etching window. The first dielectric layer 20 and the substrate 10 are etched according to the etching window to form trenches on the first dielectric layer 20. The trenches include trenches corresponding to semiconductor devices and first trenches 40. The trenches corresponding to semiconductor devices use the semiconductor device as an etching stop layer and expose the surface of the semiconductor device after etching. The first trenches 40 are formed to penetrate the first dielectric layer 20 and stop within the substrate 10.

[0083] In some embodiments, step S131, forming a first mask pattern on the first dielectric layer 20, includes:

[0084] S1311. A first hard mask layer 30 is formed on the first dielectric layer 20;

[0085] A first hard mask layer 30 is formed on the surface of the first dielectric layer 20 away from the substrate 10 using a deposition process.

[0086] S1312, A first mask pattern is formed on the first hard mask layer 30.

[0087] Specifically, a photoresist layer is formed on the first hard mask layer 30 using a spin coating process, the photoresist layer is patterned using an exposure process, and the first hard mask layer 30 is etched according to the patterned photoresist layer to form the first mask pattern.

[0088] In some embodiments, after step S132 involves etching the first dielectric layer 20 using the first mask pattern to form a first trench 40 extending from the first dielectric layer 20 into the substrate 10, the method further includes:

[0089] S170, Form a second hard mask layer 50 covering the first mask pattern and the first trench 40;

[0090] refer to Figure 3 As shown, the second hard mask layer 50 is formed on the surface of the first mask pattern (formed by patterning the first hard mask layer 30 using an etching process) away from the substrate 10, and fills the etched windows of the first mask pattern and the trenches formed on the first dielectric layer 20.

[0091] S180, A patterned photoresist layer 60 is formed on the second hard mask layer 50;

[0092] refer to Figure 4 As shown, a patterned photoresist layer 60 is formed on the surface of the second hard mask layer 50 facing away from the substrate 10. It is understood that the photoresist layer 60 can be formed on the second hard mask layer 50 using a spin coating process, and the photoresist layer 60 can be patterned using an exposure process.

[0093] S190. Using a dry etching process, the pattern of the photoresist layer 60 is transferred to the first dielectric layer 20.

[0094] refer to Figure 5 As shown, the second hard mask layer 50 is dry etched according to the patterned photoresist layer 60, and the pattern of the photoresist layer 60 is transferred to the second hard mask layer 50, the first hard mask layer 30 and the first dielectric layer 20, so that the side of the first dielectric layer 20 facing away from the substrate 10 forms a patterned structure.

[0095] In other embodiments, after transferring the pattern of the photoresist layer 60 to the first dielectric layer 20 using a dry etching process in step S190, the method further includes:

[0096] S191. Remove the hard mask and photoresist on the first dielectric layer 20 using a wet cleaning process.

[0097] A wet cleaning process is used to remove the hard mask and photoresist on the first dielectric layer 20. The hard mask includes a first hard mask layer 30 and a second hard mask layer 50, which are stacked on the first dielectric layer 20 after pattern transfer. (Reference) Figure 6 As shown, Figure 6 The figure shows the semiconductor structure after cleaning. As can be seen, a patterned structure has been formed on the side of the first dielectric layer 20 away from the substrate 10. A trench is formed above each semiconductor device to expose the surface of the semiconductor device. The first trench 40 after formation exposes the surface of the substrate 10.

[0098] In some embodiments, after step S140 forms the first barrier layer 70 on the first dielectric layer 20, the method further includes:

[0099] S200, a first metal layer 80 is formed covering the first barrier layer 70.

[0100] refer to Figure 7 As shown, a first metal layer 80 is formed on the side of the first dielectric layer 20 where a patterned structure is formed. The first metal layer 80 covers the surface of the first barrier layer 70, and the first barrier layer 70 is located between the first metal layer 80 and the first dielectric layer 20. The first metal layer 80 fills the trenches on the first dielectric layer 20, specifically including trenches corresponding to each semiconductor device and first trench 40. The material of the first metal layer 80 can be copper.

[0101] In some embodiments, before step S150 forms the second trench 100 corresponding to the first trench 40 on the second surface 12 of the substrate 10, the method further includes:

[0102] S210, flipped substrate 10;

[0103] Flip the substrate 10 so that its second surface 12 serves as the fabrication surface in the semiconductor structure fabrication process, as referenced. Figures 8 to 12 It can be seen that substrate 10 has been flipped 180 degrees.

[0104] S220, Thinning treatment is performed on the second surface 12 side of the substrate 10.

[0105] The second surface 12 is ground using a chemical mechanical polishing (CMP) process to reduce the thickness of the substrate 10.

[0106] In some embodiments, step S150, which involves forming a second trench 100 on the second surface 12 of the substrate 10 corresponding to the first trench 40, includes:

[0107] S151. A second mask pattern is formed on the second surface 12 of the substrate 10;

[0108] refer to Figure 8 A second mask pattern is formed on the second surface 12 of the substrate 10, and the second mask pattern defines the etching window.

[0109] S152. The substrate 10 is etched using the second mask pattern to form a second trench 100 that stops at the first barrier layer 70.

[0110] refer to Figure 9 As shown, the substrate 10 is etched according to the etching window defined by the second mask pattern, and the first barrier layer 70 is used as the stop layer to etch out the second trench 100 that stops at the first barrier layer 70.

[0111] In some embodiments, step S151, forming a second mask pattern on the second surface 12 of the substrate 10, includes:

[0112] S1511. A third hard mask layer 90 is formed on the second surface 12 of the substrate 10;

[0113] refer to Figure 8 In this application, a third hard mask layer 90 is formed on the second surface 12 of the substrate 10 using a deposition process.

[0114] S1512. The third hard mask layer 90 is processed using an exposure process to form the second mask pattern.

[0115] A photoresist layer is formed on the third hard mask layer 90 using a spin coating process. The photoresist layer is then patterned using an exposure process. The third hard mask layer 90 is etched according to the patterned photoresist layer to form a second mask pattern. The second mask pattern defines the etching window for etching the second trench 100.

[0116] In some embodiments, step S160, prior to forming the second barrier layer 120 on the substrate 10, further includes:

[0117] S230, A second dielectric layer 110 is formed on the substrate 10, the second dielectric layer 110 covering the second surface 12 and the inner wall of the second trench 100.

[0118] refer to Figure 10 A second dielectric layer 110 is formed on the substrate 10 using a deposition process. The second dielectric layer 110 is formed to cover the inner wall of the second surface 12 and the second trench 100. The material of the second dielectric layer 110 can be at least one of SiN (silicon nitride), SiO2 (silicon oxide), SiON (silicon oxynitride), and BARC (bottom anti-reflective layer). (Continue to the previous section) Figure 10 The second medium layer 110 located at the bottom of the second trench 100 is connected to the first barrier layer 70.

[0119] In some embodiments, after forming the second dielectric layer 110 on the substrate 10 in step S230, the method further includes:

[0120] S240, The second dielectric layer 110 formed at the bottom of the second trench 100 is removed by an etching process.

[0121] refer to Figure 11 Using the first barrier layer 70 as the etching stop layer, the second dielectric layer 110 at the bottom of the second trench 100 is etched to expose the surface of the first barrier layer 70.

[0122] In some embodiments, after step S160 forms the second barrier layer 120 on the substrate 10, the method further includes:

[0123] S250, a second metal layer 130 is formed covering the second barrier layer 120.

[0124] refer to Figure 12 A second metal layer 130 is formed on the surface of the second barrier layer 120, and the second barrier layer 120 is located between the second metal layer 130 and the second dielectric layer 110. The second metal layer 130 fills the second trench 100. (Continue to refer to...) Figure 12 The second barrier layer 120 is connected to the first barrier layer 70 at the bottom of the second trench 100, thereby interconnecting the first barrier layer 70 and the second barrier layer 120. The second metal layer 130 is made of copper.

[0125] In this embodiment, on the one hand, the TSV process flow is optimized. By using the TSV first process to form a first trench 40 and a second trench 100 on two opposite surfaces of the substrate 10 (which can also be called a wafer), the problem of excessive wafer fabrication area and high cost caused by both fabricating semiconductor devices on the same surface of the wafer and reserving TSV fabrication area can be solved. By forming the second trench 100 on the second surface 12 of the substrate 10, the number of first trenches 40 on the first surface 11 of the substrate 10 can be reduced, effectively controlling the wafer manufacturing area and saving semiconductor manufacturing costs. On the other hand, by making full use of the two opposite surfaces of the substrate 10, a 3D TSV structure composed of the first trench 40 and the second trench 100 is formed. The second barrier layer 120 in the second trench 100 and the first barrier layer 70 in the first trench 40 are interconnected with metal, realizing the 3D architecture of the internal subsystem of the system-on-a-chip. The subsystem interconnection is more flexible and the interconnection lines are shorter, improving semiconductor performance.

[0126] In some embodiments, there are multiple first trenches 40 and second trenches 100, with each of the multiple second trenches 100 and the multiple first trenches 40 arranged in a one-to-one correspondence. The first trenches 40 are formed between two adjacent semiconductor devices.

[0127] In this embodiment, the two opposing surfaces of the substrate 10 are fully utilized to form a 3D TSV structure consisting of a first trench 40 and a second trench 100. The second barrier layer 120 in the second trench 100 and the first barrier layer 70 in the first trench 40 are interconnected with each other, realizing a 3D architecture of the subsystems inside the system-on-a-chip. The subsystem interconnection is more flexible and the interconnection lines are shorter, thus improving semiconductor performance.

[0128] In some embodiments, the cross-section of the second groove 100 is wedge-shaped, and the opening size of the second groove 100 gradually decreases along the direction from the second surface 12 to the first surface 11.

[0129] According to a second aspect of this application, a semiconductor structure is provided, comprising a substrate 10, a first dielectric layer 20, a first barrier layer 70, and a second barrier layer 120. The substrate 10 includes a first surface 11 and a second surface 12 opposite to each other. The first dielectric layer 20 is formed on the first surface 11 of the substrate 10, and a semiconductor device is formed within the first dielectric layer 20; wherein the semiconductor structure includes a first trench 40 formed on the first dielectric layer 20 extending into the substrate 10. The first barrier layer 70 is formed on the first dielectric layer 20, covering the inner wall of the first trench 40 and the surface of the first dielectric layer 20, and is connected to the semiconductor device; wherein the semiconductor structure includes a second trench 100 formed on the second surface 12 of the substrate 10 corresponding to the first trench 40, and the first barrier layer 70 serves as a stop layer during the formation of the second trench 100. The second barrier layer 120 is formed on the substrate 10, covering the second surface 12 and the inner wall of the second trench 100, wherein the second barrier layer 120 is connected to the first barrier layer 70.

[0130] In this embodiment, on the one hand, the TSV process flow is optimized. By using the TSV first process to form a first trench 40 and a second trench 100 on two opposite surfaces of the substrate 10 (which can also be called a wafer), the problem of excessive wafer fabrication area and high cost caused by both fabricating semiconductor devices on the same surface of the wafer and reserving TSV fabrication area can be solved. By forming the second trench 100 on the second surface 12 of the substrate 10, the number of first trenches 40 on the first surface 11 of the substrate 10 can be reduced, effectively controlling the wafer manufacturing area and saving semiconductor manufacturing costs. On the other hand, by making full use of the two opposite surfaces of the substrate 10, a 3D TSV structure composed of the first trench 40 and the second trench 100 is formed. The second barrier layer 120 in the second trench 100 and the first barrier layer 70 in the first trench 40 are interconnected with metal, realizing the 3D architecture of the internal subsystem of the system-on-a-chip. The subsystem interconnection is more flexible and the interconnection lines are shorter, improving semiconductor performance.

[0131] In some embodiments, the semiconductor structure further includes a first metal layer 80, which is formed to cover the first barrier layer 70.

[0132] In some embodiments, the semiconductor structure further includes a second dielectric layer 110 formed on the substrate 10; wherein the second dielectric layer 110 covers the second surface 12 and the inner wall of the second trench 100.

[0133] In some embodiments, the semiconductor structure further includes a second metal layer 130, which is formed to cover the second barrier layer 120.

[0134] In some embodiments, there are multiple first grooves 40 and multiple second grooves 100, and the multiple second grooves 100 and multiple first grooves 40 are arranged in a one-to-one correspondence.

[0135] In this embodiment, the two opposing surfaces of the substrate 10 are fully utilized to form a 3D TSV structure consisting of a first trench 40 and a second trench 100. The second barrier layer 120 in the second trench 100 and the first barrier layer 70 in the first trench 40 are interconnected with each other, realizing a 3D architecture of the subsystems inside the system-on-a-chip. The subsystem interconnection is more flexible and the interconnection lines are shorter, thus improving semiconductor performance.

[0136] It is understood that the semiconductor structure fabricated according to the embodiments described above can be applied to the fabrication of various integrated circuits (ICs). The ICs according to this application are, for example, memory circuits, such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or read-only memory (ROM), etc. The ICs according to this application can also be logic devices, such as programmable logic arrays (PLAs), application-specific integrated circuits (ASICs), integrated DRAM logic integrated circuits (buried DRAM), radio frequency circuits, or any other circuit devices. The IC chips according to this application can be used in, for example, user electronic products, such as personal computers, portable computers, game consoles, cellular phones, personal digital assistants, cameras, digital cameras, mobile phones, and various other electronic products.

[0137] According to a third aspect of this application, this application provides a memory including the semiconductor structure described above.

[0138] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising opposing first and second surfaces; A first dielectric layer is formed on the first surface of the substrate, wherein a semiconductor device is formed within the first dielectric layer; A first trench extending into the substrate is formed on the first dielectric layer; A first barrier layer is formed on the first dielectric layer, the first barrier layer covering the inner wall of the first trench and the surface of the first dielectric layer, wherein the first barrier layer is connected to the semiconductor device; A second trench corresponding to the first trench is formed on the second surface of the substrate, wherein the first barrier layer serves as a stop layer when the second trench is formed; A second barrier layer is formed on the substrate, the second barrier layer covering the second surface and the inner wall of the second trench, wherein the second barrier layer is connected to the first barrier layer.

2. The semiconductor structure fabrication method as described in claim 1, characterized in that, The step of forming a first trench extending into the substrate on the first dielectric layer includes: A first mask pattern is formed on the first dielectric layer; The first dielectric layer is etched using the first mask pattern to form the first trench extending from the first dielectric layer into the substrate.

3. The semiconductor structure fabrication method as described in claim 2, characterized in that, The process of forming a first mask pattern on the first dielectric layer includes: A first hard mask layer is formed on the first dielectric layer; The first mask pattern is formed on the first hard mask layer.

4. The semiconductor structure fabrication method as described in claim 2, characterized in that, After etching the first dielectric layer using the first mask pattern to form the first trench extending from the first dielectric layer into the substrate, the method further includes: A second hard mask layer is formed covering the first mask pattern and the first trench; A patterned photoresist layer is formed on the second hard mask layer; The pattern of the photoresist layer is transferred to the first dielectric layer using a dry etching process.

5. The semiconductor structure fabrication method as described in claim 4, characterized in that, After transferring the pattern of the photoresist layer to the first dielectric layer using a dry etching process, the method further includes: The hard mask and photoresist on the first dielectric layer are removed using a wet cleaning process.

6. The semiconductor structure fabrication method as described in claim 1, characterized in that, After forming the first barrier layer on the first dielectric layer, the method further includes: A first metal layer is formed to cover the first barrier layer.

7. The semiconductor structure fabrication method as described in claim 1, characterized in that, Before forming a second trench corresponding to the first trench on the second surface of the substrate, the method further includes: The second surface side of the substrate is thinned.

8. The semiconductor structure fabrication method as described in claim 1, characterized in that, The step of forming a second trench corresponding to the first trench on the second surface of the substrate includes: A second mask pattern is formed on the second surface of the substrate; The substrate is etched using the second mask pattern to form the second trench that stops at the first barrier layer.

9. The semiconductor structure fabrication method as described in claim 8, characterized in that, The process of forming a second mask pattern on the second surface of the substrate includes: A third hard mask layer is formed on the second surface of the substrate; The third hard mask layer is processed using an exposure process to form the second mask pattern.

10. The semiconductor structure fabrication method as described in claim 1, characterized in that, Before forming the second barrier layer on the substrate, the method further includes: A second dielectric layer is formed on the substrate, the second dielectric layer covering the second surface and the inner wall of the second trench.

11. The semiconductor structure fabrication method as described in claim 10, characterized in that, After forming the second dielectric layer on the substrate, the method further includes: The second dielectric layer formed at the bottom of the second trench is removed by an etching process.

12. The semiconductor structure fabrication method as described in claim 1, characterized in that, After forming the second barrier layer on the substrate, the method further includes: A second metal layer is formed to cover the second barrier layer.

13. The semiconductor structure fabrication method as described in claim 1, characterized in that, There are multiple first trenches and multiple second trenches, and the multiple second trenches and multiple first trenches are arranged in a one-to-one correspondence.

14. The semiconductor structure fabrication method as described in claim 1, characterized in that, The second groove has a wedge-shaped cross-section, and the opening size of the second groove gradually decreases along the direction from the second surface to the first surface.

15. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising opposing first and second surfaces; A first dielectric layer is formed on the first surface of the substrate, and a semiconductor device is formed within the first dielectric layer; wherein the semiconductor structure includes a first trench formed on the first dielectric layer extending into the substrate; A first barrier layer is formed on the first dielectric layer, covering the inner wall of the first trench and the surface of the first dielectric layer, and the first barrier layer is connected to the semiconductor device; wherein the semiconductor structure includes a second trench formed on the second surface of the substrate corresponding to the first trench, and the first barrier layer serves as a stop layer when the second trench is formed. A second barrier layer covers the second surface and the inner wall of the second trench, wherein the second barrier layer is connected to the first barrier layer.

16. The semiconductor structure as claimed in claim 15, characterized in that, Also includes: A first metal layer is formed to cover the first barrier layer.

17. The semiconductor structure as claimed in claim 15, characterized in that, Also includes: A second dielectric layer covers the second surface and the inner wall of the second trench.

18. The semiconductor structure as claimed in claim 15, characterized in that, Also includes: A second metal layer is formed to cover the second barrier layer.

19. The semiconductor structure as described in claim 15, characterized in that, There are multiple first trenches and multiple second trenches, and the multiple second trenches and multiple first trenches are arranged in a one-to-one correspondence.

20. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 15-19.

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