Semiconductor wafer and testing method

Abstract

Embodiments of the present application provide a semiconductor wafer and a testing method. The semiconductor wafer comprises: a substrate; the substrate comprises a plurality of chip regions and a plurality of street regions between adjacent chip regions; a circuit testing device, the circuit testing device is located in the street region and has a plurality of testing ports; a crack prevention conductive structure, the crack prevention conductive structure is located in the street region and is arranged around the chip region, and is located between the circuit testing device and the chip region; and at least one first wire layer, one end of the first wire layer is connected with a corresponding testing port, and the other end is connected with adjacent crack prevention conductive structures. Embodiments of the present application solve the problem of insufficient wire layout space in the street region by using the crack prevention conductive structure to provide testing signals for the circuit testing device.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a semiconductor wafer and a testing method. Background Technology

[0002] To confirm the yield of semiconductor wafers during the production process, wafer inspection is usually performed on the semiconductor wafers. Wafer inspection is carried out by using test probes and test machines to test the functionality and electrical parameters of the components on the wafer.

[0003] Semiconductor wafers can be divided into chip areas and dicing areas. Generally, pad structures and circuit test devices are set in the dicing area, and wires are used to connect the pad structures and circuit test devices. Test probes and testers provide electrical signals to the pad structures, and in turn provide corresponding electrical signals to the circuit test devices for testing.

[0004] However, there is currently a problem of insufficient space for wire routing in the cutting area. Summary of the Invention

[0005] The technical problem solved by the embodiments of the present invention is to provide a semiconductor wafer and a testing method, which solves the problem of insufficient space for wire routing in the dicing area by utilizing a crack-resistant conductive structure.

[0006] This invention provides a semiconductor wafer, comprising: a substrate; the substrate including a plurality of chip regions and dicing regions located between adjacent chip regions; a circuit test device located in the dicing regions and having a plurality of test ports; a crack-resistant conductive structure located in the dicing regions and disposed around the chip regions, and located between the circuit test device and the chip regions; and at least one first conductive layer, one end of the first conductive layer being connected to a corresponding test port, and the other end being connected to an adjacent crack-resistant conductive structure.

[0007] In addition, the circuit test device is provided with the crack-resistant conductive structure on both sides; the circuit test device is connected to the crack-resistant conductive structure on at least one side through the first conductive layer.

[0008] In addition, there are two first conductor layers, one of which is connected to the crack-resistant conductive structure located on one side of the circuit test device, and the other of which is connected to the crack-resistant conductive structure located on the other side of the circuit test device.

[0009] In addition, the semiconductor wafer also includes: a plurality of first pad structures, which are located on the dicing track and spaced apart from the circuit test device; and a second conductive layer, one end of which is connected to the first pad structure and the other end of which is connected to the corresponding test port.

[0010] In addition, the circuit test device has the first pad structure on both sides; there are two second conductor layers, one of which is connected to the first pad structure on one side of the circuit test device, and the other is connected to the first pad structure on the other side of the circuit test device.

[0011] In addition, there are three first pad structures electrically connected to the circuit test device; and there are three second conductor layers, each of which electrically connects the circuit test device to the corresponding first pad structure.

[0012] Additionally, the three second conductor layers include: two straight conductors electrically connecting the circuit test device to the adjacent first pad structure; and one zigzag conductor electrically connecting the circuit test device to the first pad structure furthest from the circuit test device.

[0013] In addition, the first pad structure includes: a plurality of first conductive layers stacked together and a first conductive post electrically connected to adjacent first conductive layers; wherein the second conductive layer is in the same layer and connected to at least one of the first conductive layers.

[0014] In addition, the semiconductor wafer also includes: a plurality of second pad structures, which are located in the dicing area and spaced apart from the first pad structure; and a third conductive layer, one end of which is connected to the second pad structure and the other end of which is connected to the crack-resistant conductive structure.

[0015] In addition, the second pad structure includes: a plurality of stacked second conductive layers and a second conductive post electrically connected to adjacent second conductive layers; the crack-resistant conductive structure includes: a plurality of stacked third conductive layers and a third conductive post electrically connected to adjacent third conductive layers; the third conductive layer is in the same layer and connected to at least one second conductive layer and the third conductive layer.

[0016] In addition, the second pad structure is located on the side of the first pad structure that is away from the circuit test device.

[0017] In addition, there are two second pad structures that are electrically connected to the crack-resistant conductive structure, one of which is electrically connected to the crack-resistant conductive structure located on one side of the circuit test device, and the other is electrically connected to the crack-resistant conductive structure located on the opposite side of the circuit test device.

[0018] In addition, embodiments of the present invention also provide a testing method, comprising: providing a semiconductor wafer as described in any of the above claims; providing a first test signal to the crack-resistant conductive structure, wherein the first test signal is transmitted through the first conductive layer to the test port of the circuit test device.

[0019] In addition, the semiconductor wafer further includes: a plurality of first pad structures, the plurality of first pad structures being located in the dicing area and spaced apart from the circuit test device; a second conductive layer, one end of the second conductive layer being connected to the first pad structure and the other end being connected to the corresponding test port; the test method further includes: providing a second test signal to the first pad structure, and the second test signal being transmitted to the test port of the circuit test device through the second conductive layer.

[0020] In addition, the first test signal includes a power supply signal or a ground signal.

[0021] The technical solution provided by the embodiments of the present invention has the following advantages:

[0022] In the above technical solution, at least one first conductive layer is used to connect the circuit test device to the adjacent crack-resistant conductive structure. By providing a corresponding electrical signal to the crack-resistant conductive structure, a corresponding electrical signal is provided to the circuit test device, reducing the wiring space required for wafer inspection and thus allowing the number of circuit test devices to be increased as needed. Furthermore, the semiconductor wafer provided in this embodiment can also be applied to small-size dicing areas to solve the problem of insufficient wiring space required for testing in small-size dicing areas.

[0023] In addition, the semiconductor wafer also includes: a plurality of first pad structures and a plurality of second conductive layers. Other test ports of the circuit test device are connected to the first pad structures through the second conductive layers, thereby providing the circuit test device with the electrical signals required by the circuit test device through the first pad structures. In this embodiment of the invention, the number of first pad structures required for testing the same circuit test device is reduced, thus improving the utilization of the space in the dicing area. For example, the layout space of the first and second conductive layers in the dicing area can be increased, which is beneficial for better spatial layout of the first and second conductive layers. Furthermore, the surface of the first pad structure connected to the second conductive layer can have a larger size, thereby providing sufficient contact space between the test probe and the first pad structure, avoiding the problem of the test probe slipping out of the first pad structure or sticking into areas outside the first pad structure, thereby improving the reliability of the test results and preventing damage to the test probe. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a semiconductor wafer;

[0025] Figure 2 This is a schematic diagram of the structure of a semiconductor wafer provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic cross-sectional view of an embodiment of the present invention along the AA1 direction;

[0027] Figure 4 This is a schematic diagram of another cross-sectional structure along the AA1 direction according to an embodiment of the present invention;

[0028] Figure 5 This is a partially enlarged cross-sectional view of an embodiment of the present invention along the AA2 direction;

[0029] Figure 6 This is a schematic diagram of the structure of a semiconductor wafer provided in another embodiment of the present invention;

[0030] Figure 7 This is a schematic cross-sectional view of another embodiment of the present invention along the AA3 direction;

[0031] Figure 8 This is a schematic diagram of another cross-sectional structure along the AA3 direction according to another embodiment of the present invention. Detailed Implementation

[0032] As can be seen from the background technology, there is currently a problem in semiconductor wafer testing where there is insufficient space for wire routing in the dicing area.

[0033] Figure 1 This is a schematic diagram of the structure of a semiconductor wafer in the related art, for reference. Figure 1 The semiconductor wafer includes: a substrate 10; the substrate 10 includes a chip region 100 and a dicing region 101, the dicing region 101 being located between two adjacent chip regions 100; circuit test devices 102 are distributed in the dicing region 101, the circuit test devices 102 having a plurality of test ports; a crack-resistant conductive structure 103, the crack-resistant conductive structure 103 being distributed within the dicing region 101 and surrounding the chip region 100; a pad structure 104; the pad structure 104 being spaced apart from the circuit test devices 102; and a wire 105, one end of the wire 105 being connected to the pad structure 104, and the other end being connected to the test port of the circuit test device 102.

[0034] Depend on Figure 1It is known that when the circuit test device 102 has more than two test ports, the conductor 105 will include a zigzag conductor. The zigzag conductor will occupy a considerable portion of the space of the cut-and-cover area 101, and as the size of the cut-and-cover area 101 becomes smaller, the layout space of the conductor 105 also becomes smaller. In order to leave enough layout space for the conductor 105, the usual method is to reduce the size of the pad structure 104 in exchange for the layout space of the conductor 105.

[0035] Analysis revealed that while reducing the size of the pad structure 104 improves the utilization of its surrounding space, it also creates insufficient contact points between the test probes and the pad structure 104 during semiconductor wafer testing. This makes the probes prone to slipping out of the pad structure 104, or even piercing it, leading to instability in the Wafer Acceptance Test (WAT) and unreliable test parameters. Furthermore, the test probes are easily damaged. Therefore, reducing the size of the pad structure 104 is not suitable for solving the space shortage problem caused by the reduction in the dicing area 101.

[0036] This invention provides a semiconductor wafer and a testing method. By utilizing a crack-resistant conductive structure to change the wire layout in the dicing area, the area occupied by the wires in the dicing area is reduced, thus making better use of the space within the dicing area.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0038] Figures 2 to 5 This is a schematic diagram of the structure of a semiconductor wafer provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a semiconductor wafer provided in an embodiment of the present invention. Figure 3 for Figure 2 A schematic diagram of a cross-sectional structure cut along the AA1 direction. Figure 4 for Figure 2 A superimposed schematic diagram of another cross-sectional structure cut along the AA1 direction. Figure 5 for Figure 2 A partially enlarged schematic diagram of a cross-sectional structure cut along the AA2 direction.

[0039] refer to Figures 2 to 5In some embodiments, the semiconductor wafer includes: a substrate 20; the substrate 20 includes a plurality of chip regions 200 and dicing regions 201 located between adjacent chip regions 200; a circuit test device 202 located in the dicing region 201 and having a plurality of test ports; a crack-resistant conductive structure 203 located in the dicing region 201 and disposed around the chip regions 200, and located between the circuit test device 202 and the chip regions 200; and at least one first conductive layer 204, one end of the first conductive layer 204 being connected to a corresponding test port, and the other end being connected to the crack-resistant conductive structure 203.

[0040] By connecting the test port to the crack-resistant conductive structure 203 with at least one first conductor layer 204, the space occupied by the conductor in the cut channel area 201 is reduced. For the same circuit test device 202, the number of first pad structures 205 required for testing is reduced, thus increasing the surface area of ​​the first pad structure 205. This allows the first pad structure 205 to have sufficient space to contact the test probe, preventing the test probe from sliding out of the first pad structure 205 or sticking into areas outside the first pad structure 205, thereby improving the reliability of the test results and preventing damage to the test probe.

[0041] The semiconductor wafer provided in this embodiment will now be described in more detail with reference to the accompanying drawings.

[0042] The substrate 20 is a wafer made of semiconductor single crystal material, such as a silicon substrate, germanium substrate, silicon-germanium substrate, gallium arsenide substrate, etc. Among them, silicon is the most commonly used material, and this embodiment takes a silicon substrate as an example.

[0043] The substrate 20 has a stacked structure, which includes a dielectric layer and a conductive layer. In some embodiments, the number of conductive layers can be four; in other embodiments, the number of conductive layers can be eight. It is understood that the number of conductive layers can be adjusted according to actual needs.

[0044] Chip area 200 includes a functional device area and a sealing ring (SR, Seal Ring), with the sealing ring surrounding the functional device area. The functional device area is the central circuit area of ​​the chip's integrated circuit. The sealing ring is a multi-layered metal structure designed to protect the functional device area from cracks during the cutting process.

[0045] The dicing zone 201 defines the dicing area where a semiconductor wafer is diced into several chips, and the sealing ring is located between the dicing zone 201 and the functional device area.

[0046] The circuit test device 202 is used to simulate and test the components in the chip area 200, such as components in the functional device area like MOS transistors and storage capacitors. During chip fabrication, the same components as those in the functional device area are fabricated in the dicing area 201 using the same process. By testing the circuit test device 202 in the dicing area 201, the quality of the same components in the chip area 200 can be indirectly fed back.

[0047] Depending on the type of component simulated, the circuit test device 202 has a different number of test ports. For example, if the circuit test device 202 simulates a MOS transistor, it has 4 test ports; if it simulates a storage capacitor, it has 2 test ports, and so on. This embodiment uses the circuit test device 202 simulating a MOS transistor as an example.

[0048] The circuit test devices 202 are spaced apart on the cutting track 201. It is understood that the number of circuit test devices 202 can be reasonably set according to the size of the cutting track area 201 and the test requirements.

[0049] The crack-resistant conductive structure 203 is located within the dicing area 201 and surrounds the chip area 200. In some embodiments, for the same chip area 200, there are two parallel crack-resistant conductive structures 203 with a gap between them. The crack-resistant conductive structure 203 is used to further protect the chip area 200 from cracks generated during semiconductor wafer dicing. In some embodiments, the crack-resistant conductive structure 203 can also be used to provide electrical signals to the circuit test device 202.

[0050] The crack-resistant conductive structure 203 includes several layers of third conductive layers 21 stacked together and third conductive pillars 22 electrically connected to adjacent third conductive layers 21.

[0051] The circuit test device 202 has anti-crack conductive structures 203 on both sides, and the circuit test device 202 is connected to at least one anti-crack conductive structure 203 through the first conductive layer 204. By using the anti-crack conductive structures 203 to reduce the wiring area required for the cut track area 201, the number of first pad structures 205 required for the circuit test device 202 can also be reduced, thereby increasing the number of circuit test devices 202 as needed and improving the space utilization of the cut track area 201.

[0052] In some embodiments, the circuit test device 202 is connected to the crack-resistant conductive structures 203 on both sides through the first conductive layer 204.

[0053] Specifically, in some embodiments, there are two first conductive layers 204. One first conductive layer 204 is connected to the crack-resistant conductive structure 203 on one side of the circuit test device 202, and the other first conductive layer 204 is connected to the crack-resistant conductive structure 203 on the other side of the circuit test device 202. By providing two test signals to the crack-resistant conductive structures 203 on both sides of the circuit test device 202, a test signal is provided to the circuit test device 202. This reduces the number of first pad structures 205 required for a single circuit test device 202, thereby increasing the number of circuit test devices 202 or increasing the surface area of ​​the first pad structures 205 as needed. This ensures that the test probe has sufficient contact space with the first pad structure 205, preventing the test probe from slipping out of the first pad structure 205 or sticking into areas outside the first pad structure 205, thus improving the reliability of the test results and preventing damage to the test probe. In other embodiments, the number of first conductive layers can be greater. For a circuit test device, two anti-crack conductive structures are distributed on each side of the circuit test device, so that the first conductive layer can be connected to the conductive layers in different anti-crack conductive structures, and then provide electrical signals to the test ports of the circuit test device through the anti-crack conductive structures of different layers.

[0054] It should be noted that in some embodiments, the circuit test device has two test ports. In this case, the test of the circuit test device can be completed using two first conductive layers and a corresponding crack-resistant conductive structure. Specifically, a corresponding test signal is provided to the crack-resistant conductive structure. This test signal is transmitted to the test port of the circuit test device via the first conductive layers. Furthermore, the test signal transmitted from the test port to the crack-resistant conductive structure via the first conductive layers can also be collected.

[0055] The semiconductor wafer may further include: a plurality of first pad structures 205, the first pad structures 205 being located on the dicing area 201 and spaced apart from the circuit test device 202; and a second conductive layer 206, one end of the second conductive layer 206 being connected to the first pad structures 205 and the other end being connected to the circuit test device 202. By utilizing the first pad structures 205 to provide electrical signals to the remaining test ports of the circuit test device 202, functional testing of the circuit test device 202 is achieved. It is understood that for each circuit test device 202, the number of first pad structures 205 required is related to the number of its test ports. For example, if there are 4 test ports, then each circuit test device 202 requires 2 first pad structures 205.

[0056] In some embodiments, for a circuit test device 202, there are two first pad structures 205, which are disposed on opposite sides of the circuit test device 202. There are two second conductive layers 206, one of which is connected to the first pad structure 205 on one side of the circuit test device 202, and the other is connected to the first pad structure 205 on the other side of the circuit test device 202. By utilizing the two first pad structures 205 and the anti-crack conductive structures 203 on opposite sides of the circuit test device 202, the required electrical signals are provided to the four test ports of the circuit test device 202 to achieve functional testing of the circuit test device 202. Furthermore, the area occupied by the first conductive layers 204 and the second conductive layers 206 in the cut-and-cover area 201 is relatively small, thereby reducing the wiring area of ​​the cut-and-cover area 201.

[0057] Thus, two of the four test ports of the circuit test device 202 are connected to the crack-resistant conductive structures 203 on opposite sides of the circuit test device 202, and the other two ports are connected to the two adjacent first pad structures 205. At this time, the circuit test device 202 can be tested through the crack-resistant conductive structures 203 and the first pad structures 205.

[0058] Furthermore, the first pad structure 205 may include: a plurality of stacked first conductive layers 23 and first conductive pillars 24 electrically connected to the first conductive layers 23, wherein the second conductive layer 206 is at least on the same layer as and connected to one of the first conductive layers 23 of the first pad structure 205. The stacked structure can provide electrical signals to the first pad structure 205 through any one of the first conductive layers 23.

[0059] In some embodiments, the semiconductor wafer may further include: a plurality of second pad structures 207, the second pad structures 207 being located in the dicing area 201 and arranged at intervals from the first pad structures 205; and a third conductive layer 208, one end of which is connected to the second pad structures 207 and the other end of which is connected to the crack-resistant conductive structure 203.

[0060] In some embodiments, the second pad structure 207 is located on the side of the first pad structure 205 away from the circuit test device 202, which facilitates the connection of the circuit test device 202 to the first pad structure 205 in the cut track area 201.

[0061] The second pad structure 207 is electrically connected to the crack-resistant conductive structure 203. Therefore, a test probe can contact the second pad structure 207 to allow test signals to reach the crack-resistant conductive structure 203 via the second pad structure 207, or vice versa, so that the test signal can reach the second pad structure 207 via the crack-resistant conductive structure 203 and be detected by the test probe. Further, in some embodiments, two second pad structures 207 are electrically connected to the crack-resistant conductive structure 203. One second pad structure 207 is electrically connected to the crack-resistant conductive structure 203 on one side of the circuit test device 202, and the other second pad structure 207 is electrically connected to the crack-resistant conductive structure 203 on the opposite side of the circuit test device 202. Through these two second pad structures 207, electrical signals can be provided to the crack-resistant conductive structures 203 on opposite sides of the circuit test device 202, thereby providing electrical signals to the two test ports of the circuit test device 202.

[0062] It is understood that in some embodiments, the second pad structure 207 can be used to provide electrical signals to the crack-resistant conductive structure 203, and in turn, to the circuit test device 202. When the second pad structure 207 is used to provide electrical signals to the crack-resistant conductive structure 203, it facilitates signal access to the second pad structure 207. In other embodiments, electrical signals can also be provided directly to the crack-resistant conductive structure from the outside, thereby eliminating the need for the second pad structure and saving space in the cut track area. This allows for an increase in the number of circuit test devices or an increase in the area of ​​the first pad structure as needed.

[0063] Furthermore, the second pad structure 207 includes: a plurality of second conductive layers 25 stacked together and second conductive pillars 26 electrically connected to adjacent second conductive layers 25; the crack-resistant conductive structure 203 includes: a plurality of third conductive layers 21 stacked together and third conductive pillars 22 electrically connected to adjacent third conductive layers 21, and the third conductor layer 208 is in the same layer and connected to at least one second conductive layer 25 and the third conductive layer 21.

[0064] In some embodiments, such as Figure 3 As shown, Figure 3 for Figure 2 The schematic diagram shown illustrates the superimposed cross-sections of the second pad structures 207 on both sides along the AA1 direction. The third conductive layer 21 at the top layer is connected to the second conductive layer 25, thereby achieving electrical connection between the crack-resistant conductive structure 203 and the second pad structure 207. It can be understood that electrical connection between the crack-resistant conductive structure 203 and the second pad structure 207 can also be achieved by connecting any layer of the third conductive layer 21 to the second conductive layer 25. In other embodiments, such as... Figure 4 As shown, Figure 4 for Figure 2The diagram shows a cross-sectional view of the second pad structures 207 on both sides along the AA1 direction. Multiple layers of third conductive layers 21 are connected to the second conductive layer 25. This connection increases the stability of the electrical signal. For example, each layer of third conductive layer 21 can be connected to the second conductive layer 25 on the same layer, or at least two layers of third conductive layers 21 can be connected to the second conductive layer 25 on the same layer. It also increases testing flexibility. For instance, an electrical signal can be applied to each layer of second conductive layer 25, and then applied to the test port of the circuit test device 202 through the crack-resistant conductive structure 203, thereby measuring the electrical performance of the components on each layer separately, avoiding the situation where component performance problems can only be discovered during the final test.

[0065] It is understood that in some embodiments, the circuit test devices in the cut channel area may have different test ports. For example, in the same cut channel, there may be circuit test devices that simulate testing MOS transistors and circuit test devices that simulate testing storage capacitors. Accordingly, the corresponding electrical signals are connected to the corresponding test ports of the different circuit test devices.

[0066] This embodiment utilizes the anti-crack conductive structures 203 on both sides of the circuit test device 202, thereby reducing the number of first pad structures 205 required for the circuit test device 202. This improves the space utilization of the cut track area 201 and allows for a relative increase in the surface area of ​​the first pad structure 205 as needed. This ensures sufficient contact space between the test probe and the first pad structure 205, preventing the test probe from slipping out of the first pad structure 205 or puncturing areas outside the first pad structure 205. This enhances the reliability of the test results and prevents damage to the test probe. Alternatively, the number of circuit test devices 202 can be increased as needed to simulate testing more components in the chip area 200, thereby more accurately determining the yield of the components in the chip area 200.

[0067] Another embodiment of the present invention provides a semiconductor wafer, which is substantially the same as the aforementioned embodiment. The main differences include: in some embodiments, only the crack-resistant conductive structure on the side of the circuit test device is utilized. The semiconductor wafer provided by another embodiment of the present invention will be described below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to the aforementioned embodiments can be referred to the corresponding descriptions of the aforementioned embodiments, and will not be repeated below.

[0068] Figure 6 This is a schematic diagram of the structure corresponding to a semiconductor wafer provided in another embodiment of the present invention. Figure 7 for Figure 6 A schematic diagram of a cross-sectional structure along the AA3 direction. Figure 8 for Figure 6 Another cross-sectional view along the AA3 direction.

[0069] refer to Figure 6 The semiconductor wafer includes: a substrate 30, a chip area 300, a dicing area 301, a circuit testing device 302, a crack-resistant conductive structure 303, a first conductive layer 304, a first pad structure 305, a second conductive layer 306, a second pad structure 307, and a third conductive layer 308.

[0070] In some embodiments, for a circuit test device 302, there is one first conductive layer 304, three first pad structures 305, and three second conductive layers 306. Each second conductive layer 306 electrically connects the circuit test device 302 to the corresponding first pad structure 305. By utilizing the three first pad structures 305 and the crack-resistant conductive structure 303 on one side of the circuit test device 302, the required electrical signals are provided to the four test ports of the circuit test device 302 to achieve functional testing of the circuit test device 302. Furthermore, the area of ​​the cutaway region 301 occupied by the crack-resistant conductive structure 303 on one side and the three first pad structures 305 is smaller than the area of ​​the cutaway region 301 occupied by the four first pad structures 305, thereby achieving the goal of reducing the wiring area of ​​the cutaway region 301.

[0071] The three second conductor layers 306 include: two straight conductors electrically connecting the circuit test device 302 to the adjacent first pad structure 305; and one zigzag conductor electrically connecting the circuit test device 302 to the first pad structure 305 furthest from the circuit test device 302. The three second conductor layers 306 and one first conductor layer 304 provide the necessary electrical signals to the four test ports of the circuit test device 302 to achieve functional testing of the circuit test device 302.

[0072] In some embodiments, reference Figure 7 The crack-resistant conductive structure 303 is electrically connected to the second pad structure 307 by connecting the topmost third conductive layer 31 to the second conductive layer 35. It is understood that the electrical connection between the crack-resistant conductive structure 303 and the second pad structure 307 can also be achieved by connecting any layer of the third conductive layer 31 to the second conductive layer 35. In other embodiments, such as... Figure 4As shown, multiple layers of third conductive layers 31 are connected to the second conductive layer 35. This connection increases the stability of the electrical signal. For example, each layer of third conductive layer 31 is connected to the second conductive layer 35 on the same layer, or at least two layers of third conductive layers 31 are connected to the second conductive layer 35 on the same layer. It also increases testing flexibility. For instance, an electrical signal can be applied to each second conductive layer 35 and then applied to the test port of the circuit test device 302 through the crack-resistant conductive structure 303, thereby measuring the electrical performance of the components in each layer separately, avoiding the situation where component performance problems can only be discovered during the final test.

[0073] In some embodiments, the circuit test device 302 is tested by providing electrical signals to the crack-resistant conductive structure 303 and the three first pad structures 305 on one side of the circuit test device 302. By utilizing the crack-resistant conductive structure 303 on one side of the circuit test device 302 to change the routing pattern within the cut track area 301, the space utilization of the cut track area 301 is improved. Furthermore, the area of ​​the first pad structures 305 can be relatively increased as needed, thereby improving the stability of the contact between the probe and the first pad structures 305. Alternatively, the number of circuit test devices 302 can be increased as needed, thereby simulating the testing of more components within the chip area 300, and thus more accurately determining the yield of the components in the chip area 300.

[0074] Furthermore, this embodiment of the invention also provides a testing method, comprising: a semiconductor wafer provided in the above embodiment; providing a first test signal to a crack-resistant conductive structure, wherein the first test signal is transmitted to a test port of a circuit test device through a first conductive layer; providing a second test signal to a first pad structure, wherein the second test signal is transmitted to a test port of a circuit test device through a second conductive layer.

[0075] In some embodiments, the first test signal may be a power supply signal or a ground signal. Generally, the circuit test device 302 requires both a power supply signal and a ground signal. By providing a power supply signal or a ground signal to the crack-resistant conductive structure 303, all circuit test devices 302 in the cutting zone 301 can be used, which facilitates the testing of the entire cutting zone 301. In other embodiments, the first test signal may also be a square wave signal or an AC signal.

[0076] By utilizing the crack-resistant conductive structure 303 to provide the corresponding electrical signal to the circuit test device 302, the number of zigzag wires can be reduced, thereby reducing the wire layout space. This allows for an increase in the number of circuit test devices 302 or a relative increase in the area of ​​the first pad structure 305 as needed. This ensures sufficient contact space between the test probe and the first pad structure 305, preventing the test probe from slipping out of the first pad structure 305 or piercing areas outside the first pad structure 305. This improves the reliability of the test results and prevents damage to the test probe.

[0077] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor wafer, characterized by, The application relates to a substrate, which comprises a plurality of chip areas and a plurality of cutting path areas between the adjacent chip areas; a circuit testing device is arranged in the cutting path area and has a plurality of testing ports; a crack-preventing conductive structure is arranged in the cutting path area and around the chip area, and is arranged between the circuit testing device and the chip area; at least one first wire layer is connected at one end to the corresponding testing port and at the other end to the adjacent crack-preventing conductive structure; a plurality of second pad structures are arranged in the cutting path area and are spaced apart from the circuit testing device; and a third wire layer is connected at one end to the second pad structure and at the other end to the crack-preventing conductive structure. The crack-preventing conductive structure is arranged on the opposite sides of the circuit testing device; and the circuit testing device is connected to the crack-preventing conductive structure on at least one side through the first wire layer. The first wire layer is two, one of which is connected to the crack-preventing conductive structure on one side of the circuit testing device, and the other of which is connected to the crack-preventing conductive structure on the other side of the circuit testing device. The application further relates to a substrate, which comprises a plurality of chip areas and a plurality of cutting path areas between the adjacent chip areas; a circuit testing device is arranged in the cutting path area and has a plurality of testing ports; a plurality of first pad structures are arranged in the cutting path area and are spaced apart from the circuit testing device; and a second wire layer is connected at one end to the first pad structure and at the other end to the corresponding testing port. The first pad structure is arranged on the opposite sides of the circuit testing device; and the second wire layer is two, one of which is connected to the first pad structure on one side of the circuit testing device, and the other of which is connected to the first pad structure on the other side of the circuit testing device. The first pad structure is three in number and is electrically connected to the circuit testing device; and the second wire layer is three in number, each of which electrically connects the circuit testing device and the corresponding first pad structure. The first pad structure comprises a plurality of first conductive layers arranged in layers and a first conductive column electrically connecting the adjacent first conductive layers; the second wire layer is in the same layer as and is connected to at least one first conductive layer. The second pad structure comprises a plurality of second conductive layers arranged in layers and a second conductive column electrically connecting the adjacent second conductive layers; the crack-preventing conductive structure comprises a plurality of third conductive layers arranged in layers and a third conductive column electrically connecting the adjacent third conductive layers; and the third wire layer is in the same layer as and is connected to at least one second conductive layer and at least one third conductive layer.

2. The semiconductor wafer of claim 1, wherein, ​ 3. The semiconductor wafer of claim 2, wherein, ​ 4. The semiconductor wafer of claim 1, wherein, ​ ​ ​ 5. The semiconductor wafer of claim 4, wherein, ​ 6. The semiconductor wafer of claim 4, wherein, ​ 7. The semiconductor wafer of claim 6, wherein, ​ ​ ​ 8. The semiconductor wafer of claim 4, wherein, ​ ​ 9. The semiconductor wafer of claim 1, wherein, ​ ​ ​ 10. The semiconductor wafer of claim 4, wherein, The second pad structure is located on a side of the first pad structure away from the circuit test device.

11. The semiconductor wafer of claim 1, wherein, The number of the second pad structures electrically connected with the anti-cracking conductive structure is two, one of the second pad structures is electrically connected with the anti-cracking conductive structure located on one side of the circuit test device, and the other of the second pad structures is electrically connected with the anti-cracking conductive structure located on the other side of the circuit test device.

12. A test method characterized by, The method comprises: providing the semiconductor wafer as claimed in any one of claims 1-11; providing a first test signal to the anti-cracking conductive structure, and transmitting the first test signal to the test port of the circuit test device through the first wire layer.

13. The test method of claim 12, wherein, The semiconductor wafer further comprises: a plurality of first pad structures, the plurality of first pad structures being located in the cutting path region and being arranged apart from the circuit test device; and a second wire layer, one end of the second wire layer being connected with the first pad structure, and the other end of the second wire layer being connected with the corresponding test port. The test method further comprises: providing a second test signal to the first pad structure, and transmitting the second test signal to the test port of the circuit test device through the second wire layer.

14. The test method of claim 12, wherein, The first test signal comprises a working power supply signal or a ground signal.

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