Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate comprising a substrate and a plurality of fins standing on the substrate, the substrate comprising adjacent first and second regions along an arrangement direction of the plurality of fins; wherein along the arrangement direction of the fins, fins of the first region are inclined toward a side away from the second region, and fins of the second region are inclined toward a side away from the first region; an isolation layer on the substrate and surrounding the fins, the isolation layer covering part of sidewalls of the fins; a gate structure on the isolation layer and across the fins; first source / drain doped regions in the fins on both sides of the gate structure of the first region; and second source / drain doped regions in the fins on both sides of the gate structure of the second region, and along the arrangement direction of the fins, the second source / drain doped regions have a spacing from the first source / drain doped regions. Embodiments of the present application reduce the probability of bridging between the first source / drain doped regions and the second source / drain doped regions.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In semiconductor manufacturing, with the development trend of ultra-large scale integrated circuits, the feature size of integrated circuits continues to decrease, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened. However, as the device channel length is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate structure on the channel is also deteriorated, and the difficulty of the gate voltage to pinch off the channel is also increasing, making the subthreshold leakage phenomenon, i.e. the so-called short channel effect (SCE) more likely to occur.

[0003] Therefore, in order to better adapt to the decrease of feature size, semiconductor technology gradually begins to transition from planar MOSFET to three-dimensional transistor with higher efficiency, such as FinFET. In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides, compared with planar MOSFET, the control ability of the gate structure on the channel is stronger, and the short channel effect can be well suppressed; and FinFET has better compatibility with existing integrated circuit manufacturing compared with other devices.

[0004] However, the performance of the device still needs to be improved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which optimizes the performance of the semiconductor structure.

[0006] To solve the above problems, the embodiment of the present application provides a semiconductor structure, comprising: a substrate comprising a substrate and a plurality of fins standing on the substrate, the substrate comprising adjacent first and second regions along the arrangement direction of the plurality of fins, the first and second regions being used for forming first and second transistors respectively; wherein along the arrangement direction of the fins, the fins of the first region are inclined towards a side away from the second region, and the fins of the second region are inclined towards a side away from the first region; an isolation layer located on the substrate and surrounding the fins, the isolation layer covering part of the sidewalls of the fins; a gate structure located on the isolation layer and across the fins; a first source-drain doped region located in the fins on both sides of the gate structure of the first region; a second source-drain doped region located in the fins on both sides of the gate structure of the second region, and there is a gap between the second source-drain doped region and the first source-drain doped region along the arrangement direction of the fins.

[0007] Optionally, the isolation layer on both sides of the fins of the first and second regions also has doped ions, and the doped ions are adapted to make the thermal expansion coefficient of the isolation layer material doped with the ions greater than the thermal expansion coefficient of the isolation layer material located between the fins of the first and second regions.

[0008] Optionally, the doped ions include one or both of nitrogen ions and carbon ions.

[0009] Optionally, the doping depth of the doped ions in the isolation layer is 0-100 nm.

[0010] Optionally, the angle of inclination of the fins of the first and second regions is 1-5°.

[0011] Optionally, the channel conductive types of the first and second transistors are the same; the substrate further comprises a third region for forming a third transistor, the channel conductive type of the third transistor being different from the channel conductive types of the first and second transistors; and the semiconductor structure further comprises: a third source-drain doped region located in the fins on both sides of the gate structure of the third region.

[0012] Optionally, the material of the substrate comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide; the material of the fin comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide; the material of the isolation layer comprises one or both of silicon oxide and silicon oxynitride; and the material of the gate structure comprises any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0013] Optionally, the semiconductor structure further comprises a gate dielectric layer between the gate structure and the fin.

[0014] Optionally, the material of the gate dielectric layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0015] Optionally, the substrate comprises an SRAM device, the first transistor is a first pull-up transistor, and the second transistor is a second pull-up transistor.

[0016] Correspondingly, the embodiments of the present application also provide a method for forming a semiconductor structure, comprising: providing a substrate comprising a substrate and a plurality of fins standing on the substrate, the substrate comprising a first region and a second region adjacent to each other along the arrangement direction of the plurality of fins, the first region and the second region being used for forming a first transistor and a second transistor respectively; forming an isolation layer around the fins on the substrate, the isolation layer exposing part of the sidewalls of the fins; ion-doping the isolation layer on both sides of the fins in the first region and the second region, so as to increase the thermal expansion coefficient of the material of the isolation layer; and forming a gate structure on the isolation layer and across the fins, a first source-drain doped region in the fin on both sides of the gate structure in the first region, and a second source-drain doped region in the fin on both sides of the gate structure in the second region.

[0017] Optionally, in the step of ion-doping the isolation layer on both sides of the fins in the first region and the second region, the doping ions comprise one or both of nitrogen ions and carbon ions.

[0018] Optionally, the ion-doping is performed by an ion implantation process.

[0019] Optionally, in the step of ion-doping the isolation layer on both sides of the fins in the first region and the second region, the doping depth of the doping ions in the isolation layer is 0 nm to 100 nm.

[0020] Optionally, the step of ion-doping the isolation layer on both sides of the fin in the first region and the second region comprises: forming a cover layer covering the isolation layer and the fin on the first region and the second region; taking the cover layer as a mask, ion-doping the isolation layer.

[0021] Optionally, the channel conductive types of the first transistor and the second transistor are the same; the substrate further comprises a third region for forming a third transistor, the channel conductive type of the third transistor is different from the channel conductive types of the first transistor and the second transistor; the method for forming the semiconductor structure further comprises: after forming the isolation layer, before ion-doping, forming a pseudo-gate structure across the fin on the isolation layer, the pseudo-gate structure covering part of the top and part of the sidewall of the fin; after ion-doping, before forming the first source-drain doped region and the second source-drain doped region, taking the cover layer as a mask, forming a third source-drain doped region in the fin on both sides of the pseudo-gate structure in the third region.

[0022] Optionally, the method for forming the semiconductor structure further comprises: after forming the third source-drain doped region, before forming the first source-drain doped region and the second source-drain doped region, removing the cover layer; the step of forming the first source-drain doped region and the second source-drain doped region comprises: in the same step, forming source-drain doped regions in the fin on both sides of the pseudo-gate structure in the first region and the second region, the source-drain doped region in the first region serving as the first source-drain doped region, and the source-drain doped region in the second region serving as the second source-drain doped region.

[0023] Optionally, the step of forming the gate structure comprises: after forming the first source-drain doped region and the second source-drain doped region, removing the pseudo-gate structure to form a gate opening; forming the pseudo-gate structure in the gate opening.

[0024] Optionally, the material of the isolation layer comprises one or both of silicon oxide and silicon oxynitride.

[0025] Optionally, the first transistor and the second transistor are used to form an SRAM device, the first transistor is a first pull-up transistor, and the second transistor is a second pull-up transistor.

[0026] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0027] The semiconductor structure provided by the embodiment of the present application is characterized in that, along the arrangement direction of the fins, the fins of the first region are inclined towards the side away from the second region, and the fins of the second region are inclined towards the side away from the first region, so as to increase the interval between the fins at the junction of the first region and the second region, provide more space for forming the first source / drain doped region and the second source / drain doped region, increase the distance between the first source / drain doped region and the second source / drain doped region, and further reduce the probability of bridging between the first source / drain doped region and the second source / drain doped region, thereby optimizing the performance of the semiconductor structure.

[0028] In an optional solution, the isolation layer on both sides of the fins of the first region and the second region is further doped with ions, and the doped ions are adapted to make the thermal expansion coefficient of the isolation layer material doped with the ions greater than the thermal expansion coefficient of the isolation layer material between the fins of the first region and the second region. Therefore, compared with the isolation layer between the fins of the first region and the second region, the thermal expansion coefficient of the isolation layer material on both sides of the fins of the first region and the second region is greater, and the volume of the isolation layer on both sides of the fins of the first region and the second region is reduced more greatly after the temperature decreases, so as to release part of the stress in the isolation layer, so that the fins of the first region and the second region can be inclined towards the side away from each other along the arrangement direction of the fins. Moreover, the fins of the first region and the second region are inclined by doping ions in the isolation layer on both sides of the fins of the first region and the second region, so as to increase the distance between the first source / drain doped region and the second source / drain doped region, which is less likely to change the semiconductor structure and is also beneficial to reducing the risk and improving the compatibility.

[0029] In the forming method of the semiconductor structure provided by the embodiment of the present application, the isolation layer on both sides of the fins of the first region and the second region is doped with ions, which is adapted to increase the thermal expansion coefficient of the isolation layer material. Therefore, compared with the isolation layer between the fins of the first region and the second region, the thermal expansion coefficient of the isolation layer material on both sides of the fins of the first region and the second region is greater, and the volume of the isolation layer on both sides of the fins of the first region and the second region is reduced more greatly after the temperature decreases, so as to release part of the stress in the isolation layer, so that the fins of the first region are inclined towards the side away from the second region, and the fins of the second region are inclined towards the side away from the first region along the arrangement direction of the fins, so as to increase the interval between the fins at the junction of the first region and the second region, provide more space for forming the first source / drain doped region and the second source / drain doped region, increase the distance between the first source / drain doped region and the second source / drain doped region, and further reduce the probability of bridging between the first source / drain doped region and the second source / drain doped region, thereby optimizing the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figures 1-2 is a structural schematic diagram of a semiconductor structure;

[0031] Figures 3-4 is a structural schematic diagram of an embodiment of the semiconductor structure of the present application;

[0032] Figures 5-14 is a structural schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0033] As known from the background art, the performance of the device still needs to be improved. The reasons why the performance of the device needs to be improved will be analyzed in combination with a semiconductor structure.

[0034] Reference Figures 1-2 , Figure 1 is a plan view, Figure 2 is Figure 1 is a structural schematic diagram of a semiconductor structure along the direction of 1-1'.

[0035] Taking the semiconductor structure as an example, the semiconductor structure includes: a substrate including a substrate 10 and a plurality of fins 11 standing on the substrate 10, the substrate 10 includes adjacent first and second regions 10U1 and 10U2 along the arrangement direction of the plurality of fins 11, the first and second regions 10U1 and 10U2 are respectively used for forming first and second transistors; a gate structure 12 located on the substrate 10 and crossing the fins 11; source-drain doped regions 13 located in the fins 11 on both sides of the gate structure 12.

[0036] As shown in Figure 1 , in the semiconductor structure, the first and second regions 10U1 and 10U2 are respectively used for forming first and second transistors, specifically, the first transistor is a first pull-up transistor, the second transistor is a second pull-up transistor, and the source-drain doped regions 13 of the first region 10U1 and the source-drain doped regions 13 of the second region 10U2 are spaced apart.

[0037] However, as the device size is continuously scaled down, the distance between the adjacent fins 11 of the first region 10U1 and the second region 10U2 gradually decreases, the distance between the source-drain doped regions 13 of the first region 10U1 and the source-drain doped regions 13 of the second region 10U2 becomes closer and closer, and the source-drain doped regions 13 of the first region 10U1 and the source-drain doped regions 13 of the second region 10U2 are usually formed in the same step during the formation of the semiconductor structure, which results in a higher probability of bridging between the source-drain doped regions 13 of the first region 10U1 and the source-drain doped regions 13 of the second region 10U2.

[0038] One solution is to form the source-drain doped regions of the first region and the source-drain doped regions of the second region in different steps respectively during the formation of the semiconductor structure, but this increases the process flow and process cost.

[0039] Another solution is to make the source-drain doped regions of the first region deviate from the side of the second region and make the source-drain doped regions of the second region deviate from the side of the first region during the formation of the source-drain doped regions during the formation of the semiconductor structure. However, the stress center of the source-drain doped regions deviating from one side is not on the same axis as the center of the fin, which has the risk of stress degradation and thus easily reduces the performance of the semiconductor structure.

[0040] To solve the technical problem, the embodiments of the present application provide a semiconductor structure, comprising: a substrate comprising a substrate and a plurality of fins standing on the substrate, the substrate comprising adjacent first and second regions along the arrangement direction of the plurality of fins, the first and second regions being used to form a first transistor and a second transistor respectively; wherein, along the arrangement direction of the fins, the fins of the first region are inclined towards the side away from the second region, and the fins of the second region are inclined towards the side away from the first region; an isolation layer located on the substrate and surrounding the fins, the isolation layer covering part of the sidewalls of the fins; a gate structure located on the isolation layer and crossing the fins; a first source-drain doped region located in the fins on both sides of the gate structure of the first region; a second source-drain doped region located in the fins on both sides of the gate structure of the second region, and the second source-drain doped region and the first source-drain doped region have a spacing therebetween along the arrangement direction of the fins.

[0041] The semiconductor structure provided by the embodiment of the present application is characterized in that, along the arrangement direction of the fins, the fins of the first region are inclined towards the side away from the second region, and the fins of the second region are inclined towards the side away from the first region, so as to increase the spacing between the fins at the junction of the first region and the second region, provide more space for the formation of the first source / drain doped region and the second source / drain doped region, increase the distance between the first source / drain doped region and the second source / drain doped region, and thus reduce the probability of bridging between the first source / drain doped region and the second source / drain doped region, and optimize the performance of the semiconductor structure.

[0042] In an optional solution, the isolation layer on both sides of the fins of the first region and the second region is doped with ions, and the thermal expansion coefficient of the isolation layer material doped with the ions is greater than the thermal expansion coefficient of the isolation layer material between the fins of the first region and the second region. Therefore, compared with the isolation layer between the fins of the first region and the second region, the thermal expansion coefficient of the isolation layer material on both sides of the fins of the first region and the second region is greater, and the volume of the isolation layer on both sides of the fins of the first region and the second region decreases more greatly after the temperature decreases, so as to release part of the stress in the isolation layer, so that the fins of the first region and the second region can be inclined towards the side away from each other along the arrangement direction of the fins. Moreover, by doping the isolation layer on both sides of the fins of the first region and the second region with ions to incline the fins of the first region and the second region, the distance between the first source / drain doped region and the second source / drain doped region is increased, and the semiconductor structure is changed little, which is also beneficial to reduce the risk and improve the compatibility.

[0043] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that the embodiments of the present application and the characteristics in the embodiments can be combined with each other. Figures 3-4 , Figure 3 is a top view, Figure 4 is a top view, Figure 3 is a sectional view along the 1-1' line, and shows the structure schematic diagram of the semiconductor structure according to an embodiment of the present application.

[0044] In the embodiment, the semiconductor structure comprises: a substrate, comprising a substrate 100 and a plurality of fin portions 110 standing on the substrate 100, the substrate 100 comprising adjacent first and second regions I and II along the arrangement direction of the plurality of fin portions 110, the first and second regions I and II being used for forming first and second transistors respectively; wherein along the arrangement direction of the fin portions 110, the fin portions 110 of the first region I are inclined towards a side away from the second region II, and the fin portions 110 of the second region II are inclined towards a side away from the first region I; an isolation layer 120 located on the substrate 100 and surrounding the fin portions 110, the isolation layer 120 covering part of the sidewalls of the fin portions 110; a gate structure 190 located on the isolation layer 120 and across the fin portions 110; first source-drain doped regions 170 located in the fin portions 110 on both sides of the gate structure 190 of the first region I; and second source-drain doped regions 180 located in the fin portions 110 on both sides of the gate structure 190 of the second region II, the second source-drain doped regions 180 and the first source-drain doped regions 170 being spaced apart along the arrangement direction of the fin portions 110.

[0045] The substrate is used to provide a process platform for forming the semiconductor structure.

[0046] In the embodiment, the substrate comprises a substrate 100, and the material of the substrate 100 comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium. As an example, the substrate 100 is a silicon substrate, i.e., the material of the substrate 100 is monocrystalline silicon.

[0047] The substrate 100 comprises adjacent first and second regions I and II along the arrangement direction of the plurality of fin portions 110, the first and second regions I and II being used for forming first and second transistors respectively.

[0048] In the embodiment, the substrate comprises an SRAM device, and the SRAM device comprises a plurality of SRAM cells. The number of SRAM cells included in the SRAM device can be one or more.

[0049] Correspondingly, in the embodiment, the first and second transistors are used to form an SRAM device. Specifically, the first transistor is a first pull-up transistor, the second transistor is a second pull-up transistor, and the first and second transistors have the same channel conductivity type. In the embodiment, the first and second transistors are both PMOS transistors.

[0050] In this embodiment, the substrate 100 further includes a third region III for forming a third transistor, the channel conductivity type of which is different from that of the first transistor and the second transistor. Accordingly, in this embodiment, the third transistor is an NMOS transistor.

[0051] In this embodiment, the third region III includes a first sub-region III (1) located on the side of the first region I away from the second region II along the arrangement direction of the fins 110, and a second sub-region III (2) located on the side of the second region II away from the first region I. In this embodiment, the first sub-region III (1) is used to form a first pull-down transistor, and the second sub-region III (2) is used to form a second pull-down transistor. The first pull-down transistor, the second pull-down transistor, the first pull-up transistor, and the second pull-up transistor constitute an SRAM cell.

[0052] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET), and the fin 110 is used to provide a conductive channel for the fin field-effect transistor.

[0053] Along the arrangement direction of the fins 110, the fins 110 of the first region I are inclined toward the side away from the second region II, and the fins 110 of the second region II are inclined toward the side away from the first region I. This increases the spacing between the fins 110 at the junction of the first region I and the second region II, providing a larger formation space for the first source / drain doped region 170 and the second source / drain doped region 180, increasing the distance between the first source / drain doped region 170 and the second source / drain doped region 180, thereby reducing the probability of bridging between the first source / drain doped region 170 and the second source / drain doped region 180 and optimizing the performance of the semiconductor structure.

[0054] It should be noted that the angle α of the inclination of the fins 110 in the first region I and the second region II (e.g., Figure 4 The angle α (as shown) should not be too small or too large. If the tilt angle α of the fins 110 in the first region I and the second region II is too small, the effect of increasing the spacing between the fins 110 at the junction of the first region I and the second region II will not be significant, and the corresponding reduction in the probability of bridging between the first source / drain doped region 170 and the second source / drain doped region 180 will not be significant. If the tilt angle α of the fins 110 in the first region I and the second region II is too large, it will easily increase the process risk and the probability of affecting device performance. Therefore, in this embodiment, the tilt angle α of the fins 110 in the first region I and the second region II is 1° to 5°, for example: 2°, 3°, 4°, etc.

[0055] In the embodiment, the angle a of the tilt of the fin 110 of the first region I and the second region II refers to the included angle between the fin 110 of the first region I and the second region II and the normal line of the substrate 100.

[0056] In the embodiment, the fin 110 and the substrate 100 are in an integrated structure. In other embodiments, the fin can also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

[0057] In the embodiment, the material of the fin 110 is the same as the material of the substrate 100, and the material of the fin 110 is silicon. In other embodiments, the material of the fin can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The material of the fin can also be different from the material of the substrate.

[0058] The isolation layer 120 is used to isolate adjacent fins 110, and the isolation layer 120 is also used to isolate the substrate 100 and the gate structure 190.

[0059] The material of the isolation layer 120 is an insulating material. In the embodiment, the material of the isolation layer 120 includes one or both of silicon oxide and silicon oxynitride.

[0060] In the embodiment, for the convenience of clear illustration and description, only the isolation layer 120 is illustrated in the cross-sectional view.

[0061] In the embodiment, the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II also has a doping ion, and the doping ion is suitable for making the thermal expansion coefficient of the material of the isolation layer 120 doped with the ion greater than the thermal expansion coefficient of the material of the isolation layer 120 located between the fins 110 of the first region I and the second region II.

[0062] Therefore, compared with the isolation layer 120 located between the fins 110 of the first region I and the second region II, the thermal expansion coefficient of the material of the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II is greater, and after the temperature decreases, the volume of the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II decreases more greatly, so as to release part of the stress in the isolation layer 120, so that the fin 110 of the first region I and the fin 110 of the second region II can tilt towards the side away from each other in the arrangement direction of the fin 110.

[0063] Furthermore, the first region I and the second region II are inclined by doping ions in the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II, so as to increase the distance between the first source / drain doped region 170 and the second source / drain doped region 180, and the modification of the semiconductor structure is small, and the risk is reduced and the compatibility is improved.

[0064] In the embodiment, the material of the substrate 100 and the fin 110 is silicon, and the material of the isolation layer 120 is silicon oxide.

[0065] In the embodiment, the doping ions include one or both of nitrogen ions and carbon ions.

[0066] When the doping ions are nitrogen ions, the material of the isolation layer 120 is changed into nitrogen-doped silicon oxide or silicon nitride, the thermal expansion coefficient of silicon nitride is greater than that of silicon oxide, and by doping nitrogen ions in the isolation layer 120, the thermal expansion coefficient of the isolation layer 120 is closer to that of silicon nitride, which is conducive to increasing the thermal expansion coefficient of the isolation layer 120, and the thermal expansion coefficient of the material of the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II is greater than that of the isolation layer 120 between the fins 110 of the first region I and the second region II, and the stress in the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II is released.

[0067] When the doping ions are carbon ions, the material of the isolation layer 120 is changed into carbon-doped silicon oxide or silicon carbide, the thermal expansion coefficient of silicon carbide is greater than that of silicon oxide, and by doping carbon ions in the isolation layer 120, the thermal expansion coefficient of the isolation layer 120 is closer to that of silicon carbide, which is conducive to increasing the thermal expansion coefficient of the isolation layer 120, and the thermal expansion coefficient of the material of the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II is greater than that of the isolation layer 120 between the fins 110 of the first region I and the second region II, and the stress in the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II is released.

[0068] In the embodiment, the doping ions are nitrogen ions as an example.

[0069] It should be noted that the doping depth of the doping ions in the isolation layer 120 should not be too large, otherwise the doping ions are easy to be doped into the substrate 100 and the fin 110 below the source-drain doping region, which is easy to affect the electrical performance of the device. Therefore, in the embodiment, the doping depth of the doping ions in the isolation layer 120 is 0 nm to 100 nm.

[0070] The gate structure 190 serves as a device gate structure for controlling the opening and closing of the conductive channel. The gate structure 190 is located on the isolation layer 120 and covers part of the top and part of the sidewall of the fin 110.

[0071] In the embodiment, the gate structure 190 is a metal gate structure. The material of the gate structure 190 includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

[0072] In specific implementation, the gate structure 190 can include a work function layer (not shown in the figure) and a gate electrode layer (not shown in the figure) located on the work function layer.

[0073] The work function layer is used to adjust the work function of the gate structure 190, thereby adjusting the threshold voltage of the field effect transistor. The gate electrode layer is used as an external electrode for electrical connection between the gate structure 190 and the external circuit.

[0074] In the embodiment, the gate structure 190 is taken as an example for illustration as a metal gate structure. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0075] In the embodiment, the semiconductor structure further includes a gate dielectric layer (not shown in the figure) located between the gate structure 190 and the fin 110.

[0076] The gate dielectric layer is used to achieve electrical isolation between the gate structure 190 and the fin 110.

[0077] The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0078] The first source-drain doping region 170 is used as the source or drain of the first transistor.

[0079] In this embodiment, the first source-drain doped region 170 includes a stress layer doped with ions, and the stress layer is configured to provide stress to a channel region to increase mobility of carriers.

[0080] In this embodiment, the first transistor is a PMOS transistor, and the first source-drain doped region 170 is doped with P-type ions. Specifically, the first source-drain doped region 170 includes a stress layer doped with P-type ions, and the stress layer is made of Si or SiGe.

[0081] The second source-drain doped region 180 is configured to serve as a source or a drain of the second transistor.

[0082] In this embodiment, the second source-drain doped region 180 includes a stress layer doped with ions, and the stress layer is configured to provide stress to a channel region to increase mobility of carriers.

[0083] In this embodiment, the second transistor is a PMOS transistor, and the second source-drain doped region 180 is doped with P-type ions. Specifically, the second source-drain doped region 180 includes a stress layer doped with P-type ions, and the stress layer is made of Si or SiGe.

[0084] In this embodiment, the second source-drain doped region 180 is doped with the same type of ions as the first source-drain doped region 170, and the second source-drain doped region 180 is made of the same material as the first source-drain doped region 170, because the second source-drain doped region 180 and the first source-drain doped region 170 are formed in the same step during formation of the semiconductor structure.

[0085] In this embodiment, the semiconductor structure further includes a third source-drain doped region 160 located in the fin 110 on both sides of the gate structure 190 of the third region III.

[0086] The third source-drain doped region 160 is configured to serve as a source or a drain of the third transistor.

[0087] Specifically, the third source-drain doped region 160 of the first sub-region III(1) is configured to serve as a source or a drain of the first pull-down transistor, and the third source-drain doped region 160 of the second sub-region III(2) is configured to serve as a source or a drain of the second pull-down transistor.

[0088] In this embodiment, the third source-drain doped region 160 includes a stress layer doped with ions, and the stress layer is configured to provide stress to a channel region to increase mobility of carriers.

[0089] In this embodiment, the third transistor is an NMOS, and the third source-drain doped region 160 includes a stress layer doped with N-type ions, and the stress layer is made of Si or SiC.

[0090] Correspondingly, the application further provides a semiconductor structure forming method. Figures 5-14 is a structure diagram corresponding to each step in an embodiment of the semiconductor structure forming method of the application.

[0091] The semiconductor structure forming method of the embodiment will be described in detail below with reference to the drawings.

[0092] Reference Figure 5 , a substrate is provided, including a substrate 100 and a plurality of fin portions 110 standing on the substrate 100, the substrate 100 includes adjacent first and second regions I along the arrangement direction of the plurality of fin portions 110, the first and second regions I are respectively used for forming first and second transistors.

[0093] The substrate is used to provide a process platform for subsequent processes.

[0094] In the embodiment, the substrate includes a substrate 100, and the material of the substrate 100 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium. As an example, the substrate 100 is a silicon substrate, i.e., the material of the substrate 100 is monocrystalline silicon.

[0095] The substrate 100 includes adjacent first and second regions I along the arrangement direction of the plurality of fin portions 110, the first and second regions I are respectively used for forming first and second transistors.

[0096] In the embodiment, the forming method is used to form an SRAM device, and the SRAM device includes a plurality of SRAM cells. The number of SRAM cells included in the SRAM device can be one or more.

[0097] Correspondingly, in the embodiment, the first and second transistors are used to form an SRAM device. Specifically, the first transistor is a first pull-up transistor, the second transistor is a second pull-up transistor, and the channel conductive types of the first and second transistors are the same. In the embodiment, the first and second transistors are both PMOS transistors.

[0098] In the embodiment, the substrate 100 further includes a third region III for forming a third transistor, and the channel conductive type of the third transistor is different from that of the first and second transistors. Correspondingly, in the embodiment, the third transistor is an NMOS transistor.

[0099] In this embodiment, the third region III includes a first sub-region III(1) on the side of the first region I away from the second region II along the arrangement direction of the fin 110, and a second sub-region III(2) on the side of the second region II away from the first region I. In this embodiment, the first sub-region III(1) is used to form a first pull-down transistor, and the second sub-region III(2) is used to form a second pull-down transistor. The first pull-down transistor, the second pull-down transistor, the first pull-up transistor, and the second pull-up transistor constitute an SRAM cell.

[0100] In this embodiment, the substrate is used to form a fin field effect transistor, and the fin 110 is used to provide a conductive channel of the fin field effect transistor.

[0101] In this embodiment, the fin 110 and the substrate 100 are in an integrated structure. In other embodiments, the fin can also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

[0102] In this embodiment, the material of the fin 110 is the same as the material of the substrate 100, and the material of the fin 110 is silicon. In other embodiments, the material of the fin can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The material of the fin can also be different from the material of the substrate.

[0103] Reference is made to Figure 6 An isolation layer 120 is formed on the substrate 100 to surround the fin 110, and the isolation layer 120 exposes part of the sidewall of the fin 110. The top surface of the isolation layer 120 is lower than the top surface of the fin 110.

[0104] The isolation layer 120 is used to isolate adjacent fins 110, and the isolation layer 120 is also used to isolate the substrate 100 and a subsequently formed gate structure.

[0105] The material of the isolation layer 120 is an insulating material. In this embodiment, the material of the isolation layer 120 includes one or both of silicon oxide and silicon oxynitride.

[0106] In this embodiment, for the convenience of clear illustration and description, only the isolation layer 120 is illustrated in the cross-sectional view.

[0107] Reference is made to Figure 7 A top view is shown, and the method for forming the semiconductor structure further includes: after the isolation layer 120 is formed, a dummy gate structure 140 is formed on the isolation layer 120 to span the fin 110, and the dummy gate structure 140 covers part of the top and part of the sidewall of the fin 110.

[0108] The dummy gate structure 140 is used to occupy space position for subsequent formation of gate structure.

[0109] The dummy gate structure 140 covers part of the top and part of the sidewall of the fin 110, and the extension direction of the dummy gate structure 140 is perpendicular to the extension direction of the fin 110.

[0110] The dummy gate structure 140 can be a laminated structure or a single layer structure. In the embodiment, the dummy gate structure 140 is a laminated structure, which includes a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) located on the dummy gate oxide layer.

[0111] Specifically, in the embodiment, the dummy gate structure 140 is a polysilicon gate structure, the material of the dummy gate oxide layer is silicon oxide or silicon oxynitride, and the material of the dummy gate layer is polysilicon or amorphous silicon.

[0112] Reference Figures 8-10 , Figure 8 is a top view, Figure 9 is Figure 8 is a cross-sectional view along the 1-1' cutting line, Figure 10 is a cross-sectional view based on Figure 9 The isolation layer 120 located on both sides of the fin 110 in the first region I and the second region II is ion doped 130, which is suitable for increasing the thermal expansion coefficient of the material of the isolation layer 120.

[0113] Therefore, compared with the isolation layer 120 located between the fins 110 in the first region I and the second region II, the thermal expansion coefficient of the material of the isolation layer 120 located on both sides of the fin 110 in the first region I and the second region II is larger, and after the temperature decreases, the volume of the isolation layer 120 located on both sides of the fin 110 in the first region I and the second region II decreases more greatly, which can release part of the stress in the isolation layer 120, so that in the arrangement direction of the fin 110, the fin 110 in the first region I tilts towards the side away from the second region II, and the fin 110 in the second region II tilts towards the side away from the first region I, thereby increasing the spacing between the fins 110 at the junction of the first region I and the second region II, providing more space for the formation of the first source / drain doping region in the fin 110 in the first region I and the second source / drain doping region in the fin 110 in the second region II, increasing the distance between the first source / drain doping region and the second source / drain doping region, and further reducing the probability of bridging between the first source / drain doping region and the second source / drain doping region, thereby optimizing the performance of the semiconductor structure.

[0114] In the embodiment, the doping ions include one or both of nitrogen ions and carbon ions.

[0115] In the embodiment, the material of the substrate 100 and the fin 110 is silicon, and the material of the isolation layer 120 is silicon oxide.

[0116] When the doping ions are nitrogen ions, the material of the isolation layer 120 is changed into nitrogen-doped silicon oxide or silicon nitride oxide. The thermal expansion coefficient of silicon nitride is greater than that of silicon oxide. By doping nitrogen ions in the isolation layer 120, the thermal expansion coefficient of the isolation layer 120 is closer to that of silicon nitride, which is conducive to increasing the thermal expansion coefficient of the isolation layer 120. As a result, the thermal expansion coefficient of the material of the isolation layer 120 on both sides of the fin 110 in the first region I and the second region II is greater than that of the isolation layer 120 between the fins 110 in the first region I and the second region II, which is conducive to releasing the stress in the isolation layer 120 on both sides of the fin 110 in the first region I and the second region II.

[0117] When the doping ions are carbon ions, the material of the isolation layer 120 is changed into carbon-doped silicon oxide or silicon carbide oxide. The thermal expansion coefficient of silicon carbide is greater than that of silicon oxide. By doping carbon ions in the isolation layer 120, the thermal expansion coefficient of the isolation layer 120 is closer to that of silicon carbide, which is conducive to increasing the thermal expansion coefficient of the isolation layer 120. As a result, the thermal expansion coefficient of the material of the isolation layer 120 on both sides of the fin 110 in the first region I and the second region II is greater than that of the isolation layer 120 between the fins 110 in the first region I and the second region II, which is conducive to releasing the stress in the isolation layer 120 on both sides of the fin 110 in the first region I and the second region II.

[0118] In the embodiment, the doping ions are taken as nitrogen ions as an example for illustration.

[0119] It is to be noted that, in the step of ion doping 130 of the isolation layer 120 on both sides of the fin 110 in the first region I and the second region II, the doping depth of the doping ions in the isolation layer 120 should not be too large, otherwise the doping ions are easily doped into the fin 110 below the substrate 100 and the source / drain doping region, which is likely to affect the electrical performance of the device. Therefore, in the embodiment, the doping depth of the doping ions in the isolation layer 120 is 0 nm to 100 nm.

[0120] In the embodiment, the step of ion doping 130 to the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II includes: forming a cover layer 150 covering the isolation layer 120 and the fin 110 on the first region I and the second region II as shown in Figures 8-9 ; and Figure 10 doping the isolation layer 120 with the ion doping 130 using the cover layer 150 as a mask.

[0121] The cover layer 150 is used as a mask for ion doping.

[0122] In the embodiment, the material of the cover layer 140 is a bottom anti-reflective coating (BARC).

[0123] In the embodiment, the ion doping 130 is performed by an ion implantation process. The ion implantation process is easy to control the implantation angle and implantation energy of the ion so that the doping depth and doping position of the ion in the isolation layer 120 meet the process requirements, and is also easy to control the implantation dose of the ion so that the doping concentration in the isolation layer 120 meets the process requirements, thereby significantly increasing the thermal expansion coefficient of the material of the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II, and significantly increasing the formation space and pitch of the subsequent first source / drain doping region and the second source / drain doping region, while also reducing the process risk.

[0124] In the embodiment, after the ion doping 130, the angle a of the fin 110 of the first region I and the second region II is 1° to 5°, for example, 2°, 3°, 4°, etc., thereby significantly reducing the probability of bridging between the first source / drain doping region 170 and the second source / drain doping region 180, while also reducing the process risk and the probability of affecting the performance of the device, thereby ensuring the performance of the device.

[0125] For reference Figure 11 and Figure 12 , Figure 11 is a top view, Figure 12 is Figure 11 a cross-sectional view along the 1-1' cutting line. In the embodiment, the method for forming the semiconductor structure further includes: after the ion doping 130, forming a third source / drain doping region 160 in the fin 110 on both sides of the pseudo gate structure 150 of the third region III using the cover layer 150 as a mask.

[0126] During the formation of the third source / drain doping region 160, the cover layer 150 can protect the fin 110 of the first region I and the second region II.

[0127] The third source-drain doped region 160 is used as a source or a drain of the third transistor.

[0128] Specifically, the third source-drain doped region 160 of the first sub-region III(1) is used as a source or a drain of the first pull-down transistor, and the third source-drain doped region 160 of the second sub-region III(2) is used as a source or a drain of the second pull-down transistor.

[0129] In this embodiment, after the ion doping 130, the cover layer 150 is used as a mask for forming the third source-drain doped region 160, so that the process of ion doping 130 and the process of forming the third source-drain doped region 160 are integrated, the process compatibility and process integration degree are improved, and the ion doping 130 and the formation of the third source-drain doped region 160 can share one mask, which is beneficial to save process cost.

[0130] In this embodiment, the third source-drain doped region 160 includes a stress layer doped with ions, and the stress layer is used to provide stress for the channel region, so as to improve the mobility of the carriers.

[0131] In this embodiment, the third transistor is an NMOS, and the third source-drain doped region 160 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0132] Specifically, in this embodiment, the step of forming the third source-drain doped region 160 includes: forming a first recess (not shown in the figure) in the fin 110 on both sides of the pseudo-gate structure 140 of the third region III, taking the cover layer 150 as a mask; and forming the third source-drain doped region 160 in the first recess.

[0133] The first recess is used to provide a spatial position for forming the third source-drain doped region 160.

[0134] In this embodiment, an epitaxial process is used to form the third source-drain doped region 160 in the first recess.

[0135] It should be noted that the method for forming the semiconductor structure further includes: after forming the third source-drain doped region 160, removing the cover layer 180 to expose the fin 110 of the first region I and the second region II, thereby facilitating the subsequent process.

[0136] Reference Figures 13-14 , Figure 13 is a top view, Figure 14 is Figure 13A cross-sectional view along the 1-1' line, forming a gate structure 190 on the isolation layer 120 and across the fin 110, a first source-drain doped region 170 in the fin 110 on both sides of the first region I gate structure 190, and a second source-drain doped region 180 in the fin 110 on both sides of the second region II gate structure 190.

[0137] In the foregoing step, the isolation layer 120 on both sides of the fin 110 of the first region I and the second region II is ion doped 130, which is adapted to increase the thermal expansion coefficient of the material of the isolation layer 120, so as to release part of the stress in the isolation layer 120, so that the fin 110 of the first region I is inclined to the side away from the second region II, and the fin 110 of the second region II is inclined to the side away from the first region I in the arrangement direction of the fin 110, the interval between the fins 110 at the junction of the first region I and the second region II is increased, and more space is provided for forming the first source-drain doped region 170 and the second source-drain doped region 180, the distance between the first source-drain doped region 170 and the second source-drain doped region 180 is increased, and the probability of bridging between the first source-drain doped region 170 and the second source-drain doped region 180 is reduced, thereby optimizing the performance of the semiconductor structure.

[0138] Furthermore, the embodiment only adds a process step of ion doping, and does not additionally use a mask, which is beneficial to simplify the process flow and save costs while optimizing the performance of the semiconductor structure.

[0139] The first source-drain doped region 170 is used as a source or a drain of the first transistor.

[0140] The second source-drain doped region 180 is used as a source or a drain of the second transistor.

[0141] In the embodiment, the first source-drain doped region 170 and the second source-drain doped region 180 include a stress layer doped with ions, and the stress layer is used to provide stress for a channel region, thereby improving the mobility of carriers.

[0142] In the embodiment, the channel conduction type of the first transistor and the second transistor is different from the channel conduction type of the third transistor, and therefore, the doping type of the first source-drain doped region 170 and the second source-drain doped region 180 is different from that of the third source-drain doped region 160.

[0143] In the embodiment, the first transistor and the second transistor are PMOS transistors, and the first source-drain doped region 170 and the second source-drain doped region 180 are doped with P-type ions. Specifically, the first source-drain doped region 170 and the second source-drain doped region 180 include a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

[0144] In the embodiment, the step of forming the first source / drain doped region 170 and the second source / drain doped region 180 includes: in the same step, forming source / drain doped regions in the fin 110 on both sides of the dummy gate structure 140 in the first region I and the second region II, the source / drain doped region in the first region I is used as the first source / drain doped region 170, and the source / drain doped region in the second region II is used as the second source / drain doped region 180.

[0145] In the embodiment, the first source / drain doped region 170 and the second source / drain doped region 180 are formed in the same step, compared with forming the first source / drain doped region and the second source / drain doped region in different steps, the embodiment simplifies the process flow and saves the process cost.

[0146] In the embodiment, the step of forming the source / drain doped region includes: forming a second recess (not shown in the figure) in the fin 110 on both sides of the dummy gate structure 140 in the first region I and the second region II; and forming the source / drain doped region in the second recess.

[0147] The second recess is used to provide a spatial position for forming the source / drain doped region.

[0148] In the embodiment, the source / drain doped region is formed in the second recess by using an epitaxy process.

[0149] The gate structure 190 is used as a device gate structure to control the opening and closing of the conductive channel.

[0150] In the embodiment, the gate structure 190 is a metal gate structure. The material of the gate structure 190 includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

[0151] In a specific implementation, the gate structure 190 can include a work function layer (not shown in the figure) and a gate electrode layer (not shown in the figure) on the work function layer.

[0152] The work function layer is used to adjust the work function of the gate structure 190, and further adjust the threshold voltage of the field effect transistor. The gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 and an external circuit.

[0153] In the embodiment, the gate structure 190 is taken as an example to be a metal gate structure for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, for example, a polysilicon gate structure or an amorphous silicon gate structure.

[0154] In this embodiment, the step of forming the gate structure 190 includes: after forming the first source / drain doped region 170 and the second source / drain doped region 180, removing the dummy gate structure 140 to form a gate opening (not shown in the figure); and forming the gate structure 190 in the gate opening.

[0155] It should be noted that in this embodiment, a gate dielectric layer (not shown in the figure) is further formed between the gate structure 190 and the fin 110, for realizing electrical isolation between the gate structure 190 and the fin 110.

[0156] The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0157] Specifically, after forming the gate opening and before forming the gate structure 190, the gate dielectric layer is formed on the bottom and sidewall of the gate opening.

[0158] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising a substrate and a plurality of fins standing on the substrate, the substrate comprising adjacent first and second regions along the arrangement direction of the plurality of fins, the first and second regions being used for forming a first transistor and a second transistor, respectively; wherein along the arrangement direction of the fins, the fins of the first region are inclined toward a side away from the second region, and the fins of the second region are inclined toward a side away from the first region; an isolation layer on the substrate and surrounding the fins, the isolation layer covering part of the sidewalls of the fins; a gate structure on the isolation layer and across the fins; a first source-drain doped region in the fins on both sides of the gate structure of the first region; a second source-drain doped region in the fins on both sides of the gate structure of the second region, the second source-drain doped region being spaced apart from the first source-drain doped region along the arrangement direction of the fins.

2. The semiconductor structure of claim 1, wherein, The isolation layer on both sides of the fins of the first and second regions further comprises doped ions, the doped ions being adapted to make the thermal expansion coefficient of the isolation layer material doped with the ions greater than the thermal expansion coefficient of the isolation layer material between the fins of the first and second regions; wherein the isolation layer on both sides of the fins of the first and second regions refers to the isolation layer on the side of the fins of the first region away from the second region and the isolation layer on the side of the fins of the second region away from the first region.

3. The semiconductor structure of claim 2, wherein, The doped ions comprise one or both of nitrogen ions and carbon ions.

4. The semiconductor structure of claim 2, wherein, The doping depth of the doped ions in the isolation layer is 0 nm to 100 nm.

5. The semiconductor structure of claim 1, wherein, The angle of inclination of the fins of the first and second regions is 1° to 5°.

6. The semiconductor structure of claim 1, wherein, The channel conductive types of the first and second transistors are the same; the substrate further comprises a third region for forming a third transistor, the channel conductive type of the third transistor being different from the channel conductive types of the first and second transistors; The semiconductor structure further comprises a third source-drain doped region in the fins on both sides of the gate structure of the third region.

7. The semiconductor structure of claim 1, wherein, The material of the substrate comprises one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium. The material of the fins comprises one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium. The material of the isolation layer comprises one or both of silicon oxide and silicon oxynitride. The material of the gate structure comprises any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

8. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a gate dielectric layer between the gate structure and the fins.

9. The semiconductor structure of claim 8, wherein, The material of the gate dielectric layer comprises: one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide and nitrogen-doped silicon oxide.

10. The semiconductor structure of any one of claims 1 to 9, wherein, The substrate includes an SRAM device, the first transistor is a first pull-up transistor, and the second transistor is a second pull-up transistor.

11. A method of forming a semiconductor structure, comprising: Comprise: A substrate is provided, including a substrate and a plurality of fins standing on the substrate, the substrate including adjacent first and second regions along the arrangement direction of the plurality of fins, the first and second regions being used to form first and second transistors, respectively; An isolation layer is formed on the substrate to surround the fins, and the isolation layer exposes part of the sidewalls of the fins; The isolation layer on both sides of the fins of the first and second regions is ion-doped to increase the thermal expansion coefficient of the isolation layer material, and the isolation layer on both sides of the fins of the first and second regions refers to the isolation layer on the side of the fins of the first region away from the second region and the isolation layer on the side of the fins of the second region away from the first region; A gate structure is formed on the isolation layer and across the fins, a first source-drain doped region is formed in the fins on both sides of the gate structure of the first region, and a second source-drain doped region is formed in the fins on both sides of the gate structure of the second region.

12. The method of forming a semiconductor structure of claim 11, wherein, In the step of ion-doping the isolation layer on both sides of the fins of the first and second regions, the doping ions include one or both of nitrogen ions and carbon ions.

13. The method of forming a semiconductor structure of claim 12, wherein, The ion doping is performed using an ion implantation process.

14. The method of forming a semiconductor structure of claim 11, wherein, In the step of ion-doping the isolation layer on both sides of the fins of the first and second regions, the doping depth of the doping ions in the isolation layer is 0-100 nm.

15. The method of forming a semiconductor structure of claim 11, wherein, The step of ion-doping the isolation layer on both sides of the fins of the first and second regions includes forming a cover layer on the first and second regions to cover the isolation layer and the fins, and ion-doping the isolation layer using the cover layer as a mask.

16. The method of forming a semiconductor structure of claim 15, wherein, The channel conductive types of the first and second transistors are the same; the substrate further includes a third region for forming a third transistor, and the channel conductive type of the third transistor is different from the channel conductive types of the first and second transistors; The method for forming the semiconductor structure further includes: after forming the isolation layer and before ion-doping, forming a pseudo-gate structure on the isolation layer across the fins, and the pseudo-gate structure covers part of the top and sidewalls of the fins; After the ion-doping and before forming the first and second source-drain doped regions, third source-drain doped regions are formed in the fins on both sides of the pseudo-gate structure of the third region using the cover layer as a mask.

17. The method of forming a semiconductor structure of claim 16, wherein, The method for forming the semiconductor structure further includes: after forming the third source-drain doped regions and before forming the first and second source-drain doped regions, removing the cover layer; The step of forming the first and second source / drain doped regions includes forming source / drain doped regions in the first and second regions in the fin on both sides of the dummy gate structure in the same step, the source / drain doped regions in the first region serving as the first source / drain doped regions, and the source / drain doped regions in the second region serving as the second source / drain doped regions.

18. The method of forming a semiconductor structure of claim 17, wherein, The step of forming the gate structure includes, after forming the first and second source / drain doped regions, removing the dummy gate structure to form a gate opening; and forming the gate structure in the gate opening.

19. The method of forming a semiconductor structure of claim 11, wherein, The material of the isolation layer includes one or both of silicon oxide and silicon oxynitride.

20. The method of forming a semiconductor structure according to any one of claims 11 to 19, wherein The first and second transistors are used to form an SRAM device, the first transistor being a first pull-up transistor, and the second transistor being a second pull-up transistor.

Images