A polar code decoder processing unit based on approximate calculation

Abstract

The present invention discloses a polar code decoder processing unit based on approximate calculation, comprising an exclusive-or unit that determines the sign bit of the output of node f; an adder-subtractor that performs addition and subtraction operations on the numerical bits of input data to generate temporary data; a complementer that complements the temporary data subjected to subtraction; a comparator that compares the numerical bits of the input data and outputs the smaller value as the numerical bit of node f; an AND gate unit and a NOT gate unit that generate a first control signal and outputs it to a first selector; a NAND gate unit that determines the sign bit of the output of node g; a first selector that selects the temporary data based on the first control signal to determine the numerical bit of the output of node g; and a second selector that selects the outputs of nodes f and g based on a selection signal fg to obtain a final result. This method reduces the delay and area of the decoder, reduces hardware power consumption, and can effectively reduce decoding complexity.

Description

Technical Field

[0001] The present invention belongs to the technical field of approximate circuits and computer decoding design, and in particular relates to a polar code decoder processing unit based on approximate calculation. Background Art

[0002] Decoders are a fundamental and important technology in the communications field. Polar codes have attracted considerable attention in recent years due to their ability to reach the Shannon limit and their low encoding and decoding complexity. However, as data volumes continue to increase, the complexity and latency of polar code decoders continue to increase.

[0003] The processing unit of a decoder is a crucial component. To balance hardware complexity and decoding performance, the processing unit must be optimized and approximated. In everyday life, not every application requires 100% decoding accuracy. As an emerging computing paradigm, approximate computing offers a new approach to addressing the high energy consumption of integrated circuits. This approach sacrifices appropriate accuracy in exchange for energy and area savings. Even with some loss of accuracy, approximate computing can still produce reasonable results. Optimizing the processing unit in a decoder with area as a key objective and incorporating approximate computing into it is a key research topic in approximate circuit and computer decoding design.

[0004] Traditional polar code decoder processing units require back-and-forth conversion of data from original code to complement code, and the adder uses a ripple carry adder, resulting in significant delay. Traditional approximate comparators only compare the first n-k1 bits of the input data's absolute value, ignoring the last k1 bits, leading to significant errors. (N is the input data length, and k1 is the number of bits directly truncated.) Traditional approximate adders and subtractors perform precise addition or subtraction on only the first n-k1 bits of the input data's absolute value, ignoring the last k1 bits, resulting in significant errors or requiring additional gates to perform approximate addition or subtraction, increasing hardware complexity. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the deficiencies of the above-mentioned prior art and provide a polar code decoder processing unit based on approximate calculation. The processing unit for node decoding in the decoder is optimized and approximated. The optimization part improves the structure without reducing the accuracy with the area as the improvement target. The approximation part includes approximating the comparator, adder and subtractor, and complement used in the structure: the approximation of the comparator is based on Karnaugh map simplification of the low bits of the comparator to obtain the comparison signal; the approximation of the adder and subtractor is based on the characteristics of the input data under statistical decoding conditions to perform truncation and constant compensation of the low bits; the approximation of the complement is based on setting the lowest bit position to 1 and directly inverting the remaining bits. Through the optimization and approximation of the above-mentioned processing unit, the delay and area of the decoder are reduced, the hardware power consumption is reduced, and the decoding complexity is effectively reduced without basically affecting the decoder performance, so as to seek a trade-off between hardware resource consumption and accuracy, thereby improving hardware efficiency and decoding throughput.

[0006] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0007] A polar code decoder processing unit based on approximate calculation, having f-node operation functions and g-node operation functions, the processing unit comprising an exclusive-OR unit, an adder-subtractor, a complementer, a comparator, an AND gate unit, a NOT gate unit, a NAND gate unit, a first selector, and a second selector;

[0008] The XOR unit is used to determine the sign bit of the output of the f node;

[0009] The adder-subtractor is used to perform addition and subtraction operations on the numerical bits of the input data to generate temporary data;

[0010] The complementer is used to complement the temporary data for performing the subtraction operation;

[0011] The comparator is used to compare the numerical bits of the input data and output the smaller value as the numerical bit of the f node;

[0012] The AND gate unit and the NOT gate unit are used to generate a first control signal and output it to the first selector;

[0013] The NAND gate unit is used to determine the sign bit of the g node output;

[0014] The first selector selects temporary data according to the first control signal to determine the value bit output by the g node;

[0015] The second selector selects the outputs of nodes f and g according to the selection signal fg to obtain a final result.

[0016] To optimize the above technical solutions, specific measures taken also include:

[0017] The input data of the above processing unit are the channel log-likelihood ratios LLR(a) and LLR(b), the previous bit estimate sg and the selection signal fg of the processing unit for nodes f and g at a certain moment;

[0018] Remember S a , S b , S s Represent LLR(a), LLR(b) and the sign bit of the g-node output respectively;

[0019] Remember M a , M b , M s Represent the numerical bits of LLR(a), LLR(b) and g node output respectively.

[0020] The adder-subtractor can calculate addition and subtraction operations at the same time, and its input is the numerical bit M a , M b And carry signal cin, output is temporary data of addition and subtraction and output signal cout.

[0021] The above-mentioned adder-subtractor includes a first subunit and a second subunit;

[0022] The first subunit, based on the universality of the polar code transmission system using the BPSK modulation mode of the Gaussian channel, calculates the probability of the product of the low-order bit part of the input value to determine the constant value that should be compensated after truncating the corresponding bit, and performs approximate addition;

[0023] The second subunit is a high-bit precision unit that uses a full adder to perform precise addition operations.

[0024] The adder-subtractor adopts a carry-lookahead prediction adder-subtractor to implement ripple carry addition, and the carry-lookahead prediction adder includes a selection unit, a carry prediction unit and a summing unit;

[0025] The carry prediction unit includes a generation signal, a propagation signal generation unit and a carry generation unit;

[0026] The intermediate signals of the carry lookahead adder-subtractor are as follows:

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034] Among them, Sel i Indicates the selection signal of the current level, and Represent the outputs of the carry prediction unit and the summation unit at this level, Indicates the sum of the lowest bits of the next level, Indicates the carry of the next level, and The lowest bits of the two operands representing the next level of input, It is the termination signal generated by the lowest bit of the next level. is the generated signal generated by the highest bit of the current stage, It is the propagation signal generated by the highest bit of the current stage. The superscript i represents the current stage, and i+1 represents the next stage. The subscripts 0 to l-1 represent the bit positions of the operations performed by a single l-bit adder, with 0 representing the lowest bit and l-1 representing the highest bit.

[0035] The above complementer includes two parts: a first subunit and a second subunit;

[0036] The first subunit performs a set operation on the lowest bit, and the second subunit performs an inversion operation on the remaining bits.

[0037] The comparator comprises a first subunit and a second subunit;

[0038] The first subunit obtains an expression by performing Karnaugh map simplification on the low bits, inputs the corresponding low bits of two data value bits, and outputs a 1-bit comparison signal;

[0039] If the input data is the lower two bits M a [1:0] and M b [1:0], then the output Corresponding to a NOT gate of the hardware circuit, if Out1 is high, it means M a <M b ;

[0040] If the input data is the lower three bits M a [2:0] and M b [2:0], then the output The corresponding hardware circuit has 1 NAND gate, 1 NOT gate, 1 AND gate and two OR gates. If Out2 is high, it means M a <M b ;

[0041] The second subunit compares the high bits accurately, and when the high bits are the same, selects the smaller input data through the comparison signal output by the first subunit.

[0042] The logic of the NAND gate unit determining the output sign bit of the g node is:

[0043]

[0044] in,

[0045]

[0046] cout is the output signal of the previous stage.

[0047] The above f-node operation and g-node operation formulas are:

[0048]

[0049] Among them, x, y are input parameters, and is the log-likelihood ratio value of the channel;

[0050] is the decoding result of the previous bit;

[0051] The processing unit uses the original code input form, and the information storage method includes: 1 bit sign bit, 5 bits value bit;

[0052] The f node operation only requires the XOR unit to calculate the output sign bit and the comparator to calculate the output value bit;

[0053] Assume that the input data value is M a , M b , the sign bit is S a ,S b ; The output data value of node g is M s , the sign bit is S s ;

[0054] Compare the M of the data to be processed by the comparator a and M b Generate control signals to filter temporary results and generate S of output data s and M s , the g node control signal screening rules are as follows:

[0055]

[0056] The present invention has the following beneficial effects:

[0057] (1) Traditional polar code decoder processing units require data to be converted back and forth from the original code to the complement code. This paper designs an area-oriented processing unit that reduces latency and hardware complexity while ensuring precise logical functionality.

[0058] (2) In the traditional polar code decoder processing unit, the adder uses a ripple carry adder, which has a large delay. The present invention uses a carry-lookahead predictive adder to reduce the delay.

[0059] (3) Traditional approximate comparators only compare the first n-k1 bits of the absolute value of the input data, while directly ignoring the last k1 bits of the input data, resulting in large errors. Where n is the length of the input data, and k1 is the number of bits directly truncated. The approximate lower two-bit comparator and the approximate lower three-bit comparator designed in the present invention have error rates of 12.5% and 6.25%, respectively. These accuracy is higher than the 25% of the traditional approximate comparator that truncates the lowest bit, but the gate circuit complexity is lower than the traditional approximate comparator that truncates the lowest bit.

[0060] (4) Conventional approximate adders and subtractors only perform precise addition or subtraction on the first n-k1 bits of the absolute value of the input data, while directly ignoring the last k1 bits of the input data, resulting in large errors or using additional gate circuits to perform approximate addition or subtraction, which increases hardware complexity. The approximate adder and subtractor designed in the present invention calculates the probability of the truncated partial product being 1 based on the distribution characteristics of the input data, performs truncation compensation on the low-order bits, and performs precise calculations on the high-order bits, thereby reducing power consumption while ensuring accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 It is a structural diagram of the processing unit;

[0062] Figure 2 It is the structure diagram of adder and subtractor;

[0063] Figure 3 This is the structure diagram of the carry lookahead adder;

[0064] Figure 4 The circuit structure diagram of the approximate design unit for the comparator;

[0065] Figure 5 Design the Karnaugh map of the first sub-unit of the comparator approximation unit;

[0066] Figure 6 Schematic diagram of the probability that the input data bit of the adder-subtractor is 1;

[0067] Figure 7 The figure shows the comparison of simulation results using three approximation methods. DETAILED DESCRIPTION

[0068] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0069] The polar code decoder processing unit of the present invention, based on approximate calculation, can process operations on first- and second-type nodes. Nodes that implement the f operation function in the decoder are designated as first-type nodes, while nodes that implement the g operation function are designated as second-type nodes. This is expressed as follows:

[0070]

[0071] Among them, the input parameters x and y are the log-likelihood ratio values of the channel. The decoding result of the previous bit.

[0072] The processing unit uses the original code input format, and the information storage method includes: 1 bit sign bit, 5 bits value bit (3 bits integer bit, 2 bits mantissa bit). The f node operation only needs the XOR unit to calculate the output sign bit and the comparator to calculate the output value bit. Let the input data value bit be M a , M b , the sign bit is S a ,S b ; The output data value of node g is M s , the sign bit is S s . Compare the M of the data to be processed by the comparator a and M b Generate control signals to filter temporary results and generate S of output data s and M s ,The g node control signal screening rules are shown in Table 1:

[0073] Table 1g Node control signal screening rules

[0074]

[0075] The method for optimizing the polar code decoder processing unit based on approximate calculation disclosed in the embodiment of the present invention is as follows:

[0076] like Figure 1 As shown, the processing unit includes an XOR unit, an adder-subtractor, a complementer, a comparator, an AND gate unit, a NOT gate unit, a NAND gate unit, a first selector and a second selector.

[0077] The input data are the channel log-likelihood ratios LLR(a) and LLR(b), the previous bit estimation value sg, and the selection signal fg of the processing unit for nodes f and g at a certain moment. a , S b , S s Represent LLR(a), LLR(b) and the sign bit of the g node output respectively; Ma , M b , M s Represent the numerical bits of LLR(a), LLR(b) and g node output respectively.

[0078] The XOR unit is used to determine the sign bit of the f node output;

[0079] The adder-subtractor is used to perform addition and subtraction of the numerical bits of the input data to generate temporary data;

[0080] The complementer is used to complement the temporary data for performing the subtraction operation;

[0081] The comparator is used to compare the numerical bits of the input signals and output the smaller value as the numerical bit of the f node;

[0082] The AND gate unit and NOT gate unit are used to generate a first control signal and output it to the first selector;

[0083] The NAND gate unit is used to determine the sign bit of the g node output;

[0084] The first selector selects the temporary data based on the first control signal to determine the numeric bit output by node g. For example, when the first control signal is high, indicating that a numeric bit subtraction operation is required and the numeric bit of the minuend is smaller than the subtrahend, the selector performs an inverted addition operation, i.e., selects the output value of the complement generator; otherwise, the output of the adder-subtractor is directly selected.

[0085] The second selector selects the output of nodes f and g according to the selection signal fg to obtain the final result. For example, when fg is at a high level, the output of node f is selected; otherwise, the output of node g is selected.

[0086] The structure of the adder-subtractor is as follows: Figure 2 As shown, the input is the numerical value M a , M b And carry signal cin, output is temporary data of addition and subtraction and output signal cout.

[0087] The NAND gate unit is Figure 1 It is represented by module I, and its logical expression is:

[0088]

[0089] in,

[0090]

[0091] for Figure 1The adder and subtractor can use a carry-lookahead predictor adder instead of a ripple carry adder to reduce delay. The carry-lookahead predictor adder includes a selection unit, a carry prediction unit and a summing unit, wherein the carry prediction unit includes a generation signal, a propagation signal generation unit and a carry generation unit, such as Figure 3 shown.

[0092] The intermediate signals involved are as follows:

[0093]

[0094]

[0095]

[0096]

[0097]

[0098]

[0099]

[0100] Among them, Sel i Indicates the selection signal of the current level, and Represent the outputs of the carry prediction unit and the summation unit at this level, Indicates the sum of the lowest bits of the next level, Indicates the carry of the next level, and The lowest bits of the two operands representing the next level of input, It is the termination signal generated by the lowest bit of the next level. is the generated signal generated by the highest bit of the current stage, It is the propagation signal generated by the highest bit of the current stage. The superscript i represents the current stage, and i+1 represents the next stage. The subscripts 0 to l-1 represent the bit positions of the operations performed by a single l-bit adder, with 0 representing the lowest bit and l-1 representing the highest bit.

[0101] for Figure 1 The comparator, its approximate design unit is as follows Figure 4 As shown, it includes two parts: a first subunit and a second subunit.

[0102] The first subunit obtains an expression by performing Karnaugh map simplification on the low bits. The Karnaugh map is as follows: Figure 5 As shown, the input is the corresponding low bits of two data values, and the output is a 1-bit comparison signal;

[0103] If the input data is the lower two bits M a [1:0] and M b [1:0], then the output Corresponding to a NOT gate of the hardware circuit, if Out1 is high, it means M a <M b ;

[0104] If the input data is the lower three bits M a [2:0] and M b [2:0], then the output The corresponding hardware circuit has 1 NAND gate, 1 NOT gate, 1 AND gate and two OR gates. If Out2 is high, it means M a <M b .

[0105] The second subunit compares the high bits accurately, and when the high bits are the same, selects the smaller input data through the comparison signal output by the first subunit.

[0106] for Figure 1 The adder-subtractor, whose approximate design unit includes two parts: a first subunit and a second subunit.

[0107] The first subunit, based on the universality of the polar code transmission system using the BPSK modulation mode of the Gaussian channel, calculates the probability of the product of the low-order bit part of the input value to determine the constant value that should be compensated after truncating the corresponding bit, and performs approximate addition;

[0108] The second subunit is a high-bit precision unit that uses a full adder to perform precise addition operations.

[0109] Figure 6 Lists the probability that a bit of the input data value is 1.

[0110] for Figure 1 The complementer of the present invention comprises two parts: a first sub-unit and a second sub-unit. The first sub-unit performs a set operation on the lowest bit, and the second sub-unit performs an inversion operation on the remaining bits.

[0111] To verify the effect of the present invention, a 1024-bit, 0.5-code-rate polar code is used as an example. The processing units using the three approximation methods are applied to the serial cancellation polar code decoder. The simulation results are as follows: Figure 7 According to the simulation diagram, it can be concluded that the performance of the decoder will not be significantly reduced, but the hardware resources will be greatly reduced.

[0112] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A polar code decoder processing unit based on approximate calculation, having f-node operation functions and g-node operation functions, characterized in that: The processing unit includes an XOR unit, an adder-subtractor, a complement unit, a comparator, an AND gate unit, a NOT gate unit, a NAND gate unit, a first selector and a second selector; The XOR unit is used to determine the sign bit of the output of the f node; The adder-subtractor is used to perform addition and subtraction operations on the numerical bits of the input data to generate temporary data; The complementer is used to complement the temporary data for performing the subtraction operation; The comparator is used to compare the numerical bits of the input data and output the smaller value as the numerical bit of the f node; The AND gate unit and the NOT gate unit are used to generate a first control signal and output it to the first selector; The NAND gate unit is used to determine the sign bit of the g node output; The first selector selects temporary data according to the first control signal to determine the value bit output by the g node; The second selector selects the outputs of nodes f and g according to the selection signal fg to obtain a final result; The processing units that perform node decoding in the decoder are optimized and approximated. The approximation includes approximating the comparators, adders, subtractors, and complementers used in the structure. The comparator approximation is based on Karnaugh map simplification of the comparator's low bits to obtain the comparison signal. The adder and subtractor approximation is based on the characteristics of the input data under statistical decoding conditions, performing low-bit truncation and constant compensation. The complementer approximation is based on setting the lowest bit to 1 and directly inverting the remaining bits. The adder-subtractor includes a first subunit and a second subunit. The first subunit, based on the universality of polar code transmission systems using Gaussian channel BPSK modulation, calculates the probability of the product of the low-bit portion of the input value to determine the constant value to be compensated after truncating the corresponding bit, and performs approximate addition. The second subunit is a high-bit precision unit that uses a full adder to perform precise addition operations. The adder-subtractor uses a carry-lookahead predictor adder-subtractor to implement ripple carry addition. The carry-lookahead predictor adder-subtractor includes a selection unit, a carry prediction unit, and a summing unit. The carry prediction unit includes a generation signal, a propagation signal generation unit, and a carry generation unit. The intermediate signal of the carry-lookahead predictor adder-subtractor is as follows: Among them, Sel i Indicates the selection signal of the current level, and Represent the outputs of the carry prediction unit and the summation unit at this level, Indicates the sum of the lowest bits of the next level, Indicates the carry of the next level, and The lowest bits of the two operands representing the next level of input, It is the termination signal generated by the lowest bit of the next level. is the generated signal generated by the highest bit of the current stage, It is the propagation signal generated by the highest bit of the current stage. The superscript i represents the current stage, and i+1 represents the next stage. The subscripts 0 to l-1 represent the bit positions of the operations performed by a single l-bit adder, with 0 representing the lowest bit and l-1 representing the highest bit.

2. The polar code decoder processing unit based on approximate calculation according to claim 1, characterized in that: The input data of the processing unit are the channel log likelihood ratios LLR(a) and LLR(b), the previous bit estimation value sg and the selection signal fg of the processing unit for the f node and the g node at a certain moment; Remember S a , S b , S s Represent LLR(a), LLR(b) and the sign bit of the g-node output respectively; Remember M a , M b , M s Represent the numerical bits of LLR(a), LLR(b) and g node output respectively.

3. The polar code decoder processing unit based on approximate calculation according to claim 2, characterized in that: The adder-subtractor can calculate addition and subtraction operations simultaneously, and its input is the numerical bit M a , M b And carry signal cin, output is temporary data of addition and subtraction and output signal cout.

4. The polar code decoder processing unit based on approximate calculation according to claim 2, characterized in that: The complementer comprises two parts: a first subunit and a second subunit; The first subunit performs a set operation on the lowest bit, and the second subunit performs an inversion operation on the remaining bits.

5. The polar code decoder processing unit based on approximate calculation according to claim 2, characterized in that: The comparator includes a first subunit and a second subunit; The first subunit obtains an expression by performing Karnaugh map simplification on the low bits, inputs the corresponding low bits of two data value bits, and outputs a 1-bit comparison signal; If the input data is the lower two bits M a [1:0] and M b [1:0], then the output Corresponding to a NOT gate of the hardware circuit, if Out1 is high, it means M a <M b ; If the input data is the lower three bits M a [2:0] and M b [2:0], then the output Corresponding to the hardware circuit of 1 NAND gate, 1 NOT gate, 1 AND gate and two OR gates, if Out2 is high, it means M a <M b ; The second subunit compares the high bits accurately, and when the high bits are the same, selects the smaller input data through the comparison signal output by the first subunit.

6. The polar code decoder processing unit based on approximate calculation according to claim 2, characterized in that: The logic of the NAND gate unit determining the output sign bit of the g node is: in, cout is the output signal of the previous stage.

7. The polar code decoder processing unit based on approximate calculation according to any one of claims 1 to 6, characterized in that: The calculation formulas for f node and g node are: Among them, x, y are input parameters, and is the log-likelihood ratio value of the channel; is the decoding result of the previous bit; The processing unit uses the original code input form, and the information storage method includes: 1 bit sign bit, 5 bits value bit; The f node operation only requires the XOR unit to calculate the output sign bit and the comparator to calculate the output value bit; Assume that the input data value is M a , M b , the sign bit is S a ,S b ; The output data value of node g is M s , the sign bit is S s ; Compare the M of the data to be processed by the comparator a and M b Generate control signals to filter temporary results and generate S of output data s and M s .

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