Semiconductor structure and preparation method thereof

Abstract

The present application provides a semiconductor structure and a method for preparing the same, relating to the field of semiconductor technology. The method comprises providing a substrate, forming a first initial conductive layer, a sacrificial layer, and a first mask layer having a pattern, which are sequentially stacked on the substrate, wherein the thickness of the sacrificial layer is 10 nm to 20 nm; and etching the first initial conductive layer and the substrate using the first mask layer as a mask to form a bitline contact area. The present application reduces the thickness of the sacrificial layer. When the sacrificial layer and the first initial conductive layer are subsequently etched, the entire sacrificial layer is etched while also removing the portion of the first initial conductive layer originally obscured by the sacrificial layer. This reduces the thickness of the remaining first initial conductive layer, thereby reducing the depth of the bitline contact area. When a second conductive layer is deposited into the bitline contact area, the formation of voids in the second conductive layer can be avoided, thereby reducing the resistance of the bitline contact and improving the transmission performance of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] A dynamic random access memory typically includes multiple repeated storage cells, each of which includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line through a bit line contact, and the drain is electrically connected to the capacitor through a storage node contact. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0004] However, when forming a bit line contact, a gap is easily formed in the bit line contact, which increases the resistance of the bit line contact and reduces the transmission performance of the semiconductor structure. Summary of the Invention

[0005] In view of the above problems, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can avoid the formation of gaps in bit line contacts, reduce the resistance of the bit line contacts, and thereby improve the transmission performance of the semiconductor structure.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] A first aspect of an embodiment of the present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0008] providing a substrate;

[0009] forming a first initial conductive layer and a sacrificial layer stacked in sequence on the substrate, wherein the thickness of the sacrificial layer is 10 nm to 20 nm;

[0010] forming a first mask layer having a pattern on the sacrificial layer;

[0011] Using the first mask layer as a mask, removing the sacrificial layer, a portion of the first initial conductive layer, and a portion of the substrate to form a bit line contact region in the first initial conductive layer and the substrate, with the retained first initial conductive layer constituting a first conductive layer, wherein the thickness of the first conductive layer accounts for 2 / 5 to 3 / 5 of the thickness of the first initial conductive layer;

[0012] A second conductive layer is formed in the bit line contact region, and the second conductive layer completely fills the bit line contact region.

[0013] In the method for manufacturing the semiconductor structure as described above, the depth of the bit line contact region is 34 nm to 42 nm.

[0014] The method for preparing the semiconductor structure as described above, wherein the step of forming a first mask layer having a pattern on the sacrificial layer comprises:

[0015] forming a first photoresist layer on the first mask layer;

[0016] Patterning the first photoresist layer to form a first mask pattern in the first photoresist layer, wherein the first mask pattern includes a plurality of first opening regions spaced apart from each other and a first shielding region for separating the first opening regions;

[0017] The first mask layer exposed in the first opening region is removed to form a pattern in the first mask layer.

[0018] The method for manufacturing the semiconductor structure as described above, wherein the step of forming the second conductive layer in the bit line contact region includes:

[0019] forming a second initial conductive layer in the bit line contact region, wherein the second initial conductive layer extends outside the bit line contact region and covers the first conductive layer;

[0020] A portion of the second initial conductive layer is removed, and the remaining second initial conductive layer constitutes a second conductive layer, which is connected to the first conductive layer as a whole to form a bit line contact layer.

[0021] In the method for preparing the semiconductor structure as described above, a chemical mechanical polishing process is used to remove a portion of the thickness of the second initial conductive layer.

[0022] In the method for preparing the semiconductor structure as described above, the first mask layer includes a first hard mask layer and a first silicon oxynitride layer stacked in sequence, and the first hard mask layer is disposed on the sacrificial layer.

[0023] The method for preparing the semiconductor structure as described above, wherein, after the step of providing a substrate and before the step of forming a first initial conductive layer and a sacrificial layer in a stacked arrangement on the substrate, the method further comprises:

[0024] A first insulating layer is formed on the substrate.

[0025] In the method for preparing the semiconductor structure as described above, the first conductive layer and the second conductive layer are made of the same material, both comprising polysilicon.

[0026] In the method for preparing the semiconductor structure as described above, the material of the sacrificial layer includes silicon oxide; and the material of the first insulating layer includes silicon nitride.

[0027] The method for preparing the semiconductor structure as described above, wherein, after the step of removing a portion of the second initial conductive layer, the remaining second initial conductive layer forming the second conductive layer, and the second conductive layer and the first conductive layer being connected as a whole to form the bit line contact layer, the method further comprises:

[0028] forming a bit line conductive layer and a second mask layer having a pattern stacked in sequence on the bit line contact layer;

[0029] The second mask layer with a pattern is used as a mask to remove part of the bit line conductive layer and the bit line contact layer. The remaining bit line conductive layer constitutes a bit line, and the remaining bit line contact layer constitutes a bit line contact.

[0030] The method for manufacturing the semiconductor structure as described above, wherein the step of forming a bit line conductive layer and a second mask layer having a pattern stacked in sequence on the bit line contact comprises:

[0031] forming a second photoresist layer on the second mask layer;

[0032] Patterning the second photoresist layer to form a second mask pattern in the second photoresist layer, wherein the second mask pattern includes a plurality of second opening areas that are spaced apart and a second shielding area for separating the second opening areas;

[0033] The second mask layer exposed in the second opening area is removed to form a pattern in the second mask layer.

[0034] In the method for preparing the semiconductor structure as described above, the second mask layer includes an amorphous carbon layer, a second silicon oxynitride layer, a second hard mask layer and a third silicon oxynitride layer stacked in sequence, and the amorphous carbon layer is arranged on the bit line conductive layer.

[0035] In the method for manufacturing the semiconductor structure as described above, the bit line conductive layer includes a first bit line conductive layer and a second bit line conductive layer stacked together, and the first bit line conductive layer is disposed on the bit line contact layer.

[0036] The method for manufacturing the semiconductor structure as described above, wherein the step of forming a bit line conductive layer and a second mask layer having a pattern stacked in sequence on the bit line contact layer comprises:

[0037] A second insulating layer is formed on the bit line conductive layer.

[0038] A second aspect of an embodiment of the present application provides a semiconductor structure, which is manufactured by the semiconductor structure manufacturing method as described above.

[0039] In the semiconductor structure and preparation method provided in the embodiments of the present application, by reducing the thickness of the sacrificial layer, when the sacrificial layer and the first initial conductive layer are subsequently etched, the first initial conductive layer whose thickness is partially blocked by the sacrificial layer can be removed while the entire sacrificial layer is etched, so that the thickness of the retained first initial conductive layer is reduced, thereby reducing the depth of the bit line contact area. When the second conductive layer is deposited into the bit line contact area, the formation of gaps in the second conductive layer can be avoided, thereby reducing the resistance of the bit line contact and improving the transmission performance of the semiconductor structure.

[0040] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] Figure 1 A schematic diagram of a semiconductor structure provided in the related art Figure 1 ;

[0043] Figure 2 A schematic diagram of a semiconductor structure provided in the related art Figure 2 ;

[0044] Figure 3 A flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0045] Figure 4 A schematic structural diagram of forming a first initial conductive layer, a sacrificial layer, a first mask layer, and a first photoresist layer having a pattern in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of a structure for forming a bit line contact region in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of a second initial conductive layer structure formed in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0048] Figure 7 A schematic structural diagram of forming a bit line contact layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0049] Figure 8 A schematic structural diagram of forming a bit line conductive layer, a second insulating layer, a second mask layer, and a second photoresist layer having a pattern in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0050] Figure 9 A schematic diagram of the structure for forming bit lines and bit line contacts in the method for preparing a semiconductor structure provided in an embodiment of the present application.

[0051] Reference numerals:

[0052] 10: substrate; 11: active region;

[0053] 12: Isolation structure; 20: First insulation layer;

[0054] 30: first initial conductive layer; 31: first conductive layer;

[0055] 40: sacrificial layer; 50: first mask layer;

[0056] 51: a first hard mask layer; 52: a first silicon oxynitride layer;

[0057] 60: first photoresist layer; 61: first shielding area;

[0058] 62: first opening region; 70: bit line contact region;

[0059] 80: second initial conductive layer; 81: second conductive layer;

[0060] 90: bit line contact layer; 91: bit line contact;

[0061] 100: bit line conductive layer; 101: first bit line conductive layer;

[0062] 102: second bit line conductive layer; 103: bit line;

[0063] 110: second mask layer; 120: second photoresist layer;

[0064] 121: second opening; 122: second shielding area;

[0065] 130: Second insulating layer. DETAILED DESCRIPTION

[0066] As described in the background technology, Figure 1 and Figure 2 As shown, in the related art, there is a problem of gaps in the bit line contacts, which will increase the resistance of the bit line contacts and reduce the transmission performance of the semiconductor structure. The inventors have found that the reason for this problem is that the depth of the bit line contact area is relatively large. The process of forming the bit line contact in the bit line contact area is limited by the deposition process, and gaps are easily formed in the bit line contacts.

[0067] In response to the above-mentioned technical problems, in an embodiment of the present application, the thickness of the sacrificial layer is reduced by controlling the ratio of the thickness of the sacrificial layer to the thickness of the first initial conductive layer. In this way, when the sacrificial layer and the first initial conductive layer are subsequently etched, while the entire sacrificial layer is etched, the first initial conductive layer whose thickness is originally partially blocked by the sacrificial layer can also be removed, so that the thickness of the retained first initial conductive layer is reduced, and the depth of the bit line contact area is reduced. When the second conductive layer is deposited into the bit line contact area, the formation of gaps in the second conductive layer can be avoided, thereby reducing the resistance of the bit line contact and improving the transmission performance of the semiconductor structure.

[0068] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0069] Figure 3 This is a flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 4-Figure 9 The schematic diagram of each stage of the semiconductor structure preparation method is shown below. Figure 3-Figure 9 The preparation method of semiconductor structure is introduced in detail.

[0070] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0071] like Figure 3 As shown, the method for preparing a semiconductor structure provided in an embodiment of the present application includes the following steps:

[0072] Step S100: providing a substrate.

[0073] For example, Figure 4As shown, the substrate 10 serves as a supporting component of the dynamic random access memory, and is used to support other components arranged thereon, wherein the substrate 10 can be made of a semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0074] The substrate 10 has a plurality of active regions 11 spaced apart from each other, and an isolation structure 12 for separating the active regions 11 . The plurality of active regions 11 may be arranged in a rectangular shape, and the active regions 11 are used to form semiconductor devices such as transistors or word lines.

[0075] In this embodiment, a first insulating layer 20 may be deposited on the substrate 10 through a deposition process. The first insulating layer 20 is used to achieve an insulating setting between the active area 11 in the substrate 10 and a first initial conductive layer formed subsequently. The material of the first insulating layer 20 may include insulating materials such as silicon nitride.

[0076] Step S200: forming a first initial conductive layer and a sacrificial layer stacked in sequence on a substrate, wherein the thickness of the sacrificial layer is 10 nm to 20 nm.

[0077] For example, Figure 4 As shown, the first initial conductive layer 30 and the sacrificial layer 40 may be formed on the substrate 10 by a deposition process, wherein the deposition process may be an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

[0078] The material of the first initial conductive layer 30 may include conductive materials such as polysilicon, and the sacrificial layer 40 may include insulating materials such as silicon oxide.

[0079] It should be noted that, when the first insulating layer 20 is disposed on the substrate 10 , the first initial conductive layer 30 needs to be disposed on the first insulating layer 20 .

[0080] Step S300 : forming a first mask layer having a pattern on the sacrificial layer.

[0081] Illustratively, a first photoresist layer 60 is formed on the first mask layer 50 .

[0082] The first photoresist layer 60 may be formed on the first mask layer 50 by coating.

[0083] Then, the first photoresist layer 60 is patterned by exposure, development or etching to form a first mask pattern in the first photoresist layer 60 . The first mask pattern includes a plurality of first opening areas 62 spaced apart and first blocking areas 61 for separating the first opening areas 62 .

[0084] Afterwards, the first mask layer 50 exposed in the first opening region 62 is removed using an etching solution or an etching gas to form a pattern in the first mask layer 50 .

[0085] In this embodiment, the first mask layer 50 can be a single film layer or a stacked layer. When the first mask layer 50 is a stacked layer, the first mask layer 50 can include a first hard mask layer 51 and a first silicon oxynitride layer 52 stacked in sequence, and the first hard mask layer 51 is arranged on the sacrificial layer 40.

[0086] In this embodiment, by configuring the first mask layer 50 to be a stacked structure, the accuracy of the pattern on the first photoresist layer 60 during the transfer process can be ensured, thereby improving the accuracy of the subsequent formation of the bit line contact region.

[0087] Step S400: Using the first mask layer as a mask, remove the sacrificial layer and part of the first initial conductive layer and the substrate to form a bit line contact area in the first initial conductive layer and the substrate. The retained first initial conductive layer constitutes the first conductive layer. The thickness of the first conductive layer accounts for 2 / 5 to 3 / 5 of the thickness of the first initial conductive layer. Figure 5 shown.

[0088] In this step, the first mask layer 50 is used as a mask, and the etching gas is used to remove the sacrificial layer 40. Since the thickness of the sacrificial layer 40 is 10nm to 20nm, compared with the thickness of the sacrificial layer 40 of 48nm to 52nm in the related art, the thickness of the sacrificial layer 40 is reduced. In this way, when the sacrificial layer 40 is patterned, the sacrificial layer 40 originally blocked by the first mask layer 50 will also be removed, so that the entire sacrificial layer 40 will be completely etched; when the first initial conductive layer 30 is further etched, the first initial conductive layer 30 originally blocked by the first mask layer 50 will also be removed by a certain thickness, so that the thickness of the first conductive layer 31 finally formed accounts for 2 / 5 to 3 / 5 of the thickness of the first initial conductive layer 30. In this way, the depth of the bit line contact area can be reduced to prevent the formation of gaps when the second conductive layer is subsequently formed in the bit line contact area, thereby reducing the resistance of the bit line contact and improving the transmission performance of the semiconductor structure.

[0089] It should be noted that, in this embodiment, the bit line contact region 70 is used to expose the active region 11 , so as to facilitate electrical connection between the subsequently formed bit line contact and the active region 11 .

[0090] After repeated demonstration by the inventors, it was found that if the depth of the bit line contact area 70 is greater than 42nm, the depth of the bit line contact area will be excessively increased. When the second conductive layer is subsequently formed, voids will be easily formed in the second conductive layer, affecting the transmission performance of the semiconductor structure. If the depth of the bit line contact area is less than 34nm, the depth of the bit line contact area will be reduced, thereby reducing the height of the second conductive layer formed subsequently, affecting the electrical connection between the bit line and the active area, and reducing the transmission performance of the semiconductor structure. Therefore, this embodiment prevents the formation of voids in the second conductive layer and ensures the transmission performance of the semiconductor structure by making the depth of the bit line contact area between 34nm and 52nm.

[0091] Step S500: forming a second conductive layer in the bit line contact region, wherein the second conductive layer fully fills the bit line contact region.

[0092] Conductive material can be deposited into the bit line contact area 70 through a deposition process. The conductive material can fill the bit line contact area 70. The conductive material constitutes a second conductive layer 81. The material of the second conductive layer 81 is the same as that of the first conductive layer 31, and can both include conductive materials such as polysilicon.

[0093] like Figure 6 As shown, illustratively, a second initial conductive layer 80 may be formed in the bit line contact region 70 by a chemical vapor deposition process or a physical vapor deposition process. The second initial conductive layer 80 extends outside the bit line contact region 70 and covers the first conductive layer 31 .

[0094] Afterwards, if Figure 7 As shown, a chemical mechanical polishing process can be used to remove a portion of the second initial conductive layer 80 , and the retained second initial conductive layer 80 constitutes a second conductive layer 81 , which is connected to the first conductive layer 31 to form a bit line contact layer 90 .

[0095] In this embodiment, since the top surface of the second initial conductive layer 80 is flattened by a chemical mechanical polishing process, the top surface of the bit line contact layer 90 formed by the first conductive layer 31 and the second conductive layer 81 is parallel to the horizontal plane. This can prevent the subsequent height difference of the bit line formed on the bit line contact layer, thereby ensuring the performance of the bit line.

[0096] It should be noted that the top surface of the bit line contact layer 90 formed in this embodiment may be higher than the top surface of the first conductive layer 31 , or may be flush with the top surface of the first conductive layer 31 .

[0097] In some embodiments, after the step of removing a portion of the second initial conductive layer, the remaining second initial conductive layer forming a second conductive layer, and the second conductive layer and the first conductive layer being connected to form a whole to form a bit line contact layer, the preparation method further comprises:

[0098] like Figure 8 As shown, a bit line conductive layer 100 and a second mask layer 110 having a pattern are formed on the bit line contact layer 90 , which are sequentially stacked.

[0099] For example, the bit line conductive layer 100 can be formed on the bit line contact layer 90 by a deposition process. For example, a first bit line conductive layer 101 and a second bit line conductive layer 102 can be sequentially formed on the bit line contact layer 90 , and the first bit line conductive layer 101 is disposed on the bit line contact layer 90 .

[0100] Among them, the material of the first bit line conductive layer 101 may include titanium nitride, and the material of the second bit line conductive layer 102 may include tungsten. In this embodiment, the first bit line conductive layer 101 has a conductive function and a blocking function at the same time, which can prevent the conductive material in the second bit line conductive layer 102 from diffusing into the substrate 10 or the bit line contact layer 90, thereby ensuring the conductive performance of the subsequently formed bit line.

[0101] After the bit line conductive layer 100 is formed, a second mask layer 110 may be formed on the bit line conductive layer 100 through a deposition process. The second mask layer 110 may be a single film layer or a stacked layer. When the second mask layer 110 is a stacked layer, the second mask layer 110 may include an amorphous carbon layer 111, a second silicon oxynitride layer 112, a second hard mask layer 113, and a third silicon oxynitride layer 114 stacked in sequence. The amorphous carbon layer 111 is disposed on the bit line conductive layer 100.

[0102] Thereafter, a second photoresist layer 120 may be formed on the second mask layer 110 . For example, the second photoresist layer 120 may be formed on the second mask layer 110 by coating.

[0103] The second photoresist layer 120 is then patterned by exposure, development or etching to form a second mask pattern in the second photoresist layer 120 . The second mask pattern includes a plurality of second opening areas 121 spaced apart and second blocking areas 122 for separating the second opening areas 121 .

[0104] Finally, the second mask layer 110 exposed in the second opening region 121 is removed by using an etching solution or an etching gas to form a pattern in the second mask layer 110 .

[0105] In this embodiment, the second mask layer 110 is designed as a stacked layer, so that the second mask pattern of the second photoresist layer 120 can be first transferred to the third silicon oxynitride layer 114, and then transferred to the second hard mask layer 113, the second silicon oxynitride layer 112 and the amorphous carbon layer 111 in sequence. This ensures the accuracy of the pattern on the second photoresist layer 120 during the transfer process, thereby improving the accuracy of the subsequent formation of the bit line.

[0106] like Figure 9 As shown, after the second mask layer 110 with a pattern is formed, the second mask layer 110 with a pattern is used as a mask to remove part of the bit line conductive layer 100 and the bit line contact layer 90. The retained bit line conductive layer 100 constitutes the bit line 103, and the retained bit line contact layer 90 constitutes the bit line contact 91.

[0107] It should be noted that a bit line contact 91 is provided at the bottom of each bit line 103 . Part of the bit line contact 91 contacts the active area 11 in the substrate 10 , while the other part of the bit line contact 91 does not contact the active area 11 in the substrate 10 .

[0108] In this embodiment, since the second initial conductive layer is planarized in the above process, the vertical distance between the top surface of each bit line formed in this step and the top surface of the substrate is a constant value, that is, the top surface of each bit line is flat, ensuring the performance of the bit line.

[0109] In some embodiments, in the step of forming a bit line conductive layer and a second mask layer having a pattern stacked in sequence on the bit line contact layer, the method for preparing the semiconductor structure includes: forming a second insulating layer 130 on the bit line conductive layer 100 using a deposition process, wherein the material of the second insulating layer 130 includes silicon nitride, thereby preventing electrical connection between the bit line conductive layer 100 and other devices subsequently formed on the second insulating layer 130.

[0110] An embodiment of the present invention further provides a semiconductor structure, which is obtained by using the method for preparing the semiconductor structure in the above embodiment. Therefore, the semiconductor structure has the beneficial effects of the above embodiment, and this embodiment will not be described in detail here.

[0111] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0112] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.

[0113] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: providing a substrate; forming a first initial conductive layer and a sacrificial layer stacked in sequence on the substrate, wherein the thickness of the sacrificial layer is 10 nm to 20 nm; forming a first mask layer having a pattern on the sacrificial layer; Using the first mask layer as a mask, removing the sacrificial layer, a portion of the first initial conductive layer, and a portion of the substrate to form a bit line contact region in the first initial conductive layer and the substrate, with the retained first initial conductive layer constituting a first conductive layer, wherein the thickness of the first conductive layer accounts for 2 / 5 to 3 / 5 of the thickness of the first initial conductive layer; A second conductive layer is formed in the bit line contact region, and the second conductive layer completely fills the bit line contact region.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The depth of the bit line contact region is 34 nm to 42 nm.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The step of forming a first mask layer having a pattern on the sacrificial layer includes: forming a first photoresist layer on the first mask layer; Patterning the first photoresist layer to form a first mask pattern in the first photoresist layer, wherein the first mask pattern includes a plurality of first opening regions spaced apart from each other and a first shielding region for separating the first opening regions; The first mask layer exposed in the first opening region is removed to form a pattern in the first mask layer.

4. The method for preparing a semiconductor structure according to claim 3, wherein: The step of forming a second conductive layer in the bit line contact region includes: forming a second initial conductive layer in the bit line contact region, wherein the second initial conductive layer extends outside the bit line contact region and covers the first conductive layer; A portion of the second initial conductive layer is removed, and the remaining second initial conductive layer constitutes a second conductive layer, which is connected to the first conductive layer as a whole to form a bit line contact layer.

5. The method for preparing a semiconductor structure according to claim 4, wherein: A chemical mechanical polishing process is used to remove a portion of the thickness of the second initial conductive layer.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, wherein: The first mask layer includes a first hard mask layer and a first silicon oxynitride layer stacked in sequence, and the first hard mask layer is disposed on the sacrificial layer.

7. The method for preparing a semiconductor structure according to claim 6, wherein: After the step of providing a substrate and before the step of forming a first initial conductive layer and a sacrificial layer in a stacked arrangement on the substrate, the preparation method further includes: A first insulating layer is formed on the substrate.

8. The method for preparing a semiconductor structure according to claim 7, wherein: The first conductive layer and the second conductive layer are made of the same material, both comprising polysilicon.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The material of the sacrificial layer includes silicon oxide; the material of the first insulating layer includes silicon nitride.

10. The method for preparing a semiconductor structure according to claim 4, wherein: After the step of removing a portion of the second initial conductive layer, where the remaining second initial conductive layer forms a second conductive layer, and the second conductive layer and the first conductive layer are connected to form a bit line contact layer, the preparation method further comprises: forming a bit line conductive layer and a second mask layer having a pattern stacked in sequence on the bit line contact layer; The second mask layer with a pattern is used as a mask to remove part of the bit line conductive layer and the bit line contact layer. The remaining bit line conductive layer constitutes a bit line, and the remaining bit line contact layer constitutes a bit line contact.

11. The method for preparing a semiconductor structure according to claim 10, wherein: The step of forming a bit line conductive layer and a second mask layer having a pattern stacked in sequence on the bit line contact includes: forming a second photoresist layer on the second mask layer; Patterning the second photoresist layer to form a second mask pattern in the second photoresist layer, wherein the second mask pattern includes a plurality of second opening areas that are spaced apart and a second shielding area for separating the second opening areas; The second mask layer exposed in the second opening area is removed to form a pattern in the second mask layer.

12. The method for preparing a semiconductor structure according to claim 11, wherein: The second mask layer includes an amorphous carbon layer, a second silicon oxynitride layer, a second hard mask layer, and a third silicon oxynitride layer stacked in sequence, and the amorphous carbon layer is disposed on the bit line conductive layer.

13. The method for preparing a semiconductor structure according to claim 12, wherein: The bit line conduction layer includes a first bit line conduction layer and a second bit line conduction layer that are stacked, and the first bit line conduction layer is disposed on the bit line contact layer.

14. The method for preparing a semiconductor structure according to claim 13, wherein: The step of forming a bit line conductive layer and a second mask layer having a pattern stacked in sequence on the bit line contact layer further includes: A second insulating layer is formed on the bit line conductive layer.

15. A semiconductor structure, characterized in that The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 14.

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