Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, including: providing a substrate and a dielectric layer located on the substrate, wherein the substrate in an array region has a plurality of discrete capacitor contact plugs, and a first conductive layer is formed on the top surface of the capacitor contact plugs; sequentially forming a conversion layer and a target layer on the first conductive layer and the dielectric layer, wherein the target layer in the array region and the first circuit region both have a first opening extending through the target layer; patterning the target layer in the array region to form a second opening, and patterning the target layer in the first circuit region and the second circuit region to form a third opening; etching the conversion layer using the target layer having the first opening, the second opening, and the third opening as a mask to form a first trench; forming a filling layer that completely fills the first trench, and removing the conversion layer to form a second trench; and forming a second conductive layer that completely fills the second trench. The present invention is advantageous in improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Memory is a storage device used to store information in modern information technology and is widely used in various electronic products. Depending on whether it can be directly accessed by the central processing unit (CPU), memory can be divided into internal memory and external memory. Internal memory can be further divided into dynamic random access memory (DRAM), static random access memory (SRAM), and video random access memory (VRAM).

[0003] Currently, during the process of forming a conductive layer, there are areas that are difficult to etch. Summary of the Invention

[0004] The embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure, which are beneficial to improving the performance of the semiconductor structure.

[0005] An embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate and a dielectric layer located on the substrate, wherein the substrate comprises an array area, a first circuit area, and a second circuit area, and the first circuit area is located between the array area and the second circuit area, the substrate in the array area has a plurality of discrete capacitor contact plugs, the substrate in the first circuit area has a first gate, and the first circuit area also has first conductive plugs located on opposite sides of the first gate, the substrate in the second circuit area has a second gate, and the second circuit area also has second conductive plugs located on opposite sides of the second gate, and the first gate, the second gate, and the capacitor contact plugs are located in the dielectric layer, and a first conductive layer is further formed on the top surface of the capacitor contact plug; forming a conversion layer and a target layer in sequence on the first conductive layer and the dielectric layer, and the array area and the target layer in the first circuit area both have a structure that penetrates the target layer. , and the pattern density of the first openings in the array area is greater than the pattern density of the first openings in the first circuit area; patterning the target layer between adjacent first openings in the array area to form a second opening penetrating the target layer, and patterning the target layer in the first circuit area and the second circuit area to form a third opening penetrating the target layer; using the target layer having the first opening, the second opening and the third opening as a mask, etching the conversion layer to form a first trench in the conversion layer; forming a filling layer filling the first trench, and removing the conversion layer to form a second trench penetrating the filling layer, and the second trench in the array area exposes the top surface of the first conductive layer, the second trench in the first circuit area exposes the top surface of the first conductive plug, and the second trench in the second circuit area exposes the top surface of the second conductive plug; forming a second conductive layer filling the second trench.

[0006] In addition, the process steps for forming the target layer include: forming an initial target film on the conversion layer; forming a first mask layer on the initial target film, wherein the first mask layer in the array area and the first circuit area both have a first initial opening, and the pattern density of the first initial opening in the array area is greater than the pattern density of the first initial opening in the first circuit area; forming a first sidewall layer covering the inner wall of the first initial opening; forming a second mask layer covering the first sidewall layer and filling the first initial opening, and the second mask layer also exposes the top surface of the first sidewall layer; removing the first sidewall layer, and using the first mask layer and the second mask layer as masks, etching the initial target film to form the target layer.

[0007] In addition, the material of the first mask layer is the same as that of the second mask layer.

[0008] In addition, the process steps for forming the second mask layer include: forming a second initial mask covering the first sidewall layer and filling the first initial opening, the second initial mask is also located on the top of the first mask layer, and the height of the top surface of the second initial mask in the second circuit area, the first circuit area and the array area decreases successively; etching back the second initial mask until the top surface of the first sidewall layer of the inner wall of the first initial opening is exposed, and the remaining second initial mask serves as the second mask layer.

[0009] In addition, in the process step of forming the first spacer layer, the first spacer layer is also formed at the bottom of the first initial opening and the top surface of the first mask layer; and the formed second mask layer also exposes the first spacer layer located on the top surface of the first mask layer.

[0010] In addition, the process steps for forming the second opening include: forming a third mask layer that fills the first opening and covers the top surface of the target layer, and sequentially forming a first stop layer and a fourth mask layer on the third mask layer, the fourth mask layer in the array area and the second circuit area both have a fourth opening that penetrates the fourth mask layer, and a second sidewall layer is formed on the inner wall of the fourth opening in the array area; forming a fifth mask layer that fills the fourth opening and is located on the top surface of the fourth mask layer, and the top surface of the fifth mask layer in the first circuit area is higher than the top surface of the fifth mask layer in the array area and the second circuit area; etching back the fifth mask layer to expose the second sidewall layer located on the top of the fourth mask layer in the array area; removing the second sidewall layer, and using the fifth mask layer and the fourth mask layer as masks, etching the third mask layer and the target layer to form the second opening.

[0011] In addition, the materials of the third mask layer and the fourth mask layer are the same as the material of the fifth mask layer; before forming the fifth mask layer, it also includes: forming a second stop layer on the top surface of the fourth mask layer, and the material of the second stop layer is different from the material of the fourth mask layer.

[0012] In addition, the process steps for forming the fourth opening and the second sidewall layer include: forming a fourth initial mask on the first stop layer, and the fourth initial mask in the array area has the fourth opening penetrating the fourth initial mask; forming the second sidewall layer, and the second sidewall layer is located on the inner wall of the fourth opening in the array area; patterning the fourth initial mask in the second circuit area to form the fourth opening in the fourth initial mask in the second circuit area, and the remaining fourth initial mask serves as the fourth mask layer.

[0013] In addition, the process steps of patterning the fourth initial mask of the second circuit area include: forming a first graphic layer that fills the fourth opening of the array area, and the first graphic layer of the second circuit area has a through hole that penetrates the first graphic layer; using the first graphic layer as a mask, etching the fourth initial mask of the second circuit area to form the fourth opening located in the second circuit area; and removing the first graphic layer.

[0014] In addition, in the process step of etching back the fifth mask layer, a portion of the fifth mask layer located in the fourth opening of the second circuit region is also etched away.

[0015] In addition, the process steps for forming the third opening include: forming a sixth mask layer that fills the second opening and is located on the top surface of the target layer; forming a second graphic layer located on the sixth mask layer, and the second graphic layer in the first circuit area and the second circuit area both have grooves that penetrate the second graphic layer; using the second graphic layer as a mask, etching the sixth mask layer until the target layer is exposed, and then etching the target layer using the sixth mask layer as a mask to form the third opening.

[0016] In addition, after forming the conversion layer and before forming the target layer, the method further includes: forming an amorphous carbon layer and an intermediate layer in sequence on the conversion layer; and forming the target layer on the surface of the intermediate layer.

[0017] In addition, the material of the conversion layer includes silicon nitride or polysilicon; the material of the target layer includes TEOS.

[0018] In addition, the process steps for forming the second conductive layer include: forming a conductive film that fills the second groove, and the conductive film is also located on the top surface of the filling layer; removing the conductive film above the top surface of the filling layer, and the remaining conductive film serves as the second conductive layer.

[0019] In addition, the second conductive layer is made of metal.

[0020] An embodiment of the present application further provides a semiconductor structure, which is formed by the semiconductor structure manufacturing method described above.

[0021] The technical solution provided in the embodiments of the present application has the following advantages:

[0022] In the above technical solution, a conversion layer is first patterned on the substrate surface, followed by a filling layer that completely fills the first trench. The conversion layer is then removed to form a second trench, and then the second trench is filled with a target conductive material to form a second conductive layer. Forming the second conductive layer through deposition allows the thickness of the second conductive layer to be adjusted as needed, and a second conductive layer with a precise pattern can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily described by the figures in the corresponding drawings. Unless otherwise stated, the figures in the drawings are not limited to scale.

[0024] Figures 1 to 25 Schematic diagram of a semiconductor structure corresponding to each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The present application provides a method for manufacturing a semiconductor structure, which forms a filling layer having a second trench on a dielectric layer, and then fills a target material into a target pattern in the filling layer to form a desired second conductive layer.

[0026] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in each embodiment of the present application to help readers better understand the present application. However, even without these technical details and various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0027] Figures 1 to 25 Schematic diagram of the structures corresponding to the steps of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0028] In some embodiments, taking the semiconductor structure formed as comprising a DRAM device as an example, the device corresponding to the array region is a DRAM device. In other embodiments, the semiconductor structure formed may also comprise a static random access memory, a video memory, and the like.

[0029] refer to Figure 1 and Figure 2 A substrate 31 and a dielectric layer 321 located on the substrate 31 are provided. The substrate 31 includes an array area 311, a first circuit area 312, and a second circuit area 313. The first circuit area 312 is located between the array area 311 and the second circuit area 313. A plurality of discrete capacitor contact plugs 322 are provided on the substrate 31 of the array area 311. A first gate 323 is provided on the substrate 31 of the first circuit area 312. The first circuit area 312 further includes first conductive plugs 324 located on opposite sides of the first gate 323. A second gate 325 is provided on the substrate 31 of the second circuit area 313. The second circuit area 313 further includes second conductive plugs 326 located on opposite sides of the second gate 325. The first gate 323, the second gate 325, and the capacitor contact plugs 322 are located within the dielectric layer 321. A first conductive layer 331 is further formed on the top surface of the capacitor contact plugs 322.

[0030] In some embodiments, the base 31 may include a substrate and a word line structure located within the substrate, and may further include an isolation structure. The substrate may be made of silicon, germanium, silicon germanium, or silicon carbide.

[0031] The array region 311 is where the memory array is to be formed. The memory array may include word lines, bit lines, and storage capacitors. Within the substrate 31 of the array region 311, a word line structure and a source and drain located on opposite sides of the word line structure are formed. Capacitor contact plugs 322 are electrically connected to the source. Furthermore, a bit line structure may also be formed within the dielectric layer 321 of the array region 311. The capacitor contact plugs 322 may be made of polysilicon or metal, such as copper, aluminum, or tungsten.

[0032] The first circuit region 312 may be a region where a core circuit is to be formed; and the second circuit region 313 may be a region where a peripheral circuit is to be formed.

[0033] The substrate 31 of the first circuit area 312 also has a source and a drain located on opposite sides of the first gate 323, and each first conductive plug 324 is electrically connected to the source and drain located in the first circuit area 312; the substrate 31 of the second circuit area 313 also has a source and a drain located on opposite sides of the second gate 325, and each second conductive plug 326 is electrically connected to the source and drain located in the second circuit area 313.

[0034] It should be noted that the array area 311, the first circuit area 312, and the second circuit area 313 are different areas of the semiconductor structure divided with reference to the substrate 31, and do not simply refer to different parts of the substrate 31. The array area 311, the first circuit area 312, and the second circuit area 313 refer to the substrate 31 in the corresponding area and other film layers formed on the substrate 31.

[0035] The dielectric layer 321 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride, etc. In some embodiments, the dielectric layer 321 may be a single-layer structure; in other embodiments, the dielectric layer 321 may be a stacked-layer structure.

[0036] The top surface area of the first conductive layer 331 is larger than the top surface area of the capacitor contact plug 322. This helps reduce the alignment accuracy required for the subsequent formation of the second conductive layer, thereby reducing the process difficulty. Furthermore, the material of the first conductive layer 331 can be different from that of the capacitor contact plug 322. In some embodiments, the resistivity of the material of the first conductive layer 331 can be greater than that of the capacitor contact plug 322, and the material of the first conductive layer 331 can be tungsten. This helps reduce the contact resistance between the subsequently formed second conductive layer and the first conductive layer 331, thereby improving the operating speed of the semiconductor structure.

[0037] In some embodiments, in conjunction with reference Figure 1 and Figure 2 The process steps for forming the first conductive layer 331 may include: patterning the dielectric layer 321 of the array region 311, forming a plurality of openings in the dielectric layer 321, wherein each opening exposes a top surface of a corresponding capacitor contact plug 322; forming a first conductive film 332 filling the openings, wherein the first conductive film 332 is also located on the top surface of the dielectric layer 321; and referring to FIG. Figure 2 , the first conductive film 332 is planarized, and the first conductive film 332 above the top surface of the dielectric layer 321 is removed, and the remaining first conductive film 332 serves as the first conductive layer 331 .

[0038] refer to Figures 3 to 9 A conversion layer 341 and a target layer 362 are sequentially formed on the first conductive layer 331 and the dielectric layer 321. The target layer 362 in the array area 311 and the first circuit area 312 both have first openings 36a that penetrate the target layer 362, and the pattern density of the first openings 36a in the array area 311 is greater than the pattern density of the first openings 36a in the first circuit area 312.

[0039] In some embodiments, the material of the conversion layer 341 may be silicon nitride or polysilicon, and the material of the target layer 362 may be tetraethyl orthosilicate (TEOS).

[0040] In some embodiments, the target layer 362 has multiple rows of first openings 36 a arranged along a predetermined direction, and each first opening 36 a has a first extending direction. The angle between the first extending direction and the predetermined direction may be 120°.

[0041] The arrangement density of the capacitor contact plugs 322 in the array area 311 is greater than the arrangement density of the first conductive plugs 324 in the first circuit area 312. In order to ensure the corresponding connection between the capacitor contact plugs 322 and the first conductive plugs 324, the pattern density of the first openings 36a in the array area 311 is greater than the pattern density of the first openings 36a in the first circuit area 312.

[0042] The following will be combined Figures 3 to 9 , the steps for forming the target layer 362 in some embodiments are described:

[0043] refer to Figure 3 , an initial target film 361 is formed on the conversion layer 341 .

[0044] Specifically, a continuous initial target film 361 is formed on the conversion layer 341 in the array region 311 , the first circuit region 312 , and the second circuit region 313 .

[0045] The initial target film 361 provides a process basis for subsequently forming a target layer. That is, the material of the initial target film 361 is the same as that of the target layer.

[0046] In some embodiments, before forming the initial target film 361, the process may further include sequentially forming an amorphous carbon layer 351 and an intermediate layer 352 on the conversion layer 341, and forming the initial target film 361 on the surface of the intermediate layer 352. Accordingly, a target layer is subsequently formed on the surface of the intermediate layer 352.

[0047] In some embodiments, the amorphous carbon layer 351 can cooperate with the intermediate layer 352 as a hard mask layer to improve the quality of the pattern formed by subsequent etching of the conversion layer 341. The material of the intermediate layer 352 is different from that of the conversion layer 341. For example, the intermediate layer 352 can be a silicon oxynitride material.

[0048] In other embodiments, the initial target film may also be formed directly on the surface of the conversion layer.

[0049] refer to Figure 4 A first mask layer 373 is formed on the initial target film 361, and the first mask layer 373 of the array area 311 and the first circuit area 312 both have first initial openings 37a, and the pattern density of the first initial openings 37a in the array area 311 is greater than the pattern density of the first initial openings 37a in the first circuit area 312.

[0050] In some embodiments, the process of forming the first mask layer 373 may include: forming a continuous first initial mask 371 (refer to FIG. Figure 3 ); In the first initial mask 371 (reference Figure 3 ) a photoresist layer 381 having a first initial opening 37a is formed on the surface; the first initial mask 371 is etched using the photoresist layer 381 as a mask (reference Figure 3 ), in the first initial mask 371 (reference Figure 3 ) is formed through the first initial mask 371 (reference Figure 3 ) of the first initial opening 37a, the remaining first initial mask 371 (reference Figure 3 ) as the first mask layer 373; remove the photoresist layer 381.

[0051] The first initial mask 371 (refer to Figure 3 ) The SOC (Spin On Coating) spin coating process can be used to deposit carbon or carbon-containing organic matter. The spin coating process has a faster film formation rate, which is beneficial to shortening the manufacturing process time; and the texture of carbon or carbon-containing organic matter is relatively soft and can be easily etched and removed, which is beneficial to further shorten the manufacturing process time of the semiconductor structure.

[0052] In some embodiments, before forming the photoresist layer 381, a first initial mask 371 (refer to Figure 3 ) surface to form a first isolation layer 372. The material of the first isolation layer 372 is the same as the first initial mask 371 (reference Figure 3 ) is different from the material of the first isolation layer 372, for example, the material of the first isolation layer 372 can be silicon oxynitride.

[0053] refer to Figure 5 , forming a first sidewall layer 391 covering the inner wall of the first initial opening 37 a.

[0054] The first spacer 391 is used to define the position and shape of the first opening subsequently formed in the target layer. In some embodiments, deposition is used to form the first spacer 391, which facilitates a thinner first spacer 391, which in turn facilitates the subsequent formation of a smaller first opening, thereby reducing the impact of photolithography process limitations.

[0055] The material of the first spacer 391 is different from that of the first preliminary mask 371 and is also different from that of the target layer. In some embodiments, the material of the first spacer 391 can be silicon oxide.

[0056] In some embodiments, the first sidewall layer 391 can be formed by atomic layer deposition. The first sidewall layer 391 formed by atomic layer deposition has the advantages of good density and good uniformity in covering the inner wall of the first initial opening 37a, which is beneficial to further improve the morphological accuracy of the first opening formed subsequently.

[0057] In some embodiments, during the process of forming the first spacer 391, the first spacer 391 may also be formed at the bottom of the first initial opening 37a and on the top surface of the first mask layer 373. In other words, the first spacer 391 is also located on the top surface of the first mask layer 373 in the array region 311, the first circuit region 312, and the second circuit region 313.

[0058] It is understandable that, in other embodiments, the first sidewall layer may be formed only on the inner wall of the first initial opening.

[0059] refer to Figure 6 and Figure 7 , forming a layer covering the first sidewall 391 and filling the first initial opening 37a (refer to Figure 5 ), and the second mask layer 402 also exposes the top surface of the first spacer layer 391.

[0060] The second mask layer 402 and the first mask layer 373 subsequently serve together as a mask for etching the initial target film 361. Accordingly, the material of the second mask layer 402 is different from that of the initial target film 361. The second mask layer 402 can be made of the same material as the first mask layer 373, thereby reducing the number of materials and etchants required during the production process, thereby lowering the cost and complexity of the semiconductor process.

[0061] In some embodiments, the second mask layer 402 located in the array region 311 and the first circuit region 312 is filled with the first initial opening 37a (refer to Figure 5 ), and exposes the top surface of the first spacer layer 391 in the array area 311 and the first circuit area 312; the second mask layer 402 located in the second circuit area 313 is located directly above the first mask layer 373, and covers the top surface of the first spacer layer 391 in the second circuit area 313.

[0062] In some embodiments, the process steps for forming the second mask layer 402 may include:

[0063] refer to Figure 6 , forming a layer covering the first sidewall 391 and filling the first initial opening 37a (refer to Figure 5 ), the second initial mask 401 is also located on the top of the first mask layer 373, and the top surface heights of the second initial mask 401 in the second circuit area 313, the first circuit area 312 and the array area 311 are successively reduced.

[0064] The second initial mask 401 can be formed by a deposition process or a spin coating process. Taking the deposition process as an example, the deposition rate and deposition time of different regions are the same during the deposition process, that is, the total amount of the second initial mask 401 material on the array area 311, the first circuit area 312 and the second circuit area 313 is the same. Since the first initial openings 37a (refer to Figure 5 ) are arranged in descending order. It can be understood that the total opening area of the openings in the array region 311 is the largest. Therefore, in the first initial opening 37a (reference Figure 5 ) The more material of the second initial mask 401 that can be accommodated, the lower the top surface of the second initial mask 401 in the array area 311 is. Similarly, the upper surface of the second initial mask 401 in the second circuit area 313 is the highest. That is, the upper surface of the second initial mask 401 decreases in the direction from the second circuit area 313 to the array area 311.

[0065] It can be understood that the second initial mask 401 formed by the spin coating process also has the above-mentioned top surface.

[0066] refer to Figure 7 , etch back the second initial mask 401 (refer to Figure 6 ), until the first initial opening 37a is exposed (reference Figure 5 ) The top surface of the first spacer layer 391 of the inner wall, the remaining second initial mask 401 (reference Figure 6 ) as the second mask layer 402.

[0067] In some embodiments, the second initial mask 401 may be etched back using a dry etching process (see Figure 6 ).

[0068] Specifically, the second initial mask 401 (refer to Figure 6 ) until the top surface of the first spacer layer 391 of the array area 311 and the first circuit area 312 is exposed. Figure 6 ) has the highest top surface height, so after the etch-back process is completed, the second mask layer 402 located in the second circuit region 313 is still located on the top surface of the first spacer layer 391.

[0069] refer to Figure 8 and Figure 9 , remove the first spacer layer 391 , and use the first mask layer 373 and the second mask layer 402 as masks to etch the initial target film 361 to form a target layer 362 .

[0070] Specifically, refer to Figure 8 , the first spacer layer 391 located in the array area 311 and the first circuit area 312 is removed to form a gap between the first mask layer 373 and the second mask layer 402 .

[0071] In some embodiments, a wet etching process may be used to remove the first spacer layer 391 located in the array region 311 and the first circuit region 312 .

[0072] It can be understood that removing the first spacer layer 391 in the array region 311 and the first circuit region 312 refers to removing the first initial opening 37a (refer to FIG. Figure 5 ) inner wall and the first sidewall layer 391 located on the top surface of the first mask layer 373, due to the first initial opening 37a (reference Figure 5 ) is covered by the second mask layer 402, so in this step, the first initial opening 37a (reference Figure 5 ) The first spacer layer 391 at the bottom is not removed.

[0073] refer to Figure 9 , etching the initial target film 361 located just below the gap (refer to Figure 8) to form a target layer 362 having a first opening 36a.

[0074] In some embodiments, a dry etching process may be used to etch the initial target film 361 until the top surface of the intermediate layer 352 is exposed.

[0075] After forming the target layer 362, the remaining first spacer layer 391 is removed (refer to Figure 8 ), the first mask layer 373 (reference Figure 8 ) and the second mask layer 402 (reference Figure 8 ).

[0076] Using the first mask layer 373 (reference Figure 8 ) and the second mask layer 402 (reference Figure 8 ) stacking method, that is, using a double patterning method, can form a first opening 36a with a smaller size, making the pattern morphology and position in the target layer 362 more precise.

[0077] refer to Figures 10 to 19 , patterning the target layer 362 located between adjacent first openings 36a in the array area 311 to form a second opening 36b passing through the target layer 362, and patterning the target layer 362 located in the first circuit area 312 and the second circuit area 313 to form a third opening 36c passing through the target layer 362.

[0078] In some embodiments, the target layer 362 has multiple rows of second openings 36b arranged along a preset direction, and each second opening 36b has a second extension direction. The angle between the second extension direction and the preset direction can be 60°. In a plane parallel to the substrate 31, the orthographic projection of the first extension direction is oblique to the orthographic projection of the second extension direction.

[0079] The process steps for forming the second opening 36 b in some embodiments will be described in detail below with reference to the accompanying drawings.

[0080] refer to Figure 10 , forming a first opening 36a filled with Figure 9 ) and covers the third mask layer 411 on the top surface of the target layer 362, and the top surfaces of the third mask layer 411 in the array area 311, the first circuit area 312 and the second circuit area 313 are gradually increased.

[0081] The material of the third mask layer 411 is different from the material of the target layer 362; in addition, in some embodiments, the material of the third mask layer 411 can be different from the material of the second mask layer 402 (refer to Figure 8 ) are made of the same material, which can be carbon or carbon-containing organic matter.

[0082] During the formation of the third mask layer 411, the formation rate and formation time of different regions are the same, that is, the total amount of the third mask layer 411 material on the array region 311, the first circuit region 312 and the second circuit region 313 is the same. Figure 9 ) are arranged in descending order. It can be understood that the total opening area of the openings in the array region 311 is the largest. Therefore, in the first opening 36a (reference Figure 9 ) The more material of the third mask layer 411 that can be accommodated, the top surface of the third mask layer 411 in the array area 311 is the lowest, and the top surface of the third mask layer 411 in the second circuit area 313 is the highest.

[0083] refer to Figures 10 to 13 A first stop layer 412 and a fourth mask layer 423 are sequentially formed on the third mask layer 411. The fourth mask layer 423 of the array area 311 has a fourth opening 42a that penetrates the fourth mask layer 423. The fourth mask layer 423 of the second circuit area 313 has a fourth opening 42a that penetrates the fourth mask layer 423, and a second sidewall layer 392 is formed on the inner wall of the fourth opening 42a in the array area 311.

[0084] First stop layer 412 is used to protect third mask layer 411. Accordingly, the material of first stop layer 412 is different from that of third mask layer 411 and fourth mask layer 423. In some embodiments, first stop layer 412 may be made of silicon oxide and may be formed using an atomic layer deposition process.

[0085] The fourth mask layer 423 is used as a mask for the target layer 362 to form the second opening 36b on the target layer 362. The material of the fourth mask layer 423 may be the same as that of the third mask layer 411.

[0086] Specifically, in some embodiments, the process steps of forming the fourth opening 42 a and the second spacer layer 392 may include:

[0087] refer to Figure 10 and Figure 11 A fourth preliminary mask 421 is formed on the first stop layer 412 , and a fourth opening 42 a penetrating through the fourth preliminary mask 421 is defined in the fourth preliminary mask 421 of the array region 311 .

[0088] The top surface of the fourth initial mask 421 in the array area 311, the first circuit area 312, and the second circuit area 313 gradually increases. This is because, during the formation of the fourth initial mask 421, the formation rate and formation time of different regions are the same. Since the top surface of the third mask layer 411 in the array area 311, the first circuit area 312, and the second circuit area 313 gradually increases, and the fourth initial mask 421 covers the top surface of the third mask layer 411, the top surface of the fourth initial mask 421 in the array area 311, the first circuit area 312, and the second circuit area 313 gradually increases.

[0089] refer to Figure 11 In some embodiments, a fourth opening 42 a is formed in the fourth preliminary mask 421 of the array region 311 , penetrating the fourth preliminary mask 421 .

[0090] In some embodiments, the fourth opening may be formed by mask etching.

[0091] It is understandable that the number and opening width of the fourth openings 42 a can be adjusted according to needs.

[0092] Continue to refer Figure 11 , forming a second spacer layer 392 , the second spacer layer 392 is located on the inner wall of the fourth opening 42 a of the array region 311 .

[0093] The material of the second spacer layer 392 is different from the material of the third mask layer 411 and the fourth preliminary mask layer 421 .

[0094] In some embodiments, the second sidewall layer 392 can be formed by atomic layer deposition. The second sidewall layer 392 formed by atomic layer deposition has the advantages of good density and good uniformity in covering the inner wall of the fourth opening 42a, which is beneficial to further improve the morphological accuracy of the second opening formed subsequently.

[0095] During the process of forming the second spacer 392 , a second spacer 392 is further formed at the bottom of the fourth opening 42 a and the top of the fourth initial mask 421 .

[0096] In some other embodiments, the second spacer layer may also be located only on the inner wall of the fourth opening.

[0097] refer to Figure 12 and Figure 13 , patterning the fourth preliminary mask 421 of the second circuit region 313 to form a fourth opening 42 a in the fourth preliminary mask 421 of the second circuit region 313 , and the remaining fourth preliminary mask 421 serves as a fourth mask layer 423 .

[0098] In some embodiments, the process steps of patterning the fourth initial mask 421 of the second circuit region 313 include:

[0099] refer to Figure 12 , forming a fourth opening 42a that fills the array region 311 (refer to Figure 11 ), and the first pattern layer 382 of the second circuit region 313 has a through hole 38a penetrating the first pattern layer 382.

[0100] The first pattern layer 382 is located in the array region 311 , the first circuit region 312 , and the second circuit region 313 . The material of the first pattern layer 382 can be the same as that of the fourth mask layer 423 .

[0101] refer to Figure 13 , with the first graphic layer 382 (reference Figure 12 ) is used as a mask, and the fourth initial mask 421 of the second circuit region 313 is etched (reference Figure 12 ) to form a fourth opening 42a located in the second circuit region 313, and remove the first pattern layer 382 (refer to Figure 12 ).

[0102] Specifically, a dry etching process can be used to etch the through hole 38a (refer to Figure 12 ) The fourth initial mask 421 is etched at the bottom (reference Figure 12 ), until the first stop layer 412 is exposed.

[0103] The purpose of forming the fourth opening 42a includes: a fifth mask layer will be formed subsequently. Since the second circuit area 313 has the fourth opening 42a, the top surface height of the fifth mask layer formed in the second circuit area 313 can be reduced, preventing a large difference in the top surface height of the fifth mask layer between different areas, thereby avoiding problems such as the collapse of the fifth mask layer.

[0104] It is understandable that, in other embodiments, the fourth opening 42 a may not be formed in the fourth initial mask 421 of the second circuit region 313 .

[0105] refer to Figure 14 , forming a fourth opening 42a filled with Figure 13 ) and a fifth mask layer 431 located on the top surface of the fourth mask layer 423 , and a top surface of the fifth mask layer 431 in the first circuit region 312 is higher than top surfaces of the fifth mask layer 431 in the array region 311 and the second circuit region 313 .

[0106] The material of the fifth mask layer 431 may be the same as that of the fourth mask layer 423 .

[0107] During the formation of the fifth mask layer 431, the formation rate and formation time of different regions are the same, that is, the total amount of the fifth mask layer 431 material on the array region 311, the first circuit region 312 and the second circuit region 313 is the same. Figure 13 ) is arranged at a density greater than that of the fourth openings 42a of the first circuit region 312 (reference Figure 13 ) and the fourth opening 42a of the second circuit region 313 (reference Figure 13 ) is arranged at a density greater than that of the fourth openings 42a of the first circuit region 312 (reference Figure 13 ) arrangement density, it can be understood that the total opening area of the openings in the array region 311 is larger than the total opening area of the first circuit region 312, so the fourth opening 42a (reference Figure 13 ) can accommodate more material of the fifth mask layer 431, and the top surface of the fifth mask layer 431 in the array area 311 is lower than the top surface of the fifth mask layer 431 in the first circuit area 312. Similarly, the top surface of the fifth mask layer 431 in the second circuit area 313 is lower than the top surface of the fifth mask layer 431 in the first circuit area 312. By lowering the height of the fifth mask layer 431 in the second circuit area 313, it is possible to avoid a situation where the height difference of the fifth mask layer 431 between the second circuit area 313 and the array area 311 is too large, resulting in part of the material in the second circuit area 313 sliding toward the array area 311.

[0108] In some embodiments, the materials of the third mask layer 411 , the fourth mask layer 423 and the fifth mask layer 431 may be the same, and may all be carbon or organic matter containing carbon.

[0109] Before forming the fifth mask layer 431 , the process may further include forming a second stop layer 422 on the top surface of the fourth mask layer 423 , wherein the material of the second stop layer 422 is different from that of the fourth mask layer 423 .

[0110] The material of the second stop layer 422 may be silicon oxynitride, and the second stop layer 422 serves as an etching stop during the subsequent etching process of the fifth mask layer 431 .

[0111] refer to Figure 15 , the fifth mask layer 431 is etched back to expose the second spacer layer 392 located on the top of the fourth mask layer 423 in the array area 311 .

[0112] In some embodiments, the fifth mask layer 431 may be etched back using a dry etching process.

[0113] Since the thickness of the fifth mask layer 431 located directly above the fourth mask layer 423 of the second circuit area 312 is greater than the thickness of the fifth mask layer 431 located directly above the fourth mask layer 423 of the array area 311, during the process of etching back the fifth mask layer 431, in addition to etching away the fifth mask layer 431 directly above the fourth mask layer 423 of the second circuit area 312, the fourth opening 42a located in the second circuit area 312 is also removed (refer to FIG. Figure 13 ) within a portion of the fifth mask layer 431.

[0114] refer to Figure 16 and Figure 17 , remove the second spacer layer 392 , and use the fifth mask layer 431 and the fourth mask layer 423 as masks to etch the third mask layer 411 and the target layer 362 to form a second opening 36 b .

[0115] refer to Figure 16 , remove the second spacer layer 392.

[0116] Specifically, the second spacer 392 between the fourth mask layer 423 and the fifth mask layer 431 in the array region 311 is removed until the surface of the first stop layer 412 is exposed. The second spacer 392 on the top surface of the fourth mask layer 423 in the array region 311 can also be removed.

[0117] In some embodiments, a wet etching process may be used to remove the second spacer layer.

[0118] refer to Figure 17 , with the fifth mask layer 431 (reference Figure 16 ) and the fourth mask layer 423 (reference Figure 16 ) is a mask, and the third mask layer 411 is etched (reference Figure 16 ) and the target layer 362 to form a second opening 36b.

[0119] In some embodiments, a dry etching process may be used to etch the first stop layer 412 (refer to Figure 16 ), the third mask layer 411 (reference Figure 16 ) and the target layer 362 until the surface of the intermediate layer 352 is exposed.

[0120] After forming the second opening, the fifth mask layer 431 (refer to Figure 16 ), the second sidewall layer 392 (reference Figure 16 ), the second stop layer 422 (reference Figure 16 ), the fourth mask layer 423 (reference Figure 16 ), the first stop layer 412 (reference Figure 16 ) and the third mask layer 411 (reference Figure 16 ).

[0121] The following will be combined Figure 18 and Figure 19 , the process steps for forming the third opening provided in some embodiments are described:

[0122] refer to Figure 18 , a sixth mask layer 441 is formed that fills the second opening 36 b and is located on the top surface of the target layer 362 , and the top surfaces of the sixth mask layer 441 in the array area 311 , the first circuit area 312 , and the second circuit area 313 gradually increase.

[0123] During the process of forming the sixth mask layer 441, the formation rate and formation time are the same in different regions. That is, the total amount of sixth mask layer 441 material in the array region 311, the first circuit region 312, and the second circuit region 313 is the same. Since the arrangement density of the openings in the array region 311, the first circuit region 312, and the second circuit region 313 decreases in sequence, it can be understood that the total opening area of the openings in the array region 311 is the largest. Therefore, the openings in the array region 311 can accommodate more material of the sixth mask layer 441, and the top surface of the sixth mask layer 441 in the array region 311 is the lowest.

[0124] In some embodiments, the material of the sixth mask layer 441 may be the same as that of the fifth mask layer 431 (see Figure 16 ) are made of the same material.

[0125] In some embodiments, a third stop layer 442 is further formed on the top surface of the sixth mask layer 441 , and the material of the third stop layer 442 is different from that of the sixth mask layer 441 .

[0126] The material of the third stop layer 442 may be silicon oxynitride, and the third stop layer 442 serves as an etching stop during the subsequent etching process of the sixth mask layer 441 .

[0127] Continue to refer Figure 18 , a second pattern layer 383 is formed on the sixth mask layer 441 , and the second pattern layer 383 in the first circuit region 312 and the second circuit region 313 both have trenches 38b penetrating the second pattern layer 383 .

[0128] In some embodiments, the second pattern layer 383 may be a photoresist layer.

[0129] In some embodiments, after forming the sixth mask layer 441 and before forming the second pattern layer 383, a third stop layer 442 is further formed. The material of the third stop layer 442 may be the same as that of the second stop layer 422 (see FIG. Figure 16 ) is made of the same material, thereby reducing the types of materials required for production. The third stop layer 442 serves as an etching stop in the subsequent etching process of the sixth mask layer 441.

[0130] refer to Figure 19 , with the second graphic layer 383 (reference Figure 18 ) is a mask, and the sixth mask layer 441 is etched (reference Figure 18 ) until the target layer 362 is exposed, and then the sixth mask layer 441 (reference Figure 18 ) is used as a mask to etch the target layer 362 to form a third opening 36c.

[0131] After forming the third opening 36c, the second pattern layer 383 is removed (refer to Figure 18 ), the third stop layer 442 (reference Figure 18 ) and the sixth mask layer 441 (reference Figure 18 ).

[0132] refer to Figure 20 , to have a first opening 36a (reference Figure 19 ), the second opening 36b (reference Figure 19 ) and the third opening 36c (reference Figure 19 ) target layer 362 (reference Figure 19 ) is a mask, and the intermediate layer 352 is etched in sequence (reference Figure 19 ), amorphous carbon layer 351 (reference Figure 19 ) and the conversion layer 341 to form a first trench 34a in the conversion layer 341.

[0133] In some embodiments, the conversion layer 341 is etched using a dry etching process.

[0134] After forming the first trench 34a, the target layer 362 is removed (refer to Figure 19 ), intermediate layer 352 (reference Figure 19 ) and the amorphous carbon layer 351 (reference Figure 19 ).

[0135] refer to Figure 21 and Figure 22 , forming a first trench 34a filled with Figure 20 ) filling layer 452.

[0136] Specifically, refer to Figure 21 , forming an initial filling film 451 , which also covers the top surface of the conversion layer 341 .

[0137] refer to Figure 22 , remove the initial filling film 451 on the top surface of the conversion layer 341 (reference Figure 21 ), to form a filling layer 452,

[0138] In some embodiments, the material of the filling layer 452 is different from the material of the conversion layer 341 , and the material of the filling layer 452 may be silicon nitride.

[0139] The filling layer 452 is used to ensure that the pattern of the second conductive layer is accurately formed.

[0140] refer to Figure 23 , remove the conversion layer 341 (reference Figure 22 ) to form a second trench 45a that penetrates the filling layer 452, and the second trench 45a in the array area 311 exposes the top surface of the first conductive layer 331, the second trench 45a in the first circuit area 312 exposes the top surface of the first conductive plug 324, and the second trench 45a in the second circuit area 313 exposes the top surface of the second conductive plug 326.

[0141] refer to Figure 24 and Figure 25 , forming a second trench 45a filled with Figure 23 )'s second conductive layer 333.

[0142] Specifically, in some embodiments, the process steps of forming the second conductive layer 333 include: forming a second conductive layer 333 that fills the second trench 45a (refer to Figure 23 ) of the conductive film 332, and the conductive film 332 is also located on the top surface of the filling layer 452; the conductive film 332 higher than the top surface of the filling layer 452 is removed, and the remaining conductive film 332 serves as the second conductive layer 333.

[0143] The second conductive layer 333 is used to achieve electrical connection with the capacitor contact plug 322 , the first conductive plug 324 and the second conductive plug 326 in the dielectric layer 321 .

[0144] In some embodiments, the material of the second conductive layer 333 can be metal, and can be the same as the material of the first conductive layer 331, and can be tungsten metal, etc., which is beneficial to reduce the probability of abnormalities occurring between the second conductive layer 333 and the first conductive layer 331 due to different materials, thereby improving the yield of the semiconductor structure.

[0145] It is understandable that the second conductive layer 333 may be formed on the surface of the dielectric layer 321 by performing some of the above steps.

[0146] In the embodiment of the present application, a filling layer having a second groove is formed on the dielectric layer, and then a target material is filled into the target pattern in the filling layer to form the desired second conductive layer. Thus, the thickness of the second conductive layer can be controlled by controlling the thickness of the filling layer perpendicular to the semiconductor substrate, and a second conductive layer with a precise pattern can be formed, thereby improving the performance of the semiconductor structure.

[0147] The present application also provides a semiconductor structure, referring to Figure 25, including a semiconductor structure formed by some or all of the aforementioned steps. It should be noted that the parts that are the same as or corresponding to the aforementioned embodiments can refer to the corresponding description of the aforementioned embodiments and will not be repeated below.

[0148] Specifically, a substrate 31 and a dielectric layer 321 located on the substrate 31 are provided. The substrate 31 includes an array area 311, a first circuit area 312, and a second circuit area 313. The first circuit area 312 is located between the array area 311 and the second circuit area 313. The substrate 31 of the array area 311 has a plurality of discrete capacitor contact plugs 322. The substrate 31 of the first circuit area 312 has a first gate 323. The first circuit area 312 also has first conductive plugs located on opposite sides of the first gate 323. Plug 324, a second gate 325 is provided on the substrate 31 of the second circuit area 313, and the second circuit area 313 further has second conductive plugs 326 located on opposite sides of the second gate 325, and the first gate 323, the second gate 325 and the capacitor contact plug 322 are located in the dielectric layer 321, the first conductive layer 331 is located on the top surface of the capacitor contact plug 322, the second conductive layer 333 covers a portion of the top surface of the first conductive layer 331, and the filling layer 452 fills the groove in the second conductive layer 333.

[0149] The embodiment of the present application improves the performance of the semiconductor structure by using a semiconductor structure with a second conductive layer having a precise pattern and controllable thickness.

[0150] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: A substrate and a dielectric layer located on the substrate are provided. The substrate includes an array region, a first circuit region, and a second circuit region, wherein the first circuit region is located between the array region and the second circuit region. The substrate in the array region has a plurality of discrete capacitor contact plugs. The substrate in the first circuit region has a first gate, and the first circuit region also has first conductive plugs located on opposite sides of the first gate. The substrate in the second circuit region has a second gate, and the second circuit region also has second conductive plugs located on opposite sides of the second gate. The first gate, the second gate, and the capacitor contact plugs are located within the dielectric layer, and a first conductive layer is further formed on top surfaces of the capacitor contact plugs. forming a conversion layer and a target layer on the first conductive layer and the dielectric layer in sequence, wherein the target layer in the array region and the target layer in the first circuit region both have first openings penetrating the target layer, and a pattern density of the first openings in the array region is greater than a pattern density of the first openings in the first circuit region; Patterning the target layer between adjacent first openings in the array region to form a second opening penetrating the target layer, and patterning the target layer in the first circuit region and the second circuit region to form a third opening penetrating the target layer; Using the target layer having the first opening, the second opening, and the third opening as a mask, etching the conversion layer to form a first trench in the conversion layer; forming a filling layer that completely fills the first trench and removing the conversion layer to form a second trench penetrating the filling layer, wherein the second trench in the array area exposes a top surface of the first conductive layer, the second trench in the first circuit area exposes a top surface of the first conductive plug, and the second trench in the second circuit area exposes a top surface of the second conductive plug; A second conductive layer is formed to fill the second trench.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The process steps of forming the target layer include: forming an initial target film on the conversion layer; forming a first mask layer on the initial target film, wherein the first mask layer in the array region and the first circuit region both have first initial openings, and the pattern density of the first initial openings in the array region is greater than the pattern density of the first initial openings in the first circuit region; forming a first sidewall layer covering an inner wall of the first initial opening; forming a second mask layer covering the first spacer layer and filling the first initial opening, wherein the second mask layer also exposes a top surface of the first spacer layer; The first spacer layer is removed, and the initial target film is etched using the first mask layer and the second mask layer as masks to form the target layer.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The material of the first mask layer is the same as that of the second mask layer.

4. The method for manufacturing a semiconductor structure according to claim 2, wherein: The process steps of forming the second mask layer include: forming a second initial mask covering the first spacer layer and completely filling the first initial opening, wherein the second initial mask is also located on top of the first mask layer, and the top surfaces of the second initial mask in the second circuit area, the first circuit area, and the array area decrease in height in sequence; The second initial mask is etched back until the top surface of the first sidewall layer at the inner wall of the first initial opening is exposed, and the remaining second initial mask serves as the second mask layer.

5. The method for manufacturing a semiconductor structure according to claim 2, wherein: In the process step of forming the first spacer layer, the first spacer layer is further formed at the bottom of the first initial opening and the top surface of the first mask layer; The formed second mask layer also exposes the first sidewall layer located on the top surface of the first mask layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The process steps of forming the second opening include: forming a third mask layer that fills the first opening and covers the top surface of the target layer, and sequentially forming a first stop layer and a fourth mask layer on the third mask layer, wherein the fourth mask layer in the array area and the second circuit area both has a fourth opening penetrating the fourth mask layer, and a second spacer layer is formed on an inner wall of the fourth opening in the array area; forming a fifth mask layer that fills the fourth opening and is located on a top surface of the fourth mask layer, wherein a top surface of the fifth mask layer in the first circuit area is higher than top surfaces of the fifth mask layer in the array area and the second circuit area; Etching back the fifth mask layer to expose the second sidewall spacer layer located on top of the fourth mask layer in the array area; The second spacer layer is removed, and the third mask layer and the target layer are etched using the fifth mask layer and the fourth mask layer as masks to form the second opening.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The material of the third mask layer and the fourth mask layer is the same as the material of the fifth mask layer; Before forming the fifth mask layer, the method further includes: A second stop layer is formed on the top surface of the fourth mask layer, and a material of the second stop layer is different from a material of the fourth mask layer.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: The process steps of forming the fourth opening and the second spacer layer include: forming a fourth initial mask on the first stop layer, wherein the fourth initial mask in the array region has a fourth opening penetrating the fourth initial mask; forming a second spacer layer, wherein the second spacer layer is located on an inner wall of the fourth opening in the array region; The fourth preliminary mask of the second circuit region is patterned to form the fourth opening in the fourth preliminary mask of the second circuit region, and the remaining fourth preliminary mask serves as the fourth mask layer.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: The process steps of patterning the fourth initial mask of the second circuit area include: forming a first patterned layer that completely fills the fourth opening in the array region, and forming a through hole penetrating the first patterned layer in the first patterned layer in the second circuit region; Using the first patterned layer as a mask, etching the fourth initial mask of the second circuit region to form the fourth opening located in the second circuit region; The first graphic layer is removed.

10. The method for manufacturing a semiconductor structure according to claim 6, wherein: In the process step of etching back the fifth mask layer, a portion of the fifth mask layer located in the fourth opening of the second circuit region is also etched away.

11. The method for manufacturing a semiconductor structure according to claim 1, wherein: The process steps of forming the third opening include: forming a sixth mask layer that fills the second opening and is located on a top surface of the target layer; forming a second patterned layer on the sixth mask layer, wherein the second patterned layer in the first circuit area and the second circuit area both have a groove penetrating the second patterned layer; Using the second pattern layer as a mask, the sixth mask layer is etched until the target layer is exposed, and then the target layer is etched using the sixth mask layer as a mask to form the third opening.

12. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the conversion layer and before forming the target layer, the method further includes: sequentially forming an amorphous carbon layer and an intermediate layer on the conversion layer; The target layer is formed on the surface of the intermediate layer.

13. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of the conversion layer includes silicon nitride or polysilicon; the material of the target layer includes TEOS.

14. The method for manufacturing a semiconductor structure according to claim 1, wherein: The process steps of forming the second conductive layer include: forming a conductive film that completely fills the second trench, wherein the conductive film is also located on the top surface of the filling layer; The conductive film above the top surface of the filling layer is removed, and the remaining conductive film serves as the second conductive layer.

15. The method for manufacturing a semiconductor structure according to claim 1 or 14, wherein: The second conductive layer is made of metal.

16. A semiconductor structure, characterized in that The semiconductor structure is formed by the semiconductor structure manufacturing method according to any one of claims 1 to 15.

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