Analog-to-digital conversion circuit, integrated chip, display device and analog-to-digital conversion method

Abstract

The embodiments of the present disclosure disclose an analog-to-digital conversion circuit, an integrated chip, a display device and an analog-to-digital conversion method. A first conversion circuit converts an original analog signal to obtain a digital signal with a first bit width. A voltage dividing circuit divides the first-stage analog signal to obtain a second-stage analog signal. The first-stage analog signal is the original analog signal or a second-stage analog signal obtained by a previous voltage dividing circuit adjacent to the voltage dividing circuit. A second conversion circuit converts the received second-stage analog signal according to a preset algorithm to obtain a second digital signal with a second bit width. A control calculation circuit obtains a target digital signal with a third bit width according to the first digital signal and the second digital signal. Since the bit width of the target digital signal is greater than the bit width of the first digital signal obtained by the first conversion circuit and also greater than the bit width of the second digital signal obtained by the second conversion circuit, the bit width of the output digital signal is higher than that in the prior art, thereby improving the accuracy of the output digital signal.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to an analog-to-digital conversion circuit, an integrated chip, a display device, and an analog-to-digital conversion method. Background Technology

[0002] Analog-to-digital converters (ADCs) are primarily used to convert analog signals into digital signals. With the development of science and technology, ADCs are widely used in various measurement systems that require processing analog sensor signals, such as data acquisition systems for measuring pressure, flow rate, speed, and temperature. Generally, these signals have time-domain signatures and appear in the form of impulses or step functions. In any design, understanding the overall system accuracy for these types of applications is always crucial, especially for systems that require quantification of extremely small sensitivities and variations in waveforms.

[0003] Currently, the conversion accuracy and cost of an ADC mainly depend on the ADC bit width. The higher the ADC bit width, the higher the sampling accuracy. Since the cost of an ADC increases exponentially with the ADC bit width, low-bit-width ADCs are usually used to convert analog signals in order to save costs. However, low-bit-width ADCs result in low accuracy of the converted digital signal. Summary of the Invention

[0004] This disclosure provides an analog-to-digital conversion circuit, an integrated chip, a display device, and an analog-to-digital conversion method.

[0005] In a first aspect, this disclosure provides an analog-to-digital conversion circuit, comprising:

[0006] The first conversion circuit is configured to convert the original analog signal to obtain a first digital signal with a first bit width;

[0007] At least one voltage divider circuit is configured to divide a first-stage analog signal to obtain a second-stage analog signal, wherein the first-stage analog signal is the original analog signal or the second-stage analog signal output by the previous voltage divider circuit adjacent to the voltage divider circuit.

[0008] The second conversion circuit corresponding to the voltage divider circuit is configured to convert the received second-level analog signal according to a preset algorithm to obtain a second digital signal with a second bit width;

[0009] The control calculation circuit is configured to obtain a target digital signal with a third bit width based on the first digital signal and the second digital signal;

[0010] Wherein, the third bit width is greater than the first bit width, and the third bit width is greater than the second bit width.

[0011] In some examples, the voltage divider circuit includes a plurality of voltage divider resistors and a first switching transistor corresponding to each voltage divider resistor;

[0012] The plurality of voltage divider resistors are connected in series;

[0013] In the series-connected voltage divider resistors, the first end of each voltage divider resistor is connected to the first end of its corresponding first switching transistor.

[0014] The second terminals of each first switching transistor are interconnected and connected to the second conversion circuit corresponding to the voltage divider circuit. The control terminal of each first switching transistor is connected to the control calculation circuit.

[0015] The first terminal of the first voltage divider resistor is used to input the first-stage analog signal, and the second terminal of the last voltage divider resistor is grounded.

[0016] In some examples, the number of voltage divider circuits in the at least one voltage divider circuit is one;

[0017] The first-level analog signal is the original analog signal.

[0018] In some examples, the at least one voltage divider circuit has multiple voltage divider circuits, and the multiple voltage divider circuits are connected in series;

[0019] The first-stage analog signal is the second-stage analog signal output by the previous voltage divider circuit connected in series with the voltage divider circuit.

[0020] In some examples, the at least one voltage divider circuit has multiple voltage divider circuits connected in parallel.

[0021] The first-level analog signal is the original analog signal.

[0022] In some examples, the control calculation circuit is specifically configured to control the conduction of a first switch of at least one voltage divider circuit in the voltage divider circuit according to the first digital signal.

[0023] In some examples, the first conversion circuit includes a first analog-to-digital converter with the first bit width and a second switching transistor;

[0024] The first terminal of the second switch is configured to input the original analog signal, the second terminal of the second switch is electrically connected to the input terminal of the first analog-to-digital converter, the control terminal of the second switch is electrically connected to the control calculation circuit, and the output terminal of the first analog-to-digital converter is electrically connected to the control calculation circuit.

[0025] The control calculation circuit is specifically configured to control the second switch to be turned on at a first sampling time and to control the second switch to be turned off at a second sampling time, wherein the first sampling time is earlier than the second sampling time.

[0026] In some examples, the second conversion circuit includes a second analog-to-digital converter;

[0027] The input terminal of the second analog-to-digital converter is electrically connected to the second terminal of each first switching transistor in the corresponding voltage divider circuit, and the output terminal of the second analog-to-digital converter is electrically connected to the control calculation circuit.

[0028] The control calculation circuit is specifically configured such that, if the first digital signal is within a first preset range, the first switch corresponding to the first voltage divider resistor of at least one voltage divider circuit in the voltage divider circuit is turned on at the second sampling time; if the first digital signal is within a second preset range, a first switch of at least one voltage divider circuit in the voltage divider circuit is turned on at the second sampling time according to the first digital signal.

[0029] In some examples, the control calculation circuit is specifically configured as follows:

[0030] The first digital signal is adjusted based on a preset value;

[0031] The sum of the adjusted digital signal and the second digital signal is taken as the target digital signal.

[0032] In some examples, the bit width of the first analog-to-digital converter is equal to the bit width of the second analog-to-digital converter.

[0033] In some examples, the preset algorithm is the A-law 13-segment algorithm.

[0034] In a second aspect, this disclosure provides an integrated chip including any of the analog-to-digital conversion circuits described in the first aspect.

[0035] Thirdly, this disclosure provides a display device including the integrated chip described in the second aspect.

[0036] Fourthly, this disclosure provides an analog-to-digital conversion method, applied to any of the analog-to-digital conversion circuits described in the first aspect, comprising:

[0037] The received original analog signal is converted by the first conversion circuit to obtain a first digital signal with a width of one bit.

[0038] The first-level analog signal is divided by one of the at least one voltage divider circuits to obtain the second-level analog signal, wherein the first-level analog signal is the original analog signal, or the second-level analog signal obtained by the previous voltage divider circuit adjacent to the first voltage divider circuit.

[0039] The second conversion circuit converts the received second-level analog signal according to a preset algorithm to obtain a second digital signal with a second bit width;

[0040] Based on the first digital signal and the second digital signal value, a target digital signal with a third bit width is obtained;

[0041] Wherein, the third bit width is greater than the first bit width, and the third bit width is greater than the second bit width.

[0042] In some examples, the number of voltage divider circuits in the at least one voltage divider circuit is one;

[0043] The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes:

[0044] Based on the first digital signal, the first-stage analog signal is divided by controlling the conduction of a switch in the voltage divider circuit to obtain the second-stage analog signal, wherein the first-stage analog signal is the original analog signal.

[0045] In some examples, the at least one voltage divider circuit has multiple voltage divider circuits, and the multiple voltage divider circuits are connected in series;

[0046] The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes:

[0047] Based on the first digital signal, the first-level analog signal is divided by controlling the conduction of a switch in one of the at least one voltage divider circuits to obtain the second-level analog signal, wherein the first-level analog signal is the second-level analog signal output by the previous voltage divider circuit adjacent to the voltage divider circuit.

[0048] In some examples, the at least one voltage divider circuit has multiple voltage divider circuits connected in parallel.

[0049] The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes:

[0050] Based on the first digital signal, the first-stage analog signal is divided by controlling the conduction of a switch in one of the at least one voltage divider circuits to obtain the second-stage analog signal, wherein the first-stage analog signal is the original analog signal.

[0051] In some examples, if the first digital signal is within a first preset range, the second-stage analog signal is made equal to the original analog signal by controlling the conduction of a switch in one of the voltage divider circuits in the at least one voltage divider circuit.

[0052] If the first digital signal is within a second preset range, then based on the first digital signal, the original analog signal is divided by controlling the conduction of a switching transistor in one of the at least one voltage divider circuits to obtain the second-level analog signal.

[0053] In some examples, obtaining the third-bit-width target digital signal based on the first digital signal and the second digital signal includes:

[0054] The first digital signal is adjusted based on a preset value;

[0055] The sum of the adjusted digital signal and the second digital signal is taken as the target digital signal. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of the structure of an analog-to-digital converter circuit provided in an embodiment of the present disclosure;

[0058] Figure 2 This is a schematic diagram of another analog-to-digital converter circuit provided in an embodiment of the present disclosure;

[0059] Figure 3 This is a schematic diagram of the A-rate 13-segment line algorithm curve;

[0060] Figure 4 This is a schematic diagram of another analog-to-digital converter circuit provided in an embodiment of the present disclosure;

[0061] Figure 5 This is a schematic diagram of another analog-to-digital converter circuit provided in an embodiment of the present disclosure;

[0062] Figure 6This is a schematic diagram of an analog-to-digital conversion method provided in an embodiment of the present disclosure. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0065] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual scale and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0066] like Figure 1 As shown in the embodiments of this disclosure, an analog-to-digital conversion circuit may include: a control calculation circuit 10, a first conversion circuit 20, at least one voltage divider circuit 30, and a second conversion circuit 40 corresponding to the voltage divider circuit.

[0067] The first conversion circuit 20 is configured to convert the original analog signal to obtain a first digital signal with a first bit width;

[0068] At least one voltage divider circuit 30 is configured to divide a first-stage analog signal to obtain a second-stage analog signal, wherein the first-stage analog signal is the original analog signal or the second-stage analog signal output by the previous voltage divider circuit adjacent to the voltage divider circuit.

[0069] The second conversion circuit 40, corresponding to the voltage divider circuit 30, is configured to convert the received second-level analog signal according to a preset algorithm to obtain a second digital signal with a second bit width.

[0070] The control calculation circuit 10 is configured to obtain a target digital signal with a third bit width based on the first digital signal and the second digital signal;

[0071] The width of the third character is greater than the width of the first character, and the width of the third character is greater than the width of the second character.

[0072] The analog-to-digital converter circuit provided in this embodiment converts the original analog signal to obtain a digital signal with a first bit width. A voltage divider circuit divides the first-level analog signal to obtain a second-level analog signal. The first-level analog signal is either the original analog signal or the second-level analog signal output by the previous voltage divider circuit adjacent to the voltage divider circuit. A second conversion circuit converts the received second-level analog signal according to a preset algorithm to obtain a second digital signal with a second bit width. A control calculation circuit obtains a target digital signal with a third bit width based on the first and second digital signals. The third bit width is greater than the first bit width and the third bit width is greater than the second bit width. Since the bit width of the obtained target digital signal is greater than the bit width of the first digital signal obtained by the first conversion circuit and also greater than the bit width of the second digital signal obtained by the second conversion circuit, it is higher than the bit width of the output digital signal in the prior art, thereby improving the accuracy of the output digital signal.

[0073] It should be noted that when the voltage divider circuit is connected in series with the preceding voltage divider circuit, see [reference needed]. Figure 1 For a voltage divider circuit, the voltage divider voltage closest to the input original analog signal in two adjacent voltage divider circuits.

[0074] In specific implementations, the analog-to-digital conversion circuit provided in the embodiments of this disclosure may include a voltage divider circuit and a second conversion circuit, or it may include multiple voltage divider circuits and multiple second conversion circuits, which will be described below.

[0075] In some examples, the number of voltage divider circuits in at least one analog-to-digital converter circuit is one, that is, the analog-to-digital converter circuit includes one voltage divider circuit and one second conversion circuit:

[0076] like Figure 2 The diagram shown is a schematic representation of an analog-to-digital converter circuit provided in an embodiment of this disclosure. Figure 2 As can be seen from this, the voltage divider circuit 20 includes 2 n One voltage divider resistor and 2 n Each first switching transistor has a voltage divider resistor that corresponds to a first switching transistor.

[0077] 2 nSeveral voltage divider resistors are connected in series. In this series resistor, the first terminal of the first voltage divider resistor R1 is used to input the original analog signal. The second terminal of each voltage divider resistor is connected to the first terminal of its corresponding first switching transistor, and the last voltage divider resistor R2... n The second terminal is grounded;

[0078] The second terminals of each first switching transistor are interconnected and connected to the input terminal of the second conversion circuit. The control terminal of each first switching transistor is connected to the control calculation circuit 10 to receive the control signal sent by the control calculation circuit 10 and control the first switching transistor to turn on and off.

[0079] Where n is a positive integer.

[0080] It should be noted that in the embodiments disclosed in this invention, the voltage divider resistor has a first end and a second end, the first switching transistor has a control end, a first end and a second end, and the second switching transistor has a control end, a first end and a second end.

[0081] The first-stage analog signal input to the voltage divider circuit 30 is the original analog signal, which will be processed by 2... n The voltage is divided by a voltage divider resistor, and the divided analog signal is input to the second conversion circuit 40.

[0082] In this embodiment of the invention, the first conversion circuit may include a second switching transistor G0 and a first analog-to-digital converter ADC1 with a first bit width, the second conversion circuit may include a second analog-to-digital converter ADC2, and the control calculation circuit 10 may be an MCU (Microcontroller Unit).

[0083] In implementation, the specific connection method between the circuits can be as follows: the first terminal of the second switch G0 is used to input the original analog signal; the second terminal of the second switch G0 is connected to the input terminal of ADC1; the control terminal of the second switch G0 is connected to the MCU to receive the control signal sent by the MCU to control the second switch G0 to turn on and off; the output terminal of ADC1 is connected to the MCU to input the first digital signal to the MCU; the first switches (G1, G2, G3...G2) n The second terminal of the ADC is connected to the input terminal of the ADC2; the output terminal of the ADC2 is connected to the MCU and is used to input the second digital signal to the MCU.

[0084] In practical implementation, at the first sampling moment, the MCU controls the gate voltage of switch G0 to turn it on, and the original analog signal is input to ADC1. After conversion by ADC1, the original analog signal is converted into a first digital signal with a first bit width. At the second sampling moment, the MCU controls the gate voltage of the second switch G0 to turn it off, and determines the turn-on of one of the first switches in the voltage divider circuit 30 based on the first digital signal, so that the original analog signal is converted into a second digital signal with a first bit width. n The voltage is divided by a voltage divider resistor, and the second-level analog signal obtained by the voltage division is input to the second conversion circuit 40 by controlling the conduction of the first switch transistor. The second conversion circuit 40 converts the received second-level analog signal according to a preset algorithm to obtain a second digital signal with a second bit width. The MCU obtains the target digital signal with a third bit width based on the first digital signal and the second digital signal.

[0085] The first sampling time is earlier than the second sampling time. That is to say, the original analog signal is converted first, and then the original analog signal is divided.

[0086] When the MCU determines that a switch in the voltage divider circuit 20 is turned on based on the first digital signal, it can first determine the range of the original analog signal, and then determine whether to perform voltage division based on the range. Specifically, the method can be that the first digital signal is within a first preset range and the original analog signal is directly input to ADC2, or the first digital signal is within a second preset range and the original analog signal is input to ADC2 after voltage division.

[0087] It should be noted that both values ​​of the second preset range are less than any value in the first preset range. For example, the first preset range is 0 and 1, and the second preset range is greater than 1.

[0088] If the original analog signal is directly input to ADC2, the MCU controls the first switch G1 to turn on; if the original analog signal is input to ADC2 after voltage division, the MCU determines the first switch to be turned on based on the first digital signal. Specifically, the first switch to be turned on can be determined using the following formula:

[0089] X = [(2 n [×(1-(1 / adc1))+1];

[0090] Where X is the bit number of the first switch transistor to be turned on, n is the bit width of ADC2, and adc1 is the first digital signal.

[0091] For example, if n is 8 and the first digital signal is 5, X = 255 can be calculated according to the above formula. Then, the first switch G255 is turned on. At this time, the original analog signal will be divided by 256 voltage divider resistors. Since the 255th switch is turned on, the analog signal input to ADC2 is the signal obtained after being divided by two resistors (R255 and R256) to ground.

[0092] It should be noted that when calculating the first switch transistor that needs to be turned on according to the above formula, if the calculation result is a decimal, the result should be rounded down.

[0093] The MCU determines whether to perform voltage division processing on the original analog signal based on the range of the original analog signal. If no voltage division processing is performed, the original analog signal is directly input to ADC2. If voltage division processing is determined, the original analog signal is divided and the first switch transistor is turned on by calculation. The signal input to ADC2 is the voltage to ground at the location of the first switch transistor that is turned on. ADC2 converts the input analog signal according to a preset algorithm to obtain a second digital signal with a second bit width.

[0094] In this embodiment of the invention, the analog signal is converted according to a preset algorithm. That is, the analog signal is first amplified according to the preset algorithm, and then the amplified analog signal is converted from analog to digital. Specifically, the analog signal can be amplified in ADC2, MCU, or other modules. If the conversion is performed in MCU or other modules, the analog signal is first sent to MCU or other modules, amplified in MCU or other modules according to the preset algorithm, and then the amplified analog signal is sent to ADC2, which performs analog-to-digital conversion on the amplified analog signal.

[0095] The preset algorithm in this embodiment can be the A-rate 13-segmented line algorithm. For an input level signal of 0 to 1, the A-rate 13-segmented line algorithm uses 1 / 4096 as the minimum quantization unit and performs uniform quantization with linear encoding. The number of quantization intervals is 4096 = 2^12, requiring 12 bits of binary data, plus a sign bit, for a total of 13 bits.

[0096] In the current international standard, A = 87.6. At this value, when the signal is very small, it is amplified by a factor of 16. The A-law compression expression is a continuous smooth curve, which is difficult to accurately implement using electronic circuits. However, due to the development of digital circuit technology, this characteristic can now be easily approximated using digital circuits. The 13-segmented line characteristic approximates the A-law compression characteristic, as shown in the graph below. Figure 3As shown, each segment is uniformly divided into 16 equal parts, with each part representing a quantization level. Clearly, there are 16 × 8 = 128 = 2^7 quantization levels across 8 segments, requiring 7 bits of binary encoding. It can be seen that each quantization level is non-uniform. The quantization step for small signals is very small, reducing quantization noise. If uniform quantization were used, with the smallest step (1 / 128) * (1 / 16) as the unit, the largest signal would require L = 128 × 16 = 2048 = 2^11 quantization levels, requiring 11 bits of encoding. This non-uniform encoding reduces the quantization step for small signals by a factor of 16, equivalent to a 20dB improvement in the signal-to-noise ratio for small signals.

[0097] That is, the small analog signal is amplified by 16 times using the A-rate 13-segmented line algorithm, and then converted by ADC2 to obtain the second digital signal value with the second bit width.

[0098] In this embodiment of the disclosure, the bit width of ADC1 and the bit width of ADC2 can be the same, both being the first bit width, such as 8 bits.

[0099] When calculating the target digital signal value of the third bit width, the MCU can adjust the first digital signal based on a preset value, and use the sum of the adjusted digital signal and the second digital signal as the target digital signal.

[0100] This preset value corresponds to the preset algorithm. For example, if the preset algorithm is the A-law 13-segment line algorithm, then the preset value is 16. If the preset algorithm is another algorithm, then the preset value also needs to be changed.

[0101] To facilitate understanding, a specific example will be used for illustration below.

[0102] In practical implementation, two analog-to-digital converters (ADCs) with the same bit width can be used, for example, two 8-bit low-bit-width ADCs, ADC1 and ADC2, with the same reference voltage. Simultaneously, an A-law 13-segmented linear algorithm is used to convert the second-stage analog signal. The voltage divider resistors have equal resistance values, i.e., R1 = R2 = R3 = ... = R2. n -1 = R2 n The present invention will be illustrated using an 8-bit analog-to-digital converter as an example; then there will be a total of 256 equal voltage divider resistors and the same number of first switching transistors to form a voltage divider circuit;

[0103] At the first sampling moment, the MCU controls the gate of the second switching transistor G0 to be turned on, and the original analog signal is input to ADC1. ADC1 converts the original analog signal to obtain the first digital signal. Since an 8-bit analog-to-digital converter is used, the value of the first digital signal adc1 is an integer between 0 and 255.

[0104] At the second sampling moment, the MCU controls the switch G0 to turn off and turns on the gate of the first switch according to the first digital signal value; assuming adc1 = 1, the MCU controls the switch G1 to turn on, that is, directly inputs the original analog signal to ADC2; assuming adc1 is 172, then we need to use the formula X = [(2 n The calculation is performed using [×(1-(1 / adc1))+1], resulting in X = 255 (rounded down). This means that by controlling the gate voltage of G255, G255 is turned on. The voltage divider circuit 30 divides the first-stage analog signal (i.e., the original analog signal) through 256 voltage divider resistors. Since G255 is turned on, the analog signal input to ADC2 is the original analog signal divided to ground, which is the voltage of the first terminal of R255 to ground.

[0105] Since all the voltage divider resistors in the voltage divider circuit are of equal value, according to Thevenin's theorem, the voltage across each voltage divider resistor will be evenly distributed across each voltage divider resistor. At the same time, ADC1 and ADC2 are the same analog-to-digital converter. When the preset algorithm is the A-law 13-segmented line algorithm, if the (0-1 / 64) range of this algorithm is selected to amplify the signal input to ADC2, the second-stage analog signal input to the front end of ADC2 will definitely be within the range of (0 to 1 / 64) of ADC2.

[0106] It should be noted that the resistance value of each voltage divider resistor in the embodiments of the present invention can be the same or different. If the resistance value of each voltage divider resistor is the same, the obtained analog signal after voltage division will be more accurate.

[0107] ADC2 is encoded using an A-law 13-segment polyline method. The specific encoding content can be found as follows:

[0108] Linear Input Code Compressed Code

[0109] ---------------------------------------

[0110] 0000000wxyza 000wxyz

[0111] 0000001wxyza 001wxyz

[0112] 000001wxyzab 010wxyz

[0113] 00001wxyzabc 011wxyz

[0114] 0001wxyzabcd 100wxyz

[0115] 001wxyzabcde 101wxyz

[0116] 01wxyzabcdef 110wxyz

[0117] 1wxyzabcdefg 111wxyz

[0118] After encoding is completed, the second digital signal value output by ADC2, adc2, is the digital signal value obtained by converting the second-stage analog signal using PCM encoding with A-law 13-segmented line method, which is 16 times the digital signal value output without A-law 13-segmented line method.

[0119] Since there is a linear correspondence between the first digital signal output by ADC1 and the original analog signal, the following calculation can be performed in the MCU to combine the two signal values:

[0120] ADC = (adc1-1)×16 + adc2;

[0121] In the above formula, ADC is the target digital signal, adc1 is the first digital signal, and adc2 is the second digital signal.

[0122] Specifically, when adc1 is not greater than 1, the gate of G1 is directly turned on. At this time, the second digital signal value adc2 output by ADC2 will be 16 times the digital signal value obtained by converting the original analog signal without using the A-law 13-segment method. We can perform the following calculation in the MCU:

[0123] ADC = adc2;

[0124] According to the above scheme, high-bit-width digital signal values ​​can be obtained by sampling through two low-bit-width analog-to-digital converters, thereby improving the conversion accuracy of digital signals.

[0125] In some examples, the number of voltage divider circuits in at least one voltage divider circuit in the analog-to-digital converter circuit is multiple, that is, the analog-to-digital converter circuit includes multiple voltage divider circuits and multiple second conversion circuits:

[0126] If multiple voltage divider circuits 20 are included, the connection method of the voltage divider circuits 20 can be series connection, parallel connection, or partial series connection and partial parallel connection. In specific implementation, it can be set according to actual needs.

[0127] The three connection methods will be explained below.

[0128] like Figure 1 The diagram shows an analog-to-digital converter circuit provided in an embodiment of this disclosure. Figure 1As can be seen, multiple voltage divider circuits 20 are connected in series. The first voltage divider circuit divides the original analog signal, the second voltage divider circuit divides the analog signal after it has been divided by the second voltage divider circuit, and so on.

[0129] The specific structure of each voltage divider circuit is as described above, and will not be repeated here.

[0130] In this circuit, the original analog signal is first input to the first conversion circuit. After the first conversion circuit converts the original analog signal, it obtains a first digital signal. The control calculation circuit determines to turn on a switch in the first voltage divider circuit based on the first digital signal, so that the original analog signal is divided by the voltage divider circuit to obtain a first second-level analog signal. The first second conversion circuit converts the first second-level analog signal according to a preset algorithm to obtain a first second digital signal. The control calculation circuit controls the first second conversion circuit to stop receiving analog signals and determines to turn on a switch in the second voltage divider circuit based on the first second digital signal. The second voltage divider circuit receives the second-level analog signal output from the first voltage divider circuit and divides the received second-level analog signal to obtain a second second-level analog signal. The second second conversion circuit converts the second second-level analog signal according to a preset algorithm to obtain a second second digital signal. The control calculation unit then determines to turn on a switch in the third voltage divider circuit based on the second second digital signal. Following the above method, the control calculation unit finally determines the target digital signal based on the received first digital signal and at least one second digital signal.

[0131] It should be noted that the preset algorithms in each second conversion circuit can be the same or different.

[0132] The more voltage divider circuits there are, the more accurate the conversion of the target digital signal value.

[0133] like Figure 4 The diagram shows another analog-to-digital converter circuit provided in an embodiment of this disclosure. Figure 4 As can be seen, it includes 4 voltage divider circuits and 4 second conversion circuits. The 4 voltage divider circuits are connected in parallel and all input the original analog signal. That is, they all divide the original analog signal and then input the divided analog signal to their respective second conversion circuits for conversion.

[0134] The specific implementation method of this circuit can be found in [reference]. Figure 1 The method in the middle is just Figure 1 The input to the middle voltage divider circuit is the analog signal after being divided by the previous voltage divider circuit, while Figure 4 Each voltage divider circuit in the circuit receives the original analog signal as input.

[0135] like Figure 5As shown, this is another analog-to-digital conversion circuit provided in an embodiment of this disclosure. Figure 5 In the circuit, the first and second voltage divider circuits are connected in series, and the third and fourth voltage divider circuits are connected in parallel.

[0136] The implementation method of this circuit can be referred to Figure 1 The methods described above will not be elaborated here.

[0137] It should be noted that the switching transistors mentioned in the above embodiments of the present invention can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs), and are not limited thereto. In specific implementations, the control terminal of each of the above switching transistors serves as its gate, and depending on the transistor type and the input signal, the first terminal can be used as the source and the second terminal as the drain; or the first terminal can be used as the drain and the second terminal as the source, and no specific distinction is made here.

[0138] In this embodiment of the invention, multiple voltage divider circuits are connected in parallel, such as... Figure 4 and Figure 5 As shown, the inputs of multiple voltage divider circuits are connected to each other, and the outputs of multiple voltage divider circuits are indirectly connected to the MCU. For example, the output of each voltage divider circuit is connected to the input of a corresponding second conversion circuit, and the output of the corresponding second conversion circuit is connected to the MCU.

[0139] Based on the same concept, this disclosure also provides an analog-to-digital conversion method, which can be applied to any of the above-mentioned analog-to-digital conversion circuits. The principle of this method in solving the problem is similar to that of the aforementioned analog-to-digital conversion circuits. Therefore, the implementation of the method can refer to the implementation of the analog-to-digital conversion circuits, and the repeated parts will not be described again.

[0140] like Figure 6 As shown, the analog-to-digital conversion method provided in this disclosure includes the following steps:

[0141] S601. The received original analog signal is converted by the first conversion circuit to obtain a first digital signal with a first bit width;

[0142] S602. A first-level analog signal is divided by a voltage divider circuit in at least one voltage divider circuit to obtain a second-level analog signal, wherein the first-level analog signal is the original analog signal or the second-level analog signal generated by the previous voltage divider circuit adjacent to the first voltage divider circuit.

[0143] S603. The received second-level analog signal is converted by the second conversion circuit according to the preset algorithm to obtain a second digital signal with a second bit width;

[0144] S604. Based on the first digital signal and the second digital signal value, obtain the target digital signal with a third bit width;

[0145] Wherein, the third bit width is greater than the first bit width, and the third bit width is greater than the second bit width.

[0146] In this embodiment, the original analog signal is converted by a first conversion circuit to obtain a digital signal with a first bit width. The first-level analog signal is then divided by a voltage divider circuit to obtain a second-level analog signal. The first-level analog signal is either the original analog signal or the second-level analog signal obtained by the previous voltage divider circuit adjacent to the voltage divider circuit. The second conversion circuit converts the received second-level analog signal according to a preset algorithm to obtain a second digital signal with a second bit width. Finally, based on the first and second digital signals, a target digital signal with a third bit width is obtained. The third bit width is greater than the first bit width and also greater than the second bit width. Since the bit width of the obtained target digital signal is greater than the bit width of the first digital signal obtained by the first conversion circuit and also greater than the bit width of the second digital signal obtained by the second conversion circuit, it is larger than the bit width of the output digital signal in the prior art, thereby improving the accuracy of the output digital signal.

[0147] Optionally, at least one voltage divider circuit may be used;

[0148] The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes:

[0149] Based on the first digital signal, the first-stage analog signal is divided by controlling the conduction of a switch in the voltage divider circuit to obtain the second-stage analog signal, wherein the first-stage analog signal is the original analog signal.

[0150] Optionally, at least one voltage divider circuit may have multiple voltage divider circuits, and the multiple voltage divider circuits may be connected in series.

[0151] The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes:

[0152] Based on the first digital signal, the first-level analog signal is divided by controlling the conduction of a switch in one of the at least one voltage divider circuits to obtain the second-level analog signal, wherein the first-level analog signal is the second-level analog signal output by the previous voltage divider circuit adjacent to the voltage divider circuit.

[0153] Optionally, at least one voltage divider circuit may have multiple voltage divider circuits connected in parallel.

[0154] The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes:

[0155] Based on the first digital signal, the first-stage analog signal is divided by controlling the conduction of a switch in one of the at least one voltage divider circuits to obtain the second-stage analog signal, wherein the first-stage analog signal is the original analog signal.

[0156] Optionally, if the first digital signal is within a first preset range, the second-stage analog signal is made equal to the original analog signal by controlling the conduction of a switching transistor in one of the at least one voltage divider circuits.

[0157] If the first digital signal is within a second preset range, then the original analog signal is divided by controlling the conduction of a switch in the voltage divider circuit according to the first digital signal to obtain the second-level analog signal.

[0158] Optionally, obtaining the target digital signal with the third bit width based on the first digital signal and the second digital signal includes:

[0159] The first digital signal is adjusted based on a preset value;

[0160] The sum of the adjusted digital signal and the second digital signal is taken as the target digital signal.

[0161] Optionally, the preset algorithm is the A-law 13-segment algorithm.

[0162] Based on the same concept, this disclosure also provides an integrated chip that includes any of the analog-to-digital conversion circuits described above. The principle by which this integrated chip solves the problem is similar to that of the aforementioned analog-to-digital conversion circuits; therefore, the implementation of this integrated chip can refer to the implementation of the aforementioned analog-to-digital conversion circuits, and the repetitions will not be repeated here.

[0163] Based on the same concept, this disclosure also provides a display device that includes any of the aforementioned integrated chips. The principle by which this display device solves the problem is similar to that of the analog-to-digital conversion circuit in the aforementioned integrated chip; therefore, the implementation of this display device can refer to the implementation of the analog-to-digital conversion circuit in the aforementioned integrated chip, and the repetitions will not be repeated here.

[0164] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0165] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. An analog-to-digital converter circuit, wherein, include: The first conversion circuit is configured to convert the original analog signal to obtain a first digital signal with a first bit width; At least one voltage divider circuit is configured to divide a first-stage analog signal to obtain a second-stage analog signal, wherein the first-stage analog signal is the original analog signal or the second-stage analog signal output by the previous voltage divider circuit adjacent to the voltage divider circuit. The second conversion circuit corresponding to the voltage divider circuit is configured to convert the received second-level analog signal according to a preset algorithm to obtain a second digital signal with a second bit width; The control calculation circuit is configured to obtain a target digital signal with a third bit width based on the first digital signal and the second digital signal; Wherein, the third bit width is greater than the first bit width, and the third bit width is greater than the second bit width.

2. The circuit according to claim 1, wherein, The voltage divider circuit includes multiple voltage divider resistors and a first switching transistor corresponding to each voltage divider resistor; The plurality of voltage divider resistors are connected in series; In the series-connected voltage divider resistors, the first end of each voltage divider resistor is connected to the first end of its corresponding first switching transistor. The second terminals of each first switching transistor are interconnected and connected to the second conversion circuit corresponding to the voltage divider circuit. The control terminal of each first switching transistor is connected to the control calculation circuit. The first terminal of the first voltage divider resistor is used to input the first-stage analog signal, and the second terminal of the last voltage divider resistor is grounded.

3. The circuit according to claim 2, wherein, The number of voltage divider circuits in the at least one voltage divider circuit is one; The first-level analog signal is the original analog signal.

4. The circuit according to claim 2, wherein, The at least one voltage divider circuit has multiple voltage divider circuits, and the multiple voltage divider circuits are connected in series. The first-stage analog signal is the second-stage analog signal output by the previous voltage divider circuit connected in series with the voltage divider circuit.

5. The circuit according to claim 2, wherein, The at least one voltage divider circuit has multiple voltage divider circuits connected in parallel. The first-level analog signal is the original analog signal.

6. The circuit according to claim 2, wherein, The control calculation circuit is specifically configured to control the conduction of a first switch of at least one voltage divider circuit in the voltage divider circuit according to the first digital signal.

7. The circuit according to claim 2, wherein, The first conversion circuit includes a first analog-to-digital converter with the first bit width and a second switching transistor; The first terminal of the second switch is configured to input the original analog signal, the second terminal of the second switch is electrically connected to the input terminal of the first analog-to-digital converter, the control terminal of the second switch is electrically connected to the control calculation circuit, and the output terminal of the first analog-to-digital converter is electrically connected to the control calculation circuit. The control calculation circuit is specifically configured to control the second switch to be turned on at a first sampling time and to control the second switch to be turned off at a second sampling time, wherein the first sampling time is earlier than the second sampling time.

8. The circuit according to claim 7, wherein, The second conversion circuit includes a second analog-to-digital converter; The input terminal of the second analog-to-digital converter is electrically connected to the second terminal of each first switching transistor in the corresponding voltage divider circuit, and the output terminal of the second analog-to-digital converter is electrically connected to the control calculation circuit. The control calculation circuit is specifically configured such that, if the first digital signal is within a first preset range, the first switch corresponding to the first voltage divider resistor of at least one voltage divider circuit in the voltage divider circuit is turned on at the second sampling time; if the first digital signal is within a second preset range, a first switch of at least one voltage divider circuit in the voltage divider is turned on at the second sampling time according to the first digital signal.

9. The circuit according to claim 1, wherein, The control calculation circuit is specifically configured as follows: The first digital signal is adjusted based on a preset value; The sum of the adjusted digital signal and the second digital signal is taken as the target digital signal.

10. The circuit according to claim 7, wherein, The bit width of the first analog-to-digital converter is equal to the bit width of the second analog-to-digital converter.

11. The circuit according to claim 10, wherein, The preset algorithm is the A-law 13-segment algorithm.

12. An integrated chip, wherein, Includes the analog-to-digital conversion circuit as described in any one of claims 1-11.

13. A display device, characterized in that, Including the integrated chip as described in claim 12.

14. An analog-to-digital conversion method, applied to the circuit according to any one of claims 1-11, wherein, include: The received original analog signal is converted by the first conversion circuit to obtain a first digital signal with a width of one bit. The first-level analog signal is divided by one of the at least one voltage divider circuits to obtain the second-level analog signal, wherein the first-level analog signal is the original analog signal, or the second-level analog signal obtained by the previous voltage divider circuit adjacent to the first voltage divider circuit. The second conversion circuit converts the received second-level analog signal according to a preset algorithm to obtain a second digital signal with a second bit width; Based on the first digital signal and the second digital signal, a target digital signal with a third bit width is obtained; Wherein, the third bit width is greater than the first bit width, and the third bit width is greater than the second bit width.

15. The method according to claim 14, wherein, The number of voltage divider circuits in the at least one voltage divider circuit is one; The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes: Based on the first digital signal, the first-stage analog signal is divided by controlling the conduction of a switch in the voltage divider circuit to obtain the second-stage analog signal, wherein the first-stage analog signal is the original analog signal.

16. The method of claim 14, wherein, The at least one voltage divider circuit has multiple voltage divider circuits, and the multiple voltage divider circuits are connected in series. The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes: Based on the first digital signal, the first-level analog signal is divided by controlling the conduction of a switch in one of the at least one voltage divider circuits to obtain the second-level analog signal, wherein the first-level analog signal is the second-level analog signal output by the previous voltage divider circuit adjacent to the voltage divider circuit.

17. The method of claim 14, wherein, The at least one voltage divider circuit has multiple voltage divider circuits connected in parallel. The step of dividing the first-level analog signal by one of the at least one voltage divider circuits to obtain the second-level analog signal includes: Based on the first digital signal, the first-stage analog signal is divided by controlling the conduction of a switch in one of the at least one voltage divider circuits to obtain the second-stage analog signal, wherein the first-stage analog signal is the original analog signal.

18. The method according to claim 14, wherein, If the first digital signal is within a first preset range, then the second-level analog signal is made equal to the original analog signal by controlling the conduction of a switching transistor in one of the at least one voltage divider circuits; If the first digital signal is within a second preset range, then based on the first digital signal, the original analog signal is divided by controlling the conduction of a switching transistor in one of the at least one voltage divider circuits to obtain the second-level analog signal.

19. The method of claim 14, wherein, The step of obtaining the target digital signal with the third bit width based on the first digital signal and the second digital signal includes: The first digital signal is adjusted based on a preset value; The sum of the adjusted digital signal and the second digital signal is taken as the target digital signal.

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