Dynamic self-adapting clock division circuit and method
By configuring a crystal oscillator on the daughterboard, the daughterboard clock and the main control board reference clock are made to be from different sources. The output clock is dynamically adjusted using the error amount ERR, which solves the problem of high wiring pressure in traditional clock synchronization circuits, realizes synchronous clock frequency division without the need for equal-length wiring, and improves system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU CHENGXIN TECH CO LTD
- Filing Date
- 2025-07-29
- Publication Date
- 2026-06-23
AI Technical Summary
Traditional clock synchronization circuits require the synchronization signal SYSREF and the reference clock signal FREF to originate from the same source, resulting in high wiring pressure and requiring equal-length wiring in a star topology to connect each daughterboard.
A clock frequency division circuit and method with dynamic adaptive synchronization adjustment is adopted. By configuring crystal oscillators on each daughterboard, the daughterboard clock and the main control board reference clock are not from the same source. The rising edge of the output clock clk_out is dynamically adjusted by the error amount ERR to ensure that the output clock clk_out is N*K times within the synchronization signal period, thereby realizing synchronous clock frequency division.
It reduces wiring pressure, optimizes clock synchronization circuitry, lowers wiring difficulty, and improves system stability, enabling it to withstand more clock disturbances.
Smart Images
Figure CN120928908B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of synchronous clock technology, and in particular to a clock divider circuit and method for dynamic adaptive synchronization adjustment. Background Technology
[0002] In traditional clock synchronization circuits, a common reference clock signal FREF is used as the clock for each daughterboard. To ensure that the period of the synchronization signal SYSREF is an integer multiple of the frequency division signal output by each daughterboard, SYSREF and FREF must be from the same source, and the period of SYSREF must be an integer multiple of the period of FREF. Therefore, a clock distribution module is set up to send the common synchronization signal SYSREF and the reference clock signal FREF to each daughterboard. Moreover, due to the different delays caused by different line lengths, the phase of the SYSREF signal and the reference clock signal FREF when they arrive at each daughterboard is affected. To ensure that each daughterboard can perform clock division synchronously based on the reference clock signal FREF, the clock distribution module needs to connect each daughterboard using equal-length wiring in a star topology. Therefore, this traditional clock synchronization circuit has significant wiring requirements.
[0003] Therefore, there is an urgent need to provide a clock divider circuit and method for dynamic adaptive synchronization adjustment. Summary of the Invention
[0004] To address the issue that traditional clock synchronization circuits require the synchronization signal SYSREF and the reference clock signal FREF to originate from the same source, and that the clock distribution module needs to connect each daughterboard using equal-length wiring in a star topology, resulting in significant wiring pressure, this invention provides a clock frequency divider circuit and method for dynamic adaptive synchronization adjustment.
[0005] On the one hand, a clock divider circuit with dynamic adaptive synchronization adjustment is provided, including: a main control board, several daughter boards, and a crystal oscillator configured for the main control board and each daughter board respectively;
[0006] The main control board's reference clock signal interface is connected to a crystal oscillator, and the synchronization signal interface is connected to each sub-board to output synchronization signals to each sub-board for clock synchronization.
[0007] Each sub-board's clock interface is connected to a crystal oscillator to generate its own clock, resulting in different sources for the clocks of each sub-board. Furthermore, the clocks of each sub-board and the reference clock signal of the main control board are also different sources. Each sub-board divides its own clock to generate an output clock clk_out, and then divides the output clock clk_out to generate a synchronous clock output signal.
[0008] For each sub-board, the period of the synchronization signal is a non-integer multiple of the clock period of that sub-board. Between two synchronization signal pulses, there are M*N*K ± ERR clock cycles of that sub-board. Based on the magnitude of the error ERR, the output clock clk_out of that sub-board is dynamically adjusted so that the output clock clk_out of that sub-board is N*K cycles within the synchronization signal period. Wherein, M is the frequency division factor of the clock output signal relative to the clock signal of that sub-board, N is the frequency division factor of the synchronization clock output signal relative to the clock output signal, and K is the number of clk_sync_out cycles within the synchronization signal period.
[0009] On the other hand, a clock division method for dynamic adaptive synchronization adjustment based on any circuit embodiment of the specification is provided, including:
[0010] Each main control board and each daughter board is equipped with a crystal oscillator to enable the main control board to generate a reference clock signal and enable each daughter board to generate its own clock; wherein, the clocks of each daughter board are from different sources, and the clocks of each daughter board and the reference clock signal of the main control board are also from different sources.
[0011] The synchronization signal generated by the main control board is sent to each sub-board. Each sub-board generates an output clock clk_out by dividing its own clock frequency, and generates a synchronization clock output signal by dividing the output clock clk_out frequency.
[0012] For each sub-board, the period of the synchronization signal is a non-integer multiple of the clock period of that sub-board. Between two synchronization signal pulses, there are M*N*K ± ERR clock cycles of that sub-board. Based on the magnitude of the error ERR, the output clock clk_out of that sub-board is dynamically adjusted so that the output clock clk_out of that sub-board is N*K cycles within the synchronization signal period. Wherein, M is the frequency division factor of the clock output signal relative to the clock signal of that sub-board, N is the frequency division factor of the synchronization clock output signal relative to the clock output signal, and K is the number of clk_sync_out cycles within the synchronization signal period.
[0013] The technical solution provided by this invention can bring at least the following beneficial effects:
[0014] A clock synchronization divider circuit supporting multi-node cascading without requiring a clock distribution module is proposed. Each daughterboard uses its own reference clock, which is not from the same source as the synchronization signal SYSREF. The output clock clk_out of each daughterboard is dynamically adjusted based on the magnitude of the error ERR, so that the output clock clk_out of each daughterboard is N*K times within the synchronization signal period, achieving the purpose of synchronous clock division. It does not require the synchronization signal SYSREF and the reference clock signal FREF to be from the same source, eliminates the need to consider length equalization, reduces the pressure of wiring, and optimizes the dynamically adjusted clock synchronization circuit. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of a clock divider circuit for dynamic adaptive synchronization adjustment provided in an embodiment of the present invention;
[0017] Figure 2 This is a schematic diagram of a traditional clock synchronization circuit;
[0018] Figure 3 This is a timing diagram of a traditional clock synchronous frequency divider circuit;
[0019] Figure 4 This is a schematic diagram of the signal timing relationship when ERR is negative, provided by an embodiment of the present invention;
[0020] Figure 5 This is a schematic diagram of the signal timing relationship when ERR is a positive number, provided by an embodiment of the present invention;
[0021] Figure 6 This is a schematic diagram of the signal timing relationship when the ERR is negative and the total number of adjustments is 1, provided by an embodiment of the present invention.
[0022] Figure 7 This is a schematic diagram of the signal timing relationship when the ERR is positive and the total number of adjustments is 1, provided by an embodiment of the present invention;
[0023] Figure 8 This is a flowchart of a clock division method for dynamic adaptive synchronization adjustment provided by an embodiment of the present invention. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0025] As mentioned above, please refer to Figure 2 The schematic diagram of a traditional clock synchronization circuit shows that the clock of each daughterboard is the reference clock signal FREF from the clock distribution module. The clock distribution module also distributes the synchronization signal SYSREF to each daughterboard. Both the synchronization signal SYSREF and the reference clock signal FREF are signals from the same source issued by the clock distribution module. In order to avoid different delays caused by different line lengths, which would affect the phase of the SYSREF signal and the reference clock signal FREF when they reach each daughterboard, the clock distribution module needs to connect each daughterboard with equal-length wiring in a star topology. Therefore, this traditional clock synchronization circuit has a large wiring burden.
[0026] Therefore, the inventors considered adjusting the rising edge of the output clock clk_out of the daughter board according to the error amount ERR when the daughter board clock and synchronization signal are from different sources to achieve clock synchronization frequency division. This can avoid the equal-length wiring limitation caused by the clock and synchronization signals of each daughter board being from the same source and reduce wiring pressure.
[0027] The following describes the specific implementation of the above concept.
[0028] Please refer to Figure 1 The present invention provides a clock divider circuit for dynamic adaptive synchronization adjustment, comprising: a main control board, several sub-boards, and a crystal oscillator configured for the main control board and each sub-board respectively;
[0029] The main control board's reference clock signal interface is connected to a crystal oscillator, and the synchronization signal interface is connected to each daughter board to output synchronization signals to each daughter board for clock synchronization.
[0030] Each daughterboard's clock interface is connected to a crystal oscillator to generate its own clock, ensuring that the clocks of each daughterboard are from different sources, and that the clocks of each daughterboard and the reference clock signal of the main control board are also from different sources. Each daughterboard divides its own clock to generate an output clock clk_out, and divides the output clock clk_out to generate a synchronous clock output signal.
[0031] For each daughterboard, the period of the synchronization signal is a non-integer multiple of the clock period of that daughterboard. Between two synchronization signal pulses, there are M*N*K ± ERR clock cycles of that daughterboard. Based on the magnitude of the error ERR, the output clock clk_out of that daughterboard is dynamically adjusted so that the output clock clk_out of that daughterboard is N*K cycles within the synchronization signal period. Where M is the division factor of the clock output signal relative to the clock signal of that daughterboard, N is the division factor of the synchronization clock output signal relative to the clock output signal, and K is the number of clk_sync_out cycles within the synchronization signal period.
[0032] In this embodiment, reference Figure 1 and Figure 4 The main control board outputs a synchronization signal SYSREF, which is then sent to each daughterboard for clock synchronization. The clocks CLK1, ..., CLKN on each board have different sources and are also different from the main control board's reference clock signal FREF. Within each daughterboard, an output clock clk_out is generated by dividing its own clock, and a synchronization clock output signal clk_sync_out is generated by further dividing the output clock clk_out. The output clock clk_out signal is an M-division of the daughterboard clock clk, and the synchronization clock output signal clk_sync_out is an M*N-division of the daughterboard clock clk. Both M and N are integers.
[0033] This invention proposes a clock synchronization divider circuit that supports multi-node serial connection and does not require a clock distribution module. Each daughterboard uses its own reference clock, which is not from the same source as the synchronization signal SYSREF. The output clock clk_out of each daughterboard is dynamically adjusted based on the magnitude of the error ERR, so that the output clock clk_out of each daughterboard is N*K times within the synchronization signal period, thus achieving the purpose of synchronous clock division. It does not require the synchronization signal SYSREF and the reference clock signal FREF to be from the same source, eliminates the need to consider length equalization, reduces the pressure of wiring, and optimizes the dynamic adjustment of the clock synchronization circuit.
[0034] In some implementations, the output clock clk_out of the daughterboard is dynamically adjusted based on the magnitude of the error rate ERR, so that the output clock clk_out of the daughterboard is N*K times within the synchronization signal period, including:
[0035] The N*K clock cycles of the sub-board are considered as a loop, and the difference between the synchronization signal period and one loop is taken as the error value ERR.
[0036] When the error ERR is negative, it indicates that the synchronization signal period is less than one cycle. The output clock clk_out of the sub-board is generated with a rising edge in advance according to the error ERR, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period.
[0037] When the error ERR is positive, it indicates that the two synchronization signal pulses are greater than one cycle. The output clock clk_out of the sub-board is delayed according to the error ERR to generate a rising edge, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period.
[0038] First refer to Figure 3 The timing diagram of the traditional clock synchronization frequency divider circuit uses the reference clock signal FREF as the clock of each daughterboard. Since the reference clock signal FREF and the synchronization signal SYSREF are from the same source, the period of the synchronization signal SYSREF is an integer multiple of the period of the clock FREF of the daughterboard. There are M*N*K clock cycles of the daughterboard between two synchronization signal SYSREF pulses.
[0039] In this embodiment, since the synchronization signal SYSREF is generated by the reference clock signal FREF, and the reference clock signal FREF and the clock CLK* of each sub-board are from different sources, the synchronization signal SYSREF acts as a frequency divider for synchronizing each sub-board. Therefore, the period of the synchronization signal will not be an integer multiple of the clock period of the sub-board; that is, there will be M*N*K±ERR clock cycles of the sub-board between two synchronization signal pulses. For details, please refer to... Figure 4 When ERR is negative, it means the synchronization signal period is less than one cycle. Therefore, the output clock clk_out of the daughterboard is generated with its rising edge advanced according to the error amount ERR, so that the output clock clk_out of the daughterboard is N*K cycles within the synchronization signal period. When ERR is positive, refer to... Figure 5 If the synchronization signal period is greater than one cycle, then the output clock clk_out of the sub-board is delayed by the error amount ERR to generate a rising edge, so that the output clock clk_out of the sub-board is M*N*K times within the synchronization signal period. It can be understood that the synchronization clock output signal clk_sync_out is generated by dividing the output clock clk_out. It is only necessary to adjust the output clock clk_out.
[0040] Next, we will discuss the two cases separately: when ERR is negative and when ERR is positive. First, let's discuss when ERR is negative.
[0041] In some implementations, when the error value ERR is negative, indicating that the synchronization signal period is less than one cycle, the output clock clk_out of the sub-board is generated with a rising edge in advance according to the error value ERR, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period, including:
[0042] The total number of adjustments is determined based on the error rate (ERR) and the clock cycle of the sub-board; however, each adjustment can only be made once per synchronization signal cycle, and each adjustment corresponds to one synchronization signal cycle.
[0043] When the total number of adjustments is 1, the timing starts directly from the rising edge of the second-to-last output clock clk_out within the synchronization signal period. After M-|ERR| clock cycles of the sub-board, the rising edge of the last output clock clk_out is issued to advance the last output clock clk_out within the synchronization signal period, so that the number of output clocks clk_out of the sub-board within the synchronization signal period is N*K.
[0044] When the total number of adjustments is greater than 1, the last output clock clk_out in the synchronization signal period is advanced in multiple synchronization signal periods to converge the error in a successive adjustment manner.
[0045] In this embodiment, the error rate ERR may be too large, meaning it exceeds the period of the output clock clk_out. The period of the output clock clk_out can be understood as M clock clk cycles. Since the synchronization signal can only be adjusted once per cycle, when the error rate ERR exceeds the period of the output clock clk_out, it needs to be adjusted multiple times.
[0046] In some implementations, the total number of adjustments is calculated as follows:
[0047] k = floor(|ERR| / M) + 1
[0048] In the formula, k is the total number of adjustments, and floor(|ERR| / M) represents the integer part of the quotient.
[0049] For example, if |ERR| / M is 1 with a remainder of 1, then the total number of adjustments k is 2. Adjustments need to be made within two consecutive synchronization signal cycles, once per synchronization signal cycle.
[0050] When the total number of adjustments is 1, you can refer to... Figure 6The timing starts directly from the rising edge of the second-to-last output clock clk_out within the synchronization signal period. After M-|ERR| clock cycles of the sub-board, the rising edge of the last output clock clk_out is emitted, thus advancing the last output clock clk_out within the synchronization signal period, so that the number of output clocks clk_out of the sub-board within the synchronization signal period is N*K.
[0051] In this embodiment of the invention, when the total number of adjustments is greater than 1, the last output clock clk_out in each of the multiple synchronization signal cycles is advanced to converge the error by adjusting it sequentially, including:
[0052] Based on the error values ERR and M, determine the adjustment amount ADJ;
[0053] For each adjustment except the last one, the timing starts from the rising edge of the second-to-last output clock clk_out in the synchronization signal period corresponding to the adjustment, and the rising edge of the last output clock clk_out in the synchronization signal period is issued after M-ADJ clock cycles of the daughter board.
[0054] During the final adjustment, the timing begins at the rising edge of the second-to-last output clock clk_out within the corresponding synchronization signal cycle. After M-(|ERR|-(k-1)ADJ) clock cycles on the sub-board, the rising edge of the last output clock clk_out within the synchronization signal cycle is emitted; where k is the total number of adjustments.
[0055] In some implementations, the formula for determining the adjustment amount ADJ is:
[0056] |ERR|<ADJ<M-2
[0057] In the formula, ERR represents the error.
[0058] For example, when the total number of adjustments k is 3, during the first and second adjustments, the timing begins at the rising edge of the second-to-last output clock clk_out within the corresponding synchronization signal period. After M-ADJ clock cycles on the daughterboard, the rising edge of the last output clock clk_out within that synchronization signal period is emitted. During the third adjustment, the timing begins at the rising edge of the second-to-last output clock clk_out within the corresponding synchronization signal period. After M-ADJ clock cycles on the daughterboard, the rising edge of the last output clock clk_out within that synchronization signal period is emitted.
[0059] After (|ERR|-(k-1)ADJ) clock cycles, the rising edge of the last output clock clk_out in the synchronization signal cycle is emitted to complete the adjustment.
[0060] Next, we will discuss the case where ERR is a positive number.
[0061] In some implementations, when the error ERR is positive, indicating that the two synchronization signal pulses are greater than one cycle, the output clock clk_out of the sub-board is delayed by the error ERR to generate a rising edge, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period, including:
[0062] The total number of adjustments is determined based on the error rate (ERR) and the clock cycle of the sub-board; however, each adjustment can only be made once per synchronization signal cycle, and each adjustment corresponds to one synchronization signal cycle.
[0063] When the total number of adjustments is 1, the timing starts directly from the rising edge of the second-to-last output clock clk_out within the synchronization signal period. The rising edge of the last output clock clk_out is issued after M+ERR clock cycles of the sub-board, so as to directly delay the last output clock clk_out within the synchronization signal period, making the number of output clocks clk_out of the sub-board N*K within the synchronization signal period.
[0064] When the total number of adjustments is greater than 1, the last output clock clk_out in each of the multiple synchronization signal cycles is delayed to converge the error in a successive adjustment manner.
[0065] In this embodiment, the error rate ERR may be too large, meaning it exceeds the period of the output clock clk_out. The period of the output clock clk_out can be understood as M clock clk cycles. Since the synchronization signal can only be adjusted once per cycle, when the error rate ERR exceeds the period of the output clock clk_out, it needs to be adjusted multiple times.
[0066] In some implementations, the total number of adjustments is calculated as follows:
[0067] k = floor(|ERR| / M) + 1
[0068] In the formula, k is the total number of adjustments, and floor(|ERR| / M) represents the integer part of the quotient.
[0069] For example, if |ERR| / M is 1 with a remainder of 1, then the total number of adjustments k is 2. Adjustments need to be made within two consecutive synchronization signal cycles, once per synchronization signal cycle.
[0070] When the total number of adjustments is 1, you can refer to... Figure 7The timing starts directly from the rising edge of the second-to-last output clock clk_out within the synchronization signal period. After M+ERR clock cycles of the sub-board, the rising edge of the last output clock clk_out is emitted, thus directly delaying the last output clock clk_out within the synchronization signal period, so that the number of output clocks clk_out of the sub-board within the synchronization signal period is N*K.
[0071] In this embodiment of the invention, when the total number of adjustments is greater than 1, the last output clock clk_out in each of the multiple synchronization signal cycles is delayed to converge the error in a successive adjustment manner, including:
[0072] Based on the error values ERR and M, determine the adjustment amount ADJ;
[0073] For each adjustment except the last one, the timing starts from the rising edge of the second-to-last output clock clk_out in the synchronization signal period corresponding to the adjustment, and the rising edge of the last output clock clk_out in the synchronization signal period is issued after M+ADJ clock cycles of the daughter board.
[0074] During the final adjustment, the timing begins at the rising edge of the second-to-last output clock clk_out within the corresponding synchronization signal cycle. After M+(|ERR|-(k-1)ADJ) clock cycles on the sub-board, the rising edge of the last output clock clk_out within the synchronization signal cycle is emitted; where k is the total number of adjustments.
[0075] In some implementations, the formula for determining the adjustment amount ADJ is:
[0076] |ERR|<ADJ<M-2
[0077] In the formula, ERR represents the error.
[0078] For example, when the total number of adjustments k is 3, in the first and second adjustments, the timing starts at the rising edge of the second-to-last output clock clk_out in the corresponding synchronization signal period, and the rising edge of the last output clock clk_out in the synchronization signal period is emitted after M+ADJ clock cycles on the sub-board. In the third adjustment, the timing starts at the rising edge of the second-to-last output clock clk_out in the corresponding synchronization signal period, and the rising edge of the last output clock clk_out in the synchronization signal period is emitted after M+(|ERR|-(k-1)ADJ) clock cycles on the sub-board, thus completing the adjustment.
[0079] In summary, the advantages of this solution mainly include the following: 1) The SYSREF synchronization signal does not need to consider equal length, reducing wiring pressure. 2) Each daughterboard can have its own clock, eliminating the need for multiple daughterboards to use the same clock source, thus reducing clock wiring difficulty. 3) Better stability, because the clock is obtained through dynamic frequency division, which can resist the impact of more clock disturbances on the system.
[0080] Please refer to Figure 8 This invention provides a clock division method based on any clock division circuit in the specification, characterized by dynamic adaptive synchronization adjustment. The method includes:
[0081] Step 800: The main control board and each daughter board are equipped with a crystal oscillator to enable the main control board to generate a reference clock signal and enable each daughter board to generate its own clock; wherein, the clocks of each daughter board are from different sources, and the clocks of each daughter board and the reference clock signal of the main control board are also from different sources.
[0082] Step 802: The synchronization signal generated by the main control board is sent to each sub-board. Each sub-board divides its own clock to generate an output clock clk_out, and divides the output clock clk_out to generate a synchronization clock output signal.
[0083] Step 804: For each sub-board, the period of the synchronization signal is a non-integer multiple of the clock period of the sub-board. Between two synchronization signal pulses, there are M*N*K±ERR clock cycles of the sub-board. Based on the magnitude of the error ERR, the output clock clk_out of the sub-board is dynamically adjusted so that the output clock clk_out of the sub-board is N*K cycles within the synchronization signal period; where M is the frequency division factor of the clock output signal relative to the clock signal of the sub-board, N is the frequency division factor of the synchronization clock output signal relative to the clock output signal, and K is the number of clk_sync_out cycles within the synchronization signal period.
[0084] In step 804, based on the magnitude of the error ERR, the output clock clk_out of the sub-board is dynamically adjusted so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period, including:
[0085] The M*N*K clock cycles of the sub-board are considered as a loop, and the difference between the synchronization signal period and one loop is used as the error quantity ERR.
[0086] When the error ERR is negative, it indicates that the synchronization signal period is less than one cycle. The output clock clk_out of the sub-board is generated with a rising edge in advance according to the error ERR, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period.
[0087] When the error ERR is positive, it indicates that the two synchronization signal pulses are greater than one cycle. The output clock clk_out of the sub-board is delayed according to the error ERR to generate a rising edge, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period.
[0088] It should be noted that the above method embodiments and circuit embodiments belong to the same concept, and the specific implementation process can be found in the circuit embodiments, which will not be repeated here.
[0089] Finally, it should be noted that in this document, relational terms such as first, second, third, and fourth are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.
[0090] The above are merely preferred embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.
Claims
1. A clock divider circuit with dynamic adaptive synchronization adjustment, characterized in that, include: The system consists of a main control board, several sub-boards, and a crystal oscillator configured for each of the main control board and each sub-board. The main control board's reference clock signal interface is connected to a crystal oscillator, and the synchronization signal interface is connected to each sub-board to output synchronization signals to each sub-board for clock synchronization. Each sub-board's clock interface is connected to a crystal oscillator to generate its own clock, resulting in different sources for the clocks of each sub-board. Furthermore, the clocks of each sub-board and the reference clock signal of the main control board are also different sources. Each sub-board divides its own clock to generate an output clock clk_out, and divides the output clock clk_out to generate a synchronous clock output signal clk_sync_out. For each sub-board, the period of the synchronization signal is a non-integer multiple of the clock period of that sub-board. Between two synchronization signal pulses, there are M*N*K ± ERR clock cycles of that sub-board. Based on the magnitude of the error ERR, the output clock clk_out of that sub-board is dynamically adjusted so that the output clock clk_out of that sub-board is N*K cycles within the synchronization signal period. Wherein, M is the division factor of the clock output signal relative to the clock signal of that sub-board, N is the division factor of the synchronization clock output signal relative to the clock output signal, and K is the number of clk_sync_out cycles within the synchronization signal period. The output clock clk_out of the sub-board is dynamically adjusted based on the magnitude of the error rate ERR, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period, including: The M*N*K clock cycles of the sub-board are considered as a loop, and the difference between the period of the synchronization signal and one loop is taken as the error amount ERR; When the error amount ERR is negative, it indicates that the period of the synchronization signal is less than one cycle. The output clock clk_out of the sub-board is generated with a rising edge in advance according to the error amount ERR, so that the output clock clk_out of the sub-board is N*K times within the period of the synchronization signal. When the error amount ERR is positive, indicating that the two synchronization signal pulses are greater than one cycle, the output clock clk_out of the sub-board is delayed according to the error amount ERR to generate a rising edge, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period.
2. The circuit as described in claim 1, characterized in that, When the error amount ERR is negative, indicating that the synchronization signal period is less than one cycle, the output clock clk_out of the sub-board is generated with a rising edge in advance according to the error amount ERR, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period, including: Based on the error amount ERR and the clock cycle of the sub-board, the total number of adjustments is determined; wherein, one synchronization signal cycle can only be adjusted once, and each adjustment corresponds to one synchronization signal cycle; When the total number of adjustments is 1, the timing starts directly from the rising edge of the second-to-last output clock clk_out in the synchronization signal period. After M-|ERR| clock cycles of the sub-board, the rising edge of the last output clock clk_out is issued to advance the last output clock clk_out in the synchronization signal period, so that the number of output clocks clk_out of the sub-board in the synchronization signal period is N*K. When the total number of adjustments is greater than 1, the last output clock clk_out in each of the multiple synchronization signal cycles is advanced in order to converge the error by adjusting it step by step.
3. The circuit as described in claim 2, characterized in that, When the total number of adjustments is greater than 1, the last output clock clk_out in each of the multiple synchronization signal cycles is advanced to converge the error in a successive adjustment manner, including: Based on the error amounts ERR and M, the adjustment amount ADJ is determined; For each adjustment except the last one, the timing starts from the rising edge of the second-to-last output clock clk_out in the synchronization signal period corresponding to the adjustment, and the rising edge of the last output clock clk_out in the synchronization signal period is emitted after M-ADJ clock cycles of the sub-board. During the final adjustment, the timing begins at the rising edge of the second-to-last output clock clk_out within the synchronization signal cycle corresponding to the adjustment. After M-(|ERR|-(k-1)ADJ) clock cycles on the sub-board, the rising edge of the last output clock clk_out within the synchronization signal cycle is emitted; where k is the total number of adjustments.
4. The circuit as described in claim 1, characterized in that, When the error amount ERR is positive, indicating that the two synchronization signal pulses are greater than one cycle, the output clock clk_out of the sub-board is delayed by the error amount ERR to generate a rising edge, so that the output clock clk_out of the sub-board is N*K times within the synchronization signal period, including: Based on the error amount ERR and the clock cycle of the sub-board, the total number of adjustments is determined; wherein, one synchronization signal cycle can only be adjusted once, and each adjustment corresponds to one synchronization signal cycle; When the total number of adjustments is 1, the timing starts directly from the rising edge of the second-to-last output clock clk_out in the synchronization signal period, and the rising edge of the last output clock clk_out is issued after M+ERR clock cycles of the sub-board, so as to directly delay the last output clock clk_out in the synchronization signal period, so that the number of output clocks clk_out of the sub-board in the synchronization signal period is N*K. When the total number of adjustments is greater than 1, the last output clock clk_out in each of the multiple synchronization signal cycles is delayed in order to converge the error in a successive adjustment manner.
5. The circuit as described in claim 4, characterized in that, When the total number of adjustments is greater than 1, the last output clock clk_out in each of the multiple synchronization signal cycles is delayed to converge the error in a successive adjustment manner, including: Based on the error amounts ERR and M, the adjustment amount ADJ is determined; For each adjustment except the last one, the timing starts from the rising edge of the second-to-last output clock clk_out in the synchronization signal period corresponding to the adjustment, and the rising edge of the last output clock clk_out in the synchronization signal period is issued after M+ADJ clock cycles of the sub-board. During the final adjustment, the timing begins at the rising edge of the second-to-last output clock clk_out within the synchronization signal cycle corresponding to the adjustment. After M+(|ERR|-(k-1)ADJ) clock cycles on the sub-board, the rising edge of the last output clock clk_out within the synchronization signal cycle is emitted; where k is the total number of adjustments.
6. The circuit as described in claim 2 or 4, characterized in that, The total number of adjustments is calculated as follows: In the formula, For the total number of adjustments, floor(|ERR| / M) represents the integer part of the quotient.
7. The circuit as described in claim 3 or 5, characterized in that, The formula for determining the adjustment amount ADJ is as follows: In the formula, ERR represents the error.
8. A clock division method based on the dynamic adaptive synchronization adjustment of the clock division circuit according to any one of claims 1-7, characterized in that, include: Each main control board and each daughter board is equipped with a crystal oscillator to enable the main control board to generate a reference clock signal and enable each daughter board to generate its own clock; wherein, the clocks of each daughter board are from different sources, and the clocks of each daughter board and the reference clock signal of the main control board are also from different sources. The synchronization signal generated by the main control board is sent to each sub-board. Each sub-board generates an output clock clk_out by dividing its own clock frequency, and generates a synchronization clock output signal by dividing the output clock clk_out frequency. For each sub-board, the period of the synchronization signal is a non-integer multiple of the clock period of that sub-board. Between two synchronization signal pulses, there are M*N*K ± ERR clock cycles of that sub-board. Based on the magnitude of the error ERR, the output clock clk_out of that sub-board is dynamically adjusted so that the output clock clk_out of that sub-board is N*K cycles within the synchronization signal period. Wherein, M is the frequency division factor of the clock output signal relative to the clock signal of that sub-board, N is the frequency division factor of the synchronization clock output signal relative to the clock output signal, and K is the number of clk_sync_out cycles within the synchronization signal period.