Asynchronous signal synchronization processing circuit and chip

Abstract

The application provides an asynchronous signal synchronization processing circuit and a chip, the asynchronous signal synchronization processing circuit comprises a synchronization module, a decision module and a voting module connected with the synchronization module respectively; the synchronization module is used for performing cross-clock domain synchronization on input asynchronous signals according to a set clock signal to generate three paths of synchronization signals; the decision module is used for performing error decision on the three paths of synchronization signals and outputting a decision result; and the voting module is used for voting according to high and low levels of the three paths of synchronization signals and outputting a synchronization signal according to a voting result. The application performs cross-clock domain synchronization on asynchronous signals through the mode of synchronization, decision and voting, and performs failure inspection on the synchronization signals in the synchronization process to prevent the synchronization signals from being erroneous.

Description

Technical Field

[0001] This application relates to the field of asynchronous signal synchronization processing technology, and in particular to an asynchronous signal synchronization processing circuit and chip. Background Technology

[0002] With the rapid popularization of intelligent and electrified automotive technologies, the number of in-vehicle controllers and related electronic components is increasing, leading to a rise in the functional complexity of automotive-grade chips. Furthermore, as the number of clock cycles in chips increases, signal interaction across clock domains becomes more complex.

[0003] Currently, when performing cross-clock domain synchronization processing on single-bit asynchronous signals, the potential for errors in the synchronized signal due to synchronization circuit failure has not been considered, which could lead to functional errors. Summary of the Invention

[0004] In view of this, this application proposes an asynchronous signal synchronization processing circuit and chip, which performs cross-clock domain synchronization of asynchronous signals through synchronization, decision and voting methods, and performs failure checks on the synchronization signal during the synchronization process to prevent the synchronization signal from malfunctioning.

[0005] In a first aspect, this application provides an asynchronous signal synchronization processing circuit, including a synchronization module, a decision module and a voting module respectively connected to the synchronization module;

[0006] The synchronization module is used to synchronize the input asynchronous signal across clock domains according to the set clock signal, generating three synchronization signals;

[0007] The decision module is used to make error decisions on the three synchronization signals and output the decision results;

[0008] The voting module is used to vote based on the high and low levels of the three synchronization signals, and outputs a synchronization signal based on the voting results.

[0009] As described above, the asynchronous signal synchronization processing circuit provided in this application synchronizes the input asynchronous signal across the clock domain into three synchronization signals. A decision module then performs error detection on these three synchronization signals and outputs the results. This allows users to identify whether the synchronization circuit has failed based on the error flags in the decision results. Furthermore, a voting circuit votes on the high and low levels of the three synchronization signals and outputs a high or low level synchronization signal based on the voting results. This application enables failure checking of the synchronization circuit, preventing errors in the output synchronization signal.

[0010] Optionally, the synchronization module includes three synchronization circuits;

[0011] Each synchronization circuit includes two stages of flip-flops, which synchronize the input asynchronous signal into a synchronization signal according to a set clock signal.

[0012] As mentioned above, since the formation of data inside the flip-flop requires a certain amount of time, if the setup and hold times are not met, the flip-flop may enter a metastable state, and its output will only stabilize after a period of uncertainty. Therefore, this application uses two flip-flops to continuously latch the input asynchronous signal twice, which can prevent the metastable state generated by the flip-flop at this stage from propagating to the subsequent logic due to the asynchronous signal not meeting the setup and hold times of the clock at this stage. This effectively reduces the probability of the metastable state continuing to propagate during the synchronization of asynchronous signals across clock domains.

[0013] Optionally, the decision module includes a multi-input one-output gate circuit, a flip-flop, and a two-input AND gate circuit;

[0014] The multiple-input one-output multiple-gate circuit determines the high or low level of the three synchronization signals output by the synchronization module and outputs a level signal.

[0015] The input terminal of the trigger is connected to the output terminal of the multiple-input one-output multiple gate circuit, and is used to delay the level signal output by the multiple-input one-output multiple gate circuit by one clock cycle and send it to one input terminal of the two-input AND gate circuit according to the set clock signal.

[0016] The other input terminal of the two-input AND gate receives the level signal output by the multi-input one-output multi-gate circuit through the NOT gate circuit, and determines whether to output a high pulse signal or a low level signal based on the level signals of the two input terminals.

[0017] As described above, the high and low levels of the three synchronization signals output by the synchronization module are determined by a multi-input multi-output gate circuit, and the corresponding level signals are output. These level signals are output to one input of an AND gate circuit through a NOT gate circuit and also input to the input of a flip-flop. The flip-flop latches the level signal once according to the set clock signal and then outputs a level signal delayed by one clock cycle to the other input of the AND gate circuit. The AND gate circuit can then perform AND operation based on the level signals of its two inputs. When both inputs are high, a high-pulse error flag signal is output to alarm the failure of the synchronization circuit. When at least one input is low, a low-level error-free flag signal is output, indicating that no error has occurred in the synchronization circuit.

[0018] Optionally, the multiple-input-output (MIMO) gate circuit includes six input terminals, of which three input terminals receive the three synchronization signals output by the synchronization module, and the other three input terminals receive the three synchronization signals output by the synchronization module through NOT gate circuits respectively.

[0019] Optionally, when all three synchronization signals output by the synchronization module are high or all are low, the multi-input one-output multi-gate circuit outputs a low-level signal; otherwise, it outputs a high-level signal.

[0020] As described above, the multiple input-output (MIMO) gate circuit of this application includes six input terminals. Three input terminals receive three synchronization signals output by the synchronization module, and the other three input terminals receive three synchronization signals output by the synchronization module through NOT gate circuits. Therefore, the levels of the three synchronization signals at the three input terminals correspond exactly to the opposite levels of the three synchronization signals at the other three input terminals. When all three synchronization signals are high or low, the MIMO gate circuit outputs a low-level signal. When any one of the signals differs from the other two, a high-level signal is output. This allows for the determination of the three synchronization signals output by the synchronization module, thereby enabling failure detection of the three synchronization circuits in the synchronization module.

[0021] Optionally, the voting module includes a first three-input one-output multi-gate circuit, used to vote on the high and low levels of the three synchronization signals. When at least two of the three synchronization signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output.

[0022] As described above, the voting module can vote on the high and low levels of the three synchronization signals output by the synchronization module through the first three-input one-output multi-gate circuit. When at least two of the three synchronization signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output.

[0023] Optionally, the voting module further includes a second three-input one-output multi-gate circuit and a NOT gate circuit connected in series, wherein the second three-input one-output multi-gate circuit has the opposite function to the first three-input one-output multi-gate circuit;

[0024] The second three-input one-output multi-gate circuit and the NOT gate circuit output the same synchronization signal as the first three-input one-output multi-gate circuit.

[0025] Therefore, the voting module may also include a second three-input one-output multi-gate circuit, which has the opposite function to the first three-input one-output multi-gate circuit. The back end of the second three-input one-output multi-gate circuit is connected to a NOT gate circuit. Therefore, the high and low levels of the three synchronization signals output by the synchronization module are voted on by the second three-input one-output multi-gate circuit. When at least two of the three synchronization signals are high, the low-level synchronization signal output is inverted by the NOT gate circuit and output as a high-level synchronization signal. Otherwise, the high-level synchronization signal output is inverted by the NOT gate circuit and output as a low-level synchronization signal. Thus, the same synchronization signal output as the first three-input one-output multi-gate circuit can be achieved through the series-connected second three-input one-output multi-gate circuit and NOT gate circuit. The voting module outputs two synchronization signals to the back-end logic through these two circuits.

[0026] Optionally, the trigger is an edge-triggered trigger, and the clock signal provides the trigger edge of the edge-triggered trigger.

[0027] As described above, the trigger of this application is an edge trigger. The trigger edge is provided by a set clock signal. When the rising edge of the clock signal arrives, the edge trigger is triggered, latches the input signal and delays the output.

[0028] Secondly, this application provides a chip including the aforementioned asynchronous signal synchronization processing circuit.

[0029] Therefore, this application also provides a chip including the above-mentioned asynchronous signal synchronization processing circuit. By arranging the asynchronous signal synchronization processing circuit at the front end of the chip, the asynchronous signal input from the front end interface of the chip can be synchronized across clock domains to generate a synchronization signal to be provided to the back end logic of the chip.

[0030] These and other aspects of this application will become more apparent in the description of the following embodiments(s). Attached Figure Description

[0031] Figure 1 A schematic diagram of an asynchronous signal synchronization processing circuit provided in an embodiment of this application;

[0032] Figure 2 This is a circuit structure diagram of an asynchronous signal synchronization processing circuit provided in an embodiment of this application.

[0033] It should be understood that the dimensions and shapes of the block diagrams in the above structural diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of this application. The relative positions and inclusion relationships between the block diagrams presented in the structural diagrams are only schematic representations of the structural relationships between the block diagrams, and are not intended to limit the physical connection methods of the embodiments of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will now be described in further detail with reference to the accompanying drawings.

[0035] This application provides an asynchronous signal synchronization processing circuit that performs cross-clock domain synchronization of asynchronous signals through synchronization, decision-making, and voting methods, and performs failure checks on the synchronization signals during the synchronization process to prevent errors in the synchronization signals.

[0036] like Figure 1 As shown, the asynchronous signal synchronization processing circuit provided in this application embodiment includes a synchronization module 100, and a decision module 200 and a voting module 300 respectively connected to the synchronization module 100;

[0037] The synchronization module 100 is used to synchronize the input asynchronous signal across clock domains according to the set clock signal to generate three synchronization signals; the decision module 200 is used to make error decisions on the three synchronization signals and output the decision results; the voting module 300 is used to vote according to the high and low levels of the three synchronization signals and output the synchronization signal according to the voting results.

[0038] In some embodiments, the synchronization module 100 may include three synchronization circuits with the same function. Each synchronization circuit includes two stages of flip-flops. The two stages of flip-flops synchronize the input asynchronous signal into a synchronization signal according to a set clock signal, thereby effectively reducing the probability of metastability continuing to propagate during the synchronization process of asynchronous signals across clock domains.

[0039] The decision module 200 may include a multiple-input multiple-output (MIMO) gate circuit, a flip-flop, and a two-input AND gate circuit. The MIMO gate circuit includes six input terminals, three of which receive three synchronization signals output from the three synchronization circuits of the synchronization module 100. The other three input terminals receive the three synchronization signals output from the three synchronization circuits of the synchronization module 100 respectively through NOT gate circuits. By judging the high and low levels of the three synchronization signals output by the synchronization module 100, when all three synchronization signals are high or all three are low, the MIMO gate circuit outputs... A low-level signal is output, otherwise a high-level signal is output. The input of this flip-flop is connected to the output of a multi-input multi-output gate circuit. It is used to delay the level signal output by the multi-input multi-output gate circuit by one clock cycle according to the set clock signal and send it to one input of a two-input AND gate circuit. The other input of the two-input AND gate circuit receives the level signal output by the multi-input multi-output gate circuit through a NOT gate circuit, and outputs a high pulse signal or a low-level signal according to the level signals of the two inputs, so as to realize the failure check of the three synchronization circuits in the synchronization module 100.

[0040] The voting module 300 may include a first three-input one-output (TIA) multi-gate circuit and a second TIA multi-gate circuit. The first TIA multi-gate circuit is used to vote on the high and low levels of three synchronization signals. When at least two of the three synchronization signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output. The second TIA multi-gate circuit has the opposite function to the first TIA multi-gate circuit. The output terminal of the second TIA multi-gate circuit is also connected in series with a NOT gate circuit to invert the level signal output by the second TIA multi-gate circuit, so that the final output is the same synchronization signal as the first TIA multi-gate circuit.

[0041] Figure 2 This is a circuit structure diagram of an asynchronous signal synchronization processing circuit provided in an embodiment of this application. Figure 2 The asynchronous signal synchronization processing circuit provided in this application embodiment includes a synchronization module 100, and a decision module 200 and a voting module 300 respectively connected to the synchronization module 100;

[0042] The synchronization module 100 includes three identical synchronization circuits. Each synchronization circuit includes two stages of flip-flops, implemented using two cascaded edge-triggered flip-flops. The input R of the first stage flip-flop in each of the three synchronization circuits receives the asynchronous signal data_i with a clock domain of clk_src. The input R of the second stage flip-flop is connected to the output Q of the first stage flip-flop, which outputs the synchronization signal after cross-clock domain synchronization. In this embodiment, the destination clock signal is set as clk_dst. This destination clock signal clk_dst provides the trigger edge for the two stages of flip-flops in the three synchronization circuits. When the rising edge of the destination clock signal clk_dst arrives, the two stages of flip-flops in each synchronization circuit are triggered, latching the input asynchronous signal data_i twice consecutively to output a stable synchronization signal. In addition, the reset terminal of each flip-flop is connected to a reset signal of the destination clock domain to reset the flip-flop.

[0043] This embodiment uses two-stage flip-flops to latch the input asynchronous signal twice consecutively, which can prevent the metastable state generated by the flip-flops at this stage from propagating to subsequent logic due to the asynchronous signal not meeting the setup and hold time of the current stage clock. This effectively reduces the probability of metastable state continuing to propagate during the synchronization of asynchronous signals across clock domains.

[0044] The decision module 200 includes a multiple-input multiple-output (AOI) gate circuit 33, a flip-flop, and a two-input AND gate circuit. The AOI gate circuit 33 has six input terminals. Three input terminals are connected to the output terminals of the three synchronization circuits of the synchronization module 100 to input three synchronization signals A1, A2, and A3. The other three input terminals are connected to the output terminals of the three synchronization circuits of the synchronization module 100 via NOT gate circuits to input three synchronization signals B1, B2, and B3 with opposite levels to the three synchronization signals A1, A2, and A3. The AOI gate circuit 33 makes a decision on the high and low levels of the three synchronization signals A1, A2, and A3 and the three synchronization signals B1, B2, and B3. If all three synchronization signals A1, A2, and A3 are high (then all three synchronization signals B1, B2, and B3 are low), or if all three synchronization signals B1, B2, and B3 are high (then all three synchronization signals A1, A2, and A3 are low), then the three synchronization signals B1, A2, and B3 are low. 2. When A3 is low, the AOI33 multi-input multi-output gate circuit outputs a low-level signal; otherwise, it outputs a high-level signal. The high-level or low-level signal output by the AOI33 is inverted by a NOT gate and then input to one input of a two-input AND gate circuit. The input R of the flip-flop is connected to the output of the AOI33, and its trigger edge is also provided by the destination clock signal clk_dst. The flip-flop delays the high-level or low-level signal output by the AOI33 by one clock cycle and sends it to the other input of the two-input AND gate circuit according to the destination clock signal clk_dst. The two-input AND gate circuit outputs a fault result based on the level signals of the two inputs. The clock domain of the fault result is clk_dst, which includes a high pulse signal indicating a synchronous circuit error or a low-level signal indicating that the synchronous circuit is error-free. The circuit structure of the decision module 200 can be used to make error decisions on the three synchronization circuits in the synchronization module 100 and output the decision result fault. The output decision result fault can also be latched into the back-end status register for managing the access of the back-end CPU.

[0045] The truth table and logic expression of the AOI33 multi-input one-output multi-gate circuit in this embodiment are as follows:

[0046] The truth table is as follows:

[0047] A1 A2 A3 B1 B2 B3 ZN 0 X X 0 X X 1 0 X X 1 0 X 1 0 X X 1 1 0 1 0 X X 1 1 1 0 1 0 X 0 X X 1 1 0 X 1 0 X 1 1 0 X 1 1 0 1 1 0 X 1 1 1 0 1 1 0 0 X X 1 1 1 0 1 0 X 1 1 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 X X X 0

[0048] Logical expressions:

[0049] ZN=(!((A1&A2&A3)|(B1&B2&B3))).

[0050] The voting module 300 may include two circuits with the same output result. The first circuit is implemented by a three-input one-output multi-gate circuit MAJ23. The input terminals of the three-input one-output multi-gate circuit MAJ23 are respectively connected to the output terminals of the three synchronization circuits of the synchronization module 100. It is used to vote according to the high and low levels of the three synchronization signals A1, A2, and A3, so as to output a synchronization signal data_o[0] according to the voting result. When at least two of the three input synchronization signals A1, A2, and A3 are high, the three-input one-output multi-gate circuit MAJ23 outputs a high-level synchronization signal; otherwise, it outputs a low-level synchronization signal.

[0051] The truth table and logic expression of the three-input one-output multi-gate circuit MAJ23 in this embodiment are as follows:

[0052] The truth table is as follows:

[0053] A2 A3 A1 Z 0 0 X 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 X 1

[0054] The logical expression is:

[0055] Z=(((A1&A2)|(A2&A3)|(A1&A2)));

[0056] The second part of the voting module 100 is implemented by a three-input one-output multi-gate circuit MAOI222 and a NOT gate circuit. The three-input one-output multi-gate circuit MAOI222 has the opposite function to the three-input one-output multi-gate circuit MAJ23 mentioned above. That is, when at least two of the three input synchronization signals A, B, and C are high level, the three-input one-output multi-gate circuit MAOI222 outputs a low-level synchronization signal, otherwise it outputs a high-level synchronization signal. The synchronization signal output by the three-input one-output multi-gate circuit MAOI222 is inverted by the NOT gate circuit and outputs the same synchronization signal data_o as the three-input one-output multi-gate circuit MAOI222[1].

[0057] The truth table and logic expression of the three-input one-output multi-gate circuit MAOI222 in this embodiment are as follows:

[0058] ●The truth table is as follows:

[0059] A B C ZN 0 0 X 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 X 0

[0060] Logical expressions:

[0061] ZN=(!((A&B)|(B&C)|(A&C)));

[0062] Through the two-part circuit structure of the voting circuit 300, two identical synchronization signals can be output for use in the back-end logic.

[0063] In summary, the asynchronous signal synchronization processing circuit provided in this application synchronizes the input asynchronous signal across clock domains into three output synchronization signals. It can also perform error judgment on these three synchronization signals and output the judgment result, allowing the user to identify whether the current synchronization circuit has failed based on the error flag in the judgment result. Furthermore, it can vote on the high and low levels of the three synchronization signals and output a high or low level synchronization signal based on the voting result. Through this application embodiment, functions such as cross-clock domain synchronization of asynchronous signals and synchronization circuit failure detection can be achieved, effectively avoiding the problem of signal errors after synchronization due to synchronization circuit failure, which in turn leads to chip malfunctions.

[0064] It should be noted that the embodiments described in this application are merely some embodiments, not all embodiments. The components of the embodiments of this application typically described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0065] The terms "first, second, third, etc." or similar terms such as module A, module B, module C, etc., used in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that a specific order or sequence may be interchanged where permitted so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0066] In the above description, the labels indicating the steps do not necessarily mean that the steps will be executed. They may include intermediate steps or be replaced by other steps. Where permissible, the order of the steps may be interchanged or executed simultaneously.

[0067] The term "comprising" as used in the specification and claims should not be construed as limiting itself to what follows; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned feature, integral, step, or component, but does not exclude the presence or addition of one or more other features, integrals, steps, or components, or groups thereof. Thus, the statement "device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0068] The terms "an embodiment" or "an embodiment" as used in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of this application. Therefore, the terms "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions between different embodiments are consistent and can be mutually referenced. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0069] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present application has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. An asynchronous signal synchronization processing circuit, characterized by comprising: The synchronous module, a decision module connected with the synchronous module, and a voting module connected with the synchronous module; The synchronous module is configured to perform cross-clock domain synchronization on an input asynchronous signal according to a set clock signal to generate three synchronous signals. The decision module includes a multiple-input single-output multi-gate circuit, a flip-flop, and a two-input AND gate circuit. The multiple-input single-output multi-gate circuit determines the high and low levels of the three synchronous signals output by the synchronous module and outputs a level signal. The multiple-input single-output multi-gate circuit includes six input terminals.

2. The circuit of claim 1, wherein, Three of the input terminals receive the three synchronous signals output by the synchronous module. The other three input terminals receive the three synchronous signals output by the synchronous module through NAND gate circuits.

3. The circuit of claim 1, wherein, When the three synchronous signals output by the synchronous module are all high or all low, the multiple-input single-output multi-gate circuit outputs a low level signal, otherwise, it outputs a high level signal.

4. The circuit of claim 3, wherein, The voting module is configured to vote according to the high and low levels of the three synchronous signals and output a synchronous signal according to the voting result. The synchronous module includes three synchronous circuits.

5. The circuit of claim 1 or 2, wherein Each synchronous circuit includes two flip-flops configured to synchronize an input asynchronous signal into a synchronous signal according to a set clock signal.

6. A chip, characterized by The voting module includes a first three-input single-output multi-gate circuit configured to vote on the high and low levels of the three synchronous signals. When at least two of the three synchronous signals are high, the first three-input single-output multi-gate circuit outputs a high level synchronous signal, otherwise, it outputs a low level synchronous signal. The voting module further includes a second three-input single-output multi-gate circuit and a NAND gate circuit connected in series. The second three-input single-output multi-gate circuit has a function opposite to that of the first three-input single-output multi-gate circuit. The second three-input single-output multi-gate circuit and the NAND gate circuit output the same synchronous signal as the first three-input single-output multi-gate circuit. The flip-flop is an edge-triggered flip-flop, and the clock signal provides a trigger edge for the edge-triggered flip-flop. The asynchronous signal synchronization processing circuit includes any one of the asynchronous signal synchronization processing circuits of claims 1 to 5.

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