A chip debugging device and method

Abstract

The present invention provides a chip debugging device and method. By establishing information interaction between the interface conversion unit and an external host computer, the configuration unit sends corresponding configuration information to a signal selection controller, a logic trigger unit, and a buffer unit controller that are sequentially connected through a general interface, prompting the signal to be debugged to be logically triggered and stored in the buffer unit. The buffered data is sent to the configuration unit according to the control signal of the configuration unit, and then provided to the external host computer connected to the interface conversion unit. According to the above debugging device, by configuring the signal source and trigger conditions, the signal waveform at the target time point can be collected. The waveform data is transmitted to the host computer through the external bus interface and displayed through the host computer software, realizing the debugging of the internal logic of the chip without the participation of an oscilloscope and external debugging instruments, thereby reducing the debugging conditions and improving the convenience of debugging.

Description

Technical Field

[0001] The present invention relates to the technical field of signal debugging, and in particular to a chip debugging device and method. Background Art

[0002] The current common method for debugging internal chip signals relies on serial ports and commonly used hardware instruments, such as JTAG (Joint Test Action Group) or other analysis tools. This debugging method requires the chip to reserve specific I / O interfaces for these interfaces, which increases the difficulty of chip packaging. Furthermore, because the internal logic of large chips is very complex and the number of I / O interfaces is very limited, the number of signals that can be observed simultaneously is very limited, often failing to meet the needs of debugging unexpected issues. Finally, if signal waveforms need to be captured at specific moments, an external logic analyzer or oscilloscope must be connected to observe the signals using their trigger conditions.

[0003] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in the field of this technology. Summary of the Invention

[0004] The technical problem to be solved by the present invention is how to complete the debugging of the internal logic signals of the chip without using an external logic analyzer or oscilloscope.

[0005] The present invention adopts the following technical solutions:

[0006] In a first aspect, a chip debugging device is provided, which includes an interface conversion unit, a configuration unit, a signal selection controller, a logic trigger unit, a cache unit, and a cache unit controller, wherein:

[0007] The interface conversion unit is connected to the external host computer via an external bus, and is used to receive a signal from the external host computer via the external bus and convert it into an internal bus signal, and is also used to convert the internal bus signal into an external common interface signal and send it to the external host computer via the external bus;

[0008] The configuration unit is connected to the interface conversion unit via an internal bus, and is configured to receive the internal bus signal from the interface conversion unit via the internal bus, generate configuration information, and send it to the signal selection controller, the logic trigger unit, and the cache unit controller, and register status information and debug signal data of each cache unit according to the control signal of the cache unit controller;

[0009] The signal selection controller is used to select different signals to be adjusted according to the configuration information, splice and combine the selected signals to be adjusted, map them to the corresponding acquisition channels, and transmit them to the logic trigger unit;

[0010] The logic trigger unit is used to logically trigger the signal to be adjusted output by the signal selection controller according to the configuration information, and send the generated trigger signal to the cache unit controller;

[0011] The cache unit controller is used to write the signal to be adjusted into the cache unit according to the configuration information and the trigger signal, and is also used to transfer the data of the cache unit to the configuration unit according to the control signal of the configuration unit;

[0012] The cache unit is used to store the signal to be adjusted under the control of the cache unit controller.

[0013] Preferably, the logic trigger unit is connected to the cache unit controller through a second interface. The logic trigger unit has a multi-channel trigger judgment logic, and the multi-channel trigger judgment logic is used to perform multi-level judgment on the channel signals transmitted by the signal selection controller according to the configuration information, and transmit the judgment result and the data of each channel to the cache unit controller through the second interface.

[0014] Preferably, each channel of the multi-channel trigger judgment logic is configured to complete the logical judgment of the unit signal according to the configuration information, including one or more of rising edge, falling edge, high level, low level, and multi-bit signal logical judgment, and the combination logic judgment is completed between each channel according to the configuration information.

[0015] Preferably, when the first condition in the combination logic arrives first, the cache unit controller stores the corresponding obtained data in the cache unit. When the remaining conditions in the combination logic are obtained, the data stored in the cache unit under the satisfaction of the first condition is synchronized; it is also used to trigger the interface conversion unit to transparently transmit the data content obtained when the remaining conditions are triggered.

[0016] Preferably, after the external host computer obtains the data content of the corresponding combination logic from the cache unit and the data content of the complete combination logic transparently transmitted by the cache unit controller, through the corresponding interface conversion unit and the configuration unit, it issues adjustment control instructions to one or more of the signal selection controller, the logic trigger unit, and the cache unit controller, or sends a debugging signal reporting time adjustment instruction to the chip itself.

[0017] Preferably, the combinational logic includes one or more combinations of channel 1 & channel 2, channel 1 | channel 2, channel 1 ^ (! channel 2) and (channel 1 | channel 2) & channel 3; wherein, "&", "|", "^" and "!" are all logical operators, "&" represents logical AND, "|" represents logical OR, "^" represents logical XOR, and "!" represents logical NOT.

[0018] Preferably, the cache unit controller is connected to the cache unit through a third interface; the cache unit controller has multi-channel trigger processing logic, cache unit read and write control logic and channel status information processing logic; the cache unit controller is used to complete the setting of the acquisition parameters of each channel according to the configuration information, and after receiving the trigger signal transmitted from the logic trigger unit, complete the signal acquisition of each channel according to the acquisition parameters, write the collected waveform data into the cache unit through the third interface, and transmit the channel status information of each channel to the configuration unit through the control signal; the cache unit controller is also used to receive acquisition instructions from the configuration unit, read the data content of the cache unit through the third interface according to the acquisition instructions, and transmit it to the configuration unit.

[0019] Preferably, the cache unit is further used to temporarily store the test results, waiting for the external host computer to retrieve the results stored in the cache unit through the interface conversion unit.

[0020] In a second aspect, a chip debugging method is provided, which is applied to the chip debugging device described above, wherein:

[0021] The interface conversion unit receives a signal from an external host computer and converts it into an internal bus signal, or converts the internal bus signal into an external common interface signal and sends it to the external host computer via an external bus;

[0022] The configuration unit generates configuration information according to the internal bus signal and sends it to the signal selection controller, the logic trigger unit and the cache unit controller, and caches the configuration information in the cache unit;

[0023] The signal selection controller selects different signals to be modulated according to the configuration information, and maps the selected signals to be modulated into corresponding acquisition channels and transmits them to the logic trigger unit;

[0024] The logic trigger unit performs logic triggering on the signal selection controller to output the signal to be adjusted of each channel according to the configuration information, and stores the status information and debugging signal data of each cache unit according to the control signal of the cache unit controller;

[0025] The cache unit controller writes the signal to be adjusted into the cache unit according to the configuration information and the trigger signal, transfers the data of each channel cache unit to the configuration unit according to the control signal of the configuration unit, and transmits it to the interface conversion unit through the internal bus, temporarily stores the test completion result in the cache unit, and waits for the external host computer to retrieve the result stored in the cache unit through the interface conversion unit;

[0026] The cache unit stores the signal to be adjusted under the control of the cache unit controller.

[0027] Preferably, it further includes: temporarily storing the test completion result in the cache unit and waiting for the external host computer to retrieve the result stored in the cache unit through the interface conversion unit.

[0028] According to another aspect of the present invention, an electronic device is provided, including: a processor; a memory communicatively connected to the processor; the memory stores instructions executable by the processor, and when the instructions are executed by the processor, the processor can execute the above chip debugging method.

[0029] According to another aspect of the present invention, a computer-readable storage medium is provided, and the computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the above chip debugging method is implemented.

[0030] The chip debugging device and method provided by the present invention establish information interaction between the interface conversion unit and the external host computer. The configuration unit sends corresponding configuration information to the signal selection controller, logic trigger unit, and cache unit controller connected through the general interface, prompting the signal to be adjusted to be logically triggered and stored in the cache unit, and sending the cached data to the configuration unit according to the control signal of the configuration unit, and then providing it to the external host computer connected to the interface conversion unit; according to the above debugging device, by configuring the signal source and the trigger conditions between them, the signal waveform at the target time point can be collected, and the waveform data is transmitted to the host computer through the external bus interface and displayed through the host computer software, realizing the debugging of the internal logic of the chip without the participation of an oscilloscope and external debugging instruments, thereby reducing the debugging conditions and improving the convenience of debugging. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments of the present invention. Obviously, the following described drawings are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0032] Figure 1It is a schematic diagram of the internal unit of a chip debugging device provided by an embodiment of the present invention;

[0033] Figure 2 It is a schematic diagram of the external unit of a chip debugging device provided by an embodiment of the present invention;

[0034] Figure 3 It is a flowchart of a chip debugging method provided by an embodiment of the present invention;

[0035] Figure 4 It is a flowchart of the host computer software of a chip debugging method provided by an embodiment of the present invention;

[0036] Figure 5 It is a flowchart of another chip debugging method provided by an embodiment of the present invention;

[0037] Figure 6 It is a block diagram of the electronic device of the chip debugging device provided by an embodiment of the present invention. Detailed implementation manners

[0038] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature and not restrictive.

[0039] An embodiment of the present invention provides a chip debugging device, as Figure 1 shown, including an interface conversion unit, a configuration unit, a signal selection controller, a logic trigger unit, a buffer unit and a buffer unit controller, where:

[0040] The interface conversion unit is connected to an external host computer through an external bus. The interface conversion unit is used to receive signals from the external host computer through the external bus and convert them into internal bus signals, or convert internal bus signals into external common interface signals and send them to the external host computer through the external bus, so as to realize information interaction with the external host computer.

[0041] In some embodiments, the external bus can be UART (Universal Asynchronous Receiver / Transmitter), IIC (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), etc. When the external bus is IIC, the IIC bus transmits address and data information to the interface conversion unit based on its protocol, thereby realizing debugging operations on the debugging device.

[0042] A configuration unit, wherein the configuration unit is connected to the interface conversion unit via an internal bus, and the configuration unit is used to receive internal bus signals from the interface conversion unit via the internal bus, and generate configuration information to send to the signal selection controller, the logic trigger unit and the cache unit controller, and store the status information and debug signal data of each cache unit according to the control signal of the cache unit controller.

[0043] In some embodiments, the internal bus may be an APB (Advanced Perpheral Bus), an AXI (Advanced Extensible Interface), an AHB (Advanced High-performance Bus), or other buses; when the internal bus is an APB bus, the APB bus transmits debug commands to the slave port of the configuration unit based on the AMBA protocol, thereby realizing read and write operations on the slave port of the configuration unit.

[0044] When the configuration information is sent to the signal selection controller, logic trigger unit, and cache unit controller separately, the contents of the configuration information sent are all different. The configuration information specifically includes signal mapping configuration information of the signal selection controller, signal trigger condition configuration information of the logic trigger unit, and configuration information related to the internal channels of the cache unit controller.

[0045] The configuration unit internally contains configuration information related to a signal selection controller, a logic trigger unit, and a cache unit controller, the working status information of the cache unit controller, instruction and data decoding logic, and control logic related to the cache unit controller; when receiving instructions and data transmitted by the internal bus, the instruction and data decoding logic inside the configuration unit identifies the content of the instructions and data, and according to the identification result, on the one hand, it will be converted into corresponding module configuration information and sent to the signal selection controller through the configuration information, sent to the logic trigger unit through the configuration information, and sent to the cache unit controller through the configuration information; on the other hand, it queries the status information of the cache unit controller using the controller signal and caches the status information in the internal register. The configuration unit can send the status information of the cache unit controller and the waveform data in the cache unit to the interface conversion unit through the internal bus.

[0046] Among them, the signal selection controller is connected to the logic trigger unit through a first interface, the logic trigger unit is connected to the cache unit controller through a second interface, and the cache unit controller is connected to the cache unit through a third interface.

[0047] Among them, the first interface, the second interface, and the third interface are general interfaces. It can be understood that they can also be other customized IO interfaces, and the present invention does not limit this.

[0048] The signal selection controller is used to select different signals to be adjusted according to the configuration information, splice and combine them, and map them to the corresponding acquisition channels for transmission to the logic trigger unit.

[0049] The signal selection controller internally contains multi-channel signal mapping logic. According to the data transmitted by the configuration information, the debugging signals are spliced and mapped into each data channel as required, and then the data of each channel is transmitted to the logic trigger unit through the first interface.

[0050] The logic trigger unit is used to logically trigger the signals to be adjusted in each channel output by the signal selection controller according to the configuration information, and send the generated trigger signals to the cache unit controller.

[0051] The cache unit controller is used to write the signals to be adjusted into the cache unit according to the configuration information and the trigger signals, and transfer the data of each channel cache unit to the configuration unit according to the control signal of the configuration unit, and transmit it to the interface conversion unit through the internal bus, so as to provide it to the external host computer connected to the interface conversion unit. Or, temporarily store the test completed results in the cache unit and wait for the external host computer to retrieve the results stored in the cache unit through the interface conversion unit.

[0052] The cache unit is used to store the signal to be adjusted under the control of the cache unit controller; and / or, temporarily store the test result in the cache unit, and wait for the external host computer to retrieve the result stored in the cache unit through the interface conversion unit.

[0053] As Figure 2 shown, the debugging device is arranged in the chip, and the interface conversion unit in the debugging device is connected to the external host computer through an external bus, and establishes a data transmission relationship with the host computer software in the external host computer.

[0054] In some embodiments, according to the above debugging device, by configuring the selection signal source and the trigger conditions between them, the signal waveform at the target time point can be collected. The waveform data is transmitted to the host computer through the external bus interface and displayed through the host computer software, so as to realize function debugging; it realizes the debugging of the internal logic of the chip without the participation of the processor and external debugging instruments, thereby reducing the debugging conditions and improving the convenience of debugging.

[0055] The logic trigger unit internally includes multi-channel trigger judgment logic. The multi-channel trigger judgment logic is used to perform multi-level judgment on the channel signals transmitted by the signal selection controller according to the data transmitted by the configuration information, and then transmit the judgment result and the data of each channel to the cache unit controller through the second interface.

[0056] In some embodiments, the multi-level judgment specifically includes:

[0057] Each channel completes the logic judgment of the unit signal according to the configuration information, including rising edge, falling edge, high level, low level or multi-bit signal logic judgment, and the combination logic judgment will be completed between each channel according to the configuration information.

[0058] The logic trigger unit internally includes multi-channel trigger judgment logic. According to the data transmitted by the configuration information, multi-level judgment is performed on the channel signals transmitted by the signal selection controller, and then the judgment result and the data of each channel are transmitted to the cache unit controller through the second interface. The specific implementation process of the multi-level judgment is as follows. Each channel first completes the logic judgment of the unit signal according to the configuration information, such as rising edge, falling edge, high level and low level, or multi-bit signal logic judgment such as equal to A (representing a number), not equal to A, greater than A, less than A, greater than A and less than B (representing a number), etc. Then, the combination logic judgment will be completed between each channel according to the configuration information, including but not limited to channel 1 & channel 2, channel 1 | channel 2, channel 1 ^ (! channel 2), (channel 1 | channel 2) & channel 3, etc. Among them, "&", "|", "^" and "!" are all logical operators. "&" represents logical AND, "|" represents logical OR, "^" represents logical XOR, and "!" represents logical NOT.

[0059] Among them, logical operators such as "&", "|", "^", and "!" are used to splice each channel together to form combinational logic. It can be understood that the foregoing channel 1, channel 2, and channel 3 are exemplary channel numbers, and it is not specifically limited that there are only 3 channels.

[0060] The cache unit controller internally includes multi-channel trigger processing logic, cache unit read / write control logic, and channel status information processing logic; the cache unit controller is used to complete the setting of the acquisition parameters of each channel according to the data transmitted by the configuration information, and after receiving the trigger signal transmitted from the logic trigger unit, according to the acquisition parameters set for each channel, complete the signal acquisition of each channel, write its waveform data into the cache unit through the third interface, and transmit the channel status information to the configuration unit through the control signal.

[0061] At the same time, the cache unit controller is also used to receive the acquisition instruction from the configuration unit, read the data content of the cache unit through the third interface according to the content of the acquisition instruction, and transmit it to the configuration unit, and the configuration unit outputs the data content to the external host computer through the interface conversion unit.

[0062] The cache unit controller internally includes multi-channel trigger processing logic, cache unit read / write control logic, and channel status information processing logic. According to the data transmitted by the configuration information, the setting of the acquisition parameters of each channel is completed. On the one hand, when the trigger signal transmitted by the second interface is received, according to the acquisition parameters set for each channel, the signal acquisition of each channel is completed, its waveform data is written into the cache unit through the third interface, and the channel acquisition status information is transmitted to the configuration unit through the control signal; on the other hand, the configuration unit transmits the acquisition instruction to the cache unit controller through the control signal, and the cache unit controller reads the data content of the cache unit through the third interface according to the instruction content, and transmits it to the configuration unit through the control signal.

[0063] In some embodiments, according to the above debugging device, by configuring the selection of signal sources and the trigger conditions between them, the signal waveform at the target time point can be acquired, and the waveform data is transmitted to the host computer through the external bus interface and displayed by the host computer software, so as to realize function debugging, and realize the debugging of the internal logic of the chip without the participation of an oscilloscope and external debugging instruments, thereby reducing the debugging conditions and improving the convenience of debugging.

[0064] In some embodiments, the combinational logic includes multiple conditions. For example, assuming the combinational logic is (channel 1 | channel 2) & channel 3, the combinational logic contains 3 conditions. The data sources corresponding to the combinational logic are the data corresponding to channel 1, the data corresponding to channel 2, and the data corresponding to channel 3. The data corresponding to channel 1, the data corresponding to channel 2, and the data corresponding to channel 3 may not arrive at the same time. In this case, the data that arrives first needs to be cached in the cache unit. After the data that meets the remaining conditions arrives, the overall logic is triggered. In this case, the space of the cache unit will be occupied, and at the same time, the timeliness of the debug data trigger will be affected.

[0065] In order to solve the aforementioned problem, in this embodiment, the logic trigger unit performs the following steps when determining the combinational logic trigger:

[0066] If the first condition in the combinational logic is met first, the cache unit controller is triggered to store the corresponding acquired data in the cache unit; further, when the remaining conditions in the combinational logic are acquired, the cache unit controller is triggered to synchronize the data previously stored in the cache unit under the first condition, and the interface conversion unit is triggered to transparently transmit the data content acquired when the remaining conditions are triggered;

[0067] Among them, after the external host computer obtains the data content of the corresponding combinational logic from the cache unit and the data content under the complete combinational logic transmitted from the cache unit controller, it sends adjustment control instructions to one or more of the signal selection controller, logic trigger unit and cache unit controller through the corresponding interface conversion unit and configuration unit, or sends a debug signal reporting time adjustment instruction to the chip itself, so that the data reporting consistency triggered by the combinational logic judgment after adjustment is more in place.

[0068] In some embodiments, first, different data can be acquired in time-sharing order according to the order in which the data meeting the conditions arrive. After all the data are acquired, the previously acquired data is processed according to the combinational logic to acquire data that conforms to the combinational logic, and the corresponding acquired data is stored in the cache unit. After acquiring the data corresponding to the remaining conditions in the combinational logic, the data previously stored in the cache unit under the first condition (for the convenience of subsequent description, recorded as data A) is transmitted to the host computer, and at the same time, the interface conversion unit is triggered to transparently transmit the data content acquired when the remaining conditions are triggered (for the convenience of subsequent description, recorded as data B).

[0069] After receiving the corresponding data content, the host computer determines whether data A and data B need to be triggered at different times according to the combinational logic. If they do not need to be triggered at different times, the triggering order of the combinational logic or the sending order of the signals to be debugged can be adjusted, so that after the adjustment, the data reporting consistency triggered according to the combinational logic judgment is more in place.

[0070] Method 1: Adjust the triggering order of the combinational logic: Send an adjustment control instruction to one or more of the signal selection controller, logic trigger unit, and cache unit controller to adjust the triggering order of the combinational logic. For example, the adjustment strategy can be: Arrange multiple combinational logics with relatively high correlation together.

[0071] Or, trigger the combinational logic with fewer conditions first, so that after the adjustment, the data reporting consistency triggered according to the combinational logic judgment is more in place. The specific adjustment strategy can be determined according to the actual situation.

[0072] Method 2: Adjust the sending order of the signals to be debugged: Send a debug signal reporting time adjustment instruction to the chip itself, and send the signals to be tested that fall into the same combinational logic together or in sequence, so that the judgment of the combinational logic can be completed at one time.

[0073] According to the foregoing order, it can be ensured that the judgment of the combinational logic can be completed at one time as much as possible, waiting for other related debug signals can be avoided as much as possible, the storage space of the cache unit can be avoided from being occupied, and at the same time, after the adjustment, the data reporting consistency triggered according to the combinational logic judgment is more in place.

[0074] By using the chip debugging device and method provided in the embodiments of the present invention, information interaction is established between the interface conversion unit and the external host computer, and the configuration unit sends corresponding configuration information to the signal selection controller, logic trigger unit, and cache unit controller connected through the general interface, prompting the signal to be debugged to be logically triggered and stored in the cache unit, and sending the cached data to the configuration unit according to the control signal of the configuration unit, and then providing it to the external host computer connected to the interface conversion unit; according to the above debugging device, by configuring the selection signal source and the triggering conditions between them, the signal waveform at the target time point can be collected, and the waveform data is transmitted to the host computer through the external bus interface and displayed through the host computer software, realizing the debugging of the internal logic of the chip without the participation of an oscilloscope and external debugging instruments, thereby reducing the debugging conditions and improving the convenience of debugging.

[0075] The embodiments of the present invention also provide a chip debugging method. As Figure 3 shown, the process is as follows:

[0076] In step 101, the interface conversion unit receives signals from the external host computer through an external bus and converts them into internal bus signals, or converts internal bus signals into external common interface signals and sends them to the external host computer through the external bus, so as to realize information interaction with the external host computer.

[0077] In step 102, the configuration unit receives the internal bus signals from the interface conversion unit through the internal bus, generates configuration information and sends it to the signal selection controller, the logic trigger unit and the cache unit controller, and caches the configuration information in the cache unit.

[0078] The configuration unit internally contains configuration information related to the signal selection controller, the logic trigger unit and the cache unit controller, the working state information of the cache unit controller, the instruction and data decoding logic, and the control logic related to the cache unit controller; when receiving instructions and data transmitted through the internal bus, the instruction and data decoding logic inside the configuration unit identifies the content of the instructions and data. According to the identification results, on the one hand, it will be converted into the configuration information of the corresponding module and sent to the signal selection controller through the configuration information, sent to the logic trigger unit through the configuration information, and sent to the cache unit controller through the configuration information; on the other hand, it uses the controller signal to query the state information of the cache unit controller and caches the state information in the internal register. The configuration unit can send the state information of the cache unit controller and the waveform data in the cache unit to the interface conversion unit through the internal bus.

[0079] In step 103, the signal selection controller selects different signal sources to be adjusted according to the configuration information, splices and combines them, and maps them to the corresponding acquisition channels for transmission to the logic trigger unit.

[0080] The signal selection controller internally contains multi-channel signal mapping logic. According to the data transmitted by the configuration information, the debugging signals are spliced and mapped into each data channel as required, and then the data of each channel is transmitted to the logic trigger unit through the first interface.

[0081] In step 104, the logic trigger unit logically triggers the signals to be adjusted on each channel output by the signal selection controller according to the configuration information, and sends the generated trigger signals to the cache unit controller.

[0082] In step 105, the cache unit controller writes the signals to be adjusted into the cache unit according to the configuration information and the trigger signals, and transfers the data of each channel cache unit to the configuration unit according to the control signals of the configuration unit, and transmits it to the interface conversion unit through the internal bus, so as to provide it to the external host computer connected to the interface conversion unit.

[0083] In step 106, the buffer unit stores the signal to be adjusted under the control of the buffer unit controller.

[0084] According to the above debugging device, by configuring the signal source and the triggering conditions between them, the signal waveform at the target time point can be collected. The waveform data is transmitted to the host computer through the external bus interface and displayed through the host computer software, thereby realizing function debugging; it realizes the debugging of the internal logic of the chip without the participation of the processor and external debugging instruments, thereby reducing the debugging conditions and improving the convenience of debugging.

[0085] Such as Figure 3 , and the debugging process of the external host computer is as follows:

[0086] Step S1, the host computer software writes a fixed sequence into the debugging device through the external bus and enables the debugging function.

[0087] Step S2, the host computer software sends the configuration information required by the debugging device through the external bus to complete the configuration of all functional modules.

[0088] After the modulation device is configured, it collects the signals to be adjusted that meet the target conditions on each channel and caches the data into the buffer unit.

[0089] Step S4, the host computer software reads the status information of the buffer unit controller through the external bus interface to confirm whether the data of all channels has been collected.

[0090] Step S5, the host computer software reads out the waveform data of each channel cached inside the modulation device through the external bus interface and displays it through the graphical interface.

[0091] The internal of the logic trigger unit includes multi-channel trigger judgment logic. The multi-channel trigger judgment logic is used to perform multi-level judgments on the channel signals transmitted by the signal selection controller according to the data transmitted by the configuration information, and then transmit the judgment results and the data of each channel to the buffer unit controller through the second interface;

[0092] In some embodiments, the multi-level judgment specifically includes:

[0093] Each channel completes the logical judgment of the unit signal according to the configuration information, including rising edge, falling edge, high level, low level or multi-bit signal logical judgment, and each channel will complete one or more combination logical judgments of channel 1&channel 2, channel 1|channel 2, channel 1^(!channel 2), (channel 1|channel 2)&channel 3 according to the configuration information;

[0094] Among them, "&", "|", "^", and "!" are all logical operators. "&" represents logical AND, "|" represents logical OR, "^" represents exclusive OR, and "!" represents logical NOT.

[0095] The logic trigger unit internally includes multi-channel trigger judgment logic. According to the data transmitted by the configuration information, it performs multi-level judgments on the channel signals transmitted by the signal selection controller, and then transmits the judgment results and the data of each channel to the cache unit controller through the second interface. The specific implementation process of the multi-level judgment is as follows: Each channel first completes the unit signal logic judgment according to the configuration information, such as rising edge, falling edge, high level, and low level, or the multi-bit signal logic judgment such as equal to A (representing a number), not equal to A, greater than A, less than A, greater than A and less than B (representing a number), etc. Then, between each channel, it completes the combinational logic judgment according to the configuration information, including but not limited to channel 1 & channel 2, channel 1 | channel 2, channel 1 ^ (! channel 2), (channel 1 | channel 2) & channel 3, etc. Among them, "&", "|", "^", and "!" are all logical operators. "&" represents logical AND, "|" represents logical OR, "^" represents exclusive OR, and "!" represents logical NOT.

[0096] The cache unit controller internally includes multi-channel trigger processing logic, cache unit read / write control logic, and channel status information processing logic; the cache unit controller is used to complete the setting of the acquisition parameters of each channel according to the data transmitted by the configuration information, and after receiving the trigger signal transmitted from the logic trigger unit, according to the acquisition parameters set for each channel, complete the signal acquisition of each channel, write its waveform data into the cache unit through the third interface, and transmit the channel status information to the configuration unit through the control signal.

[0097] At the same time, the cache unit controller is also used to receive the acquisition instruction from the configuration unit, read the data content of the cache unit through the third interface according to the content of the acquisition instruction, and transmit it to the configuration unit, and the configuration unit outputs the data content to the external host computer through the interface conversion unit.

[0098] The cache unit controller internally includes multi-channel trigger processing logic, cache unit read / write control logic, and channel status information processing logic. According to the data transmitted by the configuration information, it completes the setting of the acquisition parameters of each channel. On the one hand, when receiving the trigger signal transmitted by the second interface, according to the acquisition parameters set for each channel, complete the signal acquisition of each channel, write its waveform data into the cache unit through the third interface, and transmit the channel acquisition status information to the configuration unit through the control signal; on the other hand, the configuration unit transmits the acquisition instruction to the cache unit controller through the control signal, and the cache unit controller reads the data content of the cache unit through the third interface according to the instruction content, and transmits it to the configuration unit through the control signal.

[0099] In some embodiments, when making a combined logic trigger judgment in the logic trigger unit, it specifically includes:

[0100] If the first condition in the combined logic arrives first, the cache unit controller is triggered to store the corresponding obtained data in the cache unit; further, when the remaining conditions in the combined logic are obtained, the cache unit controller is triggered to synchronize and complete the data stored in the cache unit under the satisfaction of the first condition, and the interface conversion unit is triggered to transparently transmit the data content obtained when the remaining conditions are triggered.

[0101] Among them, after the external host computer obtains the data content of the corresponding combined logic from the cache unit and the data content under the complete combined logic transparently transmitted by the cache unit controller, through the corresponding interface conversion unit and configuration unit, an adjustment control instruction is sent to one or more of the signal selection controller, logic trigger unit, and cache unit controller, or a debugging signal reporting time adjustment instruction is sent to the chip itself, so that the data reporting consistency triggered according to the combined logic judgment after adjustment is more in place.

[0102] The embodiment of the present invention also provides another chip debugging method. In this embodiment, the test completion result will not be directly provided to the external host computer.

[0103] As Figure 5 shown, the method flow is as follows:

[0104] In step 201, the interface conversion unit receives a signal from the external host computer through the external bus and converts it into an internal bus signal, or converts the internal bus signal into an external common interface signal and sends it to the external host computer through the external bus, so as to realize information interaction with the external host computer.

[0105] In step 202, the configuration unit receives the internal bus signal from the interface conversion unit through the internal bus, generates configuration information and sends it to the signal selection controller, logic trigger unit, and cache unit controller, and caches the configuration information in the cache unit.

[0106] The configuration unit internally contains configuration information related to the signal selection controller, logic trigger unit, and cache unit controller, the working status information of the cache unit controller, instruction and data decoding logic, and control logic related to the cache unit controller; when receiving instructions and data transmitted on the internal bus, the instruction and data decoding logic inside the configuration unit identifies the instruction and data content. According to the identification result, on the one hand, it will be converted into the corresponding module's configuration information and sent to the signal selection controller through the configuration information, sent to the logic trigger unit through the configuration information, and sent to the cache unit controller through the configuration information; on the other hand, it queries the status information of the cache unit controller using the controller signal and caches the status information in the internal register. The configuration unit can send the status information of the cache unit controller and the waveform data in the cache unit to the interface conversion unit using the internal bus.

[0107] In step 203, the signal selection controller selects different signal sources to be adjusted according to the configuration information and splices and combines them to map to the corresponding acquisition channels and transmits them to the logic trigger unit.

[0108] The signal selection controller internally contains multi-channel signal mapping logic. According to the data transmitted by the configuration information, it splices and maps the debugging signals into each data channel as required, and then transmits the data of each channel to the logic trigger unit through the first interface.

[0109] In step 204, the logic trigger unit logically triggers the signals to be adjusted output by the signal selection controller for each channel according to the configuration information, and sends the generated trigger signal to the cache unit controller.

[0110] In step 205, the cache unit controller writes the signal to be adjusted into the cache unit according to the configuration information and the trigger signal, and temporarily stores the test completion result in the cache unit, waiting for the external host computer to retrieve the result stored in the cache unit through the interface conversion unit.

[0111] In some embodiments, according to the above debugging device, by configuring and selecting the signal sources and the trigger conditions between them, the signal waveforms at the target time points can be collected. The waveform data is transmitted to the host computer through the external bus interface and displayed through the host computer software, thereby realizing function debugging. It realizes the debugging of the internal logic of the chip without the participation of an oscilloscope and external debugging instruments, thus reducing the debugging conditions and improving the convenience of debugging.

[0112] In step 206, the cache unit provides the signal to be adjusted to the external host computer.

[0113] By adopting the chip debugging method according to the embodiment of the present invention, information interaction is established with an external host computer, and corresponding configuration information is sent to a signal selection controller, a logic trigger unit, and a cache unit controller through a configuration unit. The signal to be debugged is logically triggered and stored in the cache unit, and the cached data is sent to the configuration unit according to the control signal of the configuration unit, and then provided to the external host computer connected to the same interface conversion unit. By configuring the selection signal and the trigger condition between them, the signal waveform at the target time point can be collected, and the waveform data is transmitted to the host computer through the external bus interface and displayed through the host computer software, realizing the debugging of the internal logic of the chip without the participation of an oscilloscope and external debugging instruments, thereby reducing the debugging conditions and improving the convenience of debugging.

[0114] Figure 6 The block diagram of an electronic device according to an embodiment of the present application. An embodiment of the present application further provides an electronic device, as Figure 6 shown, the electronic device includes: at least one processor 701, and a memory 703 communicatively connected to the at least one processor 701. Instructions executable by the at least one processor 701 are stored in the memory 703. The instructions are executed by the at least one processor 701. When the processor 701 executes the instructions, the chip debugging method in the above embodiment is implemented. The number of the memory 703 and the processor 701 can be one or more. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described herein and / or claimed.

[0115] The electronic device may further include a communication interface 705 for communicating with external devices and performing data interaction and transmission. Each device is interconnected using different buses and may be mounted on a common motherboard or otherwise mounted as required. The processor 701 may process instructions executed within the electronic device, including instructions stored in or on the memory to display graphical information of a graphical user interface (GUI) on an external input / output device (such as a display device coupled to the interface). In other embodiments, if necessary, multiple processors and / or multiple buses may be used together with multiple memories and multiple memories. Similarly, multiple electronic devices may be connected, with each device providing a portion of the necessary operations (such as an array of servers, a set of blade servers, or a multi-processor system). The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 only a thick line is shown in the figure, but this does not mean that there is only one bus or one type of bus.

[0116] Optionally, in a specific implementation, if the memory 703, the processor 701, and the communication interface 705 are integrated on a single chip, the memory 703, the processor 701, and the communication interface 705 may communicate with each other through an internal interface.

[0117] It should be understood that the above-mentioned processor may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor that supports the advanced reduced instruction set machine (ARM) architecture.

[0118] An embodiment of the present application provides a computer-readable storage medium (such as the above-mentioned memory 703), which stores computer instructions. When the program is executed by the processor, the method provided in the embodiment of the present application is implemented.

[0119] Optionally, the memory 703 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the electronic device of the driving scenario reconstruction method, etc. In addition, the memory 703 may include a high-speed random access memory and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory 703 may optionally include a memory remotely provided with respect to the processor 701, and these remote memories may be connected to the electronic device of the driving scenario reconstruction method through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0120] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0121] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0122] Any process or method description shown in the flowchart or described in other ways herein may be understood as representing a module, segment, or part of code including one or more (two or more) executable instructions for implementing a specific logical function or process. And the scope of the preferred embodiments of the present application includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in the reverse order according to the functions involved, rather than in the order shown or discussed.

[0123] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definable sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in combination with these instruction execution systems, apparatus, or devices.

[0124] It should be understood that each part of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the method in the above embodiments can be completed by a program instructing relevant hardware, and this program can be stored in a computer-readable storage medium. When this program is executed, it includes one or a combination of the steps of the method embodiments.

[0125] In addition, in each embodiment of the present application, each functional unit can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a magnetic disk, an optical disc, etc.

[0126] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of various changes or substitutions, and these should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip debugging device, characterized in that, It includes an interface conversion unit, a configuration unit, a signal selection controller, a logic trigger unit, a cache unit and a cache unit controller, wherein: The interface conversion unit is connected to the external host computer via an external bus, and is used to receive a signal from the external host computer via the external bus and convert it into an internal bus signal, and is also used to convert the internal bus signal into an external common interface signal and send it to the external host computer via the external bus; The configuration unit is connected to the interface conversion unit via an internal bus, and is configured to receive the internal bus signal from the interface conversion unit via the internal bus, generate configuration information, and send it to the signal selection controller, the logic trigger unit, and the cache unit controller, and register status information and debug signal data of each cache unit according to the control signal of the cache unit controller; The signal selection controller is used to select different signals to be modulated according to the configuration information, and map the selected signals to be modulated into corresponding acquisition channels and transmit them to the logic trigger unit; The logic trigger unit is used to perform logic triggering on the signal to be adjusted output by the signal selection controller according to the configuration information, and send the generated trigger signal to the cache unit controller; The cache unit controller is used to write the signal to be modulated into the cache unit according to the configuration information and the trigger signal, and is also used to transmit the data of the cache unit to the configuration unit according to the control signal of the configuration unit; The cache unit is used to store the signal to be adjusted under the control of the cache unit controller; The cache unit controller is connected to the cache unit through a third interface; the cache unit controller has multi-channel trigger processing logic, cache unit read and write control logic, and channel status information processing logic; the cache unit controller is used to complete the setting of the acquisition parameters of each channel according to the configuration information, and after receiving the trigger signal transmitted from the logic trigger unit, complete the signal acquisition of each channel according to the acquisition parameters, write the collected waveform data into the cache unit through the third interface, and transmit the channel status information of each channel to the configuration unit through the control signal; the cache unit controller is also used to receive acquisition instructions from the configuration unit, read the data content of the cache unit through the third interface according to the acquisition instructions, and transmit it to the configuration unit.

2. The chip debugging device according to claim 1, wherein The logic trigger unit is connected to the cache unit controller through a second interface. The logic trigger unit has multi-channel trigger judgment logic. The multi-channel trigger judgment logic is used to perform multi-level judgment on the channel signal transmitted by the signal selection controller according to the configuration information, and transmit the judgment result and the data of each channel to the cache unit controller through the second interface.

3. The chip debugging device according to claim 2, wherein Each channel of the multi-channel trigger judgment logic is configured to complete the logical judgment of the unit signal according to the configuration information, including one or more of the rising edge, falling edge, high level, low level, and multi-bit signal logic judgment, and each channel completes the combinational logic judgment according to the configuration information.

4. The chip debugging device according to claim 3, wherein The cache unit controller is used to store the corresponding acquired data in the cache unit when the first condition in the combinational logic is met first, and when the remaining conditions in the combinational logic are acquired, synchronize the data previously stored in the cache unit under the first condition; and is also used to trigger the interface conversion unit to transparently transmit the data content acquired when the remaining conditions are triggered.

5. The chip debugging device according to claim 4, wherein, in, After obtaining the data content of the corresponding combinational logic from the cache unit and the data content under the complete combinational logic transparently transmitted from the cache unit controller, the external host computer sends adjustment control instructions to one or more of the signal selection controller, the logic trigger unit and the cache unit controller through the corresponding interface conversion unit and the configuration unit, or sends a debug signal reporting time adjustment instruction to the chip itself.

6. The chip debugging device according to claim 3, wherein The combinational logic includes one or more combinations of channel 1 & channel 2, channel 1 | channel 2, channel 1 ^ (! channel 2) and (channel 1 | channel 2) & channel 3; wherein, "&", "|", "^" and "!" are all logical operators, "&" represents logical AND, "|" represents logical OR, "^" represents logical XOR, and "!" represents logical NOT.

7. The chip debugging device according to any one of claims 1-6, characterized in that, The cache unit is further used to temporarily store the test results, waiting for the external host computer to retrieve the results stored in the cache unit through the interface conversion unit.

8. A chip debugging method, characterized in that, The method is applied to the chip debugging device according to any one of claims 1 to 7, wherein: The interface conversion unit receives a signal from an external host computer and converts it into an internal bus signal, or converts the internal bus signal into an external common interface signal and sends it to the external host computer via an external bus; The configuration unit generates configuration information according to the internal bus signal and sends it to the signal selection controller, the logic trigger unit and the cache unit controller, and caches the configuration information in the cache unit; The signal selection controller selects different signals to be modulated according to the configuration information, and maps the selected signals to be modulated into corresponding acquisition channels and transmits them to the logic trigger unit; The logic trigger unit performs logic triggering on the signal selection controller to output the signal to be adjusted of each channel according to the configuration information, and stores the status information and debugging signal data of each cache unit according to the control signal of the cache unit controller; The cache unit controller writes the signal to be adjusted into the cache unit according to the configuration information and the trigger signal, transfers the data of each channel cache unit to the configuration unit according to the control signal of the configuration unit, and transmits it to the interface conversion unit through the internal bus to temporarily store the test completion result in the cache unit, waiting for the external host computer to retrieve the result stored in the cache unit through the interface conversion unit; The cache unit stores the signal to be adjusted under the control of the cache unit controller.

9. The chip debugging method according to claim 8, characterized in that, It further includes: Temporarily store the test completion result in the cache unit, waiting for the external host computer to retrieve the result stored in the cache unit through the interface conversion unit.

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