Method, device, equipment and medium for generating field effect transistor device model

Abstract

This application provides a method, apparatus, device, and medium for generating a field-effect transistor (FET) device model. The method includes: determining the source-body junction reverse current and the drain-body junction reverse current of the FET device, where the source-body junction reverse current is the current from the body terminal of the FET device to the source, and the drain-body junction reverse current is the current from the body terminal of the FET device to the drain; constructing a subcircuit model based on the source-body junction reverse current and the drain-body junction reverse current; and constructing a target FET device model based on a preset initial FET device model and the subcircuit model. The target FET device model generated by this technical solution is more accurate, can improve the accuracy of circuit simulation by technicians, and thus enhance circuit performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method, apparatus, device and medium for generating a field effect transistor device model. Background Art

[0002] With the continuous advancement of semiconductor technology, new materials and technologies are being developed and applied, driving the continuous advancement of process nodes. As process dimensions continue to shrink, device fluctuations are increasingly impacting circuit performance and reliability. Accurately characterizing device models to provide a reference for integrated circuit design and optimization is a critical issue that urgently needs to be addressed.

[0003] In the prior art, the BSIM model is mainly used as a bridge connecting semiconductor process manufacturing technology and circuit design, providing circuit designers with a device-level model for circuit simulation.

[0004] However, for field-effect transistors, reverse current is prone to occur due to the formation of a junction between the source, drain and body terminals, and the existing BSIM model cannot accurately characterize the reverse current, which leads to a decrease in the accuracy of circuit simulation by technicians. Summary of the Invention

[0005] The present application provides a method, apparatus, device and medium for generating a field effect transistor device model, which is used to solve the problem that the existing device model has poor accuracy, resulting in reduced simulation accuracy when technicians use the device model to perform circuit simulation.

[0006] In a first aspect, an embodiment of the present application provides a method for generating a field effect transistor device model, comprising:

[0007] Determining a source-body junction reverse current and a drain-body junction reverse current of a field effect transistor device, wherein the source-body junction reverse current is a current from the body terminal of the field effect transistor device to the source, and the drain-body junction reverse current is a current from the body terminal of the field effect transistor device to the drain;

[0008] Constructing a sub-circuit model according to the source-body junction reverse current and the drain-body junction reverse current;

[0009] A target field effect transistor device model is constructed based on the preset initial field effect transistor device model and the sub-circuit model.

[0010] In a second aspect, an embodiment of the present application provides a device for generating a field effect transistor device model, comprising:

[0011] a reverse current determination module, configured to determine a source-body junction reverse current and a drain-body junction reverse current of a field effect transistor device, wherein the source-body junction reverse current is the current from the body terminal of the field effect transistor device to the source, and the drain-body junction reverse current is the current from the body terminal of the field effect transistor device to the drain;

[0012] A sub-model construction module, configured to construct a sub-circuit model according to the source-body junction reverse current and the drain-body junction reverse current;

[0013] The device model construction module is used to construct a target field effect transistor device model based on a preset initial field effect transistor device model and the sub-circuit model.

[0014] In a third aspect, an embodiment of the present application provides a computer device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; and the processor executes the computer-executable instructions stored in the memory to implement the method described above.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to implement the above-mentioned method when executed by a processor.

[0016] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising computer instructions, which implement the above method when executed by a processor.

[0017] The method, apparatus, equipment and medium for generating a field effect transistor device model provided in the embodiments of the present application obtain the source current and drain reverse current of the field effect transistor device to construct a sub-circuit model, and then fit the sub-circuit model to the original BSIM4 model. The device model obtained in this way is more accurate, which improves the circuit simulation accuracy of technicians and thus enhances circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application;

[0019] Figure 1 A schematic diagram of the structure of a field effect transistor device provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a flow chart of a method for generating a field effect transistor device model provided in an embodiment of the present application;

[0021] Figure 3 A model circuit diagram of a field effect transistor device provided in an embodiment of the present application;

[0022] Figure 4 A model circuit diagram of the target field effect transistor device provided in the embodiments of the present application;

[0023] Figure 5 A schematic diagram of a parallel circuit of field effect transistors provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of a junction current curve provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of a junction current curve provided by another embodiment of the present application;

[0026] Figure 8 A schematic diagram comparing the simulated and tested values ​​of the source-body junction reverse current at different temperatures provided by an embodiment of the present application;

[0027] Figure 9 A schematic diagram of the structure of a device for generating a field effect transistor device model provided in an embodiment of the present application;

[0028] Figure 10 A schematic diagram of the structure of a computer device provided in an embodiment of the present application.

[0029] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0030] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] First, let’s explain the terms involved in this application:

[0032] SPICE models bridge the gap between semiconductor manufacturing technology and circuit design, providing circuit designers with device-level models for circuit simulation. SPICE models consist of two parts: model equations and model parameters.

[0033] BSIM model: Developed by the BSIM research group at the University of California, Berkeley, it is a physics-based, highly accurate, and predictive SPICE simulation model for metal oxide semiconductor field effect transistors (MOSFETs). It is one of the most commonly used models in the industry for bulk silicon complementary metal oxide semiconductor (CMOS) modeling.

[0034] With the continuous development of COMS technology, new materials and technologies are constantly being developed and applied, driving the continuous advancement of process nodes. As process dimensions continue to shrink, the impact of device fluctuations on circuit performance and reliability becomes increasingly serious. How to accurately characterize device models to provide a reference for integrated circuit design and optimization is an important issue that needs to be addressed urgently. In the ideal diode model, current conducts in one direction and its reverse current is zero. However, researchers have found that in actual applications, due to recombination and surface effects, reverse leakage current will occur in the diode. As process nodes continue to advance, the magnitude of the reverse leakage current of the diode becomes larger and larger, becoming non-negligible. Therefore, the SPICE model of the diode needs to be adjusted for this. At the same time, in the diode model of MOS devices, for example, the junction from the source to the drain to the ground terminal, the reverse current model cannot be well characterized. This is mainly because the BSIM4 model does not describe the reverse current of its junction in the model equation. On the other hand, taking the N-Metal-Oxide-Semiconductor (NMOS) as an example, in its working state, when the source and drain are connected to a positive voltage and the ground terminal is grounded, a source / drain-to-ground junction reverse current is generated. The MOS is in the working state, and this part of the current is often regarded as the channel current or channel leakage current. However, the source / drain-to-ground junction leakage current is also increasing with the advancement of the process node, and the temperature variation coefficient of the channel leakage current is inconsistent with that of the source / drain junction leakage current. When describing this part of the leakage current, it is easy to cause the model to be inaccurate.

[0035] In response to the above problems, the present application provides a method, apparatus, equipment and medium for generating a field effect transistor device model. In order to solve the problem that the existing model cannot well characterize the reverse current of the device, it is necessary to optimize and adjust the existing model. Specifically, by obtaining the source direction current and drain reverse current of the field effect transistor device, a sub-circuit model is constructed, and then the sub-circuit model is fitted into the original BSIM4 model. The device model obtained in this way is more accurate, which improves the circuit simulation accuracy of technicians and thus improves circuit performance.

[0036] The technical solution of the present application is described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0037] Figure 1 A schematic diagram of the structure of the field effect transistor device provided in the embodiment of the present application is shown in FIG. Figure 1 As shown, this field-effect transistor is an NMOS. The entire NMOS transistor consists of two N-type semiconductors, one P-type semiconductor, several metal electrodes, and an insulating layer. The metal electrodes form the external gate G, drain D, source S, and substrate terminal B. Thus, the entire NMOS transistor consists of two PN junctions. A positive voltage applied from P to N allows conduction, while a positive voltage applied from N to P prevents conduction. For ease of description, this article will refer to the current from P to N as forward current, and the current from N to P as reverse current. Under ideal conditions, the PN junction is unidirectional, meaning the reverse current from N to P should be zero. However, in practice, with the advancement of process nodes, the magnitude of the reverse current is increasing, becoming non-negligible.

[0038] Figure 2 This is a flow chart of a method for generating a field effect transistor device model provided in an embodiment of the present application. This method can be applied to a computer device or other electronic device with a processor. Taking a computer device as the execution subject as an example, the method can specifically include the following steps:

[0039] Step S201: Determine the source-body junction reverse current and the drain-body junction reverse current of the field effect transistor device. The source-body junction reverse current is the current from the body terminal of the field effect transistor device to the source, and the drain-body junction reverse current is the current from the body terminal of the field effect transistor device to the drain.

[0040] In this embodiment, the body end of the field effect transistor device is Figure 1 The source S is connected to the P-type semiconductor in the middle, and the source is set on the N-type semiconductor through a metal electrode. The N-type semiconductor and the P-type semiconductor form a PN junction. The source-body junction reverse current is the current from N to P in the PN junction. The drain D is set on another N-type semiconductor through a metal electrode. The other N-type semiconductor and the P-type semiconductor form another PN junction. The drain-body junction reverse current is the current from N to P in the other PN junction.

[0041] Among them, when determining the source-body junction reverse current and the drain-body junction reverse current of the field-effect transistor device, the drain-body junction reverse current and the source-body junction reverse current of the field-effect transistor device can be obtained by measurement, or the drain-body junction reverse current and the source-body junction reverse current can be calculated according to the parameters of the field-effect transistor device and the corresponding equations.

[0042] Step S202 : constructing a sub-circuit model according to the source-body junction reverse current and the drain-body junction reverse current.

[0043] In this embodiment, Figure 3 The model circuit diagram of the field effect transistor device provided in the embodiment of the present application is as follows: Figure 3 As shown, the field effect transistor device includes a gate G, a drain D, a source S, and a substrate terminal B. As mentioned in step S201, the source-body junction reverse current is actually the current from the substrate terminal B to the source S, and the drain-body junction reverse current is the current from the substrate terminal B to the drain D. Therefore, a sub-circuit model can be constructed. The sub-circuit model can include two current sources, where the current in one current source flows from the substrate terminal B to the source S, and the current in the other current source flows from the substrate terminal B to the drain D.

[0044] The magnitude of the current flowing from the substrate terminal B to the source S and the magnitude of the current flowing from the substrate terminal B to the drain D can be determined according to the magnitudes of the source-body junction reverse current and the drain-body junction reverse current in step S201.

[0045] Step S203 : constructing a target field effect transistor device model according to the preset initial field effect transistor device model and the sub-circuit model.

[0046] In this embodiment, the circuit diagram of the preset initial field effect transistor device model can be as described above. Figure 3 As shown, the preset initial field effect transistor device model includes a model equation and model parameters. The model parameters may include relevant property parameters of the field effect transistor device. The model equation may be used to calculate parameters such as current and voltage involved in the field effect transistor device.

[0047] For example, Figure 4 The model circuit diagram of the target field effect transistor device provided in the embodiment of the present application is as follows: Figure 4 As shown, a current source gd1 is added between the drain D and the substrate terminal B, and a current source gs1 is added between the source S and the substrate terminal B, and then the source-body junction reverse current and the drain-body junction reverse current determined in practice are referred to. Figure 4 The model circuit in the target FET is fitted so that the fitting result is consistent with the measured data, and the target FET device model is finally obtained. The target FET device model includes model equations and model parameters. The model equations can be calculation formulas for calculating the source-body junction reverse current and the drain-body junction reverse current. The model parameters can be relevant property parameters of the FET device and environmental parameters, such as temperature parameters and drain terminal area.

[0048] The embodiment of the present application obtains the source direction current and drain reverse current of the field effect transistor device, constructs a sub-circuit model, and then fits the sub-circuit model into the original BSIM model. The device model obtained in this way is more accurate, which improves the circuit simulation accuracy of technicians and thus improves circuit performance.

[0049] In some embodiments, the preset initial FET model can be divided into two parts: a model equation and model parameters. The preset initial FET model can calculate the source-body junction forward current and the drain-body junction forward current of the FET device through the model equation, thereby characterizing the source-body junction forward current and the drain-body junction forward current of the FET device. Therefore, the target FET model obtained after fitting the sub-model with the preset FET device model can characterize both the source-body junction forward current and the drain-body junction forward current, as well as the source-body junction reverse current and the drain-body junction reverse current of the FET device. Determining the source-body junction forward current and the drain-body junction forward current can be specifically achieved through the following steps: determining the source-body junction forward current and the drain-body junction forward current of the FET device; and constructing the preset initial FET device model based on the source-body junction forward current and the drain-body junction forward current. The source-body junction forward current is the current flowing from the source to the body of the FET device, and the drain-body junction forward current is the current flowing from the drain to the body of the FET device.

[0050] In this embodiment, you can continue to refer to Figure 1 , the source S is set on an N-type semiconductor through a metal electrode, forming a PN junction with a P-type semiconductor. The forward current of the source-body junction is the current from P to N in the PN junction. The drain D is set on another N-type semiconductor through a metal electrode. The other N-type semiconductor forms another PN junction with a P-type semiconductor. The forward current of the drain-body junction is the current from P to N in the other PN junction. It should be noted that Figure 1 The figure shows NMOS. In practical applications, MOS can be specifically divided into P-type field effect transistors (positive channel Metal Oxide Semiconductor, PMOS) and NMOS. Among them, the substrate of PMOS is an N-type semiconductor, and the source S is set on a P-type semiconductor through a metal electrode, and the drain D is set on another P-type semiconductor through a metal electrode. Different types of MOS are applicable to this solution.

[0051] The embodiment of the present application constructs a preset initial field effect transistor device model by determining the source-body junction forward current and the drain-body junction forward current of the field effect transistor device, so that the preset initial field effect transistor device model can characterize the source-body junction forward current and the drain-body junction forward current of the field effect transistor device, thereby improving the accuracy of the target field effect transistor device.

[0052] Furthermore, in other embodiments, when determining the source-body junction forward current and the drain-body junction forward current of a field-effect transistor device, it can be specifically achieved through the following steps: grounding the gate, source, and drain of the field-effect transistor device; performing a voltage scan on the body terminal of the field-effect transistor device, and reading the current changes of the source and drain of the field-effect transistor device; determining the source-body junction forward current and the drain-body junction forward current based on the current changes of the source and drain, wherein the body terminal of the field-effect transistor device is the substrate terminal.

[0053] In this embodiment, the source-body junction current and the drain-body junction current of the field-effect transistor device can be measured by grounding the gate, source and drain of the MOS device, performing a voltage scan on its body end, reading out the parameters of the source current change and the parameters of the drain current change, and then calculating the source-body junction forward current and the drain-body junction forward current based on the parameters.

[0054] In other embodiments, to ensure accurate current measurement, multiple field-effect transistors can be connected in parallel. After obtaining the measurement results, they are normalized to obtain the measurement results of the source-body junction forward current and the drain-body junction forward current of a single field-effect transistor device. This can be achieved specifically by the following steps: connecting at least two field-effect transistors in parallel and grounding the gate, source, and drain of the parallel field-effect transistor devices; performing a voltage scan on the body terminals of the parallel field-effect transistor devices and reading the current changes of the source and drain of the parallel field-effect transistor devices, where the body terminals of the field-effect transistor devices are the substrate terminals; and determining the source-body junction forward current and the drain-body junction forward current based on the current changes of the source and drain of the parallel field-effect transistor devices and the number of parallel field-effect transistor devices.

[0055] For example, Figure 5 The parallel circuit diagram of the field effect tube provided in the embodiment of the present application is as follows: Figure 5 As shown, there are two field-effect transistors connected in parallel, with the source of one field-effect transistor connected to the source of the other field-effect transistor, the drain connected to the drain, and the gate connected to the gate. The parallel field-effect transistor device can be regarded as including a gate G, a source S, a drain D, and two body terminals B.

[0056] In the embodiment of the present application, multiple field-effect transistor devices are connected in parallel, the current changes of the source and drain of the parallel field-effect transistor devices are measured, and then the measurement results are normalized to obtain the measurement results of the source-body junction forward current and the drain-body junction forward current of a single field-effect transistor device, thereby improving the measurement accuracy.

[0057] Further, in some embodiments, after reading the parameters of the source current change and the parameters of the drain current change, the source-body junction forward current can be determined specifically by the following steps: obtaining the first current per unit area, the side current per unit length along the gate edge, the side current along the shallow trench isolation edge, the source end area, the perimeter of the source end along the shallow trench isolation edge, the field effect transistor device width and the number of field effect transistor devices in parallel; calculating the source-body junction forward current based on the first current per unit area, the side current per unit length along the gate edge, the side current along the shallow trench isolation edge, the source end area, the perimeter of the source end along the shallow trench isolation edge, the field effect transistor device width and the number of field effect transistor devices in parallel.

[0058] The drain-body junction forward current can be determined by the following steps: obtaining the second current per unit area, the drain terminal area, and the perimeter of the drain terminal along the shallow trench isolation edge; and calculating the drain-body junction forward current based on the second current per unit area, the side current per unit length along the gate edge, the side current along the shallow trench isolation edge, the drain terminal area, the perimeter of the drain terminal along the shallow trench isolation edge, the field effect transistor device width, and the number of field effect transistor devices connected in parallel.

[0059] The first current may be a source-body current, and the second current may be a drain-body current. In this embodiment, when calculating the forward current of the source-body junction, it can be specifically calculated using the following formula:

[0060] I sbs =A seff J ss (T)+P seff J ssws (T)+W effcj *NF*J sswgs (T)

[0061] In the above formula, I sbs Represents the source-body junction forward current, J ss (T) represents the first current per unit area, J ssws (T) represents the side current per unit length along the gate edge, J sswgs (T) represents the side current along the edge of shallow trench isolation (STI), A seff Represents the source end area, P seff W represents the perimeter of the source end along the edge of the shallow trench isolation. effcj Indicates the width of the field effect transistor device, that is, the length along the source end and the gate edge.

[0062] When calculating the forward current of the source-body junction, it can be calculated using the following formula:

[0063] I sbd=A deff J sd (T)+P deff J sswd (T)+W effcj *NF*J sswgd (T)

[0064] In the above formula, I sbd Represents the drain-body junction forward current, J sd (T) represents the second current per unit area, J sswd (T) represents the side current per unit length along the gate edge, J sswd (T) represents the side current along the edge of the shallow trench isolation, A deff is the drain area, P deff is the perimeter of the drain end along the edge of the shallow trench isolation, W effcj Indicates the width of the field effect transistor device, that is, the length along the source end and the gate edge.

[0065] Based on the commonly used parameters of the FET device model, Aseff and Adeff can be calculated by multiplying W (device width) by SA / SB (the width of the active area beyond the gate, plus the width of the source region); Pseff and Pdeff can be calculated by W + 2*SA / W + 2*SB. Therefore, after providing W and SA / SB, the source-body junction forward current and drain-body junction forward current can be calculated using the model's built-in formulas.

[0066] The embodiment of the present application obtains the source-body junction forward current and the drain-body junction forward current through consensus calculation, which can ensure the accuracy of the source-body junction forward current and the drain-body junction forward current, thereby further improving the accuracy of the target field effect transistor device model.

[0067] In some embodiments, in the above step S201, "determining the source-body junction reverse current and the drain-body junction reverse current of the field-effect transistor device" can be specifically achieved through the following steps: obtaining the voltage across the source-body junction, the voltage across the drain-body junction, the width of the field-effect transistor device, the width of the active area beyond the gate, and the fitting parameters; calculating the source-body junction reverse current and the drain-body junction reverse current based on the voltage across the source-body junction, the voltage across the drain-body junction, the width of the field-effect transistor device, the width of the active area beyond the gate, and the fitting parameters.

[0068] In this embodiment, the source-body junction reverse current and the drain-body junction reverse current can be calculated by the following formula: I = Irev*W*SA*exp(Fac1)*V(n1, n2)-Fac2*pwr(V(n1, n2, W*Fac3)). Wherein, I represents the source-body junction reverse current and the drain-body junction reverse current, V(n1, n2) represents the voltage across the PN junction, W represents the width of the field-effect transistor device, SA represents the width of the active area beyond the gate, and Irev, Fac1, Fac2, and Fac3 are all fitting parameters. The fitting parameters can be adjusted according to the actual test values ​​so that the source-body junction reverse current and the drain-body junction reverse current calculated by the above formula fit the actual test values. Exp() is an exponential function, and pwr() is a power function. For example, pwr(A, B) is the output A to the power of B.

[0069] For example, Figure 6 A schematic diagram of a junction current curve provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the point values ​​are actual test values, and the solid lines are simulation values ​​obtained by simulating using the preset initial field effect transistor device model. It can be found that the preset initial field effect transistor device model cannot characterize the source-body junction reverse current and the drain-body junction reverse current.

[0070] Figure 7 A schematic diagram of a junction current curve is provided for another embodiment of the present application, such as Figure 7 As shown, the point values ​​are actual test values, and the solid lines are simulation values ​​obtained by simulating the target field effect transistor device model. It can be found that the target field effect transistor device model can characterize the source-body junction reverse current and the drain-body junction reverse current.

[0071] The embodiment of the present application calculates the source junction reverse current and the drain junction reverse current through the reverse current calculation formula, so that the target field effect transistor device model can accurately fit its reverse leakage current with basically no effect on the forward current, thereby improving the circuit simulation accuracy of technicians and thus improving circuit performance.

[0072] Furthermore, in some other embodiments, a temperature parameter may be added to calculate the source-body junction reverse current and the drain-body junction reverse current at different temperatures. Specifically, the voltage across the source-body junction, the voltage across the drain-body junction, the field-effect transistor device width, the width of the active region extending beyond the gate, fitting parameters, and temperature parameters may be obtained, where the temperature parameters include at least two. The source-body junction reverse current and the drain-body junction reverse current may be calculated based on the temperature parameters, the voltage across the source-body junction, the voltage across the drain-body junction, the field-effect transistor device width, the width of the active region extending beyond the gate, and the fitting parameters.

[0073] In this embodiment, the source-body junction reverse current and the drain-body junction reverse current can be calculated using the following formulas:

[0074] I=Irev*W*SA*exp(Fac1)*V(n1, n2)*(1+temper11*(temper-25))-Fac2*pwr(V(n1, n2, W*Fac3)*(1+temper2*(temper-25))).

[0075] In the above formula, I represents the source-body junction reverse current and the drain-body junction reverse current, V(n1, n2) represents the voltage across the PN junction, W represents the width of the field-effect transistor device, SA represents the width of the active area beyond the gate, and Irev, Fac1, Fac2, Fac3, temper1, and temper2 are all fitting parameters. The fitting parameters can be adjusted according to the actual test values ​​so that the source-body junction reverse current and the drain-body junction reverse current calculated by the above formula fit the actual test values. Exp() is an exponential function, and pwr() is a power function. For example, pwr(A, B) is the output A to the power of B. Temper refers to temperature. For example, Figure 8 Schematic diagram comparing the simulated and tested values ​​of the source-body junction reverse current at different temperatures provided in the embodiment of the present application, as shown in FIG. Figure 8 As shown in the figure, the dotted line represents the actual test value, and the solid line represents the simulation value calculated by the above formula. The actual test value and the simulation value are fitted at different temperatures.

[0076] By adding a temperature parameter to the reverse current calculation formula, the embodiment of the present application can also calculate the target field effect transistor device model to fit the source junction reverse current and the drain junction reverse current to the test data for test data at different temperatures, thereby improving the calculation results of the target field effect transistor device model at different temperatures, further making the model more accurate, and improving the circuit simulation accuracy of technicians, thereby improving circuit performance.

[0077] In some embodiments, a target field effect transistor device model can also be obtained by modeling using the following method, which includes: (1) obtaining test data for modeling through tape-out testing, adjusting the basic parameter model of the field effect transistor device so that the DC characteristic simulation model of the model is consistent with the test data; (2) measuring the source-body junction current and drain-body junction current of the field effect transistor device, wherein the gate, source, and drain of the field effect transistor device are grounded, voltage scanning is performed on its body terminal, and the parameters of the source-drain current change are read. To ensure the accuracy of current measurement, multiple field effect transistor devices can be connected in parallel, and after obtaining the measurement results, they are normalized to obtain the measurement results of the source / drain-body junction current of a single field effect transistor device; (3) establishing a sub-circuit model for the field effect transistor device, using the added sub-circuit model, adding a junction reverse current source, referring to the measured data, fitting the model so that the fitting result is consistent with the measured data, optimizing the model, reducing the error between the model and the measured data, and obtaining the final complete target field effect transistor device model.

[0078] It should be noted that in this application, the fitting parameters in the formula can be adjusted, and simulation calculations can be performed based on the adjusted fitting parameters and the above-mentioned calculation formula to obtain simulation values. At the same time, the simulation values ​​can be compared with the actual test values ​​to further optimize the fitting parameters, ultimately reducing the error between the target field effect transistor device model and the measured data, thereby improving the accuracy of the target field effect transistor device model. Among them, the target field effect transistor device model can be constructed using relevant software in a computer device. The simulation process can also be implemented using relevant software in a computer device.

[0079] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0080] Figure 9 This is a schematic diagram of the structure of the device for generating a field effect transistor device model provided in an embodiment of the present application. The device for generating a field effect transistor device model can be integrated into a computer device, or can be independent of the computer device and work together with the computer device to implement this solution. Figure 9 As shown, the generating apparatus 900 includes a reverse current determining module 910 , a sub-model building module 920 and a device model building module 930 .

[0081] The reverse current determination module 910 is used to determine the source-body junction reverse current and drain-body junction reverse current of the field-effect transistor device. The source-body junction reverse current is the current from the body terminal of the field-effect transistor device to the source, and the drain-body junction reverse current is the current from the body terminal of the field-effect transistor device to the drain. The sub-model construction module 920 is used to construct a sub-circuit model based on the source-body junction reverse current and the drain-body junction reverse current. The device model construction module 930 is used to construct a target field-effect transistor device model based on the preset initial field-effect transistor device model and the sub-circuit model.

[0082] Optionally, the generating device further includes an initial device model construction module for determining a source-body junction forward current and a drain-body junction forward current of the field-effect transistor device; and constructing a preset initial field-effect transistor device model based on the source-body junction forward current and the drain-body junction forward current. The source-body junction forward current is the current flowing from the source to the body of the field-effect transistor device, and the drain-body junction forward current is the current flowing from the drain to the body of the field-effect transistor device.

[0083] Optionally, the initial device model construction module can be specifically used to: ground the gate, source and drain of the field effect transistor device; perform a voltage scan on the body end of the field effect transistor device and read the current changes of the source and drain of the field effect transistor device; determine the source-body junction forward current and the drain-body junction forward current based on the current changes of the source and drain, wherein the body end of the field effect transistor device is the substrate end.

[0084] Optionally, the initial device model construction module can be specifically used to: connect at least two field effect transistor devices in parallel, and ground the gate, source and drain of the parallel field effect transistor devices; perform voltage scanning on the body terminals of the parallel field effect transistor devices, and read the current changes of the source and drain of the parallel field effect transistor devices; determine the source-body junction forward current and the drain-body junction forward current based on the current changes of the source and drain of the parallel field effect transistor devices and the number of parallel field effect transistor devices, wherein the body terminal of the field effect transistor device is the substrate terminal.

[0085] Optionally, the initial device model construction module can be specifically used to: obtain a first current per unit area, a side current per unit length along a gate edge, a side current along a shallow trench isolation edge, a source terminal area, a perimeter of the source terminal along a shallow trench isolation edge, a field effect transistor device width, and the number of field effect transistor devices connected in parallel; and calculate a source-body junction forward current based on the first current per unit area, the side current per unit length along a gate edge, the side current along a shallow trench isolation edge, the source terminal area, the perimeter of the source terminal along a shallow trench isolation edge, the field effect transistor device width, and the number of field effect transistor devices connected in parallel;

[0086] In addition, the second current per unit area, the drain area, and the perimeter of the drain along the shallow trench isolation edge are obtained; based on the second current per unit area, the side current per unit length along the gate edge, the side current along the shallow trench isolation edge, the drain area, the perimeter of the drain along the shallow trench isolation edge, the field effect transistor device width, and the number of field effect transistor devices in parallel, the drain-body junction forward current is calculated.

[0087] Optionally, the reverse current determination module can be specifically used to: obtain the voltage across the source-body junction, the voltage across the drain-body junction, the field-effect transistor device width, the width of the active area beyond the gate, and fitting parameters; and calculate the source-body junction reverse current and the drain-body junction reverse current based on the voltage across the source-body junction, the voltage across the drain-body junction, the field-effect transistor device width, the width of the active area beyond the gate, and fitting parameters.

[0088] Optionally, the reverse current determination module can be specifically used to: obtain the voltage across the source-body junction, the voltage across the drain-body junction, the width of the field-effect transistor device, the width of the active area beyond the gate, fitting parameters and temperature parameters, where the temperature parameters include at least two; and calculate the source-body junction reverse current and the drain-body junction reverse current based on the temperature parameters, the voltage across the source-body junction, the voltage across the drain-body junction, the width of the field-effect transistor device, the width of the active area beyond the gate and the fitting parameters.

[0089] The device provided in the embodiments of the present application can be used to execute the method in the embodiments shown above. Its implementation principle and technical effects are similar and will not be repeated here.

[0090] It should be noted that it should be understood that the division of the various modules of the above device is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. And these modules can all be implemented in the form of software called by processing elements; they can also all be implemented in the form of hardware; some modules can also be implemented in the form of software called by processing elements, and some modules can be implemented in the form of hardware. For example, the reverse current determination module can be a separately established processing element, or it can be integrated into a chip of the above device. In addition, it can also be stored in the memory of the above device in the form of program code, and called and executed by a processing element of the above device to perform the function of the above reverse current determination module. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each module above can be completed by the hardware integrated logic circuit in the processor element or the instructions in the form of software.

[0091] Figure 10 This is a schematic diagram of the structure of the computer device provided in the embodiment of the present application. Figure 10 As shown, the computer device 1000 includes: at least one processor 1010, a memory 1020, a bus 1030 and a communication interface 1040. The processor 1010, the communication interface 1040 and the memory 1020 communicate with each other via the bus 1030. The communication interface is used to communicate with other devices. The communication interface includes a communication interface for data transmission. The processor 1010 is used to execute computer-executable instructions stored in the memory, and specifically can execute the relevant steps of the method described in the above embodiment. The processor may be a central processing unit, or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The one or more processors included in the computer device may be processors of the same type, such as one or more CPUs; or they may be processors of different types, such as one or more CPUs and one or more ASICs. The memory is used to store computer-executable instructions. The memory may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage.

[0092] This embodiment also provides a computer-readable storage medium, which stores computer instructions. When at least one processor of a computer device executes the computer instructions, the computer device executes the method for generating a field effect transistor device model provided by the various embodiments described above.

[0093] This embodiment further provides a computer program product, comprising computer instructions stored in a readable storage medium. At least one processor of a computer device can read the computer instructions from the readable storage medium, and the at least one processor can execute the computer instructions to cause the computer device to implement the methods for generating field-effect transistor device models provided in the various embodiments described above.

[0094] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship; in the formula, the character " / " indicates that the previous and next associated objects are in a "division" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0095] It is understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not intended to limit the scope of the embodiments of the present application. In the embodiments of the present application, the order of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for generating a field effect transistor device model, characterized in that: include: Determining a source-body junction reverse current and a drain-body junction reverse current of a field effect transistor device, wherein the source-body junction reverse current is a current from the body terminal of the field effect transistor device to the source, and the drain-body junction reverse current is a current from the body terminal of the field effect transistor device to the drain; Constructing a sub-circuit model according to the source-body junction reverse current and the drain-body junction reverse current; Constructing a target field effect transistor device model according to a preset initial field effect transistor device model and the sub-circuit model; The following steps are also included: Determining a source-body junction forward current and a drain-body junction forward current of a field effect transistor device, wherein the source-body junction forward current is a current flowing from the source of the field effect transistor device to the body terminal, and the drain-body junction forward current is a current flowing from the drain of the field effect transistor device to the body terminal; The preset initial field effect transistor device model is constructed based on the source-body junction forward current and the drain-body junction forward current.

2. The method according to claim 1, characterized in that The determining of the source-body junction reverse current and the drain-body junction reverse current of the field effect transistor device includes: Obtain the voltage across the source-body junction, the voltage across the drain-body junction, the width of the field-effect transistor device, the width of the active region beyond the gate, and fitting parameters; The source-body junction reverse current and the drain-body junction reverse current are calculated based on the voltage across the source-body junction, the voltage across the drain-body junction, the field effect transistor device width, the width of the active region beyond the gate, and the fitting parameters.

3. The method according to claim 1, characterized in that The determining of the source-body junction reverse current and the drain-body junction reverse current of the field effect transistor device includes: Obtaining a voltage across a source-body junction, a voltage across a drain-body junction, a width of a field-effect transistor device, a width of an active region extending beyond a gate, a fitting parameter, and a temperature parameter, wherein the temperature parameter includes at least two; The source-body junction reverse current and the drain-body junction reverse current are calculated based on the temperature parameters, the voltage across the source-body junction, the voltage across the drain-body junction, the field effect transistor device width, the width of the active region beyond the gate, and the fitting parameters.

4. The method according to claim 1, wherein The determining of the source-body junction forward current and the drain-body junction forward current of the field effect transistor device includes: Connecting at least two field effect transistors in parallel, and grounding the gate, source, and drain of the parallel field effect transistors; Performing voltage scanning on the body terminals of the parallel-connected field effect transistor devices to read current changes at the source and drain terminals of the parallel-connected field effect transistor devices, where the body terminals of the field effect transistor devices are substrate terminals; The source-body junction forward current and the drain-body junction forward current are determined according to current changes of the source and drain of the parallel-connected field effect transistor devices and the number of the parallel-connected field effect transistor devices.

5. The method according to claim 1, characterized in that The determining of the source-body junction forward current and the drain-body junction forward current of the field effect transistor device includes: Grounding the gate, source and drain of the field effect transistor device; Performing a voltage scan on the body terminal of the field effect transistor device and reading current changes of the source and drain of the field effect transistor device, where the body terminal of the field effect transistor device is the substrate terminal; The source-body junction forward current and the drain-body junction forward current are determined according to the current changes of the source and the drain.

6. The method according to claim 4 or 5, characterized in that Determine the source-body junction forward current, including: Obtaining a first current per unit area, a side current per unit length along a gate edge, a side current along a shallow trench isolation edge, a source terminal area, a perimeter of the source terminal along a shallow trench isolation edge, a field effect transistor device width, and the number of field effect transistor devices connected in parallel; The source-body junction forward current is calculated based on the first current per unit area, the side current per unit length along the gate edge, the side current along the shallow trench isolation edge, the source terminal area, the perimeter of the source terminal along the shallow trench isolation edge, the field effect transistor device width, and the number of field effect transistor devices connected in parallel; Determine the drain-body junction forward current, including: Obtaining a second current per unit area, an area of ​​the drain terminal, and a perimeter of the drain terminal along an edge of the shallow trench isolation; The drain-body junction forward current is calculated based on the second current per unit area, the side current per unit length along the gate edge, the side current along the shallow trench isolation edge, the drain end area, the perimeter of the drain end along the shallow trench isolation edge, the field effect transistor device width and the number of field effect transistor devices in parallel.

7. A device for generating a field effect transistor device model, characterized in that: include: a reverse current determination module, configured to determine a source-body junction reverse current and a drain-body junction reverse current of a field effect transistor device, wherein the source-body junction reverse current is the current from the body terminal of the field effect transistor device to the source, and the drain-body junction reverse current is the current from the body terminal of the field effect transistor device to the drain; A sub-model construction module, configured to construct a sub-circuit model according to the source-body junction reverse current and the drain-body junction reverse current; A device model construction module, configured to construct a target field effect transistor device model based on a preset initial field effect transistor device model and the sub-circuit model; Among them, the device model construction module is also used to: Determining a source-body junction forward current and a drain-body junction forward current of a field effect transistor device, wherein the source-body junction forward current is a current flowing from the source of the field effect transistor device to the body terminal, and the drain-body junction forward current is a current flowing from the drain of the field effect transistor device to the body terminal; The preset initial field effect transistor device model is constructed based on the source-body junction forward current and the drain-body junction forward current.

8. A computer device, characterized in that: include: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product comprising computer instructions, characterized in that When the computer instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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