Mapping method and device of time sequence neural network, accelerator

Abstract

The disclosure provides a mapping method and device of a time sequence neural network, and an accelerator, the time sequence neural network comprising a processing unit, the processing unit being configured to sequentially execute a calculation task of each time step corresponding to an input sequence, the mapping method comprising: dividing a plurality of processing cores in a many-core chip into a plurality of execution core clusters, each execution core cluster comprising a plurality of processing cores; dividing the plurality of processing cores in each execution core cluster into a plurality of core groups, each core group comprising at least one processing core; mapping a plurality of time sequence neural networks to the plurality of execution core clusters respectively, each execution core cluster being configured to independently run a corresponding time sequence neural network, and each core group in the execution core cluster being configured to deploy a processing unit; and for each execution core cluster, configuring the plurality of core groups in the execution core cluster to execute, in a cyclic pipeline manner, the calculation task of a plurality of time steps of the mapped time sequence neural network corresponding to the input sequence. The disclosure also provides an electronic device and a computer readable storage medium.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a mapping method and apparatus for a temporal neural network, a temporal neural network accelerator, an electronic device, and a computer-readable storage medium. Background Technology

[0002] With the application of neural networks across various industries, accelerating their execution has become a crucial issue. Many-core chips represent a key architectural direction for accelerating neural networks, including the acceleration of temporal neural networks. Summary of the Invention

[0003] This disclosure provides a mapping method and apparatus for temporal neural networks, a temporal neural network accelerator, an electronic device, and a computer-readable storage medium.

[0004] In a first aspect, this disclosure provides a mapping method for a temporal neural network, the temporal neural network including a processing unit, the processing unit being configured to sequentially execute computational tasks corresponding to each time step of an input sequence, the mapping method including:

[0005] The multiple processing cores in the many-core chip are divided into multiple execution core clusters, and the execution core clusters include multiple processing cores;

[0006] The execution core cluster is divided into multiple core groups, and each core group includes at least one processing core.

[0007] Multiple temporal neural networks are respectively mapped to multiple execution kernel clusters, each execution kernel cluster is configured to independently run a corresponding temporal neural network, and each kernel group in the execution kernel cluster is deployed with a corresponding processing unit;

[0008] For each execution kernel cluster, multiple kernel groups within the execution kernel cluster are configured to perform computational tasks corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner.

[0009] Secondly, this disclosure provides a mapping device for a temporal neural network, the temporal neural network including a processing unit, the processing unit being configured to sequentially execute the computation task corresponding to each time step of the input sequence, the mapping device including:

[0010] A partitioning unit is used to: divide multiple processing cores in a many-core chip into multiple execution core clusters, wherein each execution core cluster includes multiple processing cores; and divide the multiple processing cores in each execution core cluster into multiple core groups, wherein each core group includes at least one processing core.

[0011] The mapping unit is used to: map multiple temporal neural networks to multiple execution kernel clusters, each execution kernel cluster being configured to independently run a corresponding temporal neural network, and each kernel group in the execution kernel cluster being deployed with a corresponding processing unit; for each execution kernel cluster, the multiple kernel groups in the execution kernel cluster are configured to execute the computation tasks of multiple time steps corresponding to the input sequence of the mapped temporal neural network in a cyclic pipeline manner.

[0012] Thirdly, this disclosure provides a temporal neural network accelerator, the temporal neural network including a processing unit, the processing unit being configured to sequentially execute computational tasks corresponding to each time step of the input sequence, the accelerator including:

[0013] A many-core chip includes multiple execution core clusters, each execution core cluster including multiple processing cores. The multiple processing cores in the execution core cluster are divided into multiple core groups, each core group including at least one processing core. Each execution core cluster is configured to independently run a corresponding temporal neural network. Each core group in the execution core cluster is deployed with one processing unit. The multiple core groups in the execution core cluster are configured to execute computation tasks corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner.

[0014] A time-space determiner is used to configure the input time and corresponding kernel group of the current input sequence of the temporal neural network.

[0015] Fourthly, this disclosure provides an electronic device comprising:

[0016] At least one processor; and

[0017] A memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores one or more computer programs that can be executed by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the mapping method described in the first aspect above.

[0019] Fifthly, this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the mapping method described in the first aspect.

[0020] According to the technical solution of the mapping method for temporal neural networks in this disclosure, multiple temporal neural networks are mapped to multiple execution core clusters by dividing the multiple processing cores of a many-core chip into execution core clusters. This allows multiple execution core clusters to execute multiple input sequences of the temporal neural network in parallel, thereby accelerating the execution of the temporal neural network, improving the processing efficiency of the input sequences, and improving the computational efficiency of the temporal neural network. Simultaneously, for each execution core cluster, by dividing it into core groups, each core group deploys a processing unit of the temporal neural network. Multiple core groups are configured to execute the computational tasks corresponding to multiple time steps of the mapped temporal neural network's input sequence in a cyclic pipeline manner. At each time step, only... The core group executing the computation task at the current time step needs to read the required input data from off-chip. After each time step, only the core group executing the computation task at the current time step and the core group executing the computation task at the next time step need to interact with each other. Therefore, it helps to reduce on-chip and off-chip data interaction, reduce the load on on-chip storage resources, and reduce the data transmission cost of on-chip network NoC. In addition, mapping the temporal neural network to an execution core cluster composed of multiple processing cores allows the weight parameters of the temporal neural network to be distributed and stored in multiple processing cores of the execution core cluster, without having to store the weight parameters separately in a single processing core. This helps to improve the load balancing of on-chip storage resources for each processing core and reduce the transmission cost of weight parameters.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0023] Figure 1 This is a schematic diagram of a temporal neural network architecture provided in an embodiment of the present disclosure;

[0024] Figure 2 A schematic diagram of the architecture of a many-core chip provided in an embodiment of this disclosure;

[0025] Figure 3 A flowchart illustrating a mapping method for a temporal neural network provided in an embodiment of this disclosure;

[0026] Figure 4 This is a schematic diagram illustrating an execution kernel cluster and a kernel group division method within the execution kernel cluster, provided by an embodiment of this disclosure.

[0027] Figure 5 This is a schematic diagram illustrating the pipelined execution sequence of multiple execution core groups within an execution core cluster.

[0028] Figure 6 This is a schematic diagram showing the arrangement of communication cores and non-communication cores in a many-core chip.

[0029] Figure 7 A schematic diagram of the structure of a mapping device for a temporal neural network provided in an embodiment of this disclosure;

[0030] Figure 8 This is a schematic diagram of the structure of a temporal neural network accelerator provided in an embodiment of the present disclosure;

[0031] Figure 9 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0033] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0034] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0036] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0037] In this embodiment, temporal neural networks, represented by RNNs (Recurrent Neural Networks), are commonly used to process sequential data problems, such as text classification, speech recognition, and text translation. These networks have one or more basic processing units composed of multiple neurons. Common processing units include LSTM (Long Short-Term Memory) units and GRU (Gate Recurrent Unit) units. The processing units are used cyclically in the time dimension. At each time step, a processing unit obtains one input data point from the corresponding input sequence and the intermediate result obtained from the previous time step. The intermediate result obtained at the current time step then becomes one of the input data points for the processing unit at the next time step, ultimately completing the computation for a certain number of time steps on the same processing unit. Therefore, temporal neural networks can be represented by expanding them into time steps, such as... Figure 1 As shown, a processing unit shares a set of weight parameters at different time steps, and the processing unit processes different input data in the input sequence at different time steps.

[0038] In this embodiment, the many-core chip consists of multiple processing cores and a NoC (Network-on-Chip) between them. The many-core chip is based on a memory-in-memory many-core architecture, where each processing core has independent on-chip memory, such as... Figure 2 As shown, the processing cores are responsible for performing the main computations, while the NoCs are responsible for transferring data between the processing cores. The arrangement and implementation of the processing cores and NoCs can take many forms. Figure 2 This is merely an example illustrating one arrangement of processing cores and NoC in a many-core chip.

[0039] Figure 3 This is a flowchart illustrating a mapping method for a temporal neural network provided in an embodiment of this disclosure.

[0040] This disclosure provides a mapping method for a temporal neural network. The temporal neural network includes a processing unit, which sequentially executes the computation task corresponding to each time step of the input sequence, such as... Figure 3 As shown, the mapping method includes:

[0041] Step S1: Divide the multiple processing cores in the many-core chip into multiple execution core clusters, and each execution core cluster includes multiple processing cores.

[0042] In some embodiments, different execution core clusters may have different numbers of processing cores, meaning different execution core clusters may have different processing rates; in other embodiments, different execution core clusters may contain the same number of processing cores. This disclosure does not impose special limitations on the number of execution core clusters or the number of processing cores within each cluster, and configurations can be made according to actual needs.

[0043] Step S2: Divide the multiple processing cores in the execution core cluster into multiple core groups, and each core group includes at least one processing core.

[0044] In some embodiments, different core groups may have different numbers of processing cores, meaning different execution core groups may have different processing rates; in some embodiments, different core groups may contain the same number of processing cores. This disclosure does not impose special limitations on the number of core groups or the number of processing cores within a core group, and configuration can be made according to actual needs.

[0045] Figure 4 This is a schematic diagram illustrating an execution kernel cluster and a kernel group partitioning method within an execution kernel cluster, provided by an embodiment of this disclosure. For example, Figure 4 As shown, the multiple processing cores C in the many-core chip are divided into 4 execution core clusters, namely execution core cluster 01, execution core cluster 02, execution core cluster 03 and execution core cluster 04. Taking execution core cluster 01 as an example, the multiple processing cores C in execution core cluster 01 are divided into 3 core groups, namely core group 011, core group 012 and core group 013.

[0046] Step S3: Map multiple temporal neural networks to multiple execution kernel clusters respectively. Each execution kernel cluster is configured to run a corresponding temporal neural network independently. Each kernel group in the execution kernel cluster is deployed with a corresponding processing unit.

[0047] In some embodiments, a temporal neural network to be mapped can be replicated into multiple copies. These multiple temporal neural networks can be used to process different input sequences of the same data processing task. These multiple temporal neural networks are mapped to multiple execution kernel clusters, with each execution kernel cluster deploying one temporal neural network. The multiple execution kernel clusters can run their respective temporal neural networks independently and in parallel. For each execution kernel cluster, each kernel group within that cluster deploys a corresponding processing unit of the temporal neural network. For example, the data processing task can be any of the following: text processing tasks (such as text classification, text translation, etc.), speech processing tasks (such as speech recognition, etc.), and video image processing tasks (such as video image recognition, etc.). Correspondingly, the input sequence can be any of the following: text input sequence, speech input sequence, and video image input sequence.

[0048] In some embodiments, the number of temporal neural networks to be mapped is multiple, and these multiple temporal neural networks are different temporal neural networks. Each of these multiple temporal neural networks is applied to process a data processing task. Different temporal neural networks correspond to different data processing tasks. For example, different data processing tasks include text processing tasks, speech processing tasks, video image processing tasks, etc. The multiple temporal neural networks are mapped to multiple execution kernel clusters, and each execution kernel cluster deploys one of the temporal neural networks. The multiple execution kernel clusters can run their respective temporal neural networks independently and in parallel. For each execution kernel cluster, each kernel group in the execution kernel cluster deploys the processing unit of the corresponding temporal neural network.

[0049] For example, the multiple temporal neural networks are temporal neural network N1, temporal neural network N2, temporal neural network N3, and temporal neural network N4, combined with Figure 4 The temporal neural network N1 is mapped to the execution kernel cluster 01. Each kernel group (011, 012, 013) in the execution kernel cluster 01 is assigned a processing unit of the temporal neural network N1. The temporal neural network N2 is mapped to the execution kernel cluster 02. Each kernel group in the execution kernel cluster 02 is assigned a processing unit of the temporal neural network N2. The temporal neural network N3 is mapped to the execution kernel cluster 03. Each kernel group in the execution kernel cluster 03 is assigned a processing unit of the temporal neural network N3. The temporal neural network N4 is mapped to the execution kernel cluster 04. Each kernel group in the execution kernel cluster 04 is assigned a processing unit of the temporal neural network N4.

[0050] For each core group, when the core group includes multiple processing cores, the processing units can be split and evenly deployed to each processing core of the core group.

[0051] Step S4: For each execution kernel cluster, configure multiple kernel groups in the execution kernel cluster to perform computation tasks corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner.

[0052] Combination Figure 1 A temporal neural network requires processing an input sequence through multiple time steps, meaning the input sequence is divided into multiple time steps for processing. Each time step corresponds to a computational task, and each computational task corresponds to processing one input data in the input sequence. In one time step, the processing unit of the temporal neural network can process one input data in the input sequence and obtain the corresponding output data.

[0053] Taking a recurrent neural network (RNN) as an example, the processing unit executes the current computational task corresponding to the current time step at the current time step. This involves processing the current input data corresponding to the current time step in the input sequence to obtain the current output data. The current output data obtained by the processing unit at the current time step, along with the next input data corresponding to the next time step in the input sequence, together serve as the input data required for the processing unit to execute the next computational task at the next time step. For example, as shown... Figure 1 As shown, the current input sequence consists of four input data points: input data 1, input data 2, input data 3, and input data 4. Correspondingly, the current input sequence needs to be processed through four time steps. In time step 1, the processing unit processes input data 1 to obtain output data 1. Output data 1 and input data 2 together serve as the input data for the processing unit in time step 2. In time step 2, the processing unit processes input data 2 and output data 1 to obtain output data 2. Output data 2 and input data 3 together serve as the input data for the processing unit in time step 3. In time step 3, the processing unit processes input data 3 and output data 2 to obtain output data 3. Output data 3 and input data 4 together serve as the input data for the processing unit in time step 4. In time step 4, the processing unit processes input data 4 and output data 3 to obtain output data 4.

[0054] In this embodiment of the disclosure, for each execution core cluster, each core group within the cluster deploys a corresponding processing unit of a temporal neural network. Therefore, each core group can execute a computation task corresponding to one time step of the input sequence. Different core groups handle computation tasks at different time steps. Multiple core groups within the execution core cluster can execute computation tasks at multiple time steps corresponding to the input sequence of the mapped temporal neural network in a cyclic pipeline manner. For each core group, when the core group includes multiple processing cores, the multiple processing cores of the core group jointly and in parallel execute the computation task at the corresponding time step.

[0055] For example, an execution kernel cluster includes 3 kernel groups. An input sequence needs to be processed through 4 time steps. The 3 kernel groups execute the computation tasks corresponding to the 4 time steps of the input sequence in a cyclic pipeline manner until the computation tasks corresponding to all time steps of the input sequence are completed. Among them, the first kernel group executes the computation task of time step 1, the second kernel group executes the computation task of time step 2, the third kernel group executes the computation task of time step 3, and the first kernel group executes the computation task of time step 4.

[0056] For example, an execution kernel cluster includes 5 kernel groups. An input sequence needs to be processed through 4 time steps. The 5 kernel groups execute the computation tasks corresponding to the 4 time steps of the input sequence in a cyclic pipeline manner until the computation tasks corresponding to all time steps of the input sequence are completed. Among them, the first kernel group executes the computation task of time step 1, the second kernel group executes the computation task of time step 2, the third kernel group executes the computation task of time step 3, and the fourth kernel group executes the computation task of time step 4.

[0057] According to the technical solution of the mapping method for temporal neural networks in this disclosure, multiple temporal neural networks are mapped to multiple execution core clusters by dividing the multiple processing cores of a many-core chip into execution core clusters. This allows the multiple execution core clusters to execute multiple input sequences of the temporal neural network in parallel, thereby accelerating the execution of the temporal neural network, improving the processing efficiency of the input sequences, and improving the computational efficiency of the temporal neural network. Simultaneously, for each execution core cluster, by dividing it into core groups, each core group deploys a processing unit of the temporal neural network. The multiple core groups are configured to execute the computation tasks corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner. At each time step, only the current time step is executed. The kernel group for the computation task in each time step needs to read the required input data and output related computation data from off-chip. After each time step, only the kernel group executing the computation task of the current time step and the kernel group executing the computation task of the next time step need to interact with each other. Therefore, it is beneficial to reduce on-chip and off-chip data interaction, reduce the load on on-chip storage resources, and reduce the data transmission cost of on-chip network NoC. In addition, mapping the temporal neural network to an execution kernel cluster composed of multiple processing kernels allows the weight parameters of the temporal neural network to be distributed and stored in multiple processing kernels of the execution kernel cluster, without having to store the weight parameters separately in a single processing kernel. This is beneficial to improve the load balancing of on-chip storage resources for each processing kernel and reduce the transmission cost of weight parameters.

[0058] In some embodiments, in step S4, before configuring multiple kernel groups in the execution kernel cluster to execute the computation tasks corresponding to multiple time steps of the mapped temporal neural network input sequence in a cyclic pipeline manner, the mapping method further includes: planning the pipeline execution order corresponding to each kernel group in the multiple kernel groups of the execution kernel cluster. The pipeline execution order represents the positional order and job order of the corresponding kernel groups in the cyclic pipeline. Multiple kernel groups in the execution kernel cluster can perform cyclic pipeline operations according to the pipeline execution order for the current input sequence, thereby executing the computation tasks corresponding to multiple time steps of the current input sequence in a cyclic pipeline manner. Figure 5 This is a schematic diagram illustrating the pipelined execution sequence of multiple execution core groups within an execution core cluster, exemplarily, combined with... Figure 4 and Figure 5 The pipeline execution order corresponding to core group 011 in kernel cluster 01 is bit 1, the pipeline execution order corresponding to core group 012 is bit 2, and the pipeline execution order corresponding to core group 013 is bit 3.

[0059] In some embodiments, in step S4, configuring multiple kernel groups in the execution kernel cluster to execute the computation task of multiple time steps corresponding to the input sequence of the mapped temporal neural network in a cyclic pipeline manner includes: configuring multiple kernel groups to execute the computation task of multiple time steps corresponding to the input sequence of the mapped temporal neural network in a cyclic pipeline manner according to the pipeline execution order corresponding to each kernel group in the multiple kernel groups.

[0060] In this context, the kernel group located at the Kth position in the pipeline execution order of multiple kernel groups within the kernel cluster is configured to execute the computation task corresponding to the Lth time step of the input sequence, where L = n * m + K, n is the current loop order, m is the number of kernel groups in the multiple kernel groups within the kernel cluster, K is an integer greater than or equal to 1, the number of time steps corresponding to the input sequence is T, n is a non-negative integer less than or equal to N-1, and N is the total number of loops. When T is greater than m and T is an integer multiple of m, N = T / m; when T is greater than m and T is a non-integer multiple of m, N = [T / m] + 1, where [T / m] represents the floor function; when T is less than or equal to m, N = 1.

[0061] For example, with Figure 4 Taking kernel cluster 01 as an example, kernel cluster 01 includes kernel group 011, kernel group 012, and kernel group 013, for a total of m = 3 kernel groups. The pipeline execution order of multiple kernel groups in kernel cluster 01 is as follows: Figure 5As shown, assuming the number of time steps corresponding to the current input sequence is T = 6, the total number of loops is N = 6 / 3 = 2. In the n = 0th loop, the kernel group 011, which is located in the first position in the pipeline execution order, is configured to execute the calculation task of the first time step corresponding to the input sequence, the kernel group 012, which is located in the second position, is configured to execute the calculation task of the second time step corresponding to the input sequence, and the kernel group 013, which is located in the third position, is configured to execute the calculation task of the third time step corresponding to the input sequence. In the n = 1st loop, the kernel group 011, which is located in the first position, is configured to execute the calculation task of the fourth time step corresponding to the input sequence, the kernel group 012, which is located in the second position, is configured to execute the calculation task of the fifth time step corresponding to the input sequence, and the kernel group 013, which is located in the third position, is configured to execute the calculation task of the sixth time step corresponding to the input sequence. At this point, the calculation tasks of all time steps corresponding to the input sequence have been completed.

[0062] For example, with Figure 4 Taking kernel cluster 01 as an example, kernel cluster 01 includes kernel group 011, kernel group 012, and kernel group 013, for a total of m = 3 kernel groups. The pipeline execution order of multiple kernel groups in kernel cluster 01 is as follows: Figure 5 As shown, assuming the number of time steps corresponding to the current input sequence is T = 4, the total number of loops is N = [4 / 3] + 1 = 2. In the n = 0th loop, the kernel group 011, which is located in the first position in the pipeline execution order, is configured to execute the calculation task of the first time step corresponding to the input sequence, the kernel group 012, which is located in the second position, is configured to execute the calculation task of the second time step corresponding to the input sequence, and the kernel group 013, which is located in the third position, is configured to execute the calculation task of the third time step corresponding to the input sequence. In the n = 1st loop, the kernel group 011, which is located in the first position, is configured to execute the calculation task of the fourth time step corresponding to the input sequence. At this point, the calculation tasks of all time steps corresponding to the input sequence have been completed.

[0063] For example, with Figure 4 Taking kernel cluster 01 as an example, kernel cluster 01 includes kernel group 011, kernel group 012, and kernel group 013, for a total of m = 3 kernel groups. The pipeline execution order of multiple kernel groups in kernel cluster 01 is as follows: Figure 5 As shown, assuming the number of time steps corresponding to the current input sequence is T=2, the total number of loops is N=1. In the n=0th loop, the core group 011, which is located in the first position in the pipeline execution order, is configured to execute the calculation task of the first time step corresponding to the input sequence, and the core group 012, which is located in the second position, is configured to execute the calculation task of the second time step corresponding to the input sequence. At this point, the calculation tasks of all time steps corresponding to the input sequence have been completed.

[0064] In some embodiments, the kernel group located at the Kth position in the pipeline execution order of the multiple kernel groups in the kernel cluster is further configured to execute the computation task of the (L+1)th time step corresponding to the current input sequence while the kernel group located at the K+1th position executes the computation task of the Lth time step corresponding to the next input sequence.

[0065] For example, with Figure 4 Taking kernel cluster 01 as an example, after kernel cluster 011 completes the calculation task for the first time step corresponding to the current input sequence and transmits the output data to kernel cluster 012, kernel cluster 012 executes the calculation task for the second time step of the current input sequence. Simultaneously, kernel cluster 011 begins executing the calculation task for the first time step corresponding to the next input sequence. Then, after kernel cluster 012 completes the calculation task for the second time step of the current input sequence and transmits the output data to kernel cluster 013, kernel cluster 013 executes the calculation task for the third time step of the current input sequence. Simultaneously, kernel cluster 012 begins executing the calculation task for the second time step corresponding to the next input sequence. If kernel cluster 011 has also completed the calculation task for the second time step corresponding to the next input sequence... The first time step computation task is completed and the output data is transmitted to kernel group 012. Then kernel group 011 can continue to execute the first time step computation task corresponding to the next input sequence. And so on. After a kernel group completes the computation task of one time step for an input sequence, it can then execute the computation task of one time step for the next input sequence. The next input sequence does not need to wait for the current input sequence to be processed before it is executed. Instead, it is processed in parallel pipeline with the current input sequence in the above manner. This can effectively improve the processing efficiency of the input sequence, improve the computational efficiency of the temporal neural network on the mapped execution kernel cluster, improve the utilization efficiency of kernel group resources in the execution kernel cluster, and realize the accelerated execution of the temporal neural network.

[0066] In some embodiments, the length of the input sequence of a temporal neural network is usually not equal to the length of the loop pipeline. The length of the input sequence can be determined according to the number of time steps corresponding to the input sequence, and the length of the loop pipeline can be determined according to the number of kernel groups in the execution kernel cluster. When the computation of an input sequence ends, there are often remaining idle kernel groups in the loop pipeline. Therefore, in order to improve the utilization efficiency of kernel group resources in the execution kernel cluster and improve the computational load balancing of kernel group resources, in some embodiments, when the number of time steps T corresponding to the current input sequence is less than the number of kernel groups m in the multiple kernel groups in the execution kernel cluster, after the kernel group at position T in the pipeline execution order completes the computation task of the Tth time step corresponding to the current input sequence, starting from the kernel group at position T+1, the multiple kernel groups in the execution kernel cluster execute the computation task of the multiple time steps corresponding to the next input sequence based on the loop pipeline method.

[0067] For example, with Figure 4 Taking kernel cluster 01 as an example, kernel cluster 01 includes kernel group 011, kernel group 012, and kernel group 013, for a total of m = 3 kernel groups. The pipeline execution order of multiple kernel groups in kernel cluster 01 is as follows: Figure 5 As shown, assuming the number of time steps corresponding to the current input sequence is T=2, then core group 011 is configured to execute the computation task of the first time step corresponding to the current input sequence, and core group 012 is configured to execute the computation task of the second time step corresponding to the current input sequence. In the cyclic pipeline, there is a remaining idle core group 013. After the core group 012, which is the second in the pipeline execution order, completes the computation task of the second time step corresponding to the current input sequence, starting from the third core group 013, multiple core groups 013, 011, and 012 in the core cluster execute the computation tasks of multiple time steps corresponding to the next input sequence based on the cyclic pipeline method.

[0068] To further optimize the processing efficiency of input sequences, improve the computational efficiency of temporal neural networks, and accelerate their execution, in some embodiments, when the number of time steps T corresponding to the current input sequence is less than the number of kernel groups m in the execution kernel cluster, while the kernel group at position 1 in the pipeline execution order executes the computation task for the first time step of the current input sequence, starting from the (T+1)th kernel group, multiple kernel groups in the execution kernel cluster execute the computation tasks for the next input sequence's multiple time steps in a cyclic pipeline manner. That is, when the number of time steps T corresponding to the current input sequence is less than the number of kernel groups m in the execution kernel cluster, the current input sequence and the next input sequence can be executed in parallel. The next input sequence does not need to wait for the current input sequence to finish processing before execution, thereby optimizing the processing efficiency of the input sequence, improving the computational efficiency of the temporal neural network, reducing computational latency, and accelerating the execution of the temporal neural network.

[0069] In some embodiments, multiple processing cores in a many-core chip can be divided into communication cores and non-communication cores according to their communication relationships with off-chip devices. Figure 6 This is a schematic diagram showing the arrangement of communication cores and non-communication cores in a many-core chip, as shown below. Figure 6As shown, a many-core chip architecture is generally a many-core computing architecture deployed on a two-dimensional plane. Typically, processing cores located at the chip's edge are used for data communication with external devices; these are defined as communication cores, while other processing cores are non-communication cores. Communication cores still possess computational capabilities. In other words, communication cores are processing cores used for data communication with external devices, while non-communication cores are those not used for such communication. External devices are located outside the many-core chip and are used to provide the many-core chip with the data (such as input data and parameters) required for executing the computational tasks of temporal neural networks. It should be noted that... Figure 6 The three arrangements of communication cores and non-communication cores are shown only as examples. The embodiments of this disclosure include, but are not limited to, these three scenarios.

[0070] In some embodiments, in step S1, the partitioning of execution core clusters may preferentially follow the following principles: multiple processing cores in an execution core cluster are interconnected in the on-chip network of the many-core chip; the multiple processing cores in an execution core cluster include at least one communication core, or the multiple processing cores in an execution core cluster include at least one non-communication core that is adjacent to any communication core. Here, "adjacent" means that they are adjacent in communication location on the on-chip network or the communication distance is less than a distance threshold; communication location refers to the routing location of the processing core in the on-chip network; and communication distance refers to the distance between communication locations.

[0071] Since the execution core cluster contains at least one communication core, or at least one non-communication core adjacent to any communication core, when performing computational tasks of a temporal neural network, the core group in the execution core cluster can directly communicate with external devices for input and output data through the communication core, or communicate with external devices for input and output data through the non-communication core adjacent to the communication core. This can help reduce the overall data transmission cost of the chip.

[0072] In some embodiments, in the step of planning the pipeline execution order corresponding to a core group, the planning of the pipeline execution order of the core group may preferentially follow the following principles: the core group whose pipeline execution order is located at the Kth position and the core group whose pipeline execution order is located at the K+1th position are adjacent in the routing position of the on-chip network of the many-core chip; and, based on the order of the time steps corresponding to the computation tasks where the amount of input and output data exceeds the threshold, the pipeline execution order of the core group containing at least one communication core or at least one non-communication core adjacent to any communication core is determined.

[0073] On the one hand, for two core groups with adjacent pipeline execution sequences, after the core group with the earlier pipeline execution sequence completes the computation task corresponding to the current time step, it usually needs to pass the output data to the core group with the later pipeline execution sequence. Since the two core groups are adjacent in the routing position of the on-chip network, that is, the communication distance between the two core groups is relatively short, it is beneficial to improve the data transmission efficiency between the two core groups and reduce the overall data transmission cost of the chip.

[0074] On the other hand, the time steps corresponding to the input sequence of a temporal neural network are sequential. For a time step with a large amount of input and output data, the pipeline execution order of the core group is determined according to the order of the time step among all the time steps corresponding to the input sequence. The computation task corresponding to the time step is deployed to a core group that includes a communication core or a non-communication core adjacent to the communication core. In this way, when the core group executes the computation task corresponding to the time step, it can directly transmit input and output data with external devices through its own communication core, or communicate with the communication core through a non-communication core adjacent to the communication core, so as to transmit input and output data with external devices through the communication core. This can help reduce the overall data transmission cost of the chip.

[0075] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0076] In addition, this disclosure also provides a mapping device, electronic device, and computer-readable storage medium for a temporal neural network. The above-mentioned mapping device, electronic device, and computer-readable storage medium can all be used to implement the mapping method provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding descriptions in the method section, and will not be repeated here.

[0077] Figure 7 This is a schematic diagram of the structure of a mapping device for a temporal neural network provided in an embodiment of the present disclosure.

[0078] like Figure 7 As shown, this disclosure also provides a mapping device 200 for a temporal neural network. The temporal neural network includes a processing unit, which is used to sequentially execute the computation task corresponding to each time step of the input sequence. The device 200 includes:

[0079] The partitioning unit 201 is used to: divide multiple processing cores in the many-core chip into multiple execution core clusters, each execution core cluster including multiple processing cores; and divide multiple processing cores in the execution core clusters into multiple core groups, each core group including at least one processing core.

[0080] The mapping unit 202 is used to: map multiple temporal neural networks to multiple execution kernel clusters respectively, each execution kernel cluster is configured to run a corresponding temporal neural network independently, and each kernel group in the execution kernel cluster is deployed with a corresponding processing unit; for each execution kernel cluster, the multiple kernel groups in the execution kernel cluster are configured to execute the computation tasks of multiple time steps corresponding to the input sequence of the mapped temporal neural network in a cyclic pipeline manner.

[0081] In some embodiments, the mapping unit 202 is further configured to plan the pipeline execution order corresponding to each kernel group in the plurality of kernel groups in the execution kernel cluster. In some embodiments, configuring the plurality of kernel groups in the execution kernel cluster to execute the computation task corresponding to the multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner includes: configuring the plurality of kernel groups to execute the computation task corresponding to the multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner according to the pipeline execution order corresponding to each kernel group in the plurality of kernel groups.

[0082] Specifically, the kernel group whose pipeline execution order is located at position K in the plurality of kernel groups is configured to execute the computation task corresponding to the Lth time step of the input sequence, where L = n*m + K, n is the current loop order, m is the number of kernel groups in the plurality of kernel groups, K is an integer greater than or equal to 1, the number of time steps corresponding to the input sequence is T, n is a non-negative integer and n is less than or equal to N-1, and N is the total number of loops; when T is greater than m and T is an integer multiple of m, N = T / m; when T is greater than m and T is a non-integer multiple of m, N = [T / m] + 1; when T is less than or equal to m, N = 1.

[0083] In some embodiments, the kernel group located at the Kth position in the pipeline execution order of the plurality of kernel groups is further configured to execute the computation task of the L+1th time step corresponding to the current input sequence while the kernel group located at the K+1th position executes the computation task of the Lth time step corresponding to the next input sequence.

[0084] In some embodiments, when the number of time steps T corresponding to the current input sequence is less than the number of core groups m among the multiple core groups, after the core group located at the Tth position in the pipeline execution order completes the computation task of the Tth time step corresponding to the current input sequence, starting from the (T+1)th position core group, the multiple core groups execute the computation task of multiple time steps corresponding to the next input sequence based on a cyclic pipeline method.

[0085] In some embodiments, the plurality of processing cores in the many-core chip include communication cores and non-communication cores, the communication cores being used for data communication interaction with off-chip devices; the plurality of processing cores in the execution core cluster are interconnected in the on-chip network of the many-core chip; the plurality of processing cores in the execution core cluster include at least one communication core, or the plurality of processing cores in the execution core cluster include at least one non-communication core adjacent to any communication core.

[0086] In some embodiments, the plurality of processing cores in the many-core chip include communication cores and non-communication cores. The communication cores are used to perform data communication interaction with off-chip devices. The core group whose pipeline execution order is located at the Kth position and the core group whose pipeline execution order is located at the (K+1)th position are adjacent in the routing position of the on-chip network of the many-core chip. Furthermore, the pipeline execution order of a core group containing at least one communication core or at least one non-communication core adjacent to any communication core is determined based on the order of time steps corresponding to computation tasks where the amount of input and output data exceeds a threshold.

[0087] The mapping apparatus 200 provided in this embodiment is used to implement the mapping method described above. For specific details, please refer to the relevant descriptions in the mapping method of the above embodiments, which will not be repeated here.

[0088] Figure 8 This is a schematic diagram of the structure of a temporal neural network accelerator provided in an embodiment of the present disclosure.

[0089] like Figure 8 As shown, this disclosure also provides a temporal neural network accelerator. The temporal neural network includes a processing unit, which is used to sequentially execute the computation task corresponding to each time step of the input sequence. The accelerator 300 includes:

[0090] The many-core chip 301 includes multiple execution core clusters, each containing multiple processing cores. The multiple processing cores within an execution core cluster are divided into multiple core groups, each containing at least one processing core. Each execution core cluster is configured to independently run a corresponding temporal neural network. Each core group within an execution core cluster is configured to deploy a corresponding processing unit. The multiple core groups within an execution core cluster are configured to execute computational tasks corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner.

[0091] The time-regulator 302 is used to configure the input time and corresponding kernel group of the current input sequence of the temporal neural network.

[0092] In this embodiment of the disclosure, the time-controller 302 can configure the input time and corresponding kernel group of the current input sequence of the temporal neural network according to the time step corresponding to the current input sequence, so that at each time step corresponding to the current input sequence, the corresponding input data in the current input sequence is input to the corresponding kernel group, so that the kernel group performs the calculation task of the corresponding time step.

[0093] In some embodiments, such as Figure 8 As shown, the accelerator 300 also includes an off-chip device 303, which can be an off-chip memory. The off-chip memory can be used to store the input sequence and output data of the temporal neural network.

[0094] In the accelerator 300 provided in this embodiment, the temporal neural network is mapped to the many-core chip 301 based on the mapping method provided in the above embodiment. For specific related descriptions, please refer to the related descriptions in the mapping method of the above embodiment, which will not be repeated here.

[0095] Figure 9 This is a block diagram of an electronic device provided in an embodiment of the present disclosure, with reference to... Figure 9 This disclosure provides an electronic device comprising: at least one processor 41; at least one memory 42; and one or more I / O interfaces 43 connected between the processor 41 and the memory 42; wherein the memory 42 stores one or more computer programs executable by the at least one processor 41, the one or more computer programs being executed by the at least one processor 41 to enable the at least one processor 41 to perform the mapping method described above.

[0096] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the mapping method described above. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0097] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device executes the mapping method described above.

[0098] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0099] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0100] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0101] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0102] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0103] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0104] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0105] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0106] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0107] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A mapping method for a temporal neural network, characterized in that, The temporal neural network includes a processing unit, which is used to sequentially execute the computation task corresponding to each time step of the input sequence. The mapping method includes: The multiple processing cores in the many-core chip are divided into multiple execution core clusters, and the execution core clusters include multiple processing cores; The execution core cluster is divided into multiple core groups, and each core group includes at least one processing core. Multiple temporal neural networks are respectively mapped to multiple execution kernel clusters, each execution kernel cluster is configured to independently run a corresponding temporal neural network, and each kernel group in the execution kernel cluster is deployed with a corresponding processing unit; For each execution kernel cluster, multiple kernel groups in the execution kernel cluster are configured to perform computation tasks corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner. The many-core chip includes multiple processing cores, including communication cores and non-communication cores. The communication cores are used to perform data communication and interaction with external devices. Among the multiple core groups, the core group whose pipeline execution order is at position K and the core group whose pipeline execution order is at position K+1 are adjacent in the on-chip network of the many-core chip; and, Based on the order of time steps corresponding to computational tasks where the amount of input and output data exceeds a threshold, determine the pipeline execution order of a core group containing at least one communicating core or at least one non-communication core adjacent to any communicating core.

2. The mapping method according to claim 1, characterized in that, A temporal neural network to be mapped is copied into multiple copies to obtain multiple temporal neural networks, and the multiple temporal neural networks are used to process different input sequences of the same data processing task. or, The multiple temporal neural networks are different temporal neural networks, and each of the multiple temporal neural networks is applied to process a data processing task. Different temporal neural networks are used to process different data processing tasks.

3. The mapping method according to claim 1, characterized in that, Before configuring multiple kernel groups in the execution kernel cluster to execute the computation tasks corresponding to multiple time steps of the mapped temporal neural network input sequence in a cyclic pipeline manner, the mapping method further includes: planning the pipeline execution order corresponding to each kernel group in the multiple kernel groups; The step of configuring multiple kernel groups in the execution kernel cluster to execute the computation task corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner includes: configuring the multiple kernel groups to execute the computation task corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner according to the pipeline execution order corresponding to each kernel group in the multiple kernel groups; Specifically, the kernel group whose pipeline execution order is located at the Kth position among the multiple kernel groups is configured to execute the computation task corresponding to the Lth time step of the input sequence, where L = n * m + K, n is the current loop order, and m is the number of kernel groups among the multiple kernel groups.

4. The mapping method according to claim 3, characterized in that, The kernel group located at the Kth position in the pipeline execution order of the plurality of kernel groups is further configured to execute the computation task of the L+1th time step corresponding to the current input sequence while simultaneously executing the computation task of the Lth time step corresponding to the next input sequence.

5. The mapping method according to claim 3, characterized in that, When the number of time steps T corresponding to the current input sequence is less than the number of core groups m among the multiple core groups, after the core group located at the Tth position in the pipeline execution order completes the calculation task of the Tth time step corresponding to the current input sequence, starting from the (T+1)th position core group, the multiple core groups execute the calculation task of multiple time steps corresponding to the next input sequence based on a cyclic pipeline method.

6. The mapping method according to claim 1, characterized in that, The many-core chip includes multiple processing cores, including communication cores and non-communication cores. The communication cores are used to perform data communication and interaction with external devices. Multiple processing cores in the execution core cluster communicate and connect with each other in the on-chip network of the many-core chip; The execution core cluster may include at least one communication core among its multiple processing cores, or the execution core cluster may include at least one non-communication core that is adjacent to any of the communication cores.

7. A mapping device for a temporal neural network, characterized in that, The temporal neural network includes a processing unit, which is used to sequentially execute the computation task corresponding to each time step of the input sequence. The mapping device includes: A partitioning unit is used to: divide multiple processing cores in a many-core chip into multiple execution core clusters, wherein each execution core cluster includes multiple processing cores; and divide the multiple processing cores in each execution core cluster into multiple core groups, wherein each core group includes at least one processing core. The mapping unit is configured to: map multiple temporal neural networks to multiple execution kernel clusters, each execution kernel cluster being configured to independently run a corresponding temporal neural network, and each kernel group in the execution kernel cluster being deployed with a corresponding processing unit; for each execution kernel cluster, the multiple kernel groups in the execution kernel cluster are configured to execute the computation tasks of multiple time steps corresponding to the input sequence of the mapped temporal neural network in a cyclic pipeline manner; The many-core chip includes multiple processing cores, including communication cores and non-communication cores. The communication cores are used for data communication and interaction with off-chip devices. The core group whose pipeline execution order is at position K and the core group whose pipeline execution order is at position K+1 are adjacent in the routing position of the on-chip network of the many-core chip. Furthermore, the mapping unit is also used to: determine the pipeline execution order of a core group containing at least one communication core or at least one non-communication core adjacent to any communication core, based on the order of time steps corresponding to computation tasks where the amount of input and output data exceeds a threshold.

8. A temporal neural network accelerator, characterized in that, The temporal neural network includes a processing unit, which is used to sequentially execute the computation task corresponding to each time step of the input sequence. The accelerator includes: A many-core chip includes multiple execution core clusters, each execution core cluster including multiple processing cores. The multiple processing cores in the execution core cluster are divided into multiple core groups, each core group including at least one processing core. Each execution core cluster is configured to independently run a corresponding temporal neural network. Each core group in the execution core cluster is deployed with one processing unit. The multiple core groups in the execution core cluster are configured to execute computation tasks corresponding to multiple time steps of the input sequence of the mapped temporal neural network in a cyclic pipeline manner. A time-series determiner is used to configure the input time and corresponding kernel group of the current input sequence of the temporal neural network; The many-core chip includes multiple processing cores, including communication cores and non-communication cores. The communication cores are used for data communication and interaction with off-chip devices. The core group with the pipeline execution order at position K and the core group with the pipeline execution order at position K+1 are adjacent in the routing position of the on-chip network of the many-core chip. Furthermore, the pipeline execution order of a core group containing at least one communication core or at least one non-communication core adjacent to any communication core is determined based on the order of time steps corresponding to computation tasks where the amount of input and output data exceeds a threshold.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the mapping method as described in any one of claims 1-6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the mapping method as described in any one of claims 1-6.

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