Accelerator for memristor genetic algorithm for feature selection and operating method thereof

Abstract

The application discloses an accelerator for feature selection of a memristor genetic algorithm and an operation method thereof, and the accelerator comprises a first control module, a memristor array module, a second control module and a processor module; the first control module inputs data sent by the processor module into the memristor array module after converting the data into analog quantities, and updates the state of a storage unit of the memristor array module in a solution updating stage; the memristor array module stores a feature subset and realizes in-situ updating of a memristor unit in the array; the second control module receives a current signal of the memristor array module, converts the current signal into a voltage signal, and then converts the voltage signal into a digital signal and transmits the digital signal to the processor module; the processor module sends preprocessed data to the first control module in a fitness calculation stage, and receives and processes the digital signal output by the second control module. The application reduces the data transmission process, reduces the circuit overhead, and effectively reduces the operation time and power consumption.

Description

Technical Field

[0001] This invention belongs to the field of intelligent optimization technology, and more specifically, relates to an accelerator for a memristor genetic algorithm for feature selection and its operation method. Background Technology

[0002] With the rise of big data and artificial intelligence, the dimensionality of data features is increasing daily, making rapid data classification and extraction increasingly difficult. Against this backdrop, feature selection has attracted growing attention. Feature selection is a crucial task in machine learning, aiming to reduce feature dimensionality while maintaining learning performance. Some filtering methods, such as Pearson correlation coefficient and chi-square verification, can quickly select features, but they do not guarantee the quality of the selected features. On the other hand, some wrapper methods, such as forward search and metaheuristic algorithms, can guarantee the quality of the selected features, but require iterative iterations and consume significant time.

[0003] Genetic algorithms are a type of metaheuristic algorithm, widely used to solve feature selection problems due to their ability to find solutions on a large scale. However, as the feature dimension increases, genetic algorithms based on the von Neumann architecture consume a significant amount of time and power in memory and processor transfers.

[0004] Therefore, a new computational paradigm is needed to solve this problem. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an accelerator and its operation method for a memristor genetic algorithm for feature selection, aiming to solve the problems of long computation time and high power consumption in existing genetic algorithms for solving feature selection problems.

[0006] This invention provides an accelerator for a memristor genetic algorithm for feature selection, comprising: a first control module, a memristor array module, a second control module, and a processor module; the first control module is connected to the memristor array module, the memristor array module is bidirectionally connected to the second control module, the second control module is bidirectionally connected to the processor module, and the processor module is connected to the first control module; the first control module receives data sent by the processor module, converts it into analog signals and inputs them into the memristor array module, and updates the state of the storage units of the memristor array module during the de-update phase; the memristor array module stores feature subsets and, according to Kirchhoff's Law I... j =∑G ij V iThe system performs simulated vector-matrix multiplication and, under the coordinated operation of the first and second control units, updates the memristor cells in the array in situ. The second control module receives the current signal calculated by the memristor array module, converts it into a voltage signal, and then converts the voltage signal into a digital signal before transmitting it to the processor module. The processor module sends preprocessed data to the first control module during the fitness calculation phase and receives and processes the digital signal output by the second control module. Wherein, I... j Let G be the current in the j-th column of the memristor array. ij V represents the conductance of each memristor cell in the memristor array. i is the voltage applied to the i-th row of the memristor array.

[0007] Furthermore, the first control module includes a data input unit and a row control unit; the data input unit includes n digital-to-analog converters for converting data sent by the processor module into analog quantities and outputting them to the row control unit; the row control unit is used to select V during the fitness calculation phase. data The data is input to the row lines of the memristor array module and the corresponding analog signal is selected for connection during the de-update phase based on the current operation.

[0008] Furthermore, the line control unit includes a first analog multiplexer, whose six inputs are sequentially connected to the S1[2:0] signal, V... data Signal, V set Signal, V reset Signal, V read Signal and V p The signal, wherein the output of the analog multiplexer is connected to the input of the memristor array module; wherein, V data It is the analog voltage converted by the data input unit, S1[2:0] is the selection signal from the processor module, V set and V reset These are the set voltage and reset voltage of the memristor, respectively, V read It is the read voltage of the device, V p It is a protective voltage.

[0009] Furthermore, the memristor array module includes a first memristor array and a second memristor array; the first memristor array is used to store feature subsets in the algorithm and performs vector-matrix multiplication calculations within the array. During the solution update phase, a new feature subset is generated in the second memristor array through crossover operations implemented in the array; the second memristor array is used to store feature subsets in the algorithm and performs vector-matrix multiplication calculations within the array. During the solution update phase, a new feature subset is generated in the second memristor array through crossover operations implemented in the array.

[0010] Furthermore, the second control module includes a column control unit and an output acquisition unit; the column control unit is used to convert the current data obtained in a column into voltage data during the fitness calculation stage, and transmit the digital signal to the processor module through the output acquisition unit, and select the corresponding port signal output according to the operation performed during the de-update stage.

[0011] Furthermore, the column control unit includes 2m second analog multiplexers, each with the same structure, including 5 input ports, which are sequentially connected to the selection signal S2[1:0], the transimpedance amplifier TIA, and the protection voltage V. p The operating voltage VDD and ground GND are provided; the output acquisition unit includes 2m analog-to-digital conversion circuits, which are used to convert analog quantities into digital quantities and transmit them to the processor module.

[0012] Furthermore, the transimpedance amplifier TIA includes a resistor R1 and an amplifier; the inverting input terminal of the amplifier serves as the input terminal of the transimpedance amplifier, the non-inverting input terminal of the amplifier is grounded, and the output terminal of the amplifier serves as the output terminal of the transimpedance amplifier; the resistor R1 is connected between the inverting input terminal and the output terminal of the amplifier.

[0013] The present invention also provides an operating method based on the above-described accelerator, comprising the following steps:

[0014] S1 performs preprocessing of the dataset:

[0015] The statistical probabilities of each feature and each category are obtained in the processor module by using the Bayesian classifier calculation method, and Laplace smoothing is performed. The obtained data is then logarithmically taken, normalized, and sent to the data input unit.

[0016] S2 parameter initialization:

[0017] Given the population size NP, crossover rate, mutation rate, number of tournament selections, and maximum number of iterations, the population is obtained by generating a random initial solution set;

[0018] The generated initial population is mapped and stored in the first memristor array, and the memristor cells in the second memristor array are set to a high-resistivity state;

[0019] S3 evaluates the quality of a population by calculating a fitness function;

[0020] S4 population update steps:

[0021] Crossover and mutation operations are achieved by updating the population stored on the memristor array through row control units and column control units;

[0022] S5 Repeat steps S3 and S4 until the set number of iterations is completed;

[0023] After S6 completes the iteration, it reads the memristor array module and uses the selected features in the array to perform an additional fitness function calculation. This function is determined by the classification accuracy and the length of the selected features, i.e., Fitness = (1-α)×Acc + α×(1-L), where α∈(0,1), Acc is the classification accuracy, and L is the proportion of the length of the selected features to the total length of the features. The subset of features with the largest fitness value is selected as the final result.

[0024] Furthermore, step S3 specifically involves: the processor module transmitting the normalized data to the data input unit, converting it into voltage data via a digital-to-analog converter, and then applying it to the row input port of the memristor array module. According to Ohm's law and Kirchhoff's law, the cumulative current result of the input voltage and the corresponding memristor cell conductance is obtained on the column. The current signal is converted into a voltage signal by a transimpedance amplifier, and then converted into a digital signal by an analog-to-digital converter before being transmitted to the output acquisition unit. Finally, the fitness function is calculated in the processor module.

[0025] Furthermore, step S4 specifically includes:

[0026] Based on the fitness calculation results, the excellent individuals in the original population are cross-paired to generate new individuals, thus realizing the crossover operation.

[0027] The mutation operation is achieved by randomly updating certain positions in the population to cause changes.

[0028] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art:

[0029] (1) The present invention provides an accelerator for a memristor genetic algorithm for feature selection. It utilizes a memristor array structure to map and store the selected features in the array. Through simulation calculation, the vector matrix multiplication operation is implemented in hardware in one step, which reduces the data transmission process, reduces circuit overhead, and effectively reduces computation time and power consumption.

[0030] (2) The present invention provides a memristor genetic algorithm operation method that combines the memristor logic implementation method and the cross operation of the genetic algorithm. Through the control of the peripheral circuit, the cross set is directly performed on the memristor array, which reduces the steps of reading data from the array and then updating it, and reduces the time and energy consumed when iteratively updating the set.

[0031] (3) The present invention provides a memristor genetic algorithm operation method. In order to better adapt to the operation of memristor array, a two-step mutation operation genetic algorithm is proposed. While maintaining the performance of the algorithm, the complexity of mutation operation on memristor array is reduced.

[0032] (4) The genetic algorithm accelerator based on memristor devices provided by the present invention can realize an in-memory computing architecture. Compared with the CMOS circuit structure, it has higher integration density, lower power consumption and faster computing speed, which can further leverage the advantages of large-scale solving of genetic algorithms. It is suitable for processing fields with high feature dimensions, such as finance, biomedicine and electronic information. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the accelerator structure for the memristor genetic algorithm for feature selection provided by the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of the line control unit provided by the present invention;

[0035] Figure 3 This is a schematic diagram of the structure of the memristor array provided by the present invention;

[0036] Figure 4 This is a schematic diagram of the memristor array operation method provided by the present invention;

[0037] Figure 5 This is a schematic diagram of the column control unit provided by the present invention; wherein, (a) is a schematic diagram of the analog multiplexer structure of the column control unit; and (b) is a schematic diagram of the transimpedance amplifier structure.

[0038] Figure 6 This is a schematic diagram of the solution process of the memristor genetic algorithm provided by the present invention;

[0039] Figure 7 This is a schematic diagram of the crossover operation in a memristor array provided by the present invention; wherein, (a) is the copy operation in the memristor logic operation; and (b) is the implementation method of the crossover operation in the memristor array.

[0040] Figure 8 This is a schematic diagram of the mutation operation in a memristor array provided by the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0042] In this invention, novel memory devices, represented by memristors, possess advantages such as high integration, low power consumption, and the ability to perform fast multiplication and accumulation operations. They are considered one of the effective means to solve the memory wall problem in the von Neumann architecture. By implementing a genetic algorithm on a memristor array, a more efficient feature selection task can be achieved.

[0043] Figure 1 This is a schematic diagram of the accelerator structure for the memristor genetic algorithm used in this invention, including a first control module 1, a memristor array module 2, a second control module 3, and a processor module 4; wherein, the first control module 1 is connected to the memristor array module 2, the memristor array module 2 is bidirectionally connected to the second control module 3, the second control module 3 is bidirectionally connected to the processor module 4, and the processor module 4 is connected to the first control module.

[0044] The first control module 1 includes a data input unit 11 and a row control unit 12. The data input unit 11 consists of n digital-to-analog converters (DACs) used to receive data sent by the processor module 4, convert it into analog signals, and input them to the row control unit 12. Under the control of the processor module 4, the row control unit 12, based on the calculation process, selects the appropriate signals to be applied to the row lines of the memristor array module 2 via a first analog multiplexer (MUX). Its specific structure is as follows: Figure 2 As shown, S1[2:0] is the selection signal from processor module 4, V data It is the analog voltage converted by data input unit 11, V set and V reset These are the set voltage and reset voltage of the memristor, respectively, V read It is the read voltage of the device, V p This is the protection voltage, typically 1 / 2V. set During the fitness calculation phase, the row control unit 12 selects V. data As the data input to the row lines of the memristor array module 2, during the de-update phase, the row control unit 12 selects and connects the corresponding analog signal according to the current operation. The specific operation will be described later.

[0045] like Figure 3 As shown, the memristor array module 2 includes a first memristor array 21 and a second memristor array 22, with each row of the first memristor array 21 and the second memristor array 22 connected together.

[0046] Memristor array module 2 consists of cross-connected memristor cells. This array, with an n×2m specification, stores feature subsets used in the computation process. During the fitness calculation phase, it performs a dot product operation on the input data and array weights. The result is then accumulated column-wise in the form of current and output to the second control module 3. The specific computation method is as follows: Figure 4 As shown, the line control unit 12 will convert the voltage V data The data is applied to the row lines of memristor array module 2, and the column lines are grounded, according to Kirchhoff's laws and Ohm's law I. j =∑G ij V i The accumulated current obtained by multiplying voltage and conductance on each column is obtained; during the de-update phase, the data stored in the memristor is adjusted by the first control module 1 and the second control module 3, and the transistors in each column are turned on only during the adjustment and kept off under other circumstances.

[0047] The second control module 3 includes a column control unit 31 and an output acquisition unit 32. The column control unit 31 consists of 2m second analog multiplexers (MUX), and the structure of each MUX is as follows: Figure 5 As shown in (a), the selection signal S2[1:0] of processor module 4 controls the ports connected to this column, which include a transimpedance amplifier (TIA) and a protection voltage V. p Operating voltage VDD and ground GND. TIA is used for current-to-voltage conversion; its specific structure is as follows: Figure 5 As shown in (b), the value of R1 is generally the value of the memristor in its low-resistance state, and is set to 1KΩ in this example; V p As a protective voltage, a value that will not have a significant impact on the device is selected. This value varies depending on the device, but 1 / 2V is generally chosen. set VDD is the voltage value required for the update operation, V set <VDD<2×|V reset The output acquisition unit 32 consists of 2m analog-to-digital converters (ADCs) used to convert analog signals into digital signals and transmit them to the processor module 4. During the fitness calculation phase, the column control unit 31 is connected to a transimpedance amplifier (TIA) to convert the current data obtained from one column into voltage data, and then transmits the digital signal to the processor module 4 via the ADCs in the output acquisition unit 32. During the update phase, the processor module 4 selects the corresponding port signal of the MUX according to the operation performed; the specific operation is described later.

[0048] Processor module 4 is used for data processing, coordinating the algorithm process, and sending selection signals to update memristor array module 2 to row control unit 12 and column control unit 31. During the fitness calculation phase, preprocessed data is sent to data input unit 11, and output signals from second control module 3 are received and processed. By operating first control module 1 and second control module 3, the control of memristor array module 2 is achieved.

[0049] In this embodiment, the problem of feature selection is generally a data classification problem, that is, classifying a set of data according to certain conditions. There exists a dataset S = {X1, X2, ..., X...}. t}, each member X i There are r features, namely X i ={a i1 ,a i2 ,…,a ir The set of categories for classification is Y = {y1, y2, ..., y}. p Using the Bayesian algorithm as the classifier, given P(X|Y), calculate the probability of P(Y|X) according to Bayes' theorem. Where P(X|Y) is the probability of each feature appearing under category Y, i.e., P(a i |y j For discrete features, a multinomial distribution is used to calculate the probability of their occurrence. For continuous or approximately continuous features, a Gaussian distribution is used. P(Y|X) is the probability of determining the category Y to which a member belongs, given the member's features. p |X), we usually consider P(y) to have the highest probability. j |X) represents the category to which the member belongs; P(Y) represents the probability of each category appearing; P(X) represents the probability of each feature appearing.

[0050] Assuming that the features are conditionally independent Next, take the logarithm of both sides of the equation to obtain... Since it is only necessary to determine different log(P(y) j The value of |X)) is constant, while log(P(X)) remains unchanged for the same member, so log(P(X)) can be omitted during calculation.

[0051] like Figure 2As shown, this embodiment of the invention uses an n×2m memristor array. The first memristor array 21 and the second memristor array 22 are symmetrically translated about the center line, each consisting of n rows and m columns of memristors. In the memristor array, the selection or non-selection of a feature is stored through high and low resistance states. A high resistance state corresponds to 0 (not selected), and a low resistance state corresponds to 1 (selected). Each column of memristor cells stores a feature selection method, corresponding to 'a' in the classification item X. ij In addition, the memristor unit corresponding to the final category Y needs to be set to 1 for classification calculation.

[0052] Figure 6 The flowchart of the feature selection method using a genetic algorithm in this invention includes the following steps:

[0053] S1 performs preprocessing of the dataset. Using the Bayesian classifier calculation method described above, the statistical probabilities of each feature and each category are obtained in the processor module 4, and Laplace smoothing is performed. The obtained data is then logarithmized and normalized before being sent to the data input unit 11.

[0054] S2 parameter initialization: Since different problems require different algorithm parameters, the algorithm parameters for this embodiment are given here: population size NP = 200, crossover rate Pc = 0.8, mutation rate Pm = 0.02, tournament selection number Nt = 10, maximum number of iterations G = 100. First, a random initial solution set is generated, which is called the population in the genetic algorithm. The generated initial population is mapped and stored in the first memristor array 21, and the memristor cells in the second memristor array 22 are set to high impedance state;

[0055] S3 calculates the fitness function to evaluate the quality of the population. Processor module 4 transmits the normalized data to data input unit 11. After being converted into voltage data by a digital-to-analog converter, it is applied to the row input port of memristor array module 2. According to Ohm's law and Kirchhoff's law, the cumulative current result of the input voltage and the corresponding memristor cell conductance is obtained on the column. The current signal is converted into a voltage signal by a transimpedance amplifier, and then converted into a digital signal by an analog-to-digital converter before being transmitted to output acquisition unit 32. Finally, the fitness function is calculated in processor module 4. The value of the fitness function consists of two parts: classification accuracy and the number of features. The higher the accuracy and the fewer the features, the better the feature selection effect, i.e., Fitness = (1-α)×Acc + α×(1-L), where α∈(0,1), Acc is the classification accuracy, and L is the proportion of the selected feature length to the total feature length. The fitness value is used to update the subsequent solutions.

[0056] The S4 population update consists of two steps: crossover and mutation. Crossover involves pairing superior individuals from the original population based on fitness calculations to generate new individuals. Mutation randomly updates certain positions within the population, causing changes. Both operations update the population stored on the memristor array through row control unit 12 and column control unit 31.

[0057] Specifically, Figure 7 This is a schematic diagram illustrating the crossover operation implemented in the memristor array used in this invention. (a) The diagram shows the copy operation in the memristor logic operation, which involves copying the resistance state of one cell to another. When there is one low-resistance device and one high-resistance device, a voltage VDD is applied from one end of the low-resistance device, and one end of the high-resistance device is grounded. At this time, the voltage is distributed across both ends of the high-resistance device, reaching the set voltage of the device. The high-resistance device is set to a low-resistance state, thus realizing the copying of the low-resistance state. When there are two high-resistance devices, a voltage VDD is applied from one end of the device, and one end of the other device is grounded. At this time, the voltage is distributed across the two high-resistance devices, and the other high-resistance device remains high-resistance, thus realizing the copying of the high-resistance state. (b) The diagram shows the implementation method of population crossover operation in the memristor array module, C i and C j For two columns in the first memristor array 21, C m1 This is one column in the second memristor array 22; during the first population update, two columns are selected from the original population, such as C. i and C j By intersecting certain positions in these two columns, a new individual is generated, such as C. m1 The individual is then placed into a new population. The state of a column is replicated by applying VDD to one column and grounding the column containing the new individual. For positions in a column where replication is not desired, a protective voltage V can be applied to the corresponding row input. p Repeat the above operation multiple times to generate a new population in the second memristor array 22 and reset the state of the first memristor array 21 to a high-resistivity state. The same operation is used when updating the population in subsequent cycles.

[0058] Figure 8 This diagram illustrates the implementation of mutation operations in a memristor array used in this invention. To adapt to the operation of the memristor array, set and reset operations are performed at randomly selected locations. This method eliminates the need to consider the original state of the devices, further reducing the number of operation steps. Cells in a column requiring set and reset can be processed simultaneously by applying V to the corresponding row input. set and V reset Other input terminals are connected to the protection voltage V. p The column output terminal is grounded.

[0059] S5 determines the number of iterations. S3 and S4 are repeated until the set number of iterations is reached. The number of iterations will vary depending on the problem being solved. Too few iterations may result in a poor-quality solution, while too many iterations will take too long to compute. Generally, it is set between 50 and 800 iterations. In this example, it is set to 100 iterations.

[0060] After S6 iteration is completed, the memristor array module is read, and the fitness function is calculated again using the features selected in the array. The subset of features with the largest fitness value is selected as the final result.

[0061] Compared with existing technologies, the solution provided by this invention innovatively uses a memristor array as the computational core of the problem, significantly reducing the time consumed by fitness calculation in the genetic algorithm when solving the feature selection problem. Furthermore, online updates within the memristor array are achieved through peripheral circuitry, reducing data transmission and optimizing the integration between the algorithm and hardware.

[0062] This invention provides a memristor-based genetic algorithm accelerator and its operation method for feature selection. The population from the genetic algorithm is mapped and stored on a memristor array, enabling high-parallel computing, low-power consumption, and high-speed solution to the feature selection problem. Simultaneously, by employing memristor logic operations, in-situ updates of the population are performed on the memristor array, reducing the time and power consumption of updating the population. This invention systematically implements the genetic algorithm computation process on a memristor array, from solution set evaluation to solution set update, significantly improving computation speed and energy efficiency. It provides a new approach for further utilizing memristor arrays for in-memory computing and can be applied to edge computing and low-power computing scenarios.

[0063] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An accelerator for a memristor genetic algorithm for feature selection, characterized in that, The application relates to an accelerator and an operation method thereof. The accelerator comprises a first control module (1), a memristor array module (2), a second control module (3) and a processor module (4). The first control module (1) is connected with the memristor array module (2), the memristor array module (2) is bidirectionally connected with the second control module (3), the second control module (3) is bidirectionally connected with the processor module (4), and the processor module (4) is connected with the first control module (1). The first control module (1) is used for converting data sent by the processor module (4) into an analog quantity and inputting the analog quantity into the memristor array module (2), and updating the state of a storage unit of the memristor array module (2) in a solution updating stage. The memristor array module (2) is used for storing a feature subset, realizing analog operation of vector matrix multiplication through Kirchhoff's law, and realizing in-situ updating of a memristor unit in an array under the cooperation of the first control unit (1) and the second control unit (3). The second control module (3) is used for converting a current signal of the memristor array module (2) into a voltage signal, converting the voltage signal into a digital signal, and then transmitting the digital signal to the processor module (4). The processor module (4) is used for sending preprocessed data to the first control module (1) in an adaptability calculation stage, and receiving and processing the digital signal output by the second control module (3). The operation method of the accelerator comprises the following steps: S1: preprocessing of a data set: The statistical probability of each feature and each classification category is obtained in the processor module through a Bayesian classifier calculation method, Laplace smoothing is performed, the obtained data is subjected to logarithm operation and normalization, and then the data is sent to a data input unit; S2: parameter initialization: A population size NP, a crossover rate, a mutation rate, a number of tournament selection and a maximum iteration number are given, and an initial solution set is generated to obtain a population; The generated initial population is mapped and stored in a first memristor array, and the memristor units in a second memristor array are set to a high resistance state; S3: evaluation of the population through an adaptability function calculation; S4: population updating step: The population stored on the memristor array is updated through a row control unit and a column control unit to realize a crossover operation and a mutation operation; S5: repeating step S3 and step S4 until the set iteration number is completed; S6 When the iteration is completed, the memristor array module is read, and an additional calculation of the fitness function is performed using selected features in the array, which is determined by the accuracy of the classification and the length of the selected features, i.e. wherein , Acc is the accuracy of the classification, L is the proportion of the length of the selected features to the total length of the features, and the feature subset with the maximum fitness value is selected as the final selection result.

2. The accelerator of claim 1, wherein, The first control module (1) comprises a data input unit (11) and a row control unit (12). The data input unit (11) comprises n digital-to-analog converters, which are used for converting data sent by the processor module (4) into an analog quantity and outputting the analog quantity to the row control unit (12). The row control unit (12) is configured to select V data As data input to the row lines of the memristor array module (2), the corresponding analog signals are selected to be connected according to the operation currently performed in the update phase.

3. The accelerator of claim 2, wherein, The row control unit (12) comprises a first analog multiplexer, six input ends of the analog multiplexer are connected with S1[2:0] signals, V data signals, V set signals, V reset signals, V read signals and V p signals in turn, and an output end of the analog multiplexer is connected with an input end of the memristor array module (2). wherein V data is the analog voltage converted by the data input unit (11), S1[2:0] is the selection signal from the processor module (4), V set and V reset are the set voltage and reset voltage of the memristive device, respectively, V read is the read voltage, and V p is the protection voltage.

4. The accelerator of any one of claims 1-3, wherein, The memristor array module (2) comprises a first memristor array (21) and a second memristor array (22). The first memristor array (21) is used for storing a feature subset in an algorithm, and is used for performing vector matrix multiplication calculation in the array, and is used for generating a new feature subset in the second memristor array (22) through a crossover operation realized in the array in a solution updating stage. The second memristor array (22) is used for storing a feature subset in an algorithm and performing vector matrix multiplication calculation inside the array, and a new feature subset is generated in the second memristor array (11) through cross operation realized in the array in the solution update stage.

5. The accelerator of claim 1, wherein, The second control module (3) comprises a column control unit (31) and an output acquisition unit (32). The column control unit (31) is used for converting a column of obtained current data into voltage data in the fitness calculation stage, transmitting a digital signal to the processor module (4) through the output acquisition unit (32), and selecting a corresponding port signal output according to the operation performed in the solution update stage.

6. The accelerator of claim 5, wherein, The column control unit (31) comprises 2m second analog multiplexers, each of which has the same structure and comprises five input ports connected with selection signals S2[1:0], a trans-impedance amplifier TIA, a protection voltage V p , an operating voltage VDD and a ground wire GND in sequence. The output acquisition unit (32) comprises 2m analog-to-digital conversion circuits, which are used for converting analog quantities into digital quantities and transmitting the digital quantities to the processor module (4).

7. The accelerator of claim 6, wherein, The TIA comprises a resistor R1 and an amplifier. The reverse input end of the amplifier is used as the input end of the TIA, the forward input end of the amplifier is grounded, and the output end of the amplifier is used as the output end of the TIA. The resistor R1 is connected between the reverse input end and the output end of the amplifier.

8. The accelerator of claim 1, wherein, Step S3 is specifically: The processor module transmits the normalized data to the data input unit, converts the data into voltage data through a digital-to-analog converter, and then applies the voltage data to the row input port of the memristor array module, obtains the input voltage and the cumulative current result of the corresponding memristor unit conductance on the column according to Ohm's law and Kirchhoff's law, converts the current signal into a voltage signal through a trans-impedance amplifier, converts the digital signal into a digital signal through an analog-to-digital converter, and then transmits the digital signal to the output acquisition unit. Finally, the fitness function is calculated in the processor module.

9. The accelerator of claim 1 or 8, wherein Step S4 is specifically: According to the result of the fitness calculation, the excellent individuals in the original population are crossed and paired to generate new individuals, thereby realizing the cross operation; Some positions in the population are randomly updated to change, thereby realizing the mutation operation.

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