Method of manufacturing a metal gate

Abstract

The application discloses a preparation method of a metal gate, which comprises the following steps: forming a vertical dummy gate with vertical side walls on a silicon substrate; forming a first dielectric layer, which covers the side walls of the vertical dummy gate and forms a side wall; forming a second dielectric layer, which surrounds the side wall and covers the exposed silicon substrate surface around the side wall; forming a first hard mask with a first opening on the second dielectric layer and the vertical dummy gate, wherein the width of the first opening is greater than the width of the vertical dummy gate; etching the vertical dummy gate and the side wall to remove the vertical dummy gate and form an etching groove inside the side wall, wherein the side wall of the etching groove is inclined and the width of the top of the etching groove is greater than the width of the bottom of the etching groove; forming a gate dielectric layer on the exposed silicon substrate surface at the bottom of the etching groove; and filling a metal material layer in the etching groove above the gate dielectric layer to form a metal gate with a top width greater than a bottom width. The application can simplify the manufacturing process and easily control the appearance of the metal gate.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit manufacturing, and more particularly, relates to a preparation method of metal gate. BACKGROUND

[0002] In the process of integrated circuit manufacturing, metal-oxide-semiconductor field effect transistor is one of the most important devices, in which the size of the gate is defined as the feature size of the integrated circuit. With the increase of the integration of integrated circuits, the feature size of the device is required to be further reduced. When the height of the gate dielectric layer is reduced to a certain size, the gate leakage effect will be more obvious, which will affect the quality of the device.

[0003] The conventional gate dielectric material is usually silicon dioxide. When its thickness is less than 5nm, the leakage current is relatively obvious, and with the decrease of the thickness, the leakage current increases exponentially. When the thickness is less than 1nm, the leakage current will be too large to be acceptable. High-K gate dielectric gate material is used to replace the conventional silicon dioxide gate dielectric, and metal material is used as the gate electrode, which will greatly optimize the gate leakage current. Compared with the conventional polysilicon material, the metal material is more compatible with the high-K dielectric material. The high-K material is used to manufacture the gate layer, and the metal material is used to manufacture the gate electrode. The manufactured metal gate is called HKMG (High-K Metal Gate). This technology has almost become one of the necessary technologies for 45nm and below processes.

[0004] The conventional polysilicon gate has a vertical shape. The metal gate in the prior art can be manufactured in a vertical shape, a tapered shape and an inverted trapezoidal shape. The vertical and inverted trapezoidal metal gates are widely used. The inverted trapezoidal metal gate has two main advantages. First, in the back gate process, metal needs to be filled. During the metal filling process, voids are easily generated, resulting in high resistance and poor device stability. The inclined sidewall trench is more easily filled with metal, reducing the generation of voids during the filling process. Second, the inverted trapezoidal gate has a larger surface area at the top than the vertical gate, making it easier for the hole contact to align and contact with the gate.

[0005] However, the existing manufacturing method of the inverted trapezoidal metal gate has the problems of complex process, high cost and difficult control of the inverted trapezoidal angle. SUMMARY

[0006] The purpose of the present application is to provide a preparation method of metal gate, which can simplify the manufacturing process and easily control the appearance of the metal gate with the top width greater than the bottom width.

[0007] To achieve the above purpose, the present application provides a preparation method of metal gate, comprising:

[0008] A silicon substrate is provided, and a vertical dummy gate with vertical sidewalls is formed on the silicon substrate;

[0009] A first dielectric layer is formed, which covers the sidewalls of the vertical dummy gate and forms a sidewall spacer;

[0010] A second dielectric layer is formed, which surrounds the sidewall spacer and covers the silicon substrate surface exposed around the sidewall spacer, and the top surface of the second dielectric layer is flush with the top surface of the vertical dummy gate;

[0011] A first hard mask with a first opening is formed on the second dielectric layer and the vertical dummy gate, the width of the first opening is greater than the width of the vertical dummy gate, and the first opening exposes the top of the vertical dummy gate and the sidewall spacer;

[0012] The vertical dummy gate and the sidewall spacer are etched to remove the vertical dummy gate and form an etching trench inside the sidewall spacer, the sidewall of the etching trench is inclined, and the width of the top of the etching trench is greater than the width of the bottom of the etching trench;

[0013] A gate dielectric layer is formed on the silicon substrate surface exposed at the bottom of the etching trench;

[0014] A metal material layer is filled in the etching trench above the gate dielectric layer, and the metal material layer and the gate dielectric layer form a metal gate with a top width greater than a bottom width.

[0015] Optionally, during etching of the vertical dummy gate and the sidewall spacer, the etching rate selection ratio of the vertical dummy gate to the sidewall spacer is in the range of 0.9-1.1.

[0016] Optionally, the etching of the vertical dummy gate and the sidewall spacer includes:

[0017] The vertical dummy gate and the sidewall spacer are etched with an etching gas until the vertical dummy gate is completely removed, and the surface of the silicon substrate is exposed at the bottom of the etching trench;

[0018] The etching gas includes a reaction gas for etching the vertical dummy gate and the sidewall spacer, and a sidewall protection gas for forming a protection layer on the sidewall of the etching trench during etching.

[0019] Optionally, the vertical dummy gate includes a first sacrificial layer on the silicon substrate and a second sacrificial layer on the first sacrificial layer, and the thickness of the second sacrificial layer is greater than the thickness of the first sacrificial layer;

[0020] The first medium layer comprises a first sub-medium layer, a second sub-medium layer and a third sub-medium layer which are stacked, wherein the first sub-medium layer, the third sub-medium layer and the first sacrificial layer are made of the same material;

[0021] In the process of etching the vertical dummy gate and the side wall, the etching rate selection ratio range of the second sacrificial layer to the first sub-medium layer or the third sub-medium layer is 0.9-1.1; the etching rate selection ratio range of the second sacrificial layer to the second sub-medium layer is 0.9-1.1; and the etching rate selection ratio range of the second sub-medium layer to the first sub-medium layer or the third sub-medium layer is 0.9-1.1.

[0022] Optionally, the etching of the vertical dummy gate and the side wall by using the etching gas until the vertical dummy gate is completely removed and the surface of the silicon substrate is exposed at the bottom of the etching groove specifically comprises:

[0023] The vertical dummy gate and the side wall are etched by using a first etching gas, so that the surface of the silicon substrate is exposed at the bottom of the etching groove, and the width of the bottom of the etching groove is less than or equal to the width of the bottom of the vertical dummy gate;

[0024] The side wall and the bottom of the etching groove are continuously etched by using a second etching gas, so that the surface of the silicon substrate is completely exposed at the bottom of the etching groove, and the width of the bottom of the etching groove is greater than or equal to the width of the bottom of the vertical dummy gate.

[0025] Optionally, the first sacrificial layer, the first sub-medium layer and the third sub-medium layer are made of silicon oxide;

[0026] The second sacrificial layer is made of polysilicon;

[0027] The second sub-medium layer is made of silicon nitride.

[0028] Optionally, the reaction gas in the first etching gas comprises CF4 and CHF3, and the side wall protection gas in the first etching gas is O2;

[0029] The flow rate ratio range of CF4 to CHF3 is 0.4-0.9, and the flow rate ratio range of CF4 to O2 is 6-120.

[0030] Optionally, the reaction gas in the second etching gas comprises CHF3 and HBr, and the side wall protection gas in the second etching gas is O2;

[0031] The flow rate ratio range of CHF3 to HBr is 0.5-1.5, and the flow rate ratio range of HBr to O2 is 30-60.

[0032] Optionally, a dilution gas is further included in the first etching gas and the second etching gas, and the dilution gas is used to dilute plasma and adjust uniformity of etching.

[0033] Optionally, the material of the metal material layer is at least one of titanium, titanium nitride, tantalum and tantalum nitride.

[0034] The material of the gate medium layer is hafnium oxide or a hafnium-based compound.

[0035] The material of the second medium layer is silicon oxide.

[0036] The present application has the following beneficial effects:

[0037] The preparation method of the metal gate of the present application forms a side wall on the sidewall of the vertical pseudo-gate and forms a second medium layer surrounding the side wall and the vertical pseudo-gate after forming the vertical pseudo-gate, then forms a hard mask with an opening width larger than the vertical pseudo-gate on the vertical pseudo-gate and performs synchronous etching on the vertical pseudo-gate and the side wall to form an etching groove with a top width larger than a bottom width on the inner side of the side wall, then forms a gate medium layer at the bottom of the etching groove and fills a metal material layer in the etching groove to form a metal gate with a top width larger than a bottom width, the process steps of the preparation method of the metal gate of the present application are simple, and the morphology of the inclined sidewall of the etching groove is easy to control, thereby the sidewall angle of the metal gate with a top width larger than a bottom width can be accurately controlled.

[0038] The system of the present application has other characteristics and advantages, which will be apparent from and / or set forth in the accompanying drawings and the detailed description that follows, which together serve to explain certain principles of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout the several views.

[0040] Figure 1 An etching film layer schematic diagram of prior art one is shown.

[0041] Figure 2 An inverted trapezoidal pseudo-gate etching completion schematic diagram of prior art one is shown,

[0042] Figure 3 An etching source process etching bias power time-varying pulse mode schematic diagram of prior art one is shown.

[0043] Figure 4The figure shows the replacement gate structure covered by the sacrificial dielectric layer in the prior art two

[0044] Figure 5 The figure shows the step diagram of the preparation method of the metal gate in the embodiment of the present application.

[0045] Figure 6 The figure shows the film layer structure schematic diagram before the vertical dummy gate etching in the preparation method of the metal gate in the embodiment of the present application.

[0046] Figure 7 The figure shows the vertical dummy gate schematic diagram formed by etching in the preparation method of the metal gate in the embodiment of the present application.

[0047] Figure 8 The figure shows the schematic diagram of forming the light doped active region in the preparation method of the metal gate in the embodiment of the present application.

[0048] Figure 9 The figure shows the schematic diagram of the side wall manufacturing completion in the preparation method of the metal gate in the embodiment of the present application.

[0049] Figure 10 The figure shows the schematic diagram of forming the heavy doped active region in the preparation method of the metal gate in the embodiment of the present application.

[0050] Figure 11 The figure shows the schematic diagram of forming the second dielectric layer in the preparation method of the metal gate in the embodiment of the present application.

[0051] Figure 12 The figure shows the schematic diagram after the top of the vertical dummy gate is planarized in the preparation method of the metal gate in the embodiment of the present application.

[0052] Figure 13 The figure shows the schematic diagram of forming the first hard mask layer and the first photoresist layer in the preparation method of the metal gate in the embodiment of the present application.

[0053] Figure 14 The figure shows the schematic diagram of etching the first hard mask layer to form the opening in the preparation method of the metal gate in the embodiment of the present application.

[0054] Figure 15 The figure shows the schematic diagram of etching and removing the dummy gate in the preparation method of the metal gate in the embodiment of the present application.

[0055] Figure 16 The figure shows the schematic diagram of depositing and forming the gate dielectric layer in the preparation method of the metal gate in the embodiment of the present application.

[0056] Figure 17 The figure shows the schematic diagram of depositing and forming the metal material layer in the preparation method of the metal gate in the embodiment of the present application.

[0057] Figure 18 This diagram illustrates the formation of a metal gate in a method for fabricating a metal gate according to an embodiment of the present invention. Detailed Implementation

[0058] like Figure 1 and Figure 2 As shown, the prior art discloses a method for fabricating an inverted trapezoidal metal gate as follows: a gate oxide layer 201 and polysilicon 202 are sequentially deposited on a semiconductor substrate 200; a patterned photoresist layer is formed on the polysilicon layer; using the photoresist as a mask, an inverted trapezoidal polysilicon morphology is formed by etching under synchronous pulse mode conditions, using either high source power and low bias power, or low source power and high bias power conditions. Figure 3 As shown, an inverted trapezoidal alternative gate structure is fabricated using advanced pulse technology and appropriate etching process parameters.

[0059] This technology has high requirements for etching machines, and the cost of RF power supplies with pulse mode is high. In addition, the plasma ignition window is narrow in pulse mode, making process debugging difficult and the inverted trapezoidal angle difficult to control.

[0060] like Figure 4 As shown, the prior art 2 uses a conventional etching method to etch a polysilicon gate structure with a vertical morphology. First, a gate oxide layer 301 and a polysilicon 302 vertical gate are formed. Then, a sacrificial dielectric material 303 is deposited on its sidewalls. The side of the sacrificial dielectric material 303 is not perpendicular to the substrate 300 and is wider at the top and narrower at the bottom. The sacrificial dielectric material and the vertical gate material inside it together form an inverted trapezoidal replacement gate.

[0061] In this technology, the vertical polysilicon gate and its sidewall sacrificial dielectric material together form an inverted trapezoidal alternative gate structure. Another dielectric material is then deposited in the same layer of this structure via chemical vapor deposition. During the fabrication of the metal gate, the alternative gate needs to be removed; that is, the polysilicon gate and sacrificial dielectric material are removed from the gate layer, leaving the surrounding dielectric material. This removal process requires etching the alternative gate to achieve a good selectivity for the filling dielectric, placing high demands on etching precision. Furthermore, the inverted trapezoidal sidewalls, fabricated using deposition methods, are difficult to control in terms of sidewall angle. In addition, this approach has a complex process flow, requiring multiple deposition and etching operations, resulting in a long manufacturing cycle.

[0062] This invention employs a post-gate manufacturing method. By designing the gate manufacturing process and the process formulation involved, a novel method for manufacturing metal gates is proposed. This method has a simple manufacturing process, and the morphology of the metal gate with a top width greater than the bottom width is easy to control.

[0063] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0064] Example

[0065] like Figure 5 As shown, this embodiment proposes a method for fabricating a metal gate, including the following steps:

[0066] S1: Provide a silicon substrate 101, and form a vertical dummy gate with vertical sidewalls on the silicon substrate 101;

[0067] like Figure 7 As shown, the vertical dummy gate includes a first sacrificial layer 102 located on a silicon substrate 101 and a second sacrificial layer 103 located on the first sacrificial layer 102. The thickness of the second sacrificial layer 103 is greater than the thickness of the first sacrificial layer 102. In this embodiment, the material of the first sacrificial layer 102 is silicon oxide, and the material of the second sacrificial layer 103 is polycrystalline silicon.

[0068] Specifically, the structure for etching the vertical dummy gate is a well-established existing solution, using a typical sandwich structure (photoresist / antireflective layer - dielectric antireflective layer - amorphous carbon layer) and silicon oxide as a hard mask. Before etching to form the vertical dummy gate, the upper hard mask is first etched away, followed by polysilicon etching. In this embodiment, the film structure before etching the vertical dummy gate is as follows: Figure 6 As shown, it includes: a silicon substrate 101 (wafer); a first sacrificial layer 102 (gate oxide), preferably made of silicon oxide, with a thickness of 1 nm to 5 nm; a second sacrificial layer 103, made of polysilicon, with a thickness of 100 nm to 200 nm; a screen oxide layer 104, with a thickness of 1 nm to 5 nm; an advanced patterning film 105 (APF), with a thickness of 50 nm to 100 nm; a dielectric antireflective layer 106 (DARC), made of SiON, with a thickness of 20 nm to 50 nm; a bottom antireflective layer 107 (BARC), with a thickness of 20 nm to 50 nm; and a photoresist mask layer 108 (PR), with a thickness of 100 nm to 400 nm.

[0069] The etching process using an inductively coupled plasma (ICP) etching machine includes DARC, AC, BT, ME, and OE etching steps. The etching process for each step is as follows:

[0070] In the step, the DARC etching process is used to etch the bottom anti-reflective layer 107 (BARC) and the dielectric anti-reflective layer 106 (DARC). The BARC is mainly composed of C and H elements, and the DARC is mainly composed of Si, O and N elements. The etching gas used is CF4, CHF3 and N2. When etching the BARC layer, the [C][CF][N] plasma or radicals formed after ionization of the etching gas physically and chemically react with the BARC layer to generate gaseous compounds such as CH4, CH3 and CN, which are extracted from the chamber. When etching the DARC layer, the [C][CF][N] radicals formed after ionization of the etching gas physically and chemically react with the DARC layer to generate gaseous compounds such as SiF4, CO2 and CN, which are extracted from the chamber. In this embodiment, the etching process uses a process pressure of 5mt-15mt, a source power of 400W-1000W, a bias power of 50W-200W, a CF4 gas flow rate of 100sccm-200sccm, a CHF3 gas flow rate of 10sccm-50sccm, a N2 gas flow rate of 10sccm-50sccm, an electrostatic chuck temperature of 30°C-60°C, and an etching time of 30s-60s.

[0071] The AC step is used to etch the advanced pattern film 105 (APF). The APF is mainly composed of C element. The etching gas used in this step is mainly O2, HBr and Cl2. After ionization, the gas physically and chemically reacts with the APF material. The [O] ion reacts with the [C] ion to generate gaseous CO2, which is extracted from the chamber. The [Cl] ion reacts with the [C] ion to generate CCl4 gas, which is extracted from the chamber. The [H] ion generated by ionization of HBr mainly serves to solidify C atoms, thereby reducing chemical etching volatilization. Therefore, the [H] ion can protect the etching sidewall during the etching process, thereby increasing the etching anisotropy. In this embodiment, the etching process uses a process pressure of 5mt-10mt, a source power of 400W-1000W, a bias power of 50W-300W, a Cl2 gas flow rate of 20sccm-100sccm, a HBr gas flow rate of 20sccm-100sccm, an O2 gas flow rate of 100sccm-300sccm, an electrostatic chuck temperature of 30°C-60°C, and an etching time of 20s-40s.

[0072] The BT step is used to etch the shielding oxide layer 104 (silicon oxide layer). The etching gas used is CF4. After ionization, the CF4 physically and chemically reacts with the silicon oxide to generate SiF4 and CO2, which are extracted from the chamber. In this embodiment, the etching process uses a process pressure of 5mt-10mt, a source power of 400W-1000W, a bias power of 50W-200W, a CF4 gas flow rate of 20sccm-100sccm, an electrostatic chuck temperature of 30°C-60°C, and an etching time of 5s-15s.

[0073] At this point, the mask on top of the second sacrificial layer 103 (polysilicon layer) has been completely opened. Next, the polysilicon of the second sacrificial layer 103 is etched, using SF6, CH2F2 and N2 gases, where SF6 ionizes to produce a large amount of [F] ions, which react with silicon to produce SiF4, which is pumped out of the chamber, and CH2F2 and N2 ionize to produce [C], [H] and [N], which react with silicon to form difficult-to-vaporize SiC, Si3N4 and CH polymers, etc., which protect the sidewalls during etching. Increasing the proportion of SF6 gas can etch the polysilicon more straight, even causing sidewall damage, and increasing the proportion of N2 gas can protect the polysilicon sidewalls, reducing the etching sidewall angle. CH2F2 can increase the selectivity of Si etching to the mask, reducing the loss of mask material on top, and can adjust the lateral size. A large amount of CH2F2 gas generates byproducts during etching, which cover the mask and silicon sidewalls, increasing the lateral size of the etched material. In this embodiment, the etching process uses a process pressure of 5mt-10mt, a source power of 400W-1000W, a bias power of 50W-200W, a CH2F2 gas flow of 30sccm-100sccm, an N2 gas flow of 30sccm-100sccm, an SF6 gas flow of 20sccm-80sccm, an electrostatic chuck temperature of 30°C-60°C, and an etching time of 20s-60s.

[0074] When the etching reaches the underlying first sacrificial layer 102 (silicon oxide), only part of the silicon oxide is exposed, and the bottom Si remains. The OE step etching is then performed, using HBr, O2 and He gases, which requires a high selectivity of silicon oxide to etch the remaining polysilicon cleanly, while almost no etching occurs on the underlying silicon oxide. In this embodiment, the etching process uses a process pressure of 10mt-70mt, a source power of 400W-1000W, a bias power of 50W-200W, an HBr gas flow of 100sccm-200sccm, an O2 gas flow of 2sccm-10sccm, an He gas flow of 100sccm-200sccm, an electrostatic chuck temperature of 30°C-60°C, and an etching time of 20s-50s.

[0075] After the vertical dummy gate etching is completed, wet cleaning is performed to remove the etching byproducts and residual mask material, and the film structure after the cleaning is as shown in FIG. 4B. Figure 7 The vertical dummy gate structure formed includes a silicon substrate 101, a first sacrificial layer 102 (gate oxide), with a thickness of 1nm-5nm, and a second sacrificial layer 103 (poly), with a thickness of 100nm-200nm.

[0076] The above-mentioned vertical dummy gate etching process recipe is shown in Table 1

[0077] Table 1. Vertical dummy gate etching process recipe

[0078]

[0079] As shown in FIG. 2, after the vertical dummy gate is formed, the step further includes: performing ion implantation on the surface of the silicon substrate 101 exposed around the vertical dummy gate to form a lightly-doped active region 109. Figure 8

[0080] S2: Form a first dielectric layer, which covers the sidewall of the vertical dummy gate and forms a side wall;

[0081] As shown in FIG. 3, in this embodiment, the first dielectric layer includes a first sub-dielectric layer 110, a second sub-dielectric layer 111 and a third sub-dielectric layer 112 which are stacked; Figure 9 The method for forming the first dielectric layer includes:

[0082] Form the first sub-dielectric layer 110, which covers the top surface of the vertical dummy gate and the sidewall of the vertical dummy gate;

[0083] Form the second sub-dielectric layer 111, which covers the first sub-dielectric layer 110;

[0084] Form the third sub-dielectric layer 112, which covers the second sub-dielectric layer 111;

[0085] The first sub-dielectric layer 110, the second sub-dielectric layer 111 and the third sub-dielectric layer 112 covering the sidewall of the vertical dummy gate form the side wall.

[0086] Preferably, the material of the first sub-dielectric layer 110 and the third sub-dielectric layer 112 is silicon oxide;

[0087] The material of the second sub-dielectric layer 111 is silicon nitride.

[0088] Specifically, after the side wall is manufactured on both sides of the dummy gate, the structure after the side wall is manufactured is, in the direction from the gate to the outside, the first sub-dielectric layer 110 (silicon oxide), the second sub-dielectric layer 111 (silicon nitride) and the first sub-dielectric layer 112 (silicon oxide) in sequence.

[0089] As shown in FIG. 4, after the first dielectric layer is formed, the step further includes: performing ion implantation on the lightly-doped active region exposed around the side wall to form a heavily-doped active region 109.

[0090] Figure 10

[0091] ​​​S3: Form a second dielectric layer 113, which surrounds the sidewalls and covers the exposed surface of the silicon substrate 101 around the sidewalls, and the top surface of the second dielectric layer 113 is flush with the top surface of the vertical pseudo gate.

[0092] The method for forming the second dielectric layer 113 in this step specifically includes:

[0093] A second dielectric layer 113 is formed, which covers the surface of the silicon substrate 101 surrounding the vertical dummy gate and the top of the vertical dummy gate, and the height of the second dielectric layer 113 covering the surface of the silicon substrate 101 is greater than the height of the top of the vertical dummy gate; the material filling the second dielectric layer 113 is preferably SiO2, such as... Figure 11 As shown, the second dielectric layer 113 includes a first portion 113a located on the surface of the silicon substrate 101 and a second portion 113b located above the vertical dummy gate. After the dielectric is filled, the second portion 113b at the top of the dummy gate will be higher than the first portion 113a on its side.

[0094] Then as Figure 12 As shown, a planarization process is used to remove the first dielectric layer and the second dielectric layer 113 above the top of the vertical pseudo gate, and expose the top surface of the vertical pseudo gate.

[0095] S4: A first hard mask with a first opening is formed on the second dielectric layer 113 and the vertical pseudo gate. The width of the first opening is greater than the width of the vertical pseudo gate, and the first opening exposes the top of the vertical pseudo gate and the sidewall.

[0096] A first hard mask and a first patterned photoresist layer 117 are sequentially formed above the vertical dummy gate and the second dielectric layer 113. The patterned opening in the first patterned photoresist layer is located directly above the vertical dummy gate, and the width of the patterned opening is greater than the width of the vertical dummy gate.

[0097] Specifically, before removing the dummy gate using plasma etching, a mask is deposited on its upper surface, and photoresist is patterned, such as... Figure 13 As shown, the mask material used in the upper part before vertical pseudo-gate etching in this step is the same as the mask material used before etching the pseudo-gate (the film structure of 114-117 in the figure is the same). Figure 6The first hard mask includes, from bottom to top, an advanced pattern film layer 114 (APF), a dielectric anti-reflective layer 115 (DARC), and a bottom anti-reflective layer 116 (BARC), and the first patterned photoresist layer 117 is on the bottom anti-reflective layer 116. In the patterning process of the first patterned photoresist layer 117, the width k1 of the patterned opening should be greater than the lateral width k2 of the vertical dummy gate, and preferably, the k1 width is 40-120 nm. The width of the patterned opening in the photoresist layer determines the width of the first opening in the first hard mask, and the width of the first opening directly affects the angle of the trench sidewall after etching.

[0098] The etching method of the BARC, DARC, and APF layers under the first patterned photoresist layer 117 in this step is the same as the mask etching method before etching the vertical dummy gate in step S1. After the etching of the three mask layers is completed, as shown in FIG. 1F, the first opening exposing the top of the vertical dummy gate and the side wall is formed. Figure 14

[0099] S5: etching the vertical dummy gate and the side wall to remove the vertical dummy gate and form an etching trench in the inner side of the side wall, the sidewall of the etching trench is inclined, and the width of the top of the etching trench is greater than the width of the bottom of the etching trench.

[0100] The method for etching the vertical dummy gate and the side wall in this step includes:

[0101] The vertical dummy gate and the side wall are etched by using an etching gas until the vertical dummy gate is completely removed and the surface of the silicon substrate 101 is exposed at the bottom of the etching trench.

[0102] The etching gas includes a reaction gas and a sidewall protection gas, the reaction gas is used to etch the vertical dummy gate and the side wall, and the sidewall protection gas is used to form a protection layer on the sidewall of the etching trench during etching.

[0103] Preferably, the etching rate selection ratio of the second sacrificial layer to the side wall during etching the vertical dummy gate and the side wall is in the range of 0.9-1.1.

[0104] In this embodiment, the method for etching the vertical dummy gate and the side wall includes:

[0105] S501: performing a main etching step, etching the vertical dummy gate and the side wall by using a first etching gas, exposing the surface of the silicon substrate 101 at the bottom of the etching trench, and the width of the bottom of the etching trench is less than or equal to the width of the bottom of the vertical dummy gate.

[0106] As described above, in this embodiment, the materials of the first and second sacrificial layers constituting the vertical dummy gate are silicon oxide and polysilicon, respectively, and the materials of the first, second, and third sub-medium layers constituting the side wall are silicon oxide, silicon nitride, and silicon oxide, respectively.​

[0107] In the main etching step, the etching rate selection ratio of the second sacrificial layer 113 to the first or third sub dielectric layer 110, 112 is in the range of 0.9-1.1, the etching rate selection ratio of the second sacrificial layer 113 to the second sub dielectric layer 111 is in the range of 0.9-1.1, and the etching rate selection ratio of the second sub dielectric layer 111 to the first or third sub dielectric layer 110, 112 is in the range of 0.9-1.1. The etching rates of the three different materials (polysilicon, silicon oxide and silicon nitride) constituting the vertical pseudo gate and the sidewall are substantially consistent, and the polysilicon, silicon oxide and silicon nitride can be uniformly and simultaneously removed, thereby ensuring the smoothness of the etched trench sidewall.

[0108] Preferably, in the first etching gas, the reaction gas includes CF4 and CHF3, and the sidewall protection gas is O2; wherein the flow rate ratio of CF4 to CHF3 is in the range of 0.4-0.9, and the flow rate ratio of CF4 to O2 is in the range of 6-120.

[0109] S502: performing an over-etching step, and continuing to etch the sidewall and bottom of the etched trench by using a second etching gas to adjust the morphology of the etched trench, and make the width of the bottom of the etched trench greater than or equal to the width of the bottom of the vertical pseudo gate. Preferably, in the second etching gas, the reaction gas includes CHF3 and HBr, and the sidewall protection gas is O2; wherein the flow rate ratio of CHF3 to HBr is in the range of 0.5-1.5, and the flow rate ratio of HBr to O2 is in the range of 30-60.

[0110] Further, the first etching gas and the second etching gas can further include a dilution gas, and the dilution gas is used to dilute the plasma and adjust the uniformity of etching. Preferably, the dilution gas is He.

[0111] Specifically, the morphology of the etched trench directly determines the shape of the metal after the subsequent metal filling. In order to prepare a metal gate with a top width greater than a bottom width, the trench sidewall needs to be etched obliquely and smoothly in the process of removing the pseudo gate, and an upper wide and lower narrow trench is obtained after etching.

[0112] The above step S5 will be explained in more detail as follows.

[0113] As Figure 15As shown, the first sub dielectric layer 110 in the side wall structure is a silicon oxide thin layer side wall, the second sub dielectric layer 111 is a silicon nitride thin layer side wall, and the third sub dielectric layer 112 is a silicon oxide thin layer side wall. In the process of removing the vertical dummy gate, to ensure that the side wall of the etched trench is inclined and smooth, the dielectric side wall O-N-O (SiO2-Si3N4-SiO2) part of the side wall needs to be removed, that is, in the process of etching the trench, the three materials of polysilicon, silicon oxide and silicon nitride need to be removed uniformly at the same time, so as to ensure the smoothness of the etched trench side wall. The relatively difficult to volatilize silicon oxide compounds generated in the process of removing the three materials are deposited on the side wall as etching by-products, forming an inclined side wall morphology.

[0114] The key point is that the etching rates of the three materials by dry etching are equivalent, that is, the etching rates of the three materials by main etching step etching are close to each other, and the selection ratio between them is close to 1:1, so that the three materials can be removed uniformly at the same time. The selection ratio of the etching rates of polysilicon and silicon oxide in the etching process is in the range of 0.9-1.1; the selection ratio of the etching rates of polysilicon and silicon nitride is in the range of 0.9-1.1; and the selection ratio of the etching rates of silicon nitride and silicon oxide is in the range of 0.9-1.1. Under the main conditions of the etching formula, by adjusting the process parameters, the etching selection ratio of polysilicon and dielectric can be made to be 0.9-1.1. In addition, the deposition and coverage of the etching by-products on the side wall can obtain an inclined and smooth side wall morphology.

[0115] In the main etching step (ME) S501, the first etching gas used is preferably CF4, CHF3, O2 and He, wherein the main etching gas is CF4 and CHF3. The fluorine ions ionized from the two gases react with polysilicon, silicon nitride and silicon oxide to generate gaseous compounds such as silicon fluoride which are easy to volatilize and are extracted from the chamber. To ensure that the selection ratio of the etching of the dummy gate and its side wall is close to 1:1, the amount of the three main etching gases needs to be proportionally controlled. Preferably, the flow rate ratio of the main etching gas CF4 and CHF3 in the main etching step is in the range of 0.4-0.9. The reason for using this ratio is that the carbon ions and fluorine ions ionized from CHF3 are relatively low compared with CF4, and the flow rate of CHF3 is relatively high compared with CF4, which can prevent the rough morphology of the side part caused by the fast etching of polysilicon. O2 is a gas for adjusting the deposition of the side wall. The oxygen ions react with silicon ions to generate relatively difficult to volatilize silicon oxide deposits, part of which is deposited on the etched trench side wall, strengthening the protection of the side wall and reducing the etching of the side wall, that is, an inclined side wall morphology can be obtained. The amount of O2 cannot be too much, otherwise the etching rate will be low or the etching will stop abnormally. In this embodiment, the amount of O2 used is 0-20 sccm, and the ratio of the amount of CF4 to O2 is in the range of 6-120. The main function of He gas is to dilute the plasma and adjust the etching uniformity. The flow rate of He used in this step is preferably in the range of 0-150 sccm.

[0116] Through the above main etching step, the etching medium and the polysilicon selectivity ratio is close to 1:1, and the groove bottom formed after etching is close to the original pseudo gate bottom width k2. In the partial area etching to the bottom, the main etching step is stopped, and then the over-etching step is performed.

[0117] In the over-etching step (OE) S502, the second etching gas used is preferably CHF3, HBr, O2, He, the flow rate ratio of CHF3 and HBr used is in the range of 0.5-1.5, the flow rate ratio of HBr and O2 used is in the range of 30-60, and the said He has less effect on etching, and is mainly used for diluting plasma and adjusting etching uniformity. The He flow rate used in this step is preferably in the range of 100sccm-250sccm. The over-etching step has little effect on the overall etching morphology, and only completely etches the region that is not completely etched and slightly adjusts the morphology. The process chamber pressure is relatively high, the main purpose is to reduce the etching rate, reduce the damage to the bottom layer material, and slightly control the etching morphology and size, so that the etching groove bottom size after etching is greater than or equal to the original vertical pseudo gate bottom size k2.

[0118] In this embodiment, the process parameters of the main etching step are as follows:

[0119] The process chamber pressure is in the range of 5mt-10mt;

[0120] The source power is in the range of 400W-1000W;

[0121] The bias power is in the range of 50W-200W;

[0122] The CF4 gas flow rate is in the range of 20sccm-100sccm;

[0123] The CHF3 gas flow rate is in the range of 0sccm-100sccm;

[0124] The O2 gas flow rate is in the range of 0sccm-20sccm;

[0125] The He gas flow rate is in the range of 0sccm-150sccm;

[0126] The electrostatic chuck temperature is in the range of 30℃-60℃;

[0127] The etching time is in the range of 50s-150s.

[0128] The process parameters of the over-etching step are as follows:

[0129] The process chamber pressure is in the range of 10mt-70mt;

[0130] The source power is in the range of 400W-1000W;

[0131] The bias power range is 50W to 200W;

[0132] The CHF3 gas flow rate range is 0 sccm to 100 sccm;

[0133] The HBr gas flow rate range is 0 sccm to 100 sccm;

[0134] The O2 gas flow rate range is 2 sccm to 10 sccm;

[0135] The flow rate of He gas ranges from 100 sccm to 250 sccm;

[0136] The temperature range of the electrostatic chuck is 30℃~60℃;

[0137] The etching time ranges from 20s to 50s.

[0138] The typical formulation for the dummy gate removal etching process in this embodiment is shown in Table 2.

[0139] Table 2 Formulation of Etching Process for Removing Dummy Gate

[0140]

[0141] After the vertical dummy gate is removed by etching, as follows Figure 15 As shown, during the etching of the vertical pseudogate and sidewalls, the dielectric antireflective layer, the bottom antireflective layer, and part of the advanced patterning thin film layer are simultaneously removed.

[0142] S6: A gate dielectric layer is formed on the silicon substrate surface exposed at the bottom of the etch trench;

[0143] Specifically, after etching to remove the vertical dummy gate, high-dielectric material deposition (HK Dep) is performed, such as... Figure 16 As shown, a gate dielectric layer 118 is formed on the surface of the silicon substrate exposed at the bottom of the etched trench by a deposition process. The material of the gate dielectric layer 118 is preferably hafnium oxide or a high-dielectric hafnium-based compound.

[0144] S7: A metal material layer 119 is filled in the etched trench above the gate dielectric layer 118, and the metal material layer 119 and the gate dielectric layer 118 form a metal gate with a top width greater than the bottom width.

[0145] Specifically, the method for metal gate deposition in this step is as follows:

[0146] like Figure 17As shown, first, a metal material layer 119 is deposited on the silicon substrate, the metal material layer 119 includes a first metal layer 119a in the etching groove and a second metal layer 119b on the periphery thereof, and the material of the metal material layer 119 is preferably one or more combinations of titanium, titanium nitride, tantalum, tantalum nitride material.

[0147] After the deposition of the metal material layer 119, the first metal layer 119a deposited in the etching groove is not uniform in height with the second metal layer 119b on both sides thereof, and therefore a chemical mechanical polishing process is used for planarization treatment, the metal material layer 119 above the second dielectric layer 113 and the remaining advanced pattern thin film layer 114 are polished and removed, and finally the metal gate in the etching groove with the upper width larger than the lower width is the same in height with the surrounding dielectric layer. At this time, the high dielectric metal gate with the upper width larger than the lower width is manufactured, as shown in Figure 18

[0148] It should be noted that the metal gate with the upper width larger than the lower width to be prepared in the embodiment can be an inverted trapezoidal metal gate with the upper width larger than the lower width and the sidewall surface being substantially flat, or a metal gate with the upper width larger than the lower width and the sidewall surface having a certain curvature.

[0149] In addition, the film layer materials in the embodiment can be replaced, for example, the polysilicon sacrificial material in the vertical dummy gate can also be silicon oxide, silicon nitride, silicon oxynitride, etc., and when the sacrificial material is replaced, the etching process parameters are adjusted, and the same result can also be obtained.

[0150] In summary, the preparation method of the metal gate in the embodiment can precisely control the sidewall of the groove in the etching process by adjusting the dummy gate removal process, and finally the sidewall angle of the metal gate can be precisely controlled, and the process complexity can be effectively reduced.

[0151] The above has described the embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments.​

Claims

1. A method for fabricating a metal gate, characterized in that, include: A silicon substrate is provided, on which a vertical pseudo gate with vertical sidewalls is formed; A first dielectric layer is formed, which covers the sidewall of the vertical pseudogate and forms a sidewall; A second dielectric layer is formed, which surrounds the sidewall and covers the exposed silicon substrate surface around the sidewall, and the top surface of the second dielectric layer is flush with the top surface of the vertical dummy gate. A first hard mask with a first opening is formed on the second dielectric layer and the vertical pseudo-gate, the width of the first opening being greater than the width of the vertical pseudo-gate, and the first opening exposing the top of the vertical pseudo-gate and the sidewall; The vertical pseudo-gate and the sidewall are etched to remove the vertical pseudo-gate and form an etching trench inside the sidewall. The sidewall of the etching trench is inclined and the width of the top of the etching trench is greater than the width of the bottom of the etching trench. During the etching of the vertical pseudo-gate and the sidewall, the etching rate selection ratio of the vertical pseudo-gate to the sidewall is in the range of 0.9 to 1.

1. A gate dielectric layer is formed on the surface of the silicon substrate exposed at the bottom of the etched trench; A metal material layer is filled in the etched trench above the gate dielectric layer, and the metal material layer and the gate dielectric layer form a metal gate with a top width greater than the bottom width.

2. The preparation method according to claim 1, characterized in that, The etching of the vertical pseudo-gate and the sidewalls includes: The vertical dummy gate and the sidewalls are etched using an etching gas until the vertical dummy gate is completely removed and the bottom of the etch trench is exposed to the surface of the silicon substrate. The etching gas includes a reactive gas and a sidewall protection gas. The reactive gas is used to etch the vertical dummy gate and the sidewalls, and the sidewall protection gas is used to form a protective layer on the sidewalls of the etching trench during the etching process.

3. The preparation method according to claim 2, characterized in that, The vertical dummy gate includes a first sacrificial layer on the silicon substrate and a second sacrificial layer on the first sacrificial layer, wherein the thickness of the second sacrificial layer is greater than the thickness of the first sacrificial layer; The first dielectric layer includes a first sub-dielectric layer, a second sub-dielectric layer, and a third sub-dielectric layer stacked together, wherein the first sub-dielectric layer, the third sub-dielectric layer, and the first sacrificial layer are made of the same material; During the etching of the vertical pseudo gate and the sidewall, the etching rate selection ratio between the second sacrificial layer and the first sub-dielectric layer or the third sub-dielectric layer is in the range of 0.9 to 1.1; the etching rate selection ratio between the second sacrificial layer and the second sub-dielectric layer is in the range of 0.9 to 1.1; the etching rate selection ratio between the second sub-dielectric layer and the first sub-dielectric layer or the third sub-dielectric layer is in the range of 0.9 to 1.

1.

4. The preparation method according to claim 2, characterized in that, The process of etching the vertical dummy gate and the sidewalls using etching gas until the vertical dummy gate is completely removed and the bottom of the etching trench is exposed to reveal the surface of the silicon substrate specifically includes: The vertical dummy gate and the sidewall are etched using a first etching gas, so that the bottom of the etching trench is exposed on the surface of the silicon substrate, and the width of the bottom of the etching trench is less than or equal to the bottom width of the vertical dummy gate. The sidewalls and bottom of the etching trench are further etched using a second etching gas to adjust the morphology of the etching trench so that the bottom of the etching trench is fully exposed above the surface of the silicon substrate, and the width of the bottom of the etching trench is greater than or equal to the bottom width of the vertical dummy gate.

5. The preparation method according to claim 3, characterized in that, The materials of the first sacrificial layer, the first sub-dielectric layer, and the third sub-dielectric layer are all silicon oxide; The material of the second sacrificial layer is polycrystalline silicon; The material of the second sub-dielectric layer is silicon nitride.

6. The preparation method according to claim 4, characterized in that, The reactive gases in the first etching gas include CF4 and CHF3, and the sidewall protective gas in the first etching gas is O2; The flow ratio of CF4 to CHF3 ranges from 0.4 to 0.9, and the flow ratio of CF4 to O2 ranges from 6 to 120.

7. The preparation method according to claim 4, characterized in that, The reactive gases in the second etching gas include CHF3 and HBr, and the sidewall protective gas in the second etching gas is O2; The flow ratio of CHF3 to HBr ranges from 0.5 to 1.5, and the flow ratio of HBr to O2 ranges from 30 to 60.

8. The preparation method according to claim 4, characterized in that, The first etching gas and the second etching gas also include a dilution gas, which is used to dilute the plasma and adjust the uniformity of etching.

9. The preparation method according to claim 1, characterized in that, The material of the metal material layer is at least one of titanium, titanium nitride, tantalum, and tantalum nitride; The material of the gate dielectric layer is a hafnium-based compound; The material of the second dielectric layer is silicon oxide.

10. The preparation method according to claim 9, characterized in that, The hafnium-based compound is hafnium oxide.

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