Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

Embodiments of the present application belong to the technical field of semiconductor manufacturing, and particularly relate to a semiconductor structure and a manufacturing method of the semiconductor structure. Embodiments of the present application are used to solve the problems in the related art. The first conductive region and the second conductive region are located on two sides of the first gate structure, and the first conductive region and the second conductive region have different height positions in the direction perpendicular to the substrate. When a proper voltage is applied to the first gate structure, a first channel region capable of conducting electricity is formed between the first conductive region and the second conductive region and on the side close to the first gate structure. Since the first conductive region and the second conductive region have different height positions, the length of the first channel region is increased compared to the distance between the first conductive region and the second conductive region in the direction parallel to the surface of the substrate, which is conducive to reducing the leakage phenomenon of the semiconductor structure and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0002] Semiconductor structures include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which are used to perform functions such as switching and amplification. In related technologies, the channel length between the source and drain of a MOSFET is relatively short, resulting in a relatively large leakage current. Summary of the Invention

[0003] This invention provides a semiconductor structure and a method for fabricating the semiconductor structure, in order to solve the problem of the small length of the channel structure between the source and drain in related technologies.

[0004] On one hand, embodiments of the present invention provide a semiconductor structure, comprising:

[0005] A first gate structure, a first conductive region, and a second conductive region are located on a substrate. The first conductive region and the second conductive region are located on opposite sides of the first gate structure. In a direction perpendicular to the substrate, the first conductive region and the second conductive region have different height positions.

[0006] In one possible implementation, a first channel region is formed between the first conductive region and the second conductive region and on the side close to the first gate structure, the first channel region having a curved structure.

[0007] In one possible implementation, the height position of the first conductive region and the height position of the second conductive region have a height difference, the absolute value of which is greater than zero and less than the length value of the first channel region.

[0008] In one possible implementation, the first gate structure includes a first gate conductor block and a first gate dielectric layer, the first gate dielectric layer being located between the first gate structure and the substrate, the first gate dielectric layer having a curved structure.

[0009] In one possible implementation, the first gate dielectric layer is distributed in both the horizontal direction and the vertical direction along the substrate, and the first gate dielectric layer is continuously distributed.

[0010] In one possible implementation, the first gate conductor block has a first conductive layer and a second conductive layer, the first conductive layer being located between the second conductive layer and the first gate dielectric layer.

[0011] In one possible implementation, the bend in the curved structure of the first gate dielectric layer has an arc greater than 90 degrees.

[0012] In one feasible manner, the first gate structure, the first conductive region, and the second conductive region are electrically connected via a first plug, a second plug, and a third plug, respectively, in a direction perpendicular to the substrate.

[0013] In one possible implementation, a second gate structure and a third conductive region are further included on the substrate, the second conductive region and the third conductive region being located on opposite sides of the second gate structure, and the third conductive region having a different height position from the first conductive region in a direction perpendicular to the substrate.

[0014] In one possible implementation, a second channel region is formed between the third conductive region and the first conductive region and on the side close to the second gate structure, the second channel region having a curved structure.

[0015] In one possible implementation, the height position of the third conductive region has a height difference from the height position of the first conductive region, and the absolute value of the height difference between the third conductive region and the first conductive region is greater than zero and less than the length value of the second channel region.

[0016] In one possible implementation, the second gate structure includes a second gate conductor block and a second gate dielectric layer, the second gate dielectric layer being located between the second gate structure and the substrate, the second gate dielectric layer having a curved structure.

[0017] In one possible implementation, the second gate dielectric layer is distributed in both the horizontal direction and the vertical direction along the substrate, and the second gate dielectric layer is continuously distributed.

[0018] In one possible implementation, the second gate conductor block has a third conductive layer and a fourth conductive layer, the third conductive layer being located between the fourth conductive layer and the second gate dielectric layer.

[0019] In one possible implementation, the bend in the curved structure of the second gate dielectric layer has an arc greater than 90 degrees.

[0020] In one feasible manner, the second gate structure and the third conductive region are electrically connected via a fourth plug and a fifth plug, respectively, in a direction perpendicular to the substrate.

[0021] On the other hand, embodiments of the present invention also include a method for fabricating a semiconductor structure, comprising:

[0022] Provide substrate;

[0023] A first conductive region is formed on the substrate, and the first conductive region has a different height position from a predetermined surface of the substrate;

[0024] A first gate structure is formed, which is located on the predetermined surface on one side of the first conductive region;

[0025] A second conductive region is formed, which extends from the preset surface on one side of the first conductive region into the interior of the substrate, and the projection of the first conductive region on the preset surface is located outside the second conductive region.

[0026] In one feasible manner, forming the first conductive region includes:

[0027] A transition conductive region is formed, which extends from the surface of the substrate inward;

[0028] A first mask layer is formed, and the first mask layer has an etched pattern.

[0029] A portion of the substrate is removed, while the substrate corresponding to the etched pattern is retained to form the first conductive area and the preset surface.

[0030] In one feasible manner, forming the first gate structure includes:

[0031] A first gate dielectric layer is formed, which covers the preset surface and the first conductive region, and the first gate dielectric layer has a curved structure;

[0032] A first gate conductor block is formed, which is located on the preset surface on one side of the first conductive region.

[0033] In one feasible manner, forming the first gate conductor block includes:

[0034] A first conductive layer is formed, which covers the first gate dielectric layer;

[0035] A second conductive layer is formed, which covers the first conductive layer.

[0036] In one possible implementation, the bend in the curved structure of the first gate dielectric layer has an arc greater than 90 degrees.

[0037] In one possible implementation, a first channel region is formed between the first conductive region and the second conductive region and on the side close to the first gate structure, the first channel region having a curved structure.

[0038] In one possible implementation, the height position of the first conductive region and the height position of the second conductive region have a height difference, the absolute value of which is greater than zero and less than the length value of the first channel region.

[0039] In one feasible manner, forming the second conductive region includes:

[0040] A second mask layer is formed, on which the first hole is provided;

[0041] First ions are implanted to form a second conductive region on the substrate corresponding to the first hole.

[0042] In one possible implementation, after forming the second conductive region, the following is also included:

[0043] An isolation layer is formed, which covers the first conductive region, the first gate structure, and the preset surface;

[0044] A first plug, a second plug, and a third plug are formed, which penetrate the isolation layer and extend to the first conductive region, the second conductive region, and the first gate structure.

[0045] In one feasible manner, forming the isolation layer includes:

[0046] A first isolation layer is formed, which covers the first gate structure and the predetermined surface outside the first conductive region;

[0047] A portion of the first gate structure is removed to form a first groove extending into the substrate;

[0048] A second isolation layer is formed, which covers the first isolation layer and the first conductive region, and the second isolation layer fills the first groove.

[0049] In one possible implementation, after forming the first conductive region, the method further includes:

[0050] A second gate structure is formed on the preset surface on the other side of the first conductive region;

[0051] A third conductive region is formed, which extends from the preset surface on the other side of the first conductive region into the interior of the substrate, and the projection of the first conductive region on the preset surface is located outside the third conductive region.

[0052] In one feasible manner, forming the second gate structure includes:

[0053] A second gate dielectric layer is formed, which covers the preset surface and the first conductive region, and the second gate dielectric layer has a curved structure;

[0054] A second gate conductor block is formed, which is located on the preset surface on the other side of the first conductive region.

[0055] In one feasible manner, forming the second gate conductor block includes:

[0056] A third conductive layer is formed, which covers the second gate dielectric layer;

[0057] A fourth conductive layer is formed, which covers the third conductive layer.

[0058] In one possible implementation, the bend in the curved structure of the second gate dielectric layer has an arc greater than 90 degrees.

[0059] In one possible implementation, a second channel region is formed between the first conductive region and the third conductive region and on the side close to the second gate structure, the second channel region having a curved structure.

[0060] In one possible implementation, the height position of the first conductive region and the height position of the third conductive region have a height difference, the absolute value of which is greater than zero and less than the length value of the second channel region.

[0061] In one feasible manner, forming the third conductive region includes:

[0062] A second mask layer is formed, on which a second hole is provided;

[0063] A second ion is implanted to form a third conductive region on the substrate corresponding to the second hole.

[0064] In one possible implementation, after forming the third conductive region, the following is also included:

[0065] An isolation layer is formed, which covers the second gate structure;

[0066] A fourth plug and a fifth plug are formed, which penetrate the isolation layer and extend to the second gate structure and the third conductive region.

[0067] In one feasible manner, forming the isolation layer includes:

[0068] A first isolation layer is formed, which covers the predetermined surface outside the second gate structure and the third conductive region;

[0069] A portion of the second gate structure is removed to form a second groove extending into the substrate;

[0070] A second isolation layer is formed, which covers the first isolation layer and the first conductive region, and the second isolation layer fills the second groove.

[0071] The present invention provides a semiconductor structure and a method for fabricating the semiconductor structure. Specifically, the semiconductor structure includes a first gate structure, a first conductive region, and a second conductive region located on a substrate. The first and second conductive regions are located on opposite sides of the first gate structure, and have different heights in a direction perpendicular to the substrate. When an appropriate voltage is applied to the first gate structure, a first conductive channel region is formed between the first and second conductive regions, closer to the first gate structure. Because the first and second conductive regions have different heights, the length of the first channel region is increased compared to the distance between the first and second conductive regions in the direction parallel to the substrate surface. This increases the leakage current of the semiconductor structure and improves its performance. Attached Figure Description

[0072] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0074] Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0075] Figure 3 A schematic cross-sectional view of a substrate for a semiconductor structure provided in an embodiment of the present invention;

[0076] Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure forming a transition conductive region, provided as an embodiment of the present invention.

[0077] Figure 5 This is a cross-sectional schematic diagram of a semiconductor structure forming a first conductive region, provided as an embodiment of the present invention.

[0078] Figure 6 A cross-sectional schematic diagram of a semiconductor structure forming a first gate dielectric layer and a second gate dielectric layer is provided for an embodiment of the present invention;

[0079] Figure 7 A cross-sectional schematic diagram of a semiconductor structure forming a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, provided for an embodiment of the present invention;

[0080] Figure 8 A cross-sectional schematic diagram of a semiconductor structure with portions of a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer removed, provided for an embodiment of the present invention;

[0081] Figure 9 A cross-sectional schematic diagram of a semiconductor structure forming a first gate conductor block and a second gate conductor block is provided for an embodiment of the present invention;

[0082] Figure 10 This is a cross-sectional schematic diagram of a semiconductor structure forming a first isolation layer, provided in an embodiment of the present invention.

[0083] Figure 11 This is a cross-sectional schematic diagram of a semiconductor structure forming a first groove and a second groove, provided as an embodiment of the present invention;

[0084] Figure 12 This is a cross-sectional schematic diagram of a semiconductor structure forming a second isolation layer and a third isolation layer, provided as an embodiment of the present invention.

[0085] Figure 13 This is a cross-sectional schematic diagram of a semiconductor structure forming a contact hole, provided as an embodiment of the present invention.

[0086] Figure 14 This is a cross-sectional schematic diagram of a semiconductor structure forming a first plug, a second plug, a third plug, a fourth plug, and a fifth plug, provided for an embodiment of the present invention.

[0087] Explanation of reference numerals in the attached figures:

[0088] 10. Substrate; 101. Preset surface; 11. Shallow trench isolation section; 121. First conductive region; 122. Second conductive region; 123. Third conductive region; 1211. Transition conductive region;

[0089] 20. First gate structure; 21. First gate dielectric layer; 22. First gate conductor block; 221. First conductive layer; 222. Second conductive layer;

[0090] 30. Second gate structure; 31. Second gate dielectric layer; 32. Second gate conductor block; 321. Third conductive layer; 322. Fourth conductive layer;

[0091] 511. Third plug; 512. Fourth plug; 511. First plug; 521. Second plug; 523. Fifth plug;

[0092] 61. First hard mask layer; 62. First photoresist layer;

[0093] 71. Second hard mask layer; 72. Second photoresist layer;

[0094] 80. Isolation layer; 81. First isolation layer; 82. Second isolation layer; 83. Third isolation layer; 811. First groove; 812. Second groove; 84. Contact hole. Detailed Implementation

[0095] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0096] The terms "comprising" and "having" in this invention are used to indicate an open-ended meaning of inclusion, and refer to the presence of additional elements / components / etc. besides those listed. The terms "first" and "second," etc., are used only as labels and are not intended to limit the number of objects. In this invention, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" generally refer to the upper, lower, left, and right as shown in the accompanying drawings. "Inner" and "outer" refer to the inner and outer contours of the respective components. It is understood that the use of these relative directional terms in this specification is for convenience only; for example, according to the orientation of the examples described in the drawings, if the device in the icon is flipped upside down, the component described as "upper" will become the component described as "lower." In the drawings, the shapes shown may be deformed according to manufacturing processes and / or tolerances. Therefore, exemplary embodiments of the invention are not limited to the specific shapes shown in the drawings and may include shape changes caused during the manufacturing process. Furthermore, the different elements and areas in the drawings are only schematically shown, and therefore the invention is not limited to the dimensions or distances shown in the drawings.

[0097] To clearly understand the technical solution of this application, the solutions of related technologies will be described in detail first.

[0098] In related technologies, a MOSFET (or MOS transistor) includes a gate disposed on a substrate surface, a source and a drain disposed at a distance, and the projection of the gate onto the substrate lies between the source and drain. When an appropriate voltage is applied to the gate, a conductive channel structure can be formed between the source and drain. With the continuous development of the integrated circuit field, device dimensions are constantly shrinking, and the length of the channel structure between the source and drain in related technologies is also decreasing, making the semiconductor structure prone to leakage.

[0099] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure and a method for fabricating the semiconductor structure. A first conductive region and a second conductive region are located on opposite sides of the first gate structure. In a direction perpendicular to the substrate, the first conductive region and the second conductive region have different height positions. Compared to the distance between the first conductive region and the second conductive region in the direction parallel to the substrate surface, the length of the first channel region is increased, which helps to reduce leakage current in the semiconductor structure and improve the performance of the semiconductor structure.

[0100] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0101] For example, the semiconductor structure can be DRAM (Dynamic Random Access Memory), wherein the DRAM includes a transistor structure and a capacitor structure connected to the transistor structure. The capacitor structure is used to store data, and the transistor structure is used to read data from or write data to the capacitor structure. Of course, this embodiment is not limited to this, and the semiconductor structure in this embodiment can also be other structures. The transistor structure within the semiconductor structure can be a P-type MOS transistor or an N-type MOS transistor, and is not limited here.

[0102] like Figure 1 As shown, the semiconductor structure provided in this embodiment of the invention specifically includes: a first gate structure 20, a first conductive region 121, and a second conductive region 122 located on a substrate 10.

[0103] The substrate 10 can be a semiconductor substrate, such as single-crystal silicon, polycrystalline silicon, or amorphous silicon or silicon germanium (SiGe). It can also be a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors, or combinations thereof. This embodiment of the invention is not limited thereto.

[0104] The first gate structure 20 is located on the surface of the substrate 10. The first gate structure 20 includes a conductive layer, which may include one or more conductive materials. The conductive layer is used to connect with an externally applied voltage to control the conduction or disconnection of the semiconductor structure. The first gate structure 20 also includes an insulating material for protecting the first gate structure 20 from damage.

[0105] The first conductive region 121 and the second conductive region 122 are located within the substrate 10 and extend from the surface of the substrate 10 into the interior of the substrate 10. That is, the first conductive region 121 and the second conductive region 122 are located on both sides of the first gate structure 20.

[0106] For example, continue to refer to Figure 1 In a direction perpendicular to the substrate 10, the first conductive region 121 and the second conductive region 122 have different height positions. In the illustrated position, the surface of the substrate 10 where the first conductive region 121 is located is higher than the surface of the substrate 10 where the second conductive region 122 is located. Specifically, as shown... Figure 1 As shown, the substrate 10 has a "convex" structure. The first conductive region 121 is located in the convex structure of the substrate 10. The first gate structure 20 is located on one side of the first conductive region 121 and is located on the surface of the substrate 10. The second conductive region 122 is located on the other side of the first gate structure 20 and is located in the recessed structure of the substrate 10. In this embodiment, "convex" refers to the direction away from the interior of the substrate 10, and "recessed" refers to the direction close to the interior of the substrate 10.

[0107] It should be noted that the structure shown in the figure is only an example. In practical applications, the surface position of the substrate 10 where the first conductive region 121 is located may also be lower than the surface position of the substrate 10 where the second conductive region 122 is located. For example, the substrate 10 may have a "U"-shaped structure, with the first conductive region 121 located in the recessed structure of the substrate 10, the first gate structure 20 located on one side of the first conductive region 121 and on the surface of the substrate 10, and the second conductive region 122 located on the other side of the first gate structure 20 and in the protruding structure of the substrate 10.

[0108] In this embodiment, the first conductive region 121 can be the source region of the semiconductor structure, and the second conductive region 122 can be the drain region of the semiconductor structure. Of course, the first conductive region 121 can also be the drain region and the second conductive region 122 can be the source region. This is not limited here.

[0109] When an appropriate voltage is applied to the first gate structure 20, a first conductive channel region is formed between the first conductive region 121 and the second conductive region 122 and on the side closer to the first gate structure 20, so as to realize the function of the semiconductor structure.

[0110] This embodiment provides a semiconductor structure, specifically including: a first gate structure 20, a first conductive region 121, and a second conductive region 122 located on a substrate 10. The first conductive region 121 and the second conductive region 122 are located on opposite sides of the first gate structure 20, and have different height positions in a direction perpendicular to the substrate 10. When an appropriate voltage is applied to the first gate structure 20, a first conductive channel region is formed between the first conductive region 121 and the second conductive region 122, and on the side closer to the first gate structure 20. Because the first conductive region 121 and the second conductive region 122 have different height positions, the length of the first channel region is increased compared to the distance between the first conductive region 121 and the second conductive region 122 in the direction parallel to the surface of the substrate 10. This is beneficial for reducing leakage current in the semiconductor structure and improving its performance.

[0111] Furthermore, the semiconductor structure provided in this embodiment is also conducive to further reducing device size and improving device integration, thereby further improving device performance.

[0112] Optionally, the first channel region between the first conductive region 121 and the second conductive region 122 and on the side near the first gate structure 20 has a curved structure.

[0113] For example, refer to Figure 1 The first channel region includes a horizontal structure parallel to the surface of the substrate 10 and a vertical structure perpendicular to the surface of the substrate 10. The first channel region also includes a curved structure located between the horizontal and vertical portions. By setting the curved structure in the first channel region, it is beneficial to further increase the length of the first channel region, thereby further reducing the leakage phenomenon of the semiconductor structure.

[0114] Optionally, the height position of the first conductive region 121 and the height position of the second conductive region 122 have a height difference L1, the absolute value of the height difference L1 being greater than zero and less than the length value of the first channel region.

[0115] For example, as shown in the figure, the absolute value of the height difference L1 is the length of the vertical structure perpendicular to the surface of the substrate 10. In the embodiment where the position of the first conductive region 121 on the surface of the substrate 10 is lower than the position of the second conductive region 122 on the surface of the substrate 10, the absolute value of the height difference L1 is the length of the vertical structure perpendicular to the surface of the substrate 10. The length of the first channel region is the sum of the lengths of the horizontal structure, the vertical structure, and the curved structure. It can be seen that in both of the above semiconductor structures, the absolute value of the height difference L1 is greater than zero and less than the length of the first channel region.

[0116] Optionally, the first gate structure 20 includes a first gate conductor block 22 and a first gate dielectric layer 21, the first gate dielectric layer 21 being located between the first gate conductor block 22 and the substrate 10, and the first gate dielectric layer 21 having a curved structure.

[0117] For example, a first gate dielectric layer 21 covers the surface of the substrate 10. The first gate structure 20 is a curved structure covering the first channel region, and the first gate dielectric layer 21 also has a curved structure to isolate the first channel region and the first gate conductor block 22.

[0118] Optionally, the bend in the curved structure of the first gate dielectric layer 21 has an arc greater than 90 degrees. For example, the curved structure of the first gate dielectric layer 21 is disposed between the surface of the substrate 10 and the raised structure, and the curved structure is an arc with a central angle greater than 90 degrees to further isolate the first channel region and the first gate conductor block 22. In some other examples, the curved structure may also be a spline curve with a central angle greater than 90 degrees.

[0119] Optionally, the first gate dielectric layer 21 is distributed both along the horizontal direction and the vertical direction of the substrate 10, and the first gate dielectric layer 21 is continuously distributed. In one possible implementation, the first gate dielectric layer 21 can be formed by coating to ensure continuous distribution along the horizontal direction and the vertical direction of the substrate 10. The material of the first gate dielectric layer 21 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc.

[0120] Optionally, the first gate conductor block 22 has a first conductive layer 221 and a second conductive layer 222, with the first conductive layer 221 located between the second conductive layer 222 and the first gate dielectric layer 21. The materials of the first conductive layer 221 and the second conductive layer 222 can be different. In one possible implementation, the materials of the first conductive layer 221 and the second conductive layer 222 may include, for example, titanium nitride, polysilicon, tungsten, etc.

[0121] It is worth noting that, in the illustrated position, the first gate structure 20 and the second conductive region 122 are both located to the left of the first conductive region 121. The first gate structure 20, the first conductive region 121, the second conductive region 122 and the substrate 10 can form a transistor structure. To further improve the integration of the semiconductor structure, a structure symmetrical to the first conductive region 121 can also be formed to the right of the first conductive region 121 to form another transistor structure. Thus, under the condition of the same area, the number of transistors is greater, the integration is higher, and the channel length of a single transistor is longer.

[0122] Optionally, the semiconductor structure provided in this embodiment of the invention further includes a second gate structure 30 and a third conductive region 123 located on the substrate 10. The second conductive region 122 and the third conductive region 123 are located on both sides of the second gate structure 30. In the direction perpendicular to the substrate 10, the third conductive region 123 and the first conductive region 121 have different height positions.

[0123] For example, continue to refer to Figure 1 In a direction perpendicular to the substrate 10, the first conductive region 121 and the third conductive region 123 have different height positions. In the illustrated position, the surface of the substrate 10 where the first conductive region 121 is located is higher than the surface of the substrate 10 where the third conductive region 123 is located. Specifically, as shown... Figure 1 As shown, the substrate 10 has a "convex" structure. The first conductive region 121 is located in the protruding structure in the middle of the substrate 10. The first gate structure 20 is located on one side of the first conductive region 121, and the second gate structure 30 is located on the other side of the first conductive region 121. The second conductive region 122 is located on the other side of the first gate structure 20, and the second conductive region 122 is located in the recessed structure on the left side of the substrate 10. The third conductive region 123 is located on the other side of the second gate structure 30, and the third conductive region 123 is located in the recessed structure on the right side of the substrate 10.

[0124] In embodiments where the surface of the substrate 10 containing the first conductive region 121 is positioned lower than the surface of the substrate 10 containing the third conductive region 123, the substrate 10 may have a U-shaped structure. The first conductive region 121 is located in a recessed structure in the middle of the substrate 10, the first gate structure 20 is located on one side of the first conductive region 121, and the second gate structure 30 is located on the other side of the first conductive region 121. The second conductive region 122 is located on the other side of the first gate structure 20 and is situated in a protruding structure on the left side of the substrate 10. The third conductive region 123 is located on the other side of the second gate structure 30 and is situated in a protruding structure on the right side of the substrate 10.

[0125] In this embodiment, the first conductive region 121 can be the source region of the semiconductor structure, and the second conductive region 122 and the third conductive region 123 can be the drain regions of the semiconductor structure. Of course, the first conductive region 121 can also be the drain region, and the second conductive region 122 and the third conductive region 123 can be the source region. This is not limited here.

[0126] When an appropriate voltage is applied to the second gate structure 30, a conductive second channel region is formed between the first conductive region 121 and the third conductive region 123, and closer to the second gate structure 30, thereby realizing the function of the semiconductor structure. Since the first conductive region 121 and the third conductive region 123 have different height positions, the length of the second channel region is increased compared to the distance between the first conductive region 121 and the third conductive region 123 in the direction parallel to the surface of the substrate 10. This increases the length of the second channel region, which helps to reduce leakage current in the semiconductor structure and improve its performance.

[0127] Optionally, a second channel region is formed between the third conductive region 123 and the first conductive region 121 and on the side close to the second gate structure 30, and the second channel region has a curved structure.

[0128] For example, refer to Figure 1 The second channel region includes a horizontal structure parallel to the surface direction of the substrate 10 and a vertical structure perpendicular to the surface direction of the substrate 10. The second channel region also includes a curved structure located between the horizontal and vertical portions. By setting the curved structure in the second channel region, it is beneficial to further increase the length of the second channel region, thereby further reducing the leakage phenomenon of the semiconductor structure.

[0129] Optionally, the height position of the third conductive region 123 and the height position of the first conductive region 121 have a height difference L2, the absolute value of the height difference L2 being greater than zero and less than the length value of the second channel region.

[0130] For example, as shown in the figure, the absolute value of the height difference L2 is the length of the vertical structure perpendicular to the surface of the substrate 10. In the embodiment where the position of the first conductive region 121 on the surface of the substrate 10 is lower than the position of the third conductive region 123 on the surface of the substrate 10, the absolute value of the height difference L2 is the length of the vertical structure perpendicular to the surface of the substrate 10. The length of the second channel region is the sum of the lengths of the horizontal structure, the vertical structure, and the curved structure. It can be seen that in both of the above semiconductor structures, the absolute value of the height difference L1 is greater than zero and less than the length of the second channel region.

[0131] Optionally, the second gate structure 30 includes a second gate conductor block 32 and a second gate dielectric layer 31, the second gate dielectric layer 31 being located between the second gate structure 30 and the substrate 10, and the second gate dielectric layer 31 having a curved structure.

[0132] For example, the second gate dielectric layer 31 covers the surface of the substrate 10. The second gate structure 30 is a curved structure covering the second channel region, and the second gate structure 30 also has a curved structure to isolate the second channel region and the second gate conductor block 32.

[0133] Optionally, the bend in the curved structure of the second gate dielectric layer 31 has an arc greater than 90 degrees. Exemplarily, the curved structure of the second gate dielectric layer 31 is disposed between the surface of the substrate 10 and the protrusion structure, and the curved structure is an arc with a central angle greater than 90 degrees to further isolate the second channel region and the second gate dielectric layer 31. In some other examples, the curved structure may also be a spline curve with a central angle greater than 90 degrees.

[0134] Optionally, the second gate dielectric layer 31 is distributed both horizontally and vertically along the substrate 10, and the second gate dielectric layer 31 is continuously distributed. In one possible implementation, the second gate dielectric layer 31 can be formed by coating to ensure continuous distribution along both horizontally and vertically along the substrate 10. The material of the second gate dielectric layer 31 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc.

[0135] Optionally, the second gate conductor block 32 has a third conductive layer 321 and a fourth conductive layer 322, with the third conductive layer 321 located between the fourth conductive layer 322 and the second gate dielectric layer 31. To reduce the manufacturing cost of the semiconductor structure, the materials of the third conductive layer 321 and the fourth conductive layer 322 can be different. In one possible implementation, the materials of the third conductive layer 321 and the fourth conductive layer 322 may include, for example, titanium nitride, polycrystalline silicon, tungsten, etc.

[0136] Optionally, in a direction perpendicular to the substrate 10, the first plug 511, the second plug 521, and the third plug 522 are electrically connected to the first gate structure 20, the first conductive region 121, and the second conductive region 122, respectively. By providing the first plug 511, the second plug 521, and the third plug 522, electrical signals can be transmitted to the first gate structure 20, the first conductive region 121, and the second conductive region 122, respectively, to realize the function of the semiconductor structure.

[0137] Optionally, in a direction perpendicular to the substrate 10, the fourth plug 512 and the fifth plug 523 are electrically connected to the second gate structure 30 and the third conductive region 123, respectively. By providing the fourth plug 512 and the fifth plug 523, electrical signals can be conducted to the second gate structure 30 and the third conductive region 123, respectively, to realize the function of the semiconductor structure.

[0138] Specifically, the first plug 511, the second plug 521, the third plug 522, the fourth plug 512, and the fifth plug 523 are respectively inserted into the interior of the first gate structure 20, the first conductive region 121, the second conductive region 122, the second gate structure 30, and the third conductive region 123, thereby further improving the bonding strength of the plugs. In one possible implementation, an isolation layer 80 can be formed on the surface of the substrate 10, the first gate structure 20, and the second gate structure 30, and then a contact hole can be formed through the isolation layer 80. Finally, the contact hole is filled with a conductive material. The first plug 511, the second plug 521, the third plug 522, the fourth plug 512, and the fifth plug 523 can be formed simultaneously.

[0139] Specifically, as shown in the figure, the isolation layer 80 may include a first isolation layer 81, a second isolation layer 82, and a third isolation layer 83 stacked together. The first isolation layer 81 may cover the surfaces of the first gate structure 20, the second gate structure 30, and the substrate 10. The second isolation layer 82 covers the first isolation layer 81 and also covers the surface of the first conductive region. The third isolation layer 83 covers the second isolation layer 82. By setting the first isolation layer 81, the second isolation layer 82, and the third isolation layer 83, the semiconductor structure can be isolated, thereby further improving the performance of the semiconductor structure. In one possible implementation, the first isolation layer 81 and the second isolation layer 82 may be made of the same material, while the material of the third isolation layer 83 may be different from the materials of the first isolation layer 81 and the second isolation layer 82. The materials of the first isolation layer 81, the second isolation layer 82, and the third isolation layer 83 may include, for example, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0140] It should be noted that the semiconductor structure in this embodiment also includes shallow trench isolation portions 11, which are spaced apart within the substrate 10. The shallow trench isolation portions 11 are disposed perpendicular to the surface of the substrate 10 so that they can isolate active devices. For example, the shallow trench isolation portions 11 are located on the side of the second conductive region 122 opposite to the first gate structure 20, and the shallow trench isolation portions 11 are also located on the side of the third conductive region 123 opposite to the second gate structure 30. In one possible implementation, the material of the shallow trench isolation portions 11 may include silicon dioxide.

[0141] Based on the semiconductor structure of the above embodiments, another embodiment of the present invention also provides a method for fabricating a semiconductor structure, which can fabricate the above-mentioned semiconductor structure.

[0142] For example, the semiconductor structure can be DRAM (Dynamic Random Access Memory), wherein the DRAM includes a transistor structure and a capacitor structure connected to the transistor structure. The capacitor structure is used to store data, and the transistor structure is used to read data from or write data to the capacitor structure. Of course, this embodiment is not limited to this, and the semiconductor structure in this embodiment can also be other structures. The transistor structure within the semiconductor structure can be a P-type MOS transistor or an N-type MOS transistor, and is not limited here.

[0143] like Figure 2 As shown, the method for fabricating a semiconductor structure provided in this embodiment of the invention specifically includes:

[0144] Step S101: Provide a substrate.

[0145] like Figure 3 As shown, the substrate 10 can be a semiconductor substrate, such as single-crystal silicon, polycrystalline silicon, or amorphous silicon or silicon germanium (SiGe), or it can be a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors, or combinations thereof. The embodiments of the present invention are not limited thereto.

[0146] Shallow trench isolation portions 11 are also provided at intervals within the substrate 10. The shallow trench isolation portions 11 are disposed perpendicular to the surface of the substrate 10 so that the shallow trench isolation portions 11 can isolate active devices. In one possible implementation, the material of the shallow trench isolation portions 11 may include silicon dioxide.

[0147] Step S102: Form a first conductive region located on the substrate. The first conductive region has a different height position from the preset surface of the substrate.

[0148] For example, refer to Figure 4 , Figure 5 and Figure 6 In the illustrated position, the preset surface 101 of the substrate 10 is the upper surface of the substrate 10, and the first conductive region 121 is set above the preset surface 101. Specifically, the substrate 10 has a "convex" structure, and the first conductive region 121 is located in the protrusion structure in the middle of the substrate 10. In this embodiment, the "protrusion" is the direction away from the interior of the substrate 10, and the "recess" is the direction close to the interior of the substrate 10.

[0149] In one possible implementation, ions can be implanted onto the surface of the substrate 10 first, and then a portion of the substrate 10 can be etched to form a protrusion structure on the substrate 10. In another possible implementation, a protrusion structure can be formed on the substrate 10 first, and then ions can be implanted into the protrusion structure to form a first conductive region 121.

[0150] It should be noted that the structure shown in the figure is only an example. In practical applications, the first conductive region 121 can also be set below the preset surface 101. For example, the substrate 10 can also have a "U" structure, with the first conductive region 121 located in the recessed structure in the middle of the substrate 10.

[0151] Step S103: Form a first gate structure, which is located on a preset surface on one side of the first conductive region.

[0152] The first gate structure 20 is located on the preset surface 101. The first gate structure 20 includes a conductive layer, which may include one or more conductive materials. The conductive layer is used to connect with an externally applied voltage to control the conduction or disconnection of the semiconductor structure. The first gate structure 20 also includes an insulating material for protecting the first gate structure 20 from damage.

[0153] Step S104: Form a second conductive region, which extends from a preset surface on one side of the first conductive region into the substrate, and the projection of the first conductive region on the preset surface is located outside the second conductive region.

[0154] like Figure 8 As shown, the second conductive region 122 is located on the other side of the first gate structure 20. In one possible implementation, the first conductive region 121 can be formed in the substrate 10 by ion implantation.

[0155] Specifically, such as Figure 8 As shown, the substrate 10 has a "convex" structure. The first gate structure 20 is located on one side of the first conductive region 121 and is located on the surface of the substrate 10. The second conductive region 122 is located on the other side of the first gate structure 20 and is located in the recessed structure of the substrate 10.

[0156] In an embodiment where the first conductive region 121 is positioned below the preset surface 101, for example, the substrate 10 may have a U-shaped structure, with the first gate structure 20 located on one side of the first conductive region 121 and on the surface of the substrate 10, and the second conductive region 122 located on the other side of the first gate structure 20 and within the protrusion structure of the substrate 10.

[0157] In this embodiment, the first conductive region 121 can be the source region of the semiconductor structure, and the second conductive region 122 can be the drain region of the semiconductor structure. Of course, the first conductive region 121 can also be the drain region and the second conductive region 122 can be the source region. This is not limited here.

[0158] When an appropriate voltage is applied to the first gate structure 20, a first conductive channel region is formed between the first conductive region 121 and the second conductive region 122 and on the side closer to the first gate structure 20, so as to realize the function of the semiconductor structure.

[0159] This embodiment provides a method for fabricating a semiconductor structure, specifically including: providing a substrate 10; forming a first conductive region 121 located on the substrate 10, the first conductive region 121 having a different height position from a preset surface 101 of the substrate 10; forming a first gate structure 20 located on a preset surface 101 on one side of the first conductive region 121; forming a second conductive region 122 extending from the preset surface 101 on one side of the first conductive region 121 into the substrate 10, the projection of the first conductive region 121 onto the preset surface 101 located outside the second conductive region 122. When an appropriate voltage is applied to the first gate structure 20, a first conductive channel region is formed between the first conductive region 121 and the second conductive region 122, and closer to the first gate structure 20. Because the first conductive region 121 and the second conductive region 122 have different height positions, compared to the distance between the first conductive region 121 and the second conductive region 122 in the direction parallel to the surface of the substrate 10, the length of the first channel region is increased, which is beneficial to reduce leakage current in the semiconductor structure and improve the performance of the semiconductor structure.

[0160] Furthermore, the semiconductor structure provided in this embodiment is also conducive to further reducing device size and improving device integration, thereby further improving device performance.

[0161] Optionally, in the semiconductor fabrication method provided in this embodiment, the step of forming the first conductive region 121 includes: forming a transition conductive region 1211, which extends from the surface of the substrate 10 inward.

[0162] like Figure 4 As shown, a transition conductive region 1211 is disposed within the substrate 10 and extends inward from the surface of the substrate 10. In one possible implementation, the first conductive region 121 can be formed by implanting ions onto the surface of the substrate 10. Specifically, in embodiments where the substrate 10 includes a P-type substrate 10, N-type ions are implanted to form the transition conductive region 1211, while in embodiments where the substrate 10 includes an N-type substrate 10, P-type ions are implanted to form the transition conductive region 1211.

[0163] In this embodiment, after forming the transition conductive region 1211, the step of forming the first conductive region 121 further includes: forming a first mask layer, the first mask layer having an etching pattern.

[0164] like Figure 5As shown, a photolithography process can be used to transfer a pattern onto the substrate 10. The first mask layer includes a first hard mask layer 61 covering the substrate 10 and a first photoresist layer 62 covering the first hard mask layer 61. Through photolithography, an etched pattern is formed on the first photoresist layer 62. Then, an etching process is used to retain the first hard mask layer 61 corresponding to the etched pattern, so that the etched pattern can be transferred to the first hard mask layer 61. That is, the first mask layer has an etched pattern.

[0165] In this embodiment, after forming the first mask layer, the step of forming the first conductive region 121 further includes: removing part of the substrate 10 and retaining the substrate 10 corresponding to the etched pattern to form the first conductive region 121 and the preset surface 101.

[0166] An etching process can be used to remove a portion of the substrate 10. The removed portion of the substrate 10 extends from the surface of the substrate 10 into the interior of the substrate 10, so that the substrate 10 can form a "convex" structure. This allows the transition conductive region 1211 to be etched to form a first conductive region 121 located on the convex structure of the substrate 10, and the surface of the etched substrate 10 forms a predetermined surface 101. Specifically, the convex structure and the predetermined surface 101 are connected by rounded corners to facilitate the uniform distribution of subsequent film layers.

[0167] It is worth noting that, such as Figure 8 and Figure 9 As shown, the first gate structure 20 and the second conductive region 122 are both located to the left of the first conductive region 121. The first gate structure 20, the first conductive region 121, the second conductive region 122 and the substrate 10 can form a transistor structure. In order to further improve the integration of the semiconductor structure, a structure symmetrical to the first conductive region 121 can also be formed on the right side of the first conductive region 121 to form another transistor structure. This can further increase the transmission efficiency of the semiconductor structure and improve the performance of the semiconductor structure.

[0168] Optionally, in the semiconductor fabrication method provided in this embodiment, after forming the first conductive region 121, the method further includes: forming a second gate structure 30, which is located on a preset surface 101 on the other side of the first conductive region 121.

[0169] The second gate structure 30 is located on the preset surface 101. The second gate structure 30 includes a conductive layer, which may include one or more conductive materials. The conductive layer is used to connect with an externally applied voltage to control the conduction or disconnection of the semiconductor structure. The second gate structure 30 also includes an insulating material for protecting the second gate structure 30 from damage.

[0170] After forming the second gate structure 30, the method further includes forming a third conductive region 123, which extends from a preset surface 101 on the other side of the first conductive region 121 into the substrate 10, and the projection of the first conductive region 121 on the preset surface 101 is located outside the third conductive region 123.

[0171] Specifically, such as Figure 8 As shown, the substrate 10 has a "convex" structure. The first gate structure 20 is located on one side of the first conductive region 121, and the second gate structure 30 is located on the other side of the first conductive region 121. The second conductive region 122 is located on the other side of the first gate structure 20, and the second conductive region 122 is located in the recessed structure on the left side of the substrate 10. The third conductive region 123 is located on the other side of the second gate structure 30, and the third conductive region 123 is located in the recessed structure on the right side of the substrate 10.

[0172] In embodiments where the first conductive region 121 is positioned below the preset surface 101, for example, the substrate 10 may have a U-shaped structure, with the first gate structure 20 located on one side of the first conductive region 121 and the second gate structure 30 located on the other side of the first conductive region 121; the second conductive region 122 located on the other side of the first gate structure 20 and situated within a protrusion structure on the left side of the substrate 10; and the third conductive region 123 located on the other side of the second gate structure 30 and situated within a protrusion structure on the right side of the substrate 10.

[0173] In this embodiment, the first conductive region 121 can be the source region of the semiconductor structure, and the second conductive region 122 and the third conductive region 123 can be the drain regions of the semiconductor structure. Of course, the first conductive region 121 can also be the drain region, and the second conductive region 122 and the third conductive region 123 can be the source region. This is not limited here.

[0174] When an appropriate voltage is applied to the first gate structure 20, a second conductive channel region is formed between the first conductive region 121 and the third conductive region 123 and on the side closer to the first gate structure 20, so as to realize the function of the semiconductor structure.

[0175] Those skilled in the art will understand that, in order to improve manufacturing efficiency and reduce manufacturing costs, the first gate structure 20 and the second gate structure 30 can be formed simultaneously, as can the second conductive region 122 and the third conductive region 123.

[0176] Optionally, in the semiconductor fabrication method provided in this embodiment, the step of forming the first gate structure 20 includes: forming a first gate dielectric layer 21, which covers a preset surface 101 and a first conductive region 121, and the first gate dielectric layer 21 has a curved structure.

[0177] like Figure 7As shown, the first gate dielectric layer 21 is used to isolate the first gate structure 20 from the substrate 10. In one possible implementation, the first gate dielectric layer 21 can be formed by coating to ensure continuous distribution along the horizontal and vertical directions of the substrate 10, which helps protect the first gate conductor block 22 from damage. The material of the first gate dielectric layer 21 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc.

[0178] Optionally, the bend in the curved structure of the first gate dielectric layer 21 has an arc greater than 90 degrees. For example, see reference... Figure 6 The curved structure of the first gate dielectric layer 21 is disposed between the surface of the substrate 10 and the raised structure. The curved structure is in the form of an arc, and the central angle corresponding to the arc is greater than 90 degrees, so as to further isolate the first channel region and the first gate conductor block 22, thereby further protecting the first gate conductor block 22 from damage. In some other examples, the curved structure can also be in the form of a spline curve, and the central angle corresponding to the spline curve is greater than 90 degrees.

[0179] In this embodiment, after forming the first gate dielectric layer 21, forming the first gate structure 20 further includes forming a first gate conductor block 22, which is located on a preset surface 101 on one side of the first conductive region 121.

[0180] Specifically, such as Figure 8 As shown, forming the first gate conductor block 22 includes: forming a first conductive layer 221 that covers the first gate dielectric layer 21; and forming a second conductive layer 222 that covers the first conductive layer 221.

[0181] The materials of the first conductive layer 221 and the second conductive layer 222 can be different. In one possible implementation, the materials of the first conductive layer 221 and the second conductive layer 222 may include, for example, titanium nitride, polycrystalline silicon, tungsten, etc.

[0182] like Figure 8 and Figure 11 As shown, after forming the first conductive layer 221 and the second conductive layer 222, it is necessary to remove a portion of the first conductive layer 221 and the second conductive layer 222 in order to subsequently form the first gate structure 20.

[0183] The step of forming the second gate structure 30 while forming the first gate structure 20 includes: forming a second gate dielectric layer 31 that covers a preset surface 101 and a first conductive region 121, wherein the second gate dielectric layer 31 has a curved structure.

[0184] like Figure 7As shown, the second gate dielectric layer 31 is used to isolate the second gate structure 30 from the substrate 10. In one possible implementation, the second gate dielectric layer 31 can be formed simultaneously with the first gate dielectric layer 21 by coating, so as to be continuously distributed along the horizontal direction and the vertical direction of the substrate 10, which is beneficial to protect the second gate conductor block 32 from damage. The material of the second gate dielectric layer 31 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc.

[0185] Optionally, the bend in the curved structure of the second gate dielectric layer 31 has an arc greater than 90 degrees. For example, see reference... Figure 6 The curved structure of the second gate dielectric layer 31 is disposed between the surface of the substrate 10 and the raised structure. The curved structure is arc-shaped, and the central angle corresponding to the arc is greater than 90 degrees, so as to further isolate the second channel region and the second gate dielectric layer 31, thereby further protecting the second gate conductor block 32 from damage. In some other examples, the curved structure can also be a spline curve, and the central angle corresponding to the spline curve is greater than 90 degrees.

[0186] In this embodiment, after forming the second gate dielectric layer 31, forming the second gate structure 30 further includes forming a second gate conductor block 32, which is located on a preset surface 101 on the other side of the first conductive region 121.

[0187] Specifically, such as Figure 8 As shown, forming the second gate conductor block 32 includes: forming a third conductive layer 321 that covers the second gate dielectric layer 31; and forming a fourth conductive layer 322 that covers the third conductive layer 321.

[0188] To reduce the manufacturing cost of the semiconductor structure, the third conductive layer 321 and the fourth conductive layer 322 can be made of different materials. In one possible implementation, the materials of the third conductive layer 321 and the fourth conductive layer 322 may include, for example, titanium nitride, polycrystalline silicon, tungsten, etc.

[0189] like Figure 8 and Figure 11 As shown, after the third conductive layer 321 and the fourth conductive layer 322 are formed, a portion of the third conductive layer 321 and the fourth conductive layer 322 needs to be removed in order to form the second gate structure 30.

[0190] In this embodiment, the first conductive layer 221 and the third conductive layer 321 can be formed simultaneously, and the second conductive layer 222 and the fourth conductive layer 322 can be formed simultaneously, so as to improve manufacturing efficiency and reduce manufacturing cost.

[0191] like Figure 8 and Figure 9As shown, after forming the first conductive layer 221 and the third conductive layer 321, the second conductive layer 222 and the fourth conductive layer 322, it is necessary to remove one end of the first conductive layer 221 and the second conductive layer 222 that is away from the first conductive region 121 in order to form the second conductive region 122. It is also necessary to remove one end of the third conductive layer 321 and the fourth conductive layer 322 that is away from the first conductive region 121 in order to form the third conductive region 123.

[0192] Specifically, a second hard mask layer 71 and a second photoresist layer 72 can be stacked on the first conductive layer 221, the third conductive layer 321, the second conductive layer 222, and the fourth conductive layer 322. An etching pattern is formed on the second photoresist layer 72 using photolithography. Then, an etching process is used to retain the second hard mask layer 71 corresponding to the etching pattern, so that the etching pattern can be transferred to the second hard mask layer 71. Then, portions of the first conductive layer 221, the third conductive layer 321, the second conductive layer 222, and the fourth conductive layer 322 are removed, retaining the portions corresponding to the etching pattern, to form the first gate structure 20 and the second gate structure 30.

[0193] Furthermore, in this embodiment, in order to improve manufacturing efficiency and reduce manufacturing costs, the second conductive region 122 and the third conductive region 123 can be formed simultaneously.

[0194] Optionally, in the semiconductor structure fabrication method provided in this embodiment, the step of forming the second conductive region 122 includes: forming a second mask layer, on which a first hole is provided.

[0195] The first hole exposes a preset surface 101 on the side of the first gate structure 20 away from the first conductive region 121, which facilitates the subsequent formation of a second conductive region 122 on the side of the first gate structure 20 away from the first conductive region 121.

[0196] After forming the second mask layer, the step of forming the second conductive region 122 further includes: implanting first ions to form the second conductive region 122 on the substrate 10 corresponding to the first hole. Specifically, the second conductive region 122 extends from the preset surface 101 into the interior of the substrate 10.

[0197] Optionally, in the semiconductor structure fabrication method provided in this embodiment, the step of forming the third conductive region 123 includes: forming a second mask layer, on which a second hole is provided.

[0198] To ensure the simultaneous formation of the second conductive region 122 and the third conductive region 123, a first hole can be formed at one end of the second mask layer, while a second hole is formed at the other end of the second mask layer. The second hole exposes a predetermined surface 101 on the side of the second gate structure 30 facing away from the first conductive region 121, facilitating the subsequent formation of the third conductive region 123 on the side of the second gate structure 30 facing away from the first conductive region 121.

[0199] After forming the second mask layer, the step of forming the third conductive region 123 further includes: implanting second ions to form the third conductive region 123 on the substrate 10 corresponding to the second hole.

[0200] Specifically, in embodiments where the substrate 10 includes a P-type substrate 10, the implanted first and second ions are both N-type ions to form a second conductive region 122 and a third conductive region 123; while in embodiments where the substrate 10 includes an N-type substrate 10, the implanted first and second ions are both P-type ions to form a second conductive region 122 and a third conductive region 123.

[0201] Optionally, in the semiconductor structure fabrication method provided in this embodiment, after forming the second conductive region 122, the method further includes: forming an isolation layer that covers the first conductive region 121, the first gate structure 20, and the preset surface 101.

[0202] Specifically, forming the isolation layer includes forming a first isolation layer 81 that covers a preset surface 101 outside the first gate structure 20 and the first conductive region 121.

[0203] For example, such as Figure 10 As shown, the end of the first isolation layer 81 facing away from the preset surface 101 is flush with the first gate structure 20 and the first conductive region 121. In one possible implementation, the material of the first isolation layer 81 can be the same as that of the first gate dielectric layer 21 to further reduce production costs.

[0204] Optionally, after forming the first isolation layer 81, the step of forming the isolation layer further includes: removing a portion of the first gate structure 20 to form a first groove 811 extending into the substrate 10. By removing a portion of the first gate structure 20, the first gate structure 20 can be located between the first conductive region 121 and the second conductive region 122, thereby further forming a first channel region between the first conductive region 121 and the second conductive region 122, and on the side closer to the first gate structure 20.

[0205] Optionally, the first channel region between the first conductive region 121 and the second conductive region 122 and on the side near the first gate structure 20 has a curved structure.

[0206] For example, refer to Figure 11The first channel region includes a horizontal structure parallel to the surface of the substrate 10 and a vertical structure perpendicular to the surface of the substrate 10. The first channel region also includes a curved structure located between the horizontal and vertical portions. By setting the curved structure in the first channel region, it is beneficial to further increase the length of the first channel region, thereby further reducing the leakage phenomenon of the semiconductor structure.

[0207] Optionally, the height position of the first conductive region 121 and the height position of the second conductive region 122 have a height difference L1, the absolute value of the height difference L1 being greater than zero and less than the length value of the first channel region.

[0208] For example, as shown in the figure, the absolute value of the height difference L1 is the length of the vertical structure perpendicular to the surface of the substrate 10. In the embodiment where the position of the first conductive region 121 on the surface of the substrate 10 is lower than the position of the second conductive region 122 on the surface of the substrate 10, the absolute value of the height difference L1 is the length of the vertical structure perpendicular to the surface of the substrate 10. The length of the first channel region is the sum of the lengths of the horizontal structure, the vertical structure, and the curved structure. It can be seen that in both of the above semiconductor structures, the absolute value of the height difference is greater than zero and less than the length of the first channel region.

[0209] Optionally, after removing a portion of the first gate structure 20 to form a first recess 811 extending toward the substrate 10, the step of forming an isolation layer further includes: forming a second isolation layer 82 that covers the first isolation layer 81 and the first conductive region 121, and the second isolation layer 82 filling the first recess 811.

[0210] In one possible implementation, the material of the second isolation layer 82 can be the same as that of the first isolation layer 81 and the first gate dielectric layer 21, in order to further reduce production costs.

[0211] Furthermore, in this embodiment, to improve manufacturing efficiency and reduce manufacturing costs, an isolation layer is also applied to the second gate structure 30.

[0212] In this embodiment, the step of forming the first isolation layer 81 further includes: forming the first isolation layer 81, which covers the preset surface 101 outside the second gate structure 30 and the third conductive region 123.

[0213] In this embodiment, after forming the first isolation layer 81, the removal of a portion of the first gate structure 20 and a portion of the second gate structure 30 is also included to form a second groove 812 extending into the substrate 10. By removing a portion of the second gate structure 30, the second gate structure 30 can be located between the first conductive region 121 and the third conductive region 123, thereby further forming a second channel region between the first conductive region 121 and the third conductive region 123, and on the side closer to the second gate structure 30. Furthermore, the bottom of the first groove 811 is flush with the bottom of the second groove 812, thereby making the semiconductor structure more regular and improving the device performance of the semiconductor structure.

[0214] Optionally, the second channel region between the first conductive region 121 and the third conductive region 123 and on the side near the second gate structure 30 has a curved structure.

[0215] For example, refer to Figure 11 The second channel region includes a horizontal structure parallel to the surface direction of the substrate 10 and a vertical structure perpendicular to the surface direction of the substrate 10. The second channel region also includes a curved structure located between the horizontal and vertical portions. By setting the curved structure in the second channel region, it is beneficial to further increase the length of the second channel region, thereby further reducing the leakage phenomenon of the semiconductor structure.

[0216] Optionally, the height position of the first conductive region 121 and the height position of the third conductive region 123 have a height difference L2, the absolute value of the height difference L2 being greater than zero and less than the length value of the second channel region.

[0217] For example, as shown in the figure, the absolute value of the height difference L2 is the length of the vertical structure perpendicular to the surface of the substrate 10. In the embodiment where the position of the first conductive region 121 on the surface of the substrate 10 is lower than the position of the third conductive region 123 on the surface of the substrate 10, the absolute value of the height difference L2 is the length of the vertical structure perpendicular to the surface of the substrate 10. The length of the second channel region is the sum of the lengths of the horizontal structure, the vertical structure, and the curved structure. It can be seen that in both of the above semiconductor structures, the absolute value of the height difference is greater than zero and less than the length of the first channel region.

[0218] Optionally, after removing a portion of the second gate structure 30 to form a second recess 812 extending toward the substrate 10, the step of forming an isolation layer further includes: forming a second isolation layer 82 that covers the first isolation layer 81 and the first conductive region 121, and the second isolation layer 82 filling the second recess 812.

[0219] Reference Figure 12It should be noted that the isolation layer may also include a third isolation layer 83. After the second isolation layer 82 is formed, a third isolation layer 83 may be formed on the second isolation layer 82, and the third isolation layer 83 covers the second isolation layer 82. In one possible implementation, the material of the third isolation layer 83 may include silicon nitride, silicon oxide, silicon oxynitride, etc.

[0220] In this embodiment, after forming the isolation layer, conductive plugs are also formed. Specifically, this includes forming a first plug 511, a second plug 521, and a third plug 522, which penetrate the isolation layer and extend to the first conductive region 121, the second conductive region 122, and the first gate structure 20. This allows the first plug 511, the second plug 521, and the third plug 522 to be electrically connected to the first conductive region 121, the second conductive region 122, and the first gate structure 20, respectively, so that the first conductive region 121, the second conductive region 122, and the first gate structure 20 transmit electrical signals through the first plug 511, the second plug 521, and the third plug 522, respectively, to realize the function of the semiconductor structure.

[0221] In this embodiment, while forming the first plug 511, the second plug 521, and the third plug 522, a fourth plug 512 and a fifth plug 523 are also formed simultaneously. These plugs penetrate the isolation layer and extend to the second gate structure 30 and the third conductive region 123. This allows the fourth plug 512 and the fifth plug 523 to be electrically connected to the second gate structure 30 and the third conductive region 123, respectively, so that the second gate structure 30 and the third conductive region 123 can transmit electrical signals through the fourth plug 512 and the fifth plug 523, thereby realizing the function of the semiconductor structure.

[0222] like Figure 13 and Figure 14 Specifically, when forming the first plug 511, the second plug 521, the third plug 522, the fourth plug 512, and the fifth plug 523, a plurality of contact holes 84 can be formed through the isolation layer by etching. The bottom of the contact holes 84 are all located inside the first conductive region 121, the second conductive region 122, the first gate structure 20, the second gate structure 30, and the third conductive region 123. Then, conductive material is filled into the contact holes 84 to form the plugs.

[0223] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is merely an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0224] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A first gate structure, a first conductive region, and a second conductive region are located on a substrate. The first conductive region and the second conductive region are located on opposite sides of the first gate structure. In a direction perpendicular to the substrate, the first conductive region and the second conductive region have different height positions. It also includes a second gate structure and a third conductive region located on the substrate. The first conductive region and the third conductive region are located on both sides of the second gate structure. In the direction perpendicular to the substrate, the third conductive region and the first conductive region have different height positions. The substrate has a concave structure, with the first conductive area located on the substrate surface at a position lower than the second conductive area located on the substrate surface, and the first conductive area located on the substrate surface at a position lower than the third conductive area located on the substrate surface.

2. The semiconductor structure according to claim 1, characterized in that, A first channel region is formed between the first conductive region and the second conductive region and on the side closer to the first gate structure, and the first channel region has a curved structure.

3. The semiconductor structure according to claim 2, characterized in that, The height position of the first conductive region and the height position of the second conductive region have a height difference, and the absolute value of the height difference between the first conductive region and the second conductive region is greater than zero and less than the length value of the first channel region.

4. The semiconductor structure according to claim 1, characterized in that, The first gate structure includes a first gate conductor block and a first gate dielectric layer, the first gate dielectric layer being located between the first gate structure and the substrate, and the first gate dielectric layer having a curved structure.

5. The semiconductor structure according to claim 4, characterized in that, The first gate dielectric layer is distributed in both the horizontal direction and the vertical direction along the substrate, and the first gate dielectric layer is continuously distributed.

6. The semiconductor structure according to claim 4, characterized in that, The first gate conductor block has a first conductive layer and a second conductive layer, wherein the first conductive layer is located between the second conductive layer and the first gate dielectric layer.

7. The semiconductor structure according to claim 4, characterized in that, The bend in the curved structure of the first gate dielectric layer has an arc greater than 90 degrees.

8. The semiconductor structure according to claim 1, characterized in that, In a direction perpendicular to the substrate, the first plug, the second plug, and the third plug are electrically connected to the first gate structure, the first conductive region, and the second conductive region, respectively.

9. The semiconductor structure according to claim 1, characterized in that, A second channel region is formed between the third conductive region and the first conductive region and on the side closer to the second gate structure, and the second channel region has a curved structure.

10. The semiconductor structure according to claim 9, characterized in that, The height of the third conductive region has a height difference from that of the first conductive region, and the absolute value of the height difference between the third conductive region and the first conductive region is greater than zero and less than the length of the second channel region.

11. The semiconductor structure according to claim 1, characterized in that, The second gate structure includes a second gate conductor block and a second gate dielectric layer, the second gate dielectric layer being located between the second gate structure and the substrate, and the second gate dielectric layer having a curved structure.

12. The semiconductor structure according to claim 11, characterized in that, The second gate dielectric layer is distributed in both the horizontal direction and the vertical direction along the substrate, and the second gate dielectric layer is continuously distributed.

13. The semiconductor structure according to claim 11, characterized in that, The second gate conductor block has a third conductive layer and a fourth conductive layer, wherein the third conductive layer is located between the fourth conductive layer and the second gate dielectric layer.

14. The semiconductor structure according to claim 11, characterized in that, The bend in the curved structure of the second gate dielectric layer has an arc greater than 90 degrees.

15. The semiconductor structure according to claim 1, characterized in that, In a direction perpendicular to the substrate, the fourth plug and the fifth plug are electrically connected to the second gate structure and the third conductive region, respectively.

16. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first conductive region is formed on the substrate, and the first conductive region has a different height position from a predetermined surface of the substrate; A first gate structure is formed, which is located on the predetermined surface on one side of the first conductive region; A second conductive region is formed, which extends from the preset surface on one side of the first conductive region into the interior of the substrate, and the projection of the first conductive region on the preset surface is located outside the second conductive region; After forming the first conductive region, the process further includes: A second gate structure is formed on the preset surface on the other side of the first conductive region; A third conductive region is formed, which extends from the preset surface on the other side of the first conductive region into the interior of the substrate, and the projection of the first conductive region on the preset surface is located outside the third conductive region; The substrate has a concave structure, the substrate surface where the first conductive region is located is lower than the substrate surface where the second conductive region is located, and the substrate surface where the first conductive region is located is lower than the substrate surface where the third conductive region is located.

17. The method for fabricating a semiconductor structure according to claim 16, characterized in that, Forming the first conductive region includes: A transition conductive region is formed, which extends from the surface of the substrate inward; A first mask layer is formed, and the first mask layer has an etched pattern. A portion of the substrate is removed, while the substrate corresponding to the etched pattern is retained to form the first conductive area and the preset surface.

18. The method for fabricating a semiconductor structure according to claim 16, characterized in that, Forming the first gate structure includes: A first gate dielectric layer is formed, which covers the preset surface and the first conductive region, and the first gate dielectric layer has a curved structure; A first gate conductor block is formed, which is located on the preset surface on one side of the first conductive region.

19. The method for fabricating a semiconductor structure according to claim 18, characterized in that, Forming the first gate conductor block includes: A first conductive layer is formed, which covers the first gate dielectric layer; A second conductive layer is formed, which covers the first conductive layer.

20. The method for fabricating a semiconductor structure according to claim 18, characterized in that, The bend in the curved structure of the first gate dielectric layer has an arc greater than 90 degrees.

21. The method for fabricating a semiconductor structure according to claim 16, characterized in that, A first channel region is formed between the first conductive region and the second conductive region and on the side closer to the first gate structure, and the first channel region has a curved structure.

22. The method for fabricating a semiconductor structure according to claim 21, characterized in that, The height position of the first conductive region and the height position of the second conductive region have a height difference, and the absolute value of the height difference between the first conductive region and the second conductive region is greater than zero and less than the length value of the first channel region.

23. The method for fabricating a semiconductor structure according to claim 16, characterized in that, Forming the second conductive region includes: A second mask layer is formed, on which the first hole is provided; First ions are implanted to form a second conductive region on the substrate corresponding to the first hole.

24. The method for fabricating a semiconductor structure according to claim 16, characterized in that, After the formation of the second conductive region, the following steps are also included: An isolation layer is formed, which covers the first conductive region, the first gate structure, and the preset surface; A first plug, a second plug, and a third plug are formed, which penetrate the isolation layer and extend to the first conductive region, the second conductive region, and the first gate structure.

25. The method for fabricating a semiconductor structure according to claim 24, characterized in that, Forming the isolation layer includes: A first isolation layer is formed, which covers the first gate structure and the predetermined surface outside the first conductive region; A portion of the first gate structure is removed to form a first groove extending into the substrate; A second isolation layer is formed, which covers the first isolation layer and the first conductive region, and the second isolation layer fills the first groove.

26. The method for fabricating a semiconductor structure according to claim 16, characterized in that, Forming the second gate structure includes: A second gate dielectric layer is formed, which covers the preset surface and the first conductive region, and the second gate dielectric layer has a curved structure; A second gate conductor block is formed, which is located on the preset surface on the other side of the first conductive region.

27. The method for fabricating a semiconductor structure according to claim 26, characterized in that, Forming the second gate conductor block includes: A third conductive layer is formed, which covers the second gate dielectric layer; A fourth conductive layer is formed, which covers the third conductive layer.

28. The method for fabricating a semiconductor structure according to claim 26, characterized in that, The bend in the curved structure of the second gate dielectric layer has an arc greater than 90 degrees.

29. The method for fabricating a semiconductor structure according to claim 16, characterized in that, A second channel region is formed between the first conductive region and the third conductive region and on the side closer to the second gate structure, and the second channel region has a curved structure.

30. The method for fabricating a semiconductor structure according to claim 29, characterized in that, The height position of the first conductive region and the height position of the third conductive region have a height difference, and the absolute value of the height difference between the third conductive region and the first conductive region is greater than zero and less than the length value of the second channel region.

31. The method for fabricating a semiconductor structure according to claim 16, characterized in that, Forming the third conductive region includes: A second mask layer is formed, on which a second hole is provided; A second ion is implanted to form a third conductive region on the substrate corresponding to the second hole.

32. The method for fabricating a semiconductor structure according to claim 16, characterized in that, After the formation of the third conductive region, the following is also included: An isolation layer is formed, which covers the second gate structure; A fourth plug and a fifth plug are formed, which penetrate the isolation layer and extend to the second gate structure and the third conductive region.

33. The method for fabricating a semiconductor structure according to claim 32, characterized in that, Forming the isolation layer includes: A first isolation layer is formed, which covers the predetermined surface outside the second gate structure and the third conductive region; A portion of the second gate structure is removed to form a second groove extending into the substrate; A second isolation layer is formed, which covers the first isolation layer and the first conductive region, and the second isolation layer fills the second groove.

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