Partial current-reused voltage-controlled oscillator

Abstract

The present invention discloses a partial current-reused voltage-controlled oscillator, which includes a first NMOS transistor, a second NMOS transistor, a reverse-coupled differential transformer, and a variable capacitor array. The reverse-coupled differential transformer includes a first inductor, a second inductor, a third inductor, and a fourth inductor. There is a first forward coupling coefficient K1 between the first inductor and the third inductor, and a second reverse coupling coefficient K2 between the second inductor and the fourth inductor. The drain of the first NMOS transistor is connected to a power supply. The source of the first NMOS transistor is connected to one end of the first inductor. The gate of the first NMOS transistor is connected to one end of the third inductor, one end of the variable capacitor array, and serves as a first output terminal. The other end of the third inductor is connected to a first bias voltage. The other end of the first inductor is connected to a first input voltage through one end of the second inductor. The other end of the second inductor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and particularly relates to a partially current-reused voltage-controlled oscillator. Background Art

[0002] Currently, there is an increasing demand for higher data rate communications, and the operation of integrated circuits at higher frequencies such as millimeter waves has attracted more and more attention. For millimeter-wave transceivers, researchers have been working on improving the phase noise (PN) of voltage-controlled oscillators (VCOs) while avoiding sacrificing too much area and power.

[0003] Especially in the millimeter-wave band, the performance of phase-locked loops (PLLs) with integrated jitter less than 100 fs highly depends on the PN of the VCO. Although the PN performance of multi-core VCOs has been highly evaluated, the complexity of circuit and layout design and the large area are bottlenecks. Therefore, single-core structures such as class-B and class-C single-LC resonator VCOs, class-F, and class-F multi-resonator are still the first choices. In addition to PN, in millimeter-wave PLLs, the power consumption of the VCO is as high as 70%, and reducing the power consumption of the VCO is one of the most urgent problems. 2 Researchers have proposed several techniques, such as gate inductor feedback, active inductor, and third-harmonic extraction. However, gate inductor feedback enhances the oscillation of the system without suppressing PN. High power consumption hinders the wide application of active inductors. The high harmonic components are affected by their low amplitude, thus limiting the reduction of PN by the non-sinusoidal pulse sensitivity function.

[0004] Summary of the Invention In view of the above problems, the present invention provides a partially current-reused voltage-controlled oscillator to reduce the power consumption of the voltage-controlled oscillator while ensuring that the phase noise does not deteriorate much.

[0005] To solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A partially current-reused voltage-controlled oscillator includes a first NMOS transistor M

[0007] , a second NMOS transistor M U , a reverse-coupled differential transformer, and a variable capacitor array. The reverse-coupled differential transformer includes a first inductor L D , a second inductor L P1 , a third inductor L P2 , and a fourth inductor L S1 . There is a first forward coupling coefficient K between the first inductor L S2 and the third inductor L P1 , and between the third inductor L S1 and the first inductor L1 , the second inductor L P2 and the fourth inductor L S2 have a second reverse coupling coefficient K 2 , the drain of the first NMOS transistor M U is connected to the power supply, and the source of the first NMOS transistor M U is connected to one end of the first inductor L P1 , and the gate of the first NMOS transistor M U is connected to one end of the third inductor L S1 , one end of the variable capacitor array, and the first output terminal V ON , the other end of the third inductor L S1 is connected to the first bias voltage V BU , the other end of the first inductor L P1 is connected to one end of the second inductor L P2 and the first input voltage V M , the other end of the second inductor L P2 is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor M D is grounded, and the gate of the second NMOS transistor M D is connected to one end of the fourth inductor L S2 , the other end of the variable capacitor array, and the second output terminal V OP , the other end of the fourth inductor L S2 is connected to the second bias voltage V BD .

[0008] Preferably, the variable capacitor array includes a variable capacitor and a capacitor array, and the access of the capacitor array is controlled by a three-bit switch.

[0009] Preferably, the frequency of the partial current multiplexing voltage-controlled oscillator is adjusted by the variable DC modulation voltage V TUNE .

[0010] Preferably, the range of the variable DC modulation voltage V TUNE is 0 to 1.8V.

[0011] Preferably, the first NMOS transistor M U adopts gate-to-source feedback.

[0012] Preferably, the second NMOS transistor M D adopts gate-to-drain feedback.

[0013] Preferably, when laying out the circuit of the reverse-coupling differential transformer, the two inner coils adopt the AP layer, corresponding to the first inductor L P1 and the second inductor L P2 , and the two outer coils adopt the M7 layer, corresponding to the third inductor L S1 and the fourth inductor LS2 。

[0014] Preferably, the voltage of the power supply is 0.9V, and the first input voltage V M is 0.45V.

[0015] Preferably, the first bias voltage V BU is 1.25V.

[0016] Preferably, the second bias voltage V BD is 0.8V.

[0017] Adopting the present invention has the following beneficial effects:

[0018] (1) Reduce the time that the NMOS transistor M U works in the triode region, and reduce the noise brought by the transconductance G DS ;

[0019] (2) Adopt a reverse-coupled differential transformer to achieve two kinds of feedback with a smaller area;

[0020] (3) Adopt two NMOS stacks for partial current multiplexing to reduce power consumption.. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic circuit diagram of a partial current multiplexing voltage-controlled oscillator according to an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of power current and phase noise curves under different L P / L S in an embodiment of the present invention;

[0023] Figure 3 is a schematic circuit layout diagram of a reverse-coupled differential transformer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0025] Referring to Figure 1 , shown is a partial current multiplexing voltage-controlled oscillator according to an embodiment of the present invention, including a first NMOS transistor M U , a second NMOS transistor M D , a reverse-coupled differential transformer and a variable capacitor array. The reverse-coupled differential transformer includes a first inductor L P1, the second inductor L P2 , the third inductor L S1 and the fourth inductor L S2 , the first inductor L P1 and the third inductor L S1 have a first forward coupling coefficient K 1 between them. The second inductor L P2 and the fourth inductor L S2 have a second reverse coupling coefficient K 2 . The drain of the first NMOS transistor M U is connected to the power supply. The source of the first NMOS transistor M U is connected to one end of the first inductor L P1 . The gate of the first NMOS transistor M U is connected to one end of the third inductor L S1 , one end of the variable capacitor array, and the first output terminal V ON . The other end of the third inductor L S1 is connected to the first bias voltage V BU . The other end of the first inductor L P1 is connected to one end of the second inductor L P2 and the first input voltage V M . The other end of the second inductor L P2 is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor M D is grounded. The gate of the second NMOS transistor M D is connected to one end of the fourth inductor L S2 , the other end of the variable capacitor array, and the second output terminal V OP . The other end of the fourth inductor L S2 is connected to the second bias voltage V BD .

[0026] Furthermore, in an embodiment of the present invention, the variable capacitor array includes a variable capacitor and a capacitor array. The access of the capacitor array is controlled by a three-bit switch, and the frequency of the partial current multiplexing voltage-controlled oscillator is adjusted by the variable DC modulation voltage V TUNE .

[0027] In a specific application example of the present invention, the range of the variable DC modulation voltage V TUNE is 0 to 1.8V. The voltage of the power supply is 0.9V, and the first input voltage V M is 0.45V. The first bias voltage V BU is 1.25V. The second bias voltage V BD is 0.8V.

[0028] In a specific application example of the present invention, the first NMOS transistor M U employs gate-to-source feedback. The second NMOS transistor MD Use gate-to-drain feedback. In a full NMOS structure, a constant V D will result in a smaller conduction angle θ of the triode operating region, that is, the θ of the full NMOS NN is smaller than that of the traditional NMOS and PMOS stack, NP thereby reducing the phase noise brought by G DS . In the traditional current-multiplexing VCO, an NMOS and a PMOS with drain-to-gate (D2G) feedback are stacked. Due to the excessive swing at the drain terminal, the transistor operates in the triode region, thereby increasing the contribution of G DS to the phase noise.

[0029] In the embodiments of the present invention, the power current and phase noise under different L P / L S are shown in Figure 2 . When L P / L S = 1.25, the minimum current appears, and the phase noise decreases as the ratio increases. The circuit layout of the reverse-coupled differential transformer is as shown in Figure 3 . The two inner coils use the AP layer, corresponding to L P1 and L P2 , and the two outer coils use the M7 layer, corresponding to L S1 and L S2 . For the same magnetic field direction, the direction of the induced current is indicated by an arrow, indicating reverse coupling. The layout is highly compact, and all the ends connected to other parts of the circuit are on the same side to simplify placement and wiring. Additionally, a 3-bit controlled capacitor array is connected to L S to form a resonant cavity.

[0030] It should be understood that the exemplary embodiments described herein are illustrative and not restrictive. Although one or more embodiments of the present invention have been described in conjunction with the accompanying drawings, those of ordinary skill in the art should understand that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A partial current reuse voltage controlled oscillator, characterized in that, including a first NMOS transistor M U , a second NMOS transistor M D , a reverse-coupled differential transformer, and a variable capacitor array. The reverse-coupled differential transformer includes a first inductor L P1 , a second inductor L P2 , a third inductor L S1 and a fourth inductor L S2 . There is a first forward coupling coefficient K P1 between the first inductor L S1 and the third inductor L 1 , and a second reverse coupling coefficient K P2 between the second inductor L S2 and the fourth inductor L 2 . The drain of the first NMOS transistor M U is connected to a power supply. The source of the first NMOS transistor M U is connected to one end of the first inductor L P1 . The gate of the first NMOS transistor M U is connected to one end of the third inductor L S1 , one end of the variable capacitor array, and a first output terminal V ON . The other end of the third inductor L S1 is connected to a first bias voltage V BU . The other end of the first inductor L P1 is connected to one end of the second inductor L P2 and a first input voltage V M . The other end of the second inductor L P2 is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor M D is grounded. The gate of the second NMOS transistor M D is connected to one end of the fourth inductor L S2 , the other end of the variable capacitor array, and a second output terminal V OP . The other end of the fourth inductor L S2 is connected to a second bias voltage V BD .

2. The partial current reuse voltage controlled oscillator according to claim 1, characterized in that, the variable capacitor array includes a variable capacitor and a capacitor array, and the access of the capacitor array is controlled by a three-bit switch.

3. The partial current reuse voltage controlled oscillator according to claim 2, characterized in that, Adjust the frequency of the partial current multiplexed voltage controlled oscillator by the variable DC modulation voltage V TUNE ​ 4. The partial current reuse voltage controlled oscillator according to claim 1, characterized in that, Variable DC modulation voltage V TUNE ranges from 0 to 1.8V.

5. The partial current reuse voltage controlled oscillator according to claim 1, characterized in that, The first NMOS transistor M U Adopts gate-to-source feedback.

6. The partial current reuse voltage controlled oscillator according to claim 1, characterized in that, The second NMOS transistor M D Adopts gate-to-drain feedback.

7. The partial current reuse voltage controlled oscillator according to claim 1, characterized in that, When laying out the circuit of the reverse-coupled differential transformer, the two inner coils use the AP layer, corresponding to the first inductor L P1 and the second inductor L P2 , and the two outer coils use the M7 layer, corresponding to the third inductor L S1 and the fourth inductor L S2 .

8. The partial current reuse voltage controlled oscillator according to claim 1, characterized in that, The voltage of the power supply is 0.9V, and the first input voltage V M is 0.45V.

9. The partial current reuse voltage controlled oscillator according to claim 1, characterized in that, The first bias voltage V BU is 1.25 V.

10. The partial current reuse voltage controlled oscillator according to claim 1, characterized in that, The second bias voltage V BD is 0.8V.

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