A reconfigurable receiver with large dynamic anti-jamming

Abstract

The application discloses a large dynamic anti-interference reconfigurable receiver, and belongs to the technical field of communication, radar, electronic countermeasure and integrated radio frequency. The receiver is composed of a coupling amplification branch network, an array radio frequency amplification filter, an array scrambling mixing, an array intermediate frequency amplification filter, an array scrambling sampling, an array descrambling synthesis, a nonlinear equalization, a calibration and an interference generation module. Through the combination of interference cancellation, array synthesis, power backoff, forced scrambling and nonlinear equalization, the performance of specific devices is freed from the limitation of the performance of the receiver, the dynamic range and the anti-interference ability of the receiver are improved by multiple orders of magnitude, and the receiver is especially suitable for use in a receiving system in the technical field of communication, radar, electronic countermeasure and integrated radio frequency.

Description

Technical Field

[0001] This invention relates to the fields of communication, radar, electronic countermeasures and integrated radio frequency technology, and in particular to a reconfigurable receiver with high dynamic range and strong anti-interference capabilities. Background Technology

[0002] Receiving systems in communications, radar, electronic countermeasures, and integrated radio frequency fields all have requirements for receiver dynamic range. Receiver dynamics can be further subdivided into instantaneous dynamics, two-tone dynamics, single-tone dynamics, and spurious-free dynamics. Factors affecting these dynamics can be further subdivided into interference, third-order intermodulation, second-order intermodulation, mixing spuriouss, phase noise, and clock jitter. Traditional receiver designs, whether superheterodyne, zero-IF, or other architectures, are limited in dynamic performance by the core components in the link. Further performance improvements require the introduction of dynamic range enhancement techniques.

[0003] Current dynamic boosting techniques include nonlinear equalization, forced scrambling, polyphase mixing, and interference cancellation. Each technique has different applicable application scenarios, receiver solutions, and implementation effects. Nonlinear equalization has the advantage of canceling all nonlinear terms in the nonlinear inverse model, but it requires more digital resources and has a large computational load, which can affect the receiver's real-time performance. It also has limited ability to handle interference and mixing spurious signals. Forced scrambling is easy to implement and can handle mixing spurious signals, but it cannot be used with single-channel receivers and cannot handle the third-order intermodulation difference term, which mainly affects two-tone dynamics. Polyphase mixing, with the increase of mixing channels, can cancel higher-order combined spurious signals, but its cancellation is implemented in the analog domain, and its performance is still limited by device consistency. Interference cancellation can suppress external interference but cannot be used to suppress interference generated within the receiver. Summary of the Invention

[0004] To improve the receiver's dynamic range without compromising receiver sensitivity and to overcome the limitations imposed by device performance in the link, this invention improves and integrates techniques such as interference cancellation, array combining, power back-off, forced scrambling, and nonlinear equalization into a single scheme. These techniques have been simplified accordingly, reducing the overall complexity of the scheme while leveraging the key advantages of each technology, making it more suitable for engineering applications.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A reconfigurable receiver with high dynamic range and strong anti-interference capabilities includes a coupled amplification and splitter network module (A), an array RF amplification and filtering module with N channels (B), an array scrambling and mixing module with N channels (C), an array intermediate frequency amplification and filtering module with N channels (D), an array scrambling and sampling module with N channels (E), an array descrambling and synthesis module (F), a nonlinear equalization module (G), and a calibration and interference generation module (H); where N is a set value and N is a positive integer;

[0007] The Ai-1 port of the coupling amplification splitter network module (A) receives signals from the system front-end, and the Ai-R port receives calibration or interference cancellation signals generated by the calibration and interference generation module (H). After being coupled to the main path internally, the signals are split into N signals and output to the array RF amplification and filtering module (B) through N ports from Ao-1 to Ao-N.

[0008] The array RF amplification and filtering module (B) receives N signals from the coupling amplification and splitter network module (A) through its Bi-1 to Bi-N ports. After internal amplitude control, amplification, and filtering, the signals are output to the array scrambling and mixing module (C) through its Bo-1 to Bo-N ports.

[0009] The array scrambling mixer module (C) receives N signals output from the array RF amplifier and filter module (B) via its Ci-1 to Ci-N ports. Simultaneously, it synchronizes its N independent local oscillators using the reference clock input at the Ci-C port and the synchronization pulse input at the Ci-S port. It also receives ΔD through the Ci-D port. F After the scrambling vector completes the scrambling and mixing of the N signals, it is output from the Co-1 to Co-N ports to the array intermediate frequency amplification and filtering module (D).

[0010] The array intermediate frequency amplification and filtering module (D) receives N signals from the array scrambling and mixing module (C) through its Di-1 to Di-N ports. After internal amplification, amplitude control, and filtering, the signals are output to the array scrambling and sampling module (E) through its Do-1 to Do-N ports.

[0011] The array scrambling sampling module (E) receives N signals output from the array intermediate frequency amplification and filtering module (D) via ports Ei-1 to Ei-N, respectively. Simultaneously, it synchronizes the N independent sampling clocks internally through the reference clock input at port Ei-C and the synchronization pulse input at port Ei-S. The module receives ΔD through port Ei-D. F After the scrambling vector completes the scrambling and sampling of the N signals, it is output from the Eo-1 to Eo-N ports to the array descrambling and synthesis module (F);

[0012] The array descrambling synthesis module (F) receives N signals output from the array scrambling sampling module (E) through ports Fi-1 to Fi-N, respectively, internally achieving inter-channel amplitude and phase equalization, and receives ΔD through port Fi-D. R The inverse scrambling vector is descrambled and then beamformed into a single output channel via the Fo-1 port to the nonlinear equalization module (G).

[0013] The Gi-1 port of the nonlinear equalization module (G) receives the signal output from the array descrambling synthesis module (F). After processing by singular value decomposition, nonlinear compensation kernel coefficient solution, and nonlinear compensation filtering, the signal is output to the subsequent signal processing via the Go-1 port and to the calibration and interference generation module (H) via the Go-R port.

[0014] The calibration and interference generation module (H) generates the calibration signal required for nonlinear equalization and channel equalization, or processes and extracts the interference signal input from the Hi-R port, and outputs it from the Ho-R port to the coupling amplifier splitter network module (A) through internal digital-to-analog converter, mixer and signal conditioning.

[0015] Furthermore, the coupled amplification splitter network module (A) internally splits and connects to a total of N independently controllable receiving channels. The received signals of the N channels are synthesized through the array RF amplification and filtering module (B), the array scrambling and mixing module (C), the array intermediate frequency amplification and filtering module (D), the array scrambling and sampling module (E), and the array descrambling and synthesis module (F). By reducing the power of the received signals of the N independent channels, the influence of external interference and internal nonlinear products is reduced.

[0016] Furthermore, the array scrambling mixer module (C) and the array scrambling sampling module (E) employ N independent local oscillators and N independent sampling clocks, and achieve synchronization using a reference clock splitter and a synchronization signal. The resulting digital signal is synthesized by the array descrambling synthesis module (F).

[0017] Furthermore, random scrambling ΔD is introduced into the N independent local oscillators of the array scrambling mixer module (C) or the N independent sampling clocks of the array scrambling sampling module (E). F ΔD F The value is an additional random phase shift [exp(j·Δθ1),···, ... N )] or additional random frequency shift [exp(j·Δω1·t),···,exp(j·Δω N ·t)], and in the array descrambling synthesis module (F) in the inverse scrambling ΔD R ΔD R The corresponding additional phase shift is [exp(-j·Δθ1),···, ... NThe additional frequency shift is [exp(-j·Δω1·t),···,exp(-j·Δω] or [exp(-j·Δω]]. N ·t)], and then synthesized after the main signal is restored.

[0018] Furthermore, the nonlinear equalization module (G) is located after the array descrambling synthesis module (F). The nonlinear compensation filter inside the nonlinear equalization module (G) only compensates for the third-order cross-modulation term, adopts a compensation model with a memory depth of M, and the filter order is 2M.

[0019] Furthermore, the digital processing section inside the calibration and interference generation module (H) generates a calibration signal for nonlinear equalization or an inverse interference signal for interference cancellation. These signals are converted into analog signals by a digital-to-analog converter, and after up-conversion and signal conditioning, they are coupled into the main signal path through the Ai-R port of the input coupling amplification splitter network module (A).

[0020] Compared to other receiver designs, this invention has the following main advantages:

[0021] 1. By combining multiple dynamic enhancement technologies, the limitations of specific devices on the dynamic performance of the receiver are eliminated, and dynamic enhancement of several orders of magnitude is achieved without affecting the sensitivity, depending on the value of N.

[0022] 2. By using N independent local oscillators and sampling clocks, not only is the combined gain of phase noise and clock jitter achieved, correspondingly improving the instantaneous dynamic range by 10logN, but ΔD can also be introduced in the analog domain. F Thus, in the inverse scrambling ΔD R After synthesis, suppression of all nonlinear products except for the third-order cross-modulation term was obtained;

[0023] 3. In the digital domain, a memory polynomial inverse compensation model is adopted, which only includes third-order terms with a memory depth of M. This saves computing resources while only canceling the third-order crosstalk terms. By adjusting the value of M, it can adapt to different instantaneous bandwidths.

[0024] The calibration and inverse interference generation module introduced in section 4 can realize channel equalization calibration, nonlinear equalization and adaptive extraction of interference signals to complete the cancellation at the input end. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the receiver scheme of the present invention.

[0026] Figure 2 This is a schematic diagram of the coupling amplification splitter network module according to an embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram of the array radio frequency amplification and filtering module according to an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram of the array scrambling mixer module according to an embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of the array intermediate frequency amplification and filtering module according to an embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of the array scrambling sampling module according to an embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram of the array descrambling and synthesis module according to an embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram of the nonlinear equalization module in an embodiment of the present invention.

[0033] Figure 9 This is a schematic diagram of the calibration and interference generation module in an embodiment of the present invention. Detailed Implementation

[0034] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] like Figure 1 As shown, a reconfigurable receiver with high dynamic range and strong anti-interference capabilities includes a coupled amplification and splitter network module, an array RF amplification and filtering module with N channels, an array scrambling and mixing module with N channels, an array intermediate frequency amplification and filtering module with N channels, an array scrambling module with N channels, an array descrambling and synthesis module, a nonlinear equalization module, and a calibration and interference generation module; where N is a set value.

[0036] like Figure 2 As shown, the coupling amplification and splitting network module A consists of an A1 coupler, an A2 gain-adjustable amplifier, and an A3 splitter. The signals entering from the Ai-1 port and the Ai-C port are combined into one channel in the A1 coupler and then enter the A2 gain-adjustable amplifier. After amplification, the signal is split into N channels by the A3 splitter and then output through N ports from Ao-1 to Ao-N.

[0037] like Figure 3 As shown, the array RF amplification and filtering module B consists of N digitally controlled attenuators B1-1 to B1-N, N amplifiers B2-1 to B2-N, and N adjustable filters B3-1 to B3-N. The N signals input from ports Bi-1 to Bi-N are sequentially attenuated by B1, amplified by B2 for low noise, and finally bandpass filtered by B3 before being output from Bo-1 to Bo-N.

[0038] like Figure 4As shown, the array scrambling mixer module C consists of N mixers C1-1 to C1-N and N independent local oscillators C2-1 to C2-N. The N independent local oscillators are synchronized via a reference clock input to the Ci-C port and a synchronization signal output from the Ci-S port, and via a ΔD input to the Ci-D port. F Phase or amplitude scrambling is achieved. The N signals input from ports Ci-1 to Ci-N are frequency-converted and output from ports Co-1 to Co-N.

[0039] like Figure 5 As shown, the array intermediate frequency amplification and filtering module D consists of N amplifiers D1-1 to D1-N, N digitally controlled attenuators D2-1 to D2-N, N adjustable filters D3-1 to D3-N, and N final stage amplifiers D4-1 to D4-N. The N signals input from ports Di-1 to Di-N are sequentially amplified by D1, attenuated by D2, filtered by D3, and amplified by the final stage amplifier D4 before being output from Do-1 to Do-N.

[0040] like Figure 6 As shown, the array scrambling sampling module E consists of N samplers E1-1 to E1-N and N independent sampling clocks E2-1 to E2-N. The N independent clocks are synchronized via a reference clock input to the Ei-C port and a synchronization signal input to the Ei-S port, and via a ΔD input to the Ei-D port. F Phase scrambling is implemented. The N analog signals input from ports Ei-1 to Ei-N are sampled and transformed into the digital domain, and then output from Eo-1 to Eo-N.

[0041] like Figure 7 As shown, the array descrambling and synthesis module F consists of N equalization filters F1-1 to F1-N, N descrambling frequency shifters and phase shifters F2-1 to F2-N, and one synthesis module F3. The N signals input from ports Fi-1 to Fi-N are first equalized by the channels of F1, and then ΔD is input through port Fi-D. R The N-channel signals are descrambled, and finally F3 sums the digital signals of the N channels and outputs the result.

[0042] like Figure 8 As shown, the nonlinear equalization module G consists of a singular value decomposition module G1, a nonlinear compensation and coefficient solving module G2, and a nonlinear compensation filtering module G3. The signal entering from Gi-1 is decomposed using singular values, and then the nonlinear compensation kernel coefficients are obtained through matrix inversion. These coefficients are then provided to the reconfigurable nonlinear compensation filter for filtering, and finally output from Go-1 to the subsequent processing circuit. The Go-C output is used for interference cancellation extraction and the generation of calibration signals.

[0043] like Figure 9As shown, the calibration and interference generation module H consists of a calibration / interference signal generation module H1, an analog-to-digital converter (DAC) module H2, a mixer H3, a local oscillator H4, and a signal conditioning module H5. Interference signal information or calibration signals are extracted via the Hi-R converter. After being converted into analog signals by the DAC, the signals are up-converted by the mixer and local oscillator to be in the same frequency band as the input signal. The signal amplitude and phase are controlled by the signal conditioning circuit, and the signal is output from the Ho-R port to the coupling amplification and splitter network module A to complete the feedback loop.

[0044] In summary, this invention realizes a reconfigurable receiver with large dynamic range and strong anti-interference capability, which enables the receiver to be unaffected by the dynamic level of the device, effectively improving the instantaneous dynamic range, dual-tone dynamic range and anti-interference capability, and is particularly suitable for use in receiving systems in the fields of communication, radar, electronic countermeasures and integrated radio frequency technology.

Claims

1. A reconfigurable receiver with large dynamic anti-jamming, characterized in that, It comprises a coupling amplification branching network module (A), an array radio frequency amplification filter module (B) containing N channels, an array scrambling mixing module (C) containing N channels, an array intermediate frequency amplification filter module (D) containing N channels, an array scrambling sampling module (E) containing N channels, an array descrambling synthesis module (F), a nonlinear equalization module (G) and a calibration and interference generation module (H); wherein N is a set value, and N is a positive integer; The Ai-1 port of the coupling amplification branching network module (A) receives signals from the front stage of the system, the Ai-R port receives calibration or interference cancellation signals generated by the calibration and interference generation module (H), and after being coupled to the main path, the signals are branched into N signals, which are output to the array radio frequency amplification filter module (B) through the Ao-1 to Ao-N ports. The Bi-1 to Bi-N ports of the array radio frequency amplification filter module (B) respectively receive N signals output by the coupling amplification branching network module (A), and then perform amplitude control, amplification and filtering internally, and output to the array scrambling mixing module (C) through the Bo-1 to Bo-N ports. The Ci-1 to Ci-N ports of the array scrambling and mixing module (C) respectively receive N signals output by the array radio frequency amplification and filtering module (B), simultaneously input a reference clock through the Ci-C port and a synchronization pulse through the Ci-S port to realize synchronization of N independent local oscillators, and receive a scrambling vector through the Ci-D port After the scrambling vector is used to complete scrambling and mixing of the N signals, the Co-1 to Co-N ports output the signals to the array intermediate frequency amplification and filtering module (D). The Di-1 to Di-N ports of the array intermediate frequency amplification filter module (D) respectively receive N signals output by the array scrambling mixing module (C), and after performing amplification, amplitude control and filtering internally, output to the array scrambling sampling module (E) through the Do-1 to Do-N ports. The Ei-1 to Ei-N ports of the array scrambling sampling module (E) respectively receive N signals output by the array intermediate frequency amplification filtering module (D), and simultaneously realize synchronization of N independent sampling clocks through the reference clock input through the Ei-C port and the synchronization pulse input through the Ei-S port, and receive The scrambling vector is output to the array descrambling synthesis module (F) through the Eo-1 to Eo-N ports after completing scrambling and sampling of the N signals. The Fi-1 to Fi-N ports of the array descrambling and combining module (F) respectively receive N signals output by the array scrambling sampling module (E), realize inter-channel amplitude and phase equalization internally, and receive the signal output by the array descrambling and combining module (F) through the Fi-D port The inverse scrambling vector descrambling and beam combining are combined into one path, which is output through the Fo-1 port to the non-linear equalization module (G). The Gi-1 port of the nonlinear equalization module (G) receives signals output by the array descrambling synthesis module (F), and after singular value decomposition, nonlinear compensation kernel coefficient solving and nonlinear compensation filtering, outputs to the subsequent signal processing through the Go-1 port and outputs to the calibration and interference generation module (H) through the Go-R port. The calibration and interference generation module (H) generates calibration signals required for nonlinear equalization and channel equalization, or processes and extracts interference signals input through the Hi-R port, and outputs to the coupling amplification branching network module (A) through the Ho-R port after digital-to-analog conversion, mixing and signal conditioning.

2. A reconfigurable receiver with large dynamic anti-jamming according to claim 1, characterized in that, The coupling amplification branching network module (A) is connected with N independently controllable receiving channels after branching, and the receiving signals of the N independent channels are combined in the array radio frequency amplification filter module (B), the array scrambling mixing module (C), the array intermediate frequency amplification filter module (D), the array scrambling sampling module (E) and the array descrambling synthesis module (F), and the influence of external interference and internal nonlinear products is reduced by reducing the power of the N independent channel receiving signals.

3. A reconfigurable receiver with large dynamic anti-jamming according to claim 2, characterized in that, The array scrambling mixing module (C) and the array scrambling sampling module (E) use N independent local oscillators and N independent sampling clocks, and are synchronized by using reference clock branching and synchronization signals, and the obtained digital signals are combined by the array descrambling synthesis module (F).

4. A reconfigurable receiver with large dynamic anti-jamming according to claim 3, characterized in that, N independent local oscillator sources for array scrambling mixing module (C) or N independent sampling clocks for array scrambling sampling module (E) introduce random scrambling , with values being additional random phase shifts or additional random frequency shifts and inverse scrambling is introduced in array descrambling combining module (F) , with values being corresponding additional phase shifts or additional frequency shifts before the main signal is recovered and combined.

5. A reconfigurable receiver with large dynamic anti-jamming according to claim 4, characterized in that, The nonlinear equalization module (G) is located after the array descrambling synthesis module (F), and the nonlinear compensation filter in the nonlinear equalization module (G) only compensates for the third-order intermodulation difference, uses a compensation model with a memory depth of M, and the filter order is 2M.

6. A reconfigurable receiver with large dynamic anti-jamming according to claim 5, characterized in that, The calibration and interference generation module (H) generates calibration signals for non-linear equalization or generates inverse interference signals for interference cancellation inside the digital processing part, which are converted into analog signals by a digital-to-analog converter, and after up-conversion and signal conditioning, are input into the Ai-R port of the coupling and amplification shunt network module (A) to be coupled into the main signal path.

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