Semiconductor structure and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises: providing active regions and first isolation structures which are arranged at intervals; forming second isolation structures between adjacent active regions, the top surface of the second isolation structures being higher than or flush with the top surface of the active regions; forming a mask layer, a pattern opening of the mask layer exposing the top surface of part of the active regions, the second isolation structures being located on opposite sides of the part of the active regions; etching part of the active regions and part of the first isolation structures exposed by the pattern opening to form intermediate grooves, the intermediate grooves exposing at least part of the surface of the active regions; and forming bit line structures which are electrically connected to the top surface of the active regions exposed by the intermediate grooves. Embodiments of the present application are beneficial to improving the electrical performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and particularly to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Isolation media such as oxide or nitride play an extremely important role in the process of semiconductor chip manufacturing, for example, as insulating media and sacrificial media. A large number of isolation media exposed to the outside also brings some unavoidable troubles, for example, the etching process of other film layers may cause over-etching of the isolation media, thereby causing the film thickness of the isolation layer to not meet the requirements or even causing mutual crosstalk between conductive components.

[0003] At present, the method of improving the etching selectivity of etchants or etching gases is often used to reduce the over-etching of the isolation media. However, in many process scenarios, this method is difficult to play a role. SUMMARY

[0004] Embodiments of the present application provide a semiconductor structure and a forming method thereof, which are beneficial to improve the electrical performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present application provide a forming method of a semiconductor structure, comprising: providing active regions and first isolation structures arranged at intervals; forming a second isolation structure, the second isolation structure being located between adjacent active regions, and the top surface of the second isolation structure being higher than or flush with the top surface of the active region; forming a mask layer, the pattern opening of the mask layer exposing part of the top surface of the active region, and the second isolation structure being located on opposite sides of part of the active region; etching part of the active region and part of the first isolation structure exposed by the pattern opening to form an intermediate groove; and forming a bit line structure, the bit line structure being electrically connected with the top surface of the active region exposed by the intermediate groove.

[0006] In addition, the second isolation structure is located in the first isolation structure, and the first isolation structure isolates the second isolation structure and the active region.

[0007] In addition, the process steps of forming the first isolation structure and the second isolation structure comprise: forming active regions and initial isolation structures arranged at intervals, the top surface of the initial isolation structure being flush with the top surface of the active region; etching part of the thickness of the initial isolation structure to expose part of the sidewall of the active region; forming a supplementary layer, the supplementary layer covering the sidewall and the top surface of the active region and covering the top surface of the initial isolation structure, the supplementary layer and the remaining initial isolation structure constituting the first isolation structure; and forming a second isolation structure, the second isolation structure filling the gap surrounded by the supplementary layer, the top surface of the second isolation structure being flush with the top surface of the first isolation structure and being higher than the top surface of the active region.

[0008] In addition, the second isolation structure decreases in width in the arrangement direction of the active region in a direction from the top surface of the second isolation structure to the bottom surface of the second isolation structure.

[0009] In addition, the width of the top surface of the second isolation structure in the arrangement direction of the active region is 3-5 nm.

[0010] In addition, the thickness of the first isolation structure in a direction perpendicular to the top surface of the first isolation structure is 5-7 nm.

[0011] In addition, after the bit line structure is formed, the method further comprises: forming an isolation layer covering the sidewall of the bit line structure; forming an intermediate sidewall, the intermediate sidewall dividing a trench between adjacent bit line structures into a plurality of contact grooves; etching part of the active region under the contact grooves to form a capacitor contact window containing the contact grooves.

[0012] In addition, the bottom surface of the bit line structure is higher than or flush with the bottom surface of the second isolation structure.

[0013] In addition, the bottom surface of the capacitor contact window is higher than or flush with the bottom surface of the second isolation structure.

[0014] In addition, the bottom surface width of the second isolation structure in the arrangement direction of the active region is 1-5 nm.

[0015] In addition, the hardness of the second isolation structure is greater than the hardness of the first isolation structure.

[0016] In addition, the material of the second isolation structure comprises silicon nitride, and the material of the first isolation structure comprises silicon dioxide.

[0017] In addition, the intermediate groove is formed by a dry etching process, and the etching gas of the dry etching process is NF3.

[0018] Correspondingly, the embodiment of the present application further provides a semiconductor structure, comprising: a substrate, the substrate comprising an active region, a first isolation structure and a second isolation structure, the active region and the first isolation structure being arranged at intervals, the second isolation structure being located between adjacent active regions, the top surface of the second isolation structure being higher than or flush with the top surface of the active region; an intermediate groove located in the substrate, the intermediate groove exposing at least part of the surface of the active region, the second isolation structure being located on opposite sides of the intermediate groove; and a bit line structure, the bit line structure being electrically connected with the part of the active region exposed by the intermediate groove.

[0019] In addition, the isolation layer covers the sidewall of the bit line structure, and the intermediate sidewall is used to divide the trench between adjacent bit line structures into a plurality of capacitor contact windows, part of the capacitor contact windows are located in the substrate, and the capacitor contact windows expose the surface of the active region and at least part of the sidewall of the second isolation structure.

[0020] Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:

[0021] In the above technical scheme, the second isolation structure is provided, and since the material of the second isolation structure is different from that of the first isolation structure, when the first isolation structure and the active region are etched by using an etching component, the second isolation structure can block the diffusion of the etching component, so as to avoid exposing adjacent other active regions due to over-etching of the etching component, and further avoid the other active regions from being damaged in the subsequent process due to exposure, thereby improving the electrical performance of the semiconductor structure formed based on the active region.

[0022] In addition, the first isolation structure is located between the second isolation structure and the active region, and compared with the second isolation structure filling the gap between adjacent active regions, when the first isolation structure and the active region are etched to form an intermediate recess, in the arrangement direction of the bit line structure, the minimum width of the intermediate recess is larger, so as to be beneficial to reducing the resistance of the bit line contact of the bit line structure and improving the signal transmission performance of the bit line structure. BRIEF DESCRIPTION OF DRAWINGS

[0023] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the present embodiments, wherein elements having the same reference numbers designate corresponding elements and wherein the notation "and / or" is used to describe one or more possibilities.

[0024] Figures 1 to 8 The structure schematic diagram corresponding to each step of the semiconductor structure forming method is shown in the following figures.

[0025] Figures 9 to 20 The structure schematic diagram corresponding to each step of the semiconductor structure forming method provided by the embodiment of the application is shown in the following figures. DETAILED DESCRIPTION

[0026] REFERENCE Figures 1 to 8 , Figures 1 to 8 The structure schematic diagram corresponding to each step of the semiconductor structure forming method is shown in the following figures. Figure 2 The cross-sectional structure schematic diagram of the structure shown in FIG. Figure 1 The cross-sectional structure schematic diagram of the structure shown in FIG. Figure 6 The cross-sectional structure schematic diagram of the structure shown in FIG. Figure 5 The cross-sectional structure schematic diagram of the structure shown in FIG. Figures 2 to 4Only one pattern opening of the mask layer is shown, and for the sake of simplicity, etching gas and etching agent are collectively referred to as etching component.

[0027] Referring to Figure 1 and Figure 2 , the active regions 11 and the first isolation structures 10 are provided at intervals, and the first isolation structures 10 are used to isolate adjacent active regions 11; the mask layer 12 is formed, and the pattern openings 13 of the mask layer 12 expose the top surfaces of part of the active regions 11.

[0028] The material of the first isolation structures 10 is generally silicon dioxide or other low-cost materials, so as to facilitate mass filling; the pattern openings 13 are strip-shaped openings, and a plurality of pattern openings 13 are arranged in sequence, and the pattern openings 13 not only expose part of the top surfaces of the active regions 11, but also expose part of the top surfaces of the first isolation structures 10.

[0029] Referring to Figure 3 , the part of the active regions 11 and the part of the first isolation structures 10 exposed by the etching of the pattern openings 13 (see Figure 2 ) are etched to form the intermediate grooves 14.

[0030] In theory, in the arrangement direction of the pattern openings 13, the top opening width of the intermediate grooves 14 is equal to the width of the pattern openings 13, and the first isolation structures 10 isolate the intermediate grooves 14 and the adjacent active regions 11, however, due to over-etching of the etching component, the top opening width of the intermediate grooves 14 can be greater than the width of the pattern openings 13, and the intermediate grooves 14 can even expose the adjacent active regions 11. Figure 3 The top opening width of the intermediate grooves 14 of the structure shown is equal to the width of the pattern openings 13. In addition, during the etching process, due to the consumption and intermediate accumulation of the etching component, the etching rate gradually slows down, and finally the bottom width of the intermediate grooves 14 is less than the top opening width.

[0031] Referring to Figure 4 , the intermediate grooves 14 are cleaned.

[0032] After the etching process is performed, a cleaning process is needed to remove the excess etching component that has not reacted and the corresponding derivatives. In addition to the etching component consuming the material of the first isolation structures 10 due to over-etching, the cleaning agent of the cleaning process also consumes part of the material of the first isolation structures 10, so as to increase the width of the intermediate grooves 14.

[0033] If the intermediate groove 14 exposes the adjacent active region 11, subsequent process procedures can cause damage to the exposed active region 11, which can be in the form of material loss and / or material composition change, and further cause the electrical performance of the semiconductor structure based on the active region 11 to be damaged. For example, the damaged part of the active region 11 is used to connect with the capacitor contact hole, and due to the damage of the active region 11, the charging and discharging of the capacitor is affected.

[0034] Referring to Figure 5 and Figure 6 , the bit line structure 15, the first isolation layer 161, the second isolation layer 162 and the intermediate side wall 163 are formed.

[0035] The bit line structure 15 is in contact with the active region 11 through the bit line contact 151, the first isolation layer 161 covers the sidewall of the bit line structure 15, the second isolation layer 162 covers the sidewall of the first isolation layer 161, and covers the exposed top surface of the first isolation structure 10 and the active region 11; the intermediate side wall 162 divides the groove between the adjacent bit line structures 15 into a plurality of contact grooves, each contact groove corresponds to an active region 11, and each active region 11 is used to connect with a storage capacitor of a memory.

[0036] It should be noted that since the top opening width of the intermediate groove 14 is greater than the bottom width, and the upper and lower widths of the bit line contact 151 are equal, the second isolation layer 162 also fills the intermediate groove 14, and the thickness of the second isolation layer 162 located in the intermediate groove 14 gradually thins in the direction from the top of the intermediate groove 14 to the bottom. In the case where the intermediate groove 14 does not expose the adjacent active region 11, the second isolation layer 162 is located between the first isolation structure 10 and the first isolation layer 161. The material of the first isolation layer 161 can be the same as that of the first isolation structure 10, for example, silicon dioxide.

[0037] Referring to Figure 7 , the part of the second isolation layer, the part of the first isolation structure 10 and the part of the active region 11 located below the contact groove are etched in sequence to form a capacitor contact window 17 containing the contact groove.

[0038] Among them, the first isolation structure 10 isolates the capacitor contact window 17 from the adjacent active region 11, and the second isolation layer 162 isolates the capacitor contact window 17 from the adjacent bit line contact 151.

[0039] Referring to Figure 8 , the capacitor contact window 17 is cleaned.

[0040] During the cleaning process of capacitor contact window 17, the cleaning agent may further degrade the second isolation layer 162 and the first isolation structure 10, thereby exposing another adjacent conductive structure. If multiple conductive structures are exposed in capacitor contact window 17, the capacitor contact holes will be electrically connected to multiple conductive structures when forming capacitor contact holes that fill capacitor contact window 17, thereby causing signal crosstalk problems. The conductive structures include active region 11 and bit line contact 151. The cleaning agent may degrade the first isolation structure 10 to expose the adjacent active region 11, or it may degrade the second isolation layer 162 to expose the adjacent bit line contact 151.

[0041] It should be noted that not only may the additional losses caused by the cleaning process of the capacitor contact window 17 expose another adjacent conductive structure, but the over-etching caused by the forming process of the capacitor contact window 17 may also expose another adjacent conductive structure.

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0043] Figures 9 to 20 The diagram shows the structural schematics corresponding to each step of the semiconductor structure formation method provided in this embodiment of the invention. The specific method for forming the semiconductor structure is as follows:

[0044] refer to Figure 9 An active region 21 and an initial isolation structure 201a are formed at intervals. The top surface of the initial isolation structure 201a is flush with the top surface of the active region 21. The material of the initial isolation structure 201a includes silicon dioxide.

[0045] refer to Figure 10 The initial isolation structure 201a is etched to a certain thickness, and the remaining initial isolation structure 201a exposes the sidewall of the active region 21. In the direction perpendicular to the top surface of the initial isolation structure 201a, the thickness of the etched initial isolation structure 201a is related to the thickness of the second isolation structure to be subsequently set. The thicker the required second isolation structure, the thicker the etched initial isolation structure 201a.

[0046] refer to Figure 11 This forms a supplementary layer 201b and a second isolation membrane 202a.

[0047] A maskless deposition process is performed to form a supplementary layer 201b. The supplementary layer 201b covers the sidewalls and top surface of the active region 21 and the top surface of the remaining initial isolation structure 201a. The thickness of the supplementary layer 201b is less than 1 / 2 of the vertical distance between adjacent active regions 21. In this way, a gap can be left between adjacent active regions 21 to fill the second isolation structure 202. This gap is surrounded by the supplementary layer 201b. The initial isolation structure 201a and the supplementary layer 201b together constitute the first isolation structure 201. The second isolation film 202a fills the gap surrounded by the supplementary layer 201b and is located on the top surface of the supplementary layer 201b.

[0048] The material of the supplementary layer 201b can be the same as that of the initial isolation structure 201a, such as silicon dioxide. The hardness of the material of the second isolation film 202a can be greater than that of the material of the supplementary layer 201b, such as silicon nitride, to prevent over-etching of the etching components used to etch the supplementary layer 201b and the active region 21.

[0049] refer to Figure 12 A planarization process is performed to remove the second isolation membrane 202a (refer to) that is higher than the top surface of the first isolation structure 201. Figure 11 The remaining second isolation membrane 202a constitutes the second isolation structure 202.

[0050] In this embodiment, the top surface of the second isolation structure 202 is flush with the top surface of the first isolation structure 201 and higher than the top surface of the active region 21. The first isolation structure 201 and the second isolation structure 202 together fill the gap between adjacent active regions 21.

[0051] It can be known that, with the spacing between adjacent active regions 21 remaining constant, the width of the gap in the arrangement direction of the active regions 21 is related to the thickness of the supplementary layer 201b. The thinner the supplementary layer 201b, the wider the gap. Conversely, with the thickness of the supplementary layer 201b remaining constant, the width of the gap is related to the spacing between adjacent active regions 21. The larger the spacing between adjacent active regions 21, the wider the gap.

[0052] In this embodiment, during the planarization process, only the second isolation film 202a, which is higher than the top surface of the first isolation structure 201, is etched, while the supplementary layer 201b, which is higher than the top surface of the active region 21, is retained. This helps to avoid the grinding device applying tensile stress to the active region 21 during the planarization process, thereby preventing the active region 21 from shifting position and preventing the formation of an air gap between the active region 21 and the first isolation structure 201. This ensures that the active region 21 has high positional accuracy and good electrical performance. In addition, the first isolation structure 201, which is higher than the top surface of the active region 21, can be used to isolate the active region 21 from other film layers, allowing the active region 21 to selectively connect to the bit line structure or capacitor contact hole.

[0053] In this embodiment, the cross-sectional shape of the active region 21 is trapezoidal, that is, in the arrangement direction of the active region 21, the top surface width of the active region 21 is less than the bottom surface width of the active region 21, and in the direction from the top surface to the bottom surface of the active region 21, the width of the active region 21 in the arrangement direction increases. In this way, it is beneficial to increase the top portion spacing between adjacent active regions 21 and avoid over-etching of the etching component to expose the adjacent active region 21.

[0054] Correspondingly, since the active region 21 is trapezoidal, the gap between adjacent active regions 21 is inverted trapezoidal, that is, in the direction from the top surface to the bottom surface of the active region 21, the width of the gap decreases; further, since the thickness of the supplemental layer 201b at different positions is equal, the shape of the groove surrounded by the supplemental layer 201b depends on the shape of the gap between adjacent active regions 21, in the case that the shape of the gap is inverted trapezoidal, the shape of the groove surrounded by the supplemental layer 201b is also inverted trapezoidal, and the shape of the second isolation structure 202 filled in the groove is also inverted trapezoidal. That is, in the direction from the top surface of the first isolation structure 201 to the bottom surface of the first isolation structure 201, the width of the second isolation structure 202 in the arrangement direction of the active region 21 decreases. In this way, it is beneficial to increase the bottom portion spacing between adjacent second isolation structures 202, thereby increasing the maximum width of the bit line contact in contact with the active region 21 and improving the signal transmission performance of the bit line structure.

[0055] In this embodiment, with reference to Figure 13 , Figure 13 The position of part of the second isolation structure 202 and the position of the bit line structure 25 to be formed are shown, and in the plane where the top surface of the active region 21 is located, the orthographic projection of the second isolation structure 202 surrounds the top surface of the active region 21, that is, any line connecting adjacent active regions 21 passes through the second isolation structure 202. It should be noted that Figure 13 Only part of the second isolation structure 202 is shown, in fact, the orthographic projection of the second isolation structure 202 surrounds the top surface of each active region 21, and the second isolation structure 202 surrounding each active region 21 forms a closed loop.

[0056] In other embodiments, with reference to Figure 14 , the active region 21 has a contact region electrically connected to the bit line structure 25, and the second isolation structure 202 is located on one side of the contact region. Specifically, the second isolation structure 202 is composed of a plurality of discrete isolation strips, at least two isolation strips are located on the same straight line, the at least two isolation strips are parallel to each other, and the isolation strips are located between the contact regions of adjacent active regions 21. The length of each isolation strip can be set according to actual needs.

[0057] In yet another embodiment, with reference to Figure 15The second isolation structure 302 is located on the top surface of the first isolation structure 301. The second isolation structure 302 covers the active region 31. This helps to suppress over-etching in the subsequent etching process of the intermediate groove and avoids the intermediate groove from exposing the adjacent active region 31.

[0058] refer to Figure 16 A mask layer 22 is formed, and the mask layer 22 has patterned openings 23.

[0059] Within the plane containing the top surface of the active region 21, the active region 21 has a contact area that coincides with the orthographic projection of the pattern opening 23, and the second isolation structure 202 is located at least on opposite sides of the contact area. This helps to prevent over-etching by the etching components, thus avoiding exposure of adjacent active regions 21. Adjacent active regions 21 include active regions 21 connected to the same bit line structure and active regions 21 connected to different bit line structures.

[0060] refer to Figure 17 Through pattern opening 23 (reference) Figure 16 The active region 21 and the first isolation structure 201 are etched to form the intermediate groove 24.

[0061] As the etching components continuously decrease and accumulate towards the center during the etching process of the intermediate groove 24, the resulting intermediate groove 24 is always wider at the top and narrower at the bottom. To ensure that the top surface width of the active region 21 exposed by the intermediate groove 24 is greater than or equal to the width of the bit line structure, the width of the pattern opening 23 needs to be greater than the width of the bit line structure. In addition, to ensure effective contact between the bit line contact and the active region 21, the top surface width of the active region 21 exposed by the intermediate groove 24 should be greater than or equal to the width of the bit line structure. That is, the wider the bit line structure, the wider the top surface width of the active region 21 exposed by the intermediate groove 24, and the deeper the intermediate groove 24. To ensure that the second isolation structure 202 has a better isolation effect, in the direction perpendicular to the top surface of the first isolation structure 201, the bottom surface of the second isolation structure 202 is lower than or flush with the bottom surface of the intermediate groove 24.

[0062] Specifically, in the direction perpendicular to the top surface of the first isolation structure 201, the thickness of the second isolation structure 202 is 5nm to 7nm, for example, 5.5nm, 6nm or 6.5nm.

[0063] In the embodiment, the intermediate groove 24 exposes the sidewall surface of the second isolation structure 202. Since the concentration of the etching component is relatively high in the initial stage of etching the first isolation structure 201 and the active region 21, the over-etching of the etching component is relatively obvious. Therefore, the top of the second isolation structure 202 can be set to be relatively thick, so as to avoid the etching component from etching through the top surface of the second isolation structure 202, to avoid the intermediate groove 24 from exposing another adjacent active region 21, and to ensure that each bit line structure has good signal transmission performance. In addition, since the concentration of the etching component is relatively low in the later stage of the etching process, the over-etching of the etching component is relatively weak. Therefore, the bottom of the second isolation structure 202 can be set to be relatively thin, so as to increase the distance between the bottoms of adjacent second isolation structures 202, that is, to increase the width of the bottom surface of the bit line contact, and to improve the signal transmission performance of the bit line structure.

[0064] In the embodiment, the width of the top surface of the second isolation structure 202 in the arrangement direction of the active region 21 is 3 nm to 5 nm, for example, 3.5 nm, 4 nm, or 4.5 nm, and the width of the bottom surface of the second isolation structure 202 in the arrangement direction of the active region 21 is 1 nm to 5 nm, for example, 2 nm, 3 nm, or 4 nm.

[0065] In the embodiment, the etching selectivity ratio of the etching component for etching the first isolation structure 201 and the active region 21 to the material of the first isolation structure 201 and the material of the second isolation structure 202 is greater than 1, and the second isolation structure 202 has good barrier effect. Specifically, the hardness of the material of the second isolation structure 202 is greater than the hardness of the material of the first isolation structure 201. The material of the first isolation structure 201 includes silicon dioxide, and the material of the second isolation structure 202 includes silicon nitride.

[0066] In addition, the etching process for forming the intermediate groove 24 can be a dry etching process or a wet etching process. The etching gas of the dry etching process includes NF3, and the etchant of the wet etching process is a hydrofluoric acid solution.

[0067] Referring to FIG. 6, the intermediate groove 24 is formed. Figure 18 The intermediate groove 24 is cleaned.

[0068] In the case where the bottom surface of the second isolation structure 202 is flush with the bottom surface of the intermediate groove 24, a cleaning agent with weak selectivity is selected for cleaning, which is beneficial to avoid the intermediate groove 24 from bypassing the second isolation structure 202 to expose another adjacent active region 21.

[0069] Referring to FIG. 6, the intermediate groove 24 is formed. Figure 19 The bit line structure 25, the isolation layer, and the intermediate sidewall (not shown) are formed.

[0070] The bit line contact 251 in the bit line structure 25 contacts the active region 21, the isolation layer includes a first isolation layer 261 and a second isolation layer 262, the first isolation layer 261 covers opposite sidewalls of the bit line structure 25, the second isolation layer 262 covers sidewalls of the first isolation layer 261, a top surface of the bit line structure 25, a top surface of the first isolation structure 201 and an exposed surface of the second isolation structure 202, and a middle sidewall is located between adjacent bit line structures 25 to divide a groove between the adjacent bit line structures 25 into a plurality of contact recesses, each contact recess corresponding to an active region 21.

[0071] The material of the first isolation layer 261 has a hardness less than that of the material of the second isolation layer 262, the material of the first isolation layer 261 includes silicon dioxide or silicon oxynitride, and the material of the second isolation layer 262 includes silicon oxynitride or silicon nitride.

[0072] Reference Figure 20 The second isolation layer 262, part of the first isolation structure 201 and part of the active region 21 located below the contact recess are etched to form a capacitor contact window 27 containing the contact recess.

[0073] The capacitor contact window 27 exposes part of the surface of the active region 21, and the capacitor contact window 27 is used to fill a capacitor contact hole. To avoid the capacitor contact window 27 bypassing the second isolation structure 202 due to a depth greater than the lowest position of the second isolation structure 202, thereby exposing the bit line contact 251 or other active regions 21, the bottom surface of the second isolation structure 202 is preferably lower than or flush with the bottom surface of the capacitor contact window 27.

[0074] Similarly, to avoid the cleaning process of the capacitor contact window 27 further damaging the first isolation structure 201, causing the capacitor contact window 27 to expose the bit line contact 251 or other active regions 21, the bottom surface of the second isolation structure 202 is preferably lower than the bottom surface of the capacitor contact window 27.

[0075] In the embodiment, the second isolation structure is provided, and since the material of the second isolation structure is different from that of the first isolation structure, when the first isolation structure and the active region are etched by using an etching component, the second isolation structure can block the diffusion of the etching component, avoid exposing adjacent other active regions due to over-etching of the etching component, and further avoid damage to the other active regions due to exposure in the process, thereby improving the electrical performance of the semiconductor structure.

[0076] Correspondingly, the embodiment of the present application also provides a semiconductor structure which can be formed by using the forming method of the semiconductor structure.

[0077] Reference Figure 20The semiconductor structure comprises a substrate, the substrate comprises active regions 21, a first isolation structure 201 and a second isolation structure 202, the active regions 21 and the first isolation structure 201 are arranged at intervals, the second isolation structure 202 is located between adjacent active regions 21, and a top surface of the second isolation structure 202 is higher than or flush with a top surface of the active region 21; a middle groove 24 is located in the substrate, the middle groove 24 exposes at least part of a surface of the active region 21, and the second isolation structure 202 is located on opposite sides of the middle groove 24; and a bit line structure 25 is electrically connected with the active region 21 exposed by the middle groove 24.

[0078] An isolation layer (not marked) covers a side wall of the bit line structure 25, and a middle side wall (not marked) divides a groove between adjacent bit line structures 25 into a plurality of capacitor contact windows 27, part of the capacitor contact windows 27 are located in the substrate, and the capacitor contact windows 27 expose at least part of a side wall of the active region 21 and the second isolation structure 202.

[0079] The embodiment provides a new semiconductor structure, the first isolation structure and the second isolation structure are used for common isolation, the active layer is effectively protected, the active region has a preset structure and composition, and the semiconductor structure has good performance.

[0080] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present application, therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing spaced active regions and a first isolation structure; forming a second isolation structure between adjacent active regions, the top surface of the second isolation structure being higher than or flush with the top surface of the active regions; forming a mask layer, the pattern openings of the mask layer exposing part of the top surface of the active regions, the second isolation structure being located on opposite sides of part of the active regions; etching part of the active regions and part of the first isolation structure exposed by the pattern openings to form an intermediate groove; forming a bit line structure electrically connected to the top surface of the active regions exposed by the intermediate groove; the second isolation structure is located in the first isolation structure, and the first isolation structure isolates the second isolation structure and the active regions; the process steps for forming the first isolation structure and the second isolation structure comprise: forming spaced active regions and an initial isolation structure, the top surface of the initial isolation structure being flush with the top surface of the active regions; etching part of the thickness of the initial isolation structure to expose part of the sidewall of the active regions; forming a supplementary layer covering the sidewall and top surface of the active regions and covering the top surface of the initial isolation structure, the supplementary layer and the remaining initial isolation structure constituting the first isolation structure; forming a second isolation structure filling the gap surrounded by the supplementary layer, the top surface of the second isolation structure being flush with the top surface of the first isolation structure and higher than the top surface of the active regions.

2. The method of forming a semiconductor structure of claim 1, wherein, In the direction from the top surface of the first isolation structure towards the bottom surface of the first isolation structure, the width of the second isolation structure in the arrangement direction of the active regions decreases.

3. The method of forming a semiconductor structure of claim 2, wherein, The width of the top surface of the second isolation structure in the arrangement direction of the active regions is 3-5 nm.

4. The method of forming a semiconductor structure of claim 1, wherein, In the direction perpendicular to the top surface of the first isolation structure, the thickness of the second isolation structure is 5-7 nm.

5. The method of forming a semiconductor structure of claim 1, wherein, After forming the bit line structure, the method further comprises: forming an isolation layer covering the sidewall of the bit line structure; forming an intermediate sidewall dividing the trench between adjacent bit line structures into a plurality of contact grooves; etching part of the active regions located below the contact grooves to form a capacitor contact window containing the contact grooves.

6. The method of forming a semiconductor structure of claim 5, wherein, The bottom surface of the bit line structure is higher than or flush with the bottom surface of the second isolation structure.

7. The method of forming a semiconductor structure of claim 5, wherein, The bottom surface of the capacitor contact window is higher than or flush with the bottom surface of the second isolation structure.

8. The method of forming a semiconductor structure of claim 5, wherein, The bottom surface width of the second isolation structure in the arrangement direction of the active regions is 1-5 nm.

9. The method of forming a semiconductor structure of claim 1, wherein, The hardness of the second isolation structure is greater than the hardness of the first isolation structure.

10. The method of forming a semiconductor structure of claim 9, wherein, The material of the second isolation structure comprises silicon nitride, and the material of the first isolation structure comprises silicon dioxide.

11. The method of forming a semiconductor structure of claim 10, wherein, The etching process for forming the intermediate groove is a dry etching process, and the etching gas of the dry etching process is NF3.

12. A semiconductor structure, characterized by The method comprises the following steps: a substrate comprising active regions, a first isolation structure, and a second isolation structure, the active regions and the first isolation structure being spaced, the second isolation structure being located between adjacent active regions, the top surface of the second isolation structure being higher than or flush with the top surface of the active regions; a middle groove in the substrate, the middle groove exposing at least part of the surface of the active region, the second isolation structure being located on opposite sides of the middle groove; a bit line structure, the bit line structure being electrically connected to the part of the active region exposed by the middle groove.

13. The semiconductor structure of claim 12, wherein, Further comprising: an isolation layer, the isolation layer covering the sidewall of the bit line structure; a middle sidewall, the middle sidewall dividing the trench between adjacent bit line structures into a plurality of capacitor contact windows, part of the capacitor contact windows being located in the substrate, the capacitor contact windows exposing at least part of the sidewall of the second isolation structure and the surface of the active region.

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