Method for manufacturing a magnetic random access memory and magnetic random access memory

Abstract

The present invention provides a manufacturing method of a magnetic random access memory and a magnetic random access memory. The method includes: sequentially fabricating a bottom electrode via hole, a bottom electrode, a magnetic tunnel structure, a top electrode, and an insulating layer on a semiconductor substrate; forming a first interlayer dielectric layer on the insulating layer; forming an etch stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etch stop layer; etching the second interlayer dielectric layer above the top electrode to the etch stop layer to form a first trench; performing an inclined self-aligned implantation on the first interlayer dielectric layer corresponding to the bottom of the first trench; continuing to etch the first trench to the top end face of the top electrode to form a second trench, and the first trench and the second trench penetrate to form a via hole, and the critical dimension of the second trench gradually decreases from the bottom position of the first trench towards the direction close to the top electrode; filling a top electrode contact into the via hole. The manufacturing method of the present invention avoids the deterioration of the performance of the magnetic tunnel structure and improves the production yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a manufacturing method of a magnetic random access memory and a magnetic random access memory. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile random access memory that can retain its stored data when the power is off. MRAM includes a magnetic tunnel junction (MTJ), which makes MRAM have the characteristics of high-speed reading and writing, large capacity and low energy consumption.

[0003] In MRAM, a top electrode and a top electrode contact (TEC) are sequentially formed above the MTJ. In the prior art, a through hole or a groove is usually formed directly above the top electrode, and then a metal is deposited in the through hole or the groove to form a top electrode contact to achieve the interconnection between the MTJ and the TEC. However, in the process of etching to form a through hole or a groove, over-etching is prone to occur, making the critical dimensions of the through hole or the groove larger than the critical dimensions of the top electrode and the MTJ, and the etched portion is prone to extend to the packaging layer of the MTJ, resulting in deterioration of the MTJ performance, and the subsequent process may cause the MTJ to be contaminated by metal, and also make the final TEC mismatch with the MTJ, affecting the performance of the entire magnetic random access memory and reducing the production yield.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0005] A main object of the present invention is to provide a method for manufacturing a magnetic random access memory, which can accurately control the size of a via hole forming a top electrode, avoid over-etching and deterioration of the performance of a magnetic tunnel structure.

[0006] Another object of the present invention is to provide a magnetic random access memory, the top electrode contact of which matches the size of the magnetic tunnel structure and has a higher production yield.

[0007] According to one aspect of the present invention, a method for manufacturing a magnetic random access memory is provided, including: sequentially forming a bottom electrode via hole, a bottom electrode, a magnetic tunnel structure, a top electrode, and an insulating layer on a semiconductor substrate; forming a first interlayer dielectric layer on the insulating layer; forming an etch stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etch stop layer; etching the second interlayer dielectric layer above the top electrode to the etch stop layer to form a first trench; performing an inclined self-aligned implantation on the first interlayer dielectric layer corresponding to the bottom of the first trench to form a self-aligned implantation region; continuing to etch the first trench to the top end face of the top electrode to form a second trench, the first trench and the second trench communicate to form a via hole, and a critical dimension of the second trench gradually decreases from the bottom position of the first trench towards the direction close to the top electrode; filling a top electrode contact into the via hole.

[0008] According to an exemplary embodiment of the present invention, an implantation angle of the self-aligned implantation is an included angle between a self-aligned implantation direction and a first direction.

[0009] According to an exemplary embodiment of the present invention, the implantation angle is 70° to 90°.

[0010] According to an exemplary embodiment of the present invention, a cross section of the self-aligned implantation region is an inverted trapezoid, an ion implantation concentration in the self-aligned implantation region gradually decreases from the top end of the first interlayer dielectric layer towards the direction close to the top electrode, and / or, the ion implantation concentration in the self-aligned implantation region gradually decreases from a perpendicular bisector of the cross section of the self-aligned implantation region along the first direction towards both sides away from the perpendicular bisector.

[0011] According to an exemplary embodiment of the present invention, an implantation element of the self-aligned implantation is at least one of C, N, O, F, Ar, Ne, B, and Cl.

[0012] According to an exemplary embodiment of the present invention, a maximum critical dimension of the second trench is less than or equal to a minimum critical dimension of the first trench.

[0013] According to an exemplary embodiment of the present invention, an included angle exists between a side wall of the first trench and a side wall of the second trench, and the included angle is an obtuse angle.

[0014] According to an exemplary embodiment of the present invention, the continuing to etch the first trench to the top end face of the top electrode to form a second trench includes: sequentially etching the self-aligned implantation region and the insulating layer from the bottom of the first trench; wherein, an etch selectivity between the self-aligned implantation region in the first interlayer dielectric layer and a portion of the first interlayer dielectric layer where no self-aligned implantation is performed is greater than 1.

[0015] According to an exemplary embodiment of the present invention, the first interlayer dielectric layer, the etch stop layer, and the second interlayer dielectric layer are all formed by a deposition process, and the deposition process includes atomic layer deposition, chemical vapor deposition, physical vapor deposition, or spin coating.

[0016] According to an exemplary embodiment of the present invention, filling the top electrode contact into the via includes: depositing the top electrode contact in the via and on the upper surface of the second interlayer dielectric layer; removing the top electrode contact located on the upper surface of the second interlayer dielectric layer and the top electrode contact located at the top of the via and protruding from the upper surface of the second interlayer dielectric layer, so that the top electrode contact is flush with the second interlayer dielectric layer.

[0017] According to an exemplary embodiment of the present invention, the top electrode contact is tungsten or copper.

[0018] According to an exemplary embodiment of the present invention, the magnetic tunnel structure includes: a reference layer, a barrier layer, and a memory layer stacked in sequence.

[0019] According to an exemplary embodiment of the present invention, the first interlayer dielectric layer and the second interlayer dielectric layer each include at least one of silicon dioxide, silicon oxynitride, silicon nitride, and low-k dielectric.

[0020] According to an exemplary embodiment of the present invention, the etch stop layer includes at least one of silicon carbide, silicon nitride, silicon oxide, and silicon oxynitride.

[0021] According to another aspect of the present invention, there is provided a magnetic random access memory manufactured by the method described in any of the above embodiments.

[0022] It can be seen from the above technical solutions that the present invention has at least one of the following advantages and positive effects:

[0023] By providing an etch stop layer on the first interlayer dielectric layer, the first trench formed by etching stops at the etch stop layer, and then through self-aligned implantation, a self-aligned implantation region is formed in the first interlayer dielectric layer, improving the etch selectivity of the self-aligned implantation region. During subsequent etching, the size of the via can be accurately controlled, improving the controllability of forming the via and the uniformity of the size, avoiding the key dimensions of the through hole or trench being larger than the key dimensions of the top electrode and the MTJ due to over-etching, thereby avoiding the deterioration of the performance of the magnetic tunnel structure and being contaminated by metal in subsequent processes, and at the same time improving the production yield of the magnetic random access memory. Description of the Drawings

[0024] The above and other features and advantages of the present invention will become more apparent by describing its exemplary embodiments in detail with reference to the accompanying drawings.

[0025] Figure 1 A flowchart of a manufacturing method shown in an exemplary embodiment of the present invention;

[0026] Figure 2 A schematic structural diagram of a bottom electrode via, a bottom electrode, a magnetic tunnel structure, a top electrode, and an insulating layer formed on a semiconductor substrate shown in an exemplary embodiment of the present invention;

[0027] Figure 3 A schematic diagram of forming a first interlayer dielectric layer shown in an exemplary embodiment of the present invention;

[0028] Figure 4 A schematic diagram of the ground after grinding the first interlayer dielectric layer shown in an exemplary embodiment of the present invention;

[0029] Figure 5 A schematic diagram of forming an etch stop layer shown in an exemplary embodiment of the present invention;

[0030] Figure 6 A schematic diagram of forming a second interlayer dielectric layer shown in an exemplary embodiment of the present invention;

[0031] Figure 7 A schematic diagram of forming a first trench shown in an exemplary embodiment of the present invention;

[0032] Figure 8 A schematic diagram of a self-aligned injection for tilting the bottom of the first trench shown in an exemplary embodiment of the present invention;

[0033] Figure 9 A schematic diagram of forming a via shown in an exemplary embodiment of the present invention;

[0034] Figure 10 A schematic diagram of filling a top electrode contact in the via shown in an exemplary embodiment of the present invention;

[0035] Figure 11 A schematic diagram of the ground after grinding the top electrode contact shown in an exemplary embodiment of the present invention.

[0036] Explanation of reference numerals:

[0037] 1. Semiconductor substrate; 11. Bottom electrode via hole; 12. Bottom electrode; 13. Magnetic tunnel structure; 131. Reference layer; 132. Barrier layer; 133. Memory layer; 14. Top electrode; 15. Insulating layer; 2. First interlayer dielectric layer; 3. Etch stop layer; 4. Second interlayer dielectric layer; 5. Via hole; 51. First trench; 52. Second trench; 6. Top electrode contact; S. Self-aligned implantation region; F1. First direction; L. Median perpendicular; α. Implantation angle; β. Included angle. Detailed implementation manners

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted.

[0039] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure, and in which different exemplary structures capable of implementing various aspects of the present disclosure are shown by way of example. It should be understood that other specific solutions of components, structures, exemplary devices, systems, and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although terms such as "above", "between", "inside", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, for example, according to the directions in the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as labels and are not numerical limitations on their objects.

[0040] The flowcharts shown in the accompanying drawings are only illustrative and not necessarily include all the contents and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined. Therefore, the actual execution order may change according to the actual situation.

[0041] In addition, in the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. "Above" and "below" are technical terms indicating directions. In the embodiments of the present invention, above refers to the direction in which other functional layers are sequentially formed on the semiconductor substrate 1. For example, the top electrode 14 is located above the magnetic tunnel structure 13. This technical term is only for clearer description and has no limiting effect.

[0042] According to one aspect of the present invention, a method for manufacturing a magnetic random access memory is provided. Refer to Figures 1 to 11 , wherein Figure 1 shows a flowchart of the manufacturing method according to an embodiment of the present invention, Figures 2 to 10 respectively shows schematic cross-sectional structures of the magnetic random access memory in different steps. The filled shapes in each cross-section do not represent the true structure of the layer, but are only for distinguishing each layer and do not have a limiting meaning. As Figure 1 shown, the manufacturing method of the magnetic random access memory according to an embodiment of the present invention includes:

[0043] Step S200: Sequentially form a bottom electrode via 11, a bottom electrode 12, a magnetic tunnel structure 13, a top electrode 14, and an insulating layer 15 on a semiconductor substrate 1.

[0044] Step S400: Form a first interlayer dielectric layer 2 on the insulating layer 15.

[0045] Step S600: Form an etch stop layer 3 on the first interlayer dielectric layer 2.

[0046] Step S800: Form a second interlayer dielectric layer 4 on the etch stop layer 3.

[0047] Step S1000: Etch the second interlayer dielectric layer 4 above the top electrode 14 to the etch stop layer 3 to form a first trench 51.

[0048] Step S1200: Perform an inclined self-aligned implantation on the first interlayer dielectric layer 2 corresponding to the bottom of the first trench 51 to form a self-aligned implantation region S.

[0049] Step S1400: Continue to etch the first trench 51 to the top end face of the top electrode 14 to form a second trench 52. The first trench 51 and the second trench 52 penetrate to form a via 5. The critical dimension of the second trench 52 gradually decreases from the bottom position of the first trench 51 towards the direction close to the top electrode 14.

[0050] Step S1600: Fill a top electrode contact 6 into the via 5.

[0051] In the manufacturing method of the embodiment of the present invention, by providing an etch stop layer 3 on the first interlayer dielectric layer 2, the first trench 51 formed by etching stops at the etch stop layer 3, and then through self-aligned implantation, a self-aligned implantation region S is formed in the first interlayer dielectric layer 2, improving the etch selectivity of the self-aligned implantation region S. During subsequent etching, the size of the via 5 can be accurately controlled, improving the controllability of forming the via 5 and the uniformity of the size, enabling the key dimensions of the formed top electrode contact 6 to match those of the magnetic tunnel structure 13, avoiding the deterioration of the performance of the magnetic tunnel structure 13, and at the same time improving the manufacturing yield of the magnetic random access memory.

[0052] The manufacturing method of the magnetic random access memory according to the embodiment of the present invention will be described in detail below.

[0053] First, it should be noted that the key dimension refers to the dimension along Figure 8 the first direction F1 shown in. The cross-sections mentioned in the embodiments of the present invention all refer to the cross-sections shown in Figures 2 to 11 .

[0054] Step S200: A bottom electrode via 11, a bottom electrode 12, a magnetic tunnel structure 13, a top electrode 14, and an insulating layer 15 are sequentially fabricated on the semiconductor substrate 1.

[0055] As Figure 2 shown, a semiconductor substrate 1 is provided, a bottom electrode via 11 is formed on the semiconductor substrate 1, and a bottom electrode 12, a magnetic tunnel structure 13, a top electrode 14, and an insulating layer 15 are sequentially deposited above the bottom electrode via 11.

[0056] Among them, the material of the semiconductor substrate 1 in the embodiment of the present invention can be silicon, silicon carbide, silicon nitride, silicon on insulator, stacked silicon on insulator, stacked germanium silicide on insulator, germanium silicide on insulator, or germanium on insulator, etc. The bottom electrode via 11 can be filled with at least one material among Ti, TiN, W, WN, Ta, and TaN. The material of the bottom electrode 12 can also be at least one material among Ti, TiN, W, WN, Ta, and TaN. After forming the bottom electrode 12, its surface can be planarized through a planarization process to facilitate the subsequent deposition of the magnetic tunnel structure 13.

[0057] Continue to refer to Figure 2, the magnetic tunnel structure 13 includes a reference layer 131, a barrier layer 132, and a memory layer 133 stacked in sequence from bottom to top. Among them, the reference layer 131 can be a multi-layer structure, the thickness of the reference layer 131 can be 10 - 30 nm, the material of the barrier layer 132 can be a non-magnetic metal oxide, such as MgO or Al2O3, and its thickness is 0.5 nm - 3 nm. The memory layer 133 can have variable magnetic poles, and it can also be a multi-layer structure, with a thickness of 0.8 nm - 2 nm. The total thickness of the magnetic tunnel structure 13 in the embodiment of the present application can be 5 - 20 nm, for example, 8 nm, 12 nm, 16 nm, or 18 nm, and no special limitation is made here.

[0058] The top electrode 14 is formed above the magnetic tunnel structure 13, and its material can be at least one of Ta, TaN, Ti, TiN, W, and WN, and its thickness can be 20 nm - 100 nm.

[0059] An insulating layer 15 is formed above the top electrode 14 and above the semiconductor substrate 1, and it can also be called a packaging layer, aiming to package the above bottom electrode through-hole 11, bottom electrode 12, magnetic tunnel structure 13, and top electrode 14 to be insulated from other functional layers.

[0060] The materials in the above bottom electrode through-hole 11, the bottom electrode 12, each layer in the magnetic tunnel structure 13, the top electrode 14, and the insulating layer 15 can all be formed by a deposition process. The deposition process can be chemical vapor deposition, atomic layer deposition, physical vapor deposition, or ion beam deposition. Of course, it can also be formed by other processes, and no special limitation is made here.

[0061] Step S400: Form a first interlayer dielectric layer 2 on the insulating layer 15.

[0062] As Figure 3 shown, the first interlayer dielectric layer 2 is formed above the insulating layer 15 through a deposition process. The material of the first interlayer dielectric layer 2 can be at least one of silicon dioxide, silicon oxynitride, silicon nitride, and low dielectric constant (Low-k) dielectrics. Among them, the low dielectric constant dielectric material can be hydrogen-containing silicate or porous silicate.

[0063] As Figure 4 shown, after the first interlayer dielectric layer 2 is formed, its top can be polished to remove the top part and achieve planarization of the first interlayer dielectric layer 2, which is convenient for the subsequent formation of the etch stop layer 3. Chemical mechanical polishing (CMP) can be used to polish the first interlayer dielectric layer 2.

[0064] Step S600: Form an etch stop layer 3 on the first interlayer dielectric layer 2.

[0065] AsFigure 5 As shown, an etch stop layer 3 is deposited and formed on the first interlayer dielectric layer 2 planarized in the above steps. The material of the etch stop layer 3 may be at least one of silicon carbide, silicon nitride, silicon oxide, and silicon oxynitride. The etch stop layer 3 may have multiple layers, and the materials in each layer may be the same or different, and no special limitation is made here. The etch stop layer 3 can improve the etching uniformity.

[0066] Step S800: A second interlayer dielectric layer 4 is formed on the etch stop layer 3.

[0067] As Figure 6 shown, after the etch stop layer 3 is formed, the second interlayer dielectric layer 4 is continuously deposited and formed on its upper surface. The material of the second interlayer dielectric layer 4 may be the same as or different from the material of the first interlayer dielectric layer 2. The material of the second interlayer dielectric layer 4 may also include at least one of silicon dioxide, silicon oxynitride, silicon nitride, and low dielectric constant (Low-k) dielectric.

[0068] After the second interlayer dielectric layer 4 is formed, a chemical mechanical polishing process may also be used to planarize the second interlayer dielectric layer 4.

[0069] The first interlayer dielectric layer 2, the etch stop layer 3, and the second interlayer dielectric layer 4 in the embodiments of the present invention can all be formed by a deposition process, and the deposition process may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, or spin coating.

[0070] Step S1000: The second interlayer dielectric layer 4 above the top electrode 14 is etched to the etch stop layer 3 to form a first trench 51.

[0071] As Figure 7 shown, the first trench 51 can be formed by a wet etching process or a dry etching process. The dry etching process may be a plasma etching process, and the etching gas used in the plasma etching process may be chlorine gas. By controlling the amount of the etching gas, the etching degree can be controlled. The wet etching can use concentrated sulfuric acid and hydrogen peroxide as the etchant, and by adjusting the concentration of the etchant, the etching degree can also be controlled. Those skilled in the art can make a choice according to the actual situation, and no special limitation is made here. It should be noted that the critical dimension of the first trench 51 here may remain unchanged from the top position of the first trench 51 towards the direction close to the second trench 52. The situation where the critical dimension of the top of the first trench 51 is slightly smaller than the critical dimension of the bottom due to the etching process itself in actual applications is ignored, that is, the situation where the critical dimension of the top is slightly smaller than the critical dimension of the bottom due to the etching process itself belongs to the situation where the critical dimension remains unchanged from the top position of the first trench 51 towards the direction close to the second trench 52 described in the embodiments of the present invention.

[0072] Through the etch stop layer 3, further downward etching can be stopped, facilitating the formation of the above-mentioned first trench 51 to provide conditions for subsequent self-aligned implantation.

[0073] Step S1200: Perform an inclined self-aligned implantation on the first interlayer dielectric layer 2 corresponding to the bottom of the first trench 51 to form a self-aligned implantation region S.

[0074] As Figure 8 shown, an inclined self-aligned implantation is performed on the bottom of the first trench 51. The self-aligned implantation angle α is 70° to 90°. For example, it can be 75°, 80°, or 86°. No special limitation is made here. The self-aligned implantation angle α is the angle between the self-aligned implantation direction and the first direction F1 (such as Figure 8 the double-arrow direction shown).

[0075] Through the inclined self-aligned implantation, a self-aligned implantation region S with an inverted trapezoidal cross-section can be formed in the first interlayer dielectric layer 2 between the bottom of the first trench 51 and the top electrode 14. That is to say, the size of the cross-section of the self-aligned implantation region S gradually decreases from the bottom of the first trench 51 towards the direction close to the insulating layer 15, and the minimum size of the cross-section of the self-aligned implantation region S is smaller than the size of the cross-section of the top electrode 14. Or it can be considered that this inverted trapezoid is an isosceles trapezoid, and its upper side length is greater than the lower side length. In this way, when forming the via 5 by etching subsequently, the etching range will not extend beyond both sides of the top electrode 14 along the first direction F1, avoiding over-etching and connecting the magnetic tunnel structure 13, which may damage the magnetic tunnel structure 13.

[0076] Since the etch selectivity is proportional to the ion implantation concentration, in one embodiment, when performing the self-aligned implantation, the concentration of the implanted element (or the amount of the implanted element) gradually decreases from the top of the first interlayer dielectric layer 2 in the self-aligned implantation region S towards the direction close to the top electrode 14. This makes the etch selectivity of the part of the first interlayer dielectric layer 2 implanted with ions gradually decrease from top to bottom, which is beneficial for rapid etching of the upper part. In addition, in this embodiment, the ion implantation concentration in the self-aligned implantation region gradually decreases from the mid-perpendicular line L of the cross-section of the self-aligned implantation region along the first direction towards both sides away from the mid-perpendicular line L. Therefore, in the first direction, the closer to the mid-perpendicular line L, the greater the etch selectivity, and the faster the etching speed compared to both sides, which is easy to form the above-mentioned inverted trapezoidal self-aligned implantation region S.

[0077] In another embodiment, it is possible to only set the ion implantation concentration in the self-aligned implantation region to gradually decrease from the mid-perpendicular line L of the cross-section of the self-aligned implantation region along the first direction towards both sides away from the mid-perpendicular line L. In this way, it is also beneficial to form the inverted trapezoidal self-aligned implantation region S.

[0078] It should be noted that the above perpendicular bisector L is perpendicular to the first direction, and the perpendicular bisector L passes through the middle of the bottom side of the cross-section of the self-aligned implantation region S, as Figure 9 shown. Of course, the self-aligned implantation region S may also include an etch stop layer 3 located at the bottom of the first trench 51. That is, when the bottom of the first trench 51 is the etch stop layer 3, after self-aligned implantation, ions are also implanted into the etch stop layer 3, which can improve the etch selectivity of the etch stop layer 3, so that the etch stop layer 3 and the self-aligned implantation region S in the first interlayer dielectric layer 2 adopt the same etching process, saving process steps.

[0079] In some embodiments, the implantation element for self-aligned implantation is at least one of C, N, O, F, Ar, Ne, B, and Cl. The specific implantation process is as follows: a certain amount of energy is provided to the gas containing the implantation element to dissociate the gas into an ion stream, and then the ion stream is implanted into the self-aligned implantation region S. The initial value range of the implantation energy can be 2 keV to 25 keV. For example, it can be 5 keV, 10 keV, 15 keV, and 20 keV. keV is an energy unit, and 1 keV = 1.6 * 10 -16 Joules.

[0080] In actual operation, the part of the second interlayer dielectric layer 4 outside the first trench 51 (i.e., the unetched part) can be used as a mask for the self-aligned ion implantation process, so that ions are only implanted in large quantities into the self-aligned implantation region S of the first interlayer dielectric layer. To enhance the masking effect, the second interlayer dielectric layer 4 can also use a composite structure. For example, a thin layer with a good blocking effect on the implanted ions is compounded on its upper surface. Although a small amount of ions will also be implanted into the second interlayer dielectric layer 4, these ions will only be implanted into a very thin layer on the second interlayer dielectric layer 4 or only into the thin layer of the composite structure, which will not affect the subsequent process and can be removed by subsequent second trench etching or polishing.

[0081] In addition, due to the blocking effect of the sidewall of the first trench 51, that is, the sidewall shadow effect, it can further control the ions to be implanted to the bottom of the first trench 51. Since the implantation angle α is 70° to 90°, its inclination angle is very small, and very few ions are implanted on the sidewall surface of the ion beam. This part of the ions can be ignored and will not affect the subsequent process. Therefore, the inclined self-aligned implantation with the above implantation angle α can not only concentrate the ion beam to be implanted into the self-aligned implantation region S with gradually decreasing dimensions, but also avoid implanting ions into the second interlayer dielectric layer 4 to cause adverse effects.

[0082] Through the self-aligned injection process, the ions injected into the self-aligned injection region S of the first interlayer dielectric layer 2 can change the physical or chemical properties of the self-aligned injection region S, or can damage its structure, increasing the etching selectivity of this part. For example, in some embodiments, the etching selectivity of the self-aligned injection region S in the first interlayer dielectric layer 2 to the part of the first interlayer dielectric layer 2 where self-aligned injection is not performed is greater than 1. For example, the etching selectivity is 2, 5, 10, 20, 30, 50, 60, 70, or 80 or greater, and no special limitation is made here. Therefore, when etching the first interlayer dielectric layer 2, by adjusting the etching process or parameters, the self-aligned injection region S can be preferentially etched. Therefore, the etching range is limited to the self-aligned injection region S, avoiding over-etching. For example, it is avoided that the size of the finally formed via 5 in the first direction F1 is greater than the size of the top electrode 14 in the first direction F1. Moreover, when performing selective etching in the direction perpendicular to the first direction F1, the etching can also be stopped in time at the bottom of the self-aligned injection region S, without etching the insulating layer 15, avoiding over-etching in this direction and causing the via 5 to sink into the insulating layer 15 of the magnetic tunnel structure 13, resulting in the deterioration of the performance of the magnetic tunnel structure 13, and avoiding the magnetic tunnel structure 13 being contaminated by metal elements.

[0083] Step S1400: Continue to etch the first trench 51 to the top end face of the top electrode 14 to form a second trench 52. The first trench 51 and the second trench 52 penetrate to form a via 5. The critical dimension of the second trench 52 gradually decreases from the bottom position of the first trench 51 towards the direction close to the top electrode 14.

[0084] As Figure 9 shown, after the self-aligned injection is performed, first etch away the etch stop layer 3 at the bottom of the first trench 51, and then use a suitable etching process to selectively etch the self-aligned injection region S. The suitable etching process can be selected according to the type of the injected element. The gas used for etching can be at least one of CF4, CH3OH, and CH4 / Ar. For example, when the self-aligned injection element is B (boron), the B element destroys the structure of the first interlayer dielectric layer 2, and physical bombardment can be used for selective etching. At the same time, by adjusting the atomic ratio of C, O, and F in the etching gas, the size of the cross-section of the second trench 52 can be further gradually reduced from top to bottom. When the injected element is N, a gas with a relatively fast etching rate for SiNx can be selected or adjusted. Regarding the etching gas, those skilled in the art can select or adjust according to the specific injected element, and details are not described here.

[0085] Continue to refer to Figure 9, the maximum critical dimension of the second groove 52 is less than or equal to the minimum critical dimension of the first groove 51. Additionally, there is an included angle β between the sidewalls of the first groove 51 and the second groove 52, and the included angle β is an obtuse angle. For example, this obtuse angle can be 150°, 160°, 170°, or 180°, and no special limitation is made here. Thus, it is further ensured that the size of the second groove 52 tapers from top to bottom.

[0086] In actual operation, the self-aligned implantation region S and the insulating layer 15 are etched sequentially from the bottom of the first groove 51, that is, the above-mentioned selective etching is first performed to form the second groove 52. The bottom end of the second groove 52 is the bottom end of the self-aligned implantation region S, and the lower part of the second groove 52 is the insulating layer 15. Therefore, it also avoids the second groove 52 directly passing through the insulating layer 15 and entering the top electrode 14, causing damage to the top electrode 14. After the selective etching, the insulating layer 15 is etched by other etching processes, so that the bottom of the second groove 52 continues to extend downward to the surface of the top electrode 14, that is, the final via 5 is formed. Since the insulating layer 15 is a very thin layer and the amount to be etched is also very small, it is easy to control the amount and size of the etching, so that the via 5 can be connected to the top electrode 14 without damaging the top electrode 14.

[0087] Step S1600: Fill the via 5 with the top electrode contact 6.

[0088] As Figure 10 shown, deposit the top electrode contact 6 into the via 5, which can specifically include: depositing the top electrode contact 6 in the via 5 and on the upper surface of the second interlayer dielectric layer 4. Then, the top electrode contact 6 on the upper surface of the second interlayer dielectric layer 4 and the top electrode contact 6 at the top of the via 5 and protruding from the upper surface of the second interlayer dielectric layer 4 can be removed by a chemical mechanical polishing process, making the top electrode contact 6 flush with the second interlayer dielectric layer 4, forming a structure as Figure 11 shown.

[0089] In some embodiments, the material of the top electrode contact 6 can be tungsten or copper.

[0090] In summary, in the manufacturing method of the magnetic random access memory according to the embodiment of the present invention, by providing an etch stop layer 3 on the first interlayer dielectric layer 2, the first trench 51 formed by etching is stopped at the etch stop layer 3, and then through self-aligned implantation, a self-aligned implantation region S is formed in the first interlayer dielectric layer 2, improving the etch selectivity of the self-aligned implantation region S. When etching is performed subsequently, the size of the via 5 can be accurately controlled, improving the controllability of forming the via 5 and the uniformity of the size, avoiding the key dimensions of the through hole or trench being larger than the key dimensions of the top electrode 14 and the MTJ due to over-etching, thereby avoiding the performance deterioration of the MTJ and being contaminated by metal in subsequent processes, and at the same time improving the manufacturing yield of the magnetic random access memory.

[0091] According to another aspect of the present invention, there is provided a magnetic random access memory manufactured by the method described in any of the above embodiments.

[0092] For the magnetic random access memory according to the embodiment of the present invention, the size of the top electrode contact 6 matches that of the magnetic tunnel structure 13, and the magnetic tunnel structure 13 is not contaminated by the metal elements of the top electrode contact 6, ensuring the performance of the magnetic random access memory and having a high production yield.

[0093] It should be understood that the present invention does not limit its application to the detailed structure and arrangement of the components set forth in this specification. The present invention can have other embodiments and can be implemented and executed in various ways. The foregoing variations and modifications fall within the scope of the present invention. It should be understood that the present invention disclosed and defined in this specification extends to all alternative combinations of two or more separate features mentioned or apparent in the text and / or drawings. All such different combinations constitute multiple alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for implementing the present invention and will enable those skilled in the art to utilize the present invention.

Claims

1. A manufacturing method of a magnetic random access memory, characterized in that, Comprising: Successively fabricating a bottom electrode via hole, a bottom electrode, a magnetic tunnel structure, a top electrode, and an insulating layer on a semiconductor substrate; Forming a first interlayer dielectric layer on the insulating layer; Forming an etch stop layer on the first interlayer dielectric layer; Forming a second interlayer dielectric layer on the etch stop layer; Etching the second interlayer dielectric layer above the top electrode to the etch stop layer to form a first trench; Performing an inclined self-aligned implantation on the first interlayer dielectric layer corresponding to the bottom of the first trench to form a self-aligned implantation region; Continuing to etch the first trench to the top end face of the top electrode to form a second trench, the first trench and the second trench communicate to form a via hole, and the critical dimension of the second trench gradually decreases from the bottom position of the first trench towards the direction close to the top electrode; Filling a top electrode contact into the via hole; Wherein, the cross-section of the self-aligned implantation region is an inverted trapezoid, and the ion implantation concentration in the self-aligned implantation region gradually decreases from the top end of the first interlayer dielectric layer towards the direction close to the top electrode, and / or, the ion implantation concentration in the self-aligned implantation region gradually decreases from the mid-perpendicular of the cross-section of the self-aligned implantation region along a first direction towards both sides away from the mid-perpendicular.

2. The method according to claim 1, characterized in that, The implantation angle of the self-aligned implantation is the included angle between the self-aligned implantation direction and the first direction.

3. The method according to claim 2, characterized in that, The implantation angle is 70° - 90°.

4. The method according to claim 1, characterized in that, The implantation element of the self-aligned implantation is at least one of C, N, O, F, Ar, Ne, B, and Cl.

5. The method according to claim 4, characterized in that, The maximum critical dimension of the second trench is less than or equal to the minimum critical dimension of the first trench.

6. The method according to claim 5, characterized in that, There is an included angle between the side wall of the first trench and the side wall of the second trench, and the included angle is an obtuse angle.

7. The method according to claim 1, characterized in that, The continuing to etch the first trench to the top end face of the top electrode to form a second trench includes: Sequentially etching the self-aligned implantation region and the insulating layer from the bottom of the first trench; Wherein, the etching selectivity of the self-aligned implantation region in the first interlayer dielectric layer to the part of the first interlayer dielectric layer where no self-aligned implantation is performed is greater than 1.

8. The method according to claim 7, characterized in that, The first interlayer dielectric layer, the etch stop layer, and the second interlayer dielectric layer are all formed by a deposition process, and the deposition process includes atomic layer deposition, chemical vapor deposition, physical vapor deposition, or spin coating.

9. The method according to claim 1, characterized in that, The filling the top electrode contact into the via hole includes: Depositing the top electrode contact in the via hole and on the upper surface of the second interlayer dielectric layer; Remove the top electrode contact on the upper surface of the second interlayer dielectric layer and the top electrode contact at the top of the via and protruding from the upper surface of the second interlayer dielectric layer, so that the top electrode contact is flush with the second interlayer dielectric layer.

10. The method according to claim 1, wherein the top electrode contact is tungsten or copper.

11. The method according to claim 1, wherein the magnetic tunnel structure includes: a reference layer, a barrier layer, and a memory layer stacked in sequence.

12. The method according to claim 1, wherein the first interlayer dielectric layer and the second interlayer dielectric layer each include at least one of silicon dioxide, silicon oxynitride, silicon nitride, and low-k dielectric.

13. The method according to claim 1, wherein the etch stop layer includes at least one of silicon carbide, silicon nitride, silicon oxide, and silicon oxynitride.

14. A magnetic random access memory, wherein the magnetic random access memory is manufactured by the method according to any one of claims 1 to 13.

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