Resistive memory device and preparation method thereof

Abstract

Embodiments of the present application relate to a resistive memory device and a method for manufacturing the same. The method comprises: providing a substrate; forming a bitline trench in the substrate; forming a resistive material layer on the sidewalls and bottom of the bitline trench; and filling the bitline trench to form a bitline structure; wherein the variable resistance structure comprises a bitline structure and a resistive material layer. In the resistive memory device of the present application, the bitline structure and the resistive material layer on the sidewalls of the bitline serve as part of the variable resistance structure. The variable resistance structure is formed simultaneously with the bitline structure, thereby simplifying the process flow of the resistive memory device, reducing production costs, and reducing the size of the resistive memory device.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular to a resistive memory device and a method for preparing the same. Background Art

[0002] A typical resistive random access memory (RRAM) device consists of a planar transistor and a metal-insulator-metal (MIM) structure located above the planar transistor. The planar transistor and the MIM structure are fabricated in different process steps, resulting in a complex process flow and large size. Simplifying the RRAM process flow and forming a small RRAM structure has become an urgent problem. Summary of the Invention

[0003] The embodiments of the present application provide a resistive memory device and a method for manufacturing the same, which can optimize the process flow of the resistive memory device.

[0004] A method for preparing a resistive memory device, comprising:

[0005] providing a substrate;

[0006] forming a bit line trench in a substrate;

[0007] forming a resistive material layer on the sidewalls and bottom of the bit line trench;

[0008] filling the bit line trench to form a bit line structure;

[0009] The variable resistance structure includes a bit line structure and a resistive material layer.

[0010] The present application also provides a resistive memory device, comprising:

[0011] substrate;

[0012] A bit line trench is opened in the substrate;

[0013] a resistive material layer, located on the sidewalls and bottom of the bit line trench;

[0014] A bit line structure filled in the bit line trench;

[0015] The variable resistance structure includes a bit line structure and a resistive material layer.

[0016] In the above-mentioned resistive memory device and its preparation method, the variable resistance structure includes a bit line structure and a resistive material layer, wherein the resistive material layer is located on the sidewalls and bottom of the bit line trench, and the bit line structure is filled in the bit line trench. In the resistive memory device of the present application, the bit line structure and the resistive material layer on the bit line sidewall serve as part of the variable resistance structure. The variable resistance structure is formed at the same time as the bit line structure is formed, which simplifies the process flow of the resistive memory device, reduces production costs, and reduces the size of the resistive memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 1 is a flow chart of a method for preparing a resistive memory device in one embodiment;

[0019] Figure 2 is a schematic cross-sectional view of a resistive memory device after a gate trench is formed in one embodiment;

[0020] Figure 3 is a schematic cross-sectional view of a resistive memory device after a gate trench is formed in another embodiment;

[0021] Figure 4 for Figure 2 A cross-sectional schematic diagram of the resistive memory device after the first dielectric layer is formed in a corresponding embodiment;

[0022] Figure 5 for Figure 4 A cross-sectional schematic diagram of a resistive memory device after a gate structure is formed in a corresponding embodiment;

[0023] Figure 6 for Figure 5 A cross-sectional schematic diagram of the resistive memory device after the second dielectric layer is formed in a corresponding embodiment;

[0024] Figure 7 for Figure 6 A schematic diagram of an equivalent circuit of a resistive memory device in a corresponding embodiment.

[0025] Description of reference numerals:

[0026] 102. Substrate; 104. Shallow trench isolation structure; 106. Active region; 108. Bit line trench; 110. Gate trench; 112. Second dielectric layer; 114. Source lead-out structure; 116. Source metal line layer; 202. Source region; 204. Drain region; 206. Resistive material layer; 208. First dielectric layer; 210. Bit line structure; 212. Gate structure; 214. Protective layer; 216. Transistor; 218. Variable resistor structure. DETAILED DESCRIPTION

[0027] To facilitate understanding of the embodiments of the present application, a more comprehensive description of the embodiments of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings provide preferred embodiments of the embodiments of the present application. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the embodiments of the present application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present application. The terms used herein in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0029] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0030] It will be understood that the terms "first," "second," and the like used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used solely to distinguish a first element from another element. For example, a first client may be referred to as a second client, and similarly, a second client may be referred to as a first client, without departing from the scope of this application. The first client and the second client are both clients, but they are not the same client.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0032] Resistive Random Access Memory (RRAM) is a non-charge storage device with a metal-insulator-metal sandwich structure. Under specific voltage / current stimuli, its resistance can switch between high-resistance and low-resistance states. It offers advantages such as low write voltage, short write / erase times, long memory life, non-destructive read access, multi-value storage, simple structure, and high storage density. It is expected to replace DRAM, SRAM, and Flash as a universal memory. However, compared to DRAM, RRAM is larger and has a smaller amount of RRAM per unit area. A typical RRAM cell using two FinFETs measures 0.07632 square microns.

[0033] Figure 1 FIG. 1 is a flow chart of a method for preparing a resistive memory device in an embodiment. Figure 2 FIG. 1 is a cross-sectional view of a resistive memory device after forming a gate trench 110 in one embodiment. Figure 1 、 Figure 2 To solve the above problems, in this embodiment, a method for preparing a resistive memory device is provided, comprising:

[0034] S102, providing a substrate 102.

[0035] A substrate 102 for forming a resistive memory device is provided. Specifically, the substrate 102 includes a substrate and different device regions formed on the substrate. The substrate can be made of undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). As an example, in this embodiment, the substrate is made of single-crystal silicon.

[0036] S104 , forming a bit line trench 108 in the substrate 102 .

[0037] A bit line trench 108 is formed at a predetermined position of the substrate 102 by using photolithography and etching processes well known to those skilled in the art.

[0038] S106 , forming a resistive material layer 206 on the sidewalls and bottom of the bit line trench 108 .

[0039] Specifically, a resistive material layer 206 is formed on the sidewalls and bottom of the bitline trench 108 using any of atomic layer deposition, molecular beam epitaxy, radio frequency magnetron sputtering, and chemical vapor deposition processes. Under the influence of an applied electrical signal, such as a voltage or current, the resistive material layer 206 undergoes a reversible transition between different resistance states, typically a high resistance state and a low resistance state. It is understood that the resistive material layer 206 may be a high-k material layer. In one embodiment, the resistive material layer 206 includes at least one of a hafnium oxide material layer or a tantalum oxide material layer.

[0040] S108 , filling the bit line trench 108 to form a bit line structure 210 .

[0041] Specifically, a bitline structure 210 is formed in the bitline trench 108. The material of the bitline structure 210 can be titanium nitride or tungsten. At this point, the bitline structure 210 on one side of the resistive material layer 206, the substrate 102 on the other side of the resistive material layer 206, and the resistive material layer 206 together constitute a variable resistance structure (MIM structure) in the resistive memory device. Specifically, the bitline structure 210 in this application also serves as an electrode in the MIM structure, and the resistive material layer 206 serves as the resistance conversion layer in the MIM structure. Compared to a typical preparation process for forming a separate MIM structure, this simplifies the process flow.

[0042] In the resistive memory device described above, the variable resistance structure includes a bit line structure 210 and a resistive material layer 206, wherein the resistive material layer 206 is located on the sidewalls and bottom of the bit line trench 108, and the bit line structure 210 is filled in the bit line trench 108. In the resistive memory device of the present application, the bit line structure 210 and the resistive material layer 206 on the bit line sidewalls serve as part of the variable resistance structure. The variable resistance structure is formed simultaneously with the formation of the bit line structure 210, thereby simplifying the process flow of the resistive memory device, reducing production costs, and reducing the size of the resistive memory device.

[0043] like Figure 2As shown, in this embodiment, a shallow trench isolation structure 104 is formed in the substrate 102, and the shallow trench isolation structure 104 isolates the active area 106 arranged in an array in the substrate 102; while the bit line trench 108 is formed in the substrate 102, a gate trench 110 is formed in the substrate 102, and each gate trench 110 and a bit line trench 108 span the same active area 106, and divide the active area 106 into a source region 202 located between the gate trench 110 and the shallow trench isolation structure 104, and a drain region 204 located between the gate trench 110 and the bit line trench 108. Specifically, a bit line trench 108 and a gate trench 110 are simultaneously formed in the substrate 102 through an etching process. Both the gate trench 110 and the bit line trench 108 pass through an active area 106, and the active area 106 is divided into a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110, and a drain region 204 located between the gate trench 110 and the bit line trench 108. Subsequently, a doping process can be performed on the source region 202 and the drain region 204 as needed to obtain the source and drain of the transistor in the resistive memory device, respectively.

[0044] In other embodiments, a shallow trench isolation structure 104 is formed in the substrate 102, and the shallow trench isolation structure 104 isolates an array-arranged active area 106 in the substrate 102; after forming the bit line trench 108 in the substrate 102, the method further includes: forming a gate trench 110 in the substrate 102, each gate trench 110 and a bit line trench 108 spanning the same active area 106, and dividing the active area 106 into a source region 202 located between the gate trench 110 and the shallow trench isolation structure 104, and a drain region 204 located between the gate trench 110 and the bit line trench 108. Specifically, a bit line trench 108 and a gate trench 110 are formed in the substrate 102 through an etching process. Both the gate trench 110 and the bit line trench 108 pass through an active area 106, and the active area 106 is divided into a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110, and a drain region 204 located between the gate trench 110 and the bit line trench 108. Subsequently, a doping process can be performed on the source region 202 and the drain region 204 as needed to obtain the source and drain of the transistor in the resistive memory device.

[0045] In one embodiment, the doping depth of the source and drain along the X direction is less than or equal to the depth of the gate trench 110 and the bit line trench 108. The X direction refers to the direction upward from the substrate 102, and the Y direction refers to the direction intersecting the extending direction of the bit line trench 108.

[0046] Continue to refer Figure 2In one embodiment, the bit line trench 108 and the gate trench 110 have the same depth in the X direction and width in the Y direction. In this case, the bit line trench 108 and the gate trench 110 can be formed using lithography equipment with the same overlay error. In other embodiments, the bit line trench 108 and the gate trench 110 have different morphologies. In this case, the bit line trench 108 and the gate trench 110 can be formed using lithography equipment with the same or different overlay errors according to process requirements.

[0047] like Figure 2 As shown, in one embodiment, the bit line trench 108 and the gate trench 110 cross the same active area 106, and an active area 106 exists between the bit line trench 108 and an adjacent shallow trench isolation structure 104 in the Y direction. That is, when both the gate trench 110 and the bit line trench 108 pass through an active area 106, the active area 106 is divided into a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110, a drain region 204 located between the gate trench 110 and the bit line trench 108, and a portion of the active area 106 located between the bit line trench 108 and the adjacent shallow trench isolation structure 104. Furthermore, the width W1 of the portion of the active area 106 located between the bit line trench 108 and the adjacent shallow trench isolation structure 104 along the Y direction is less than or equal to the width W2 of the source region 202 along the Y direction. The method for preparing the resistive memory device in this application is compatible with the method for preparing DRAM devices, that is, at least part of the photomask of the DRAM device can be used to prepare the resistive memory device, so that the process flow of the resistive memory device is simplified while having the density of the DRAM device, reducing the production cost and realizing a high-density array design of the resistive memory device. The size of the resistive memory device can reach 0.004 square microns, which is reduced by nearly 19 times.

[0048] Figure 3 FIG. 1 is a cross-sectional view of a resistive memory device after a gate trench is formed in another embodiment. Figure 3 In this embodiment, the bit line trench 108 and the gate trench 110 cross the same active area 106 while contacting the adjacent shallow trench isolation structure 104 in the Y direction. That is, when both the gate trench 110 and the bit line trench 108 pass through an active area 106, the active area 106 is divided into two parts: a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110, and a drain region 204 located between the gate trench 110 and the bit line trench 108. This arrangement further reduces the size of the resistive memory device.

[0049] In one embodiment, the variable resistor structure further includes a drain region 204. That is, the substrate 102 on the other side of the resistive material layer 206 in the variable resistor structure is a doped drain. In this case, the drain and the bit line structure 210 serve as two electrodes of the variable resistor structure, and the resistive material layer 206 located between the drain and the bit line structure 210 serves as a resistance conversion layer between the two electrodes of the variable resistor structure.

[0050] In one embodiment, the bit line trenches 108 are formed in the plurality of active regions 106 and in the shallow trench isolation structures 104 between adjacent active regions 106. In other embodiments, the bit line trenches 108 are formed only in the plurality of active regions 106.

[0051] Figure 4 for Figure 2 A cross-sectional view of the resistive memory device after the first dielectric layer 208 is formed in a corresponding embodiment. Figure 4 As shown, in one embodiment, a first dielectric layer 208 is formed on the sidewalls and bottom of the gate trench 110 simultaneously with forming the resistive material layer 206 on the sidewalls and bottom of the bitline trench 108. In other embodiments, after forming the resistive material layer 206 on the sidewalls and bottom of the bitline trench 108 or before forming the resistive material layer 206 on the sidewalls and bottom of the bitline trench 108, the process further includes forming the first dielectric layer 208 on the sidewalls and bottom of the gate trench 110. By forming the first dielectric layer 208, the active region 106 can be isolated from the gate structure 212 subsequently formed in the gate trench 110, wherein the active region 106 includes a source formed in the source region 202 and a drain formed in the drain region 204.

[0052] In one embodiment, the first dielectric layer 208 includes at least one of a hafnium oxide material layer, a silicon dioxide layer, or a tantalum oxide material layer.

[0053] In one embodiment, the first dielectric layer 208 and the resistive material layer 206 are made of the same material, for example, both are hafnium oxide material layers.

[0054] Figure 5 for Figure 4 A cross-sectional view of a resistive memory device after forming the gate structure 212 in one embodiment is shown. Figure 5 As shown in one embodiment, while the bit line structure 210 is being filled in the bit line trench 108, the gate structure 212 is being filled in the gate trench 110. In other embodiments, after or before the bit line structure 210 is being filled in the bit line trench 108, the step of filling the gate trench 110 with the gate structure 212 is further included.

[0055] In one embodiment, the materials of the bit line structure 210 and the gate structure 212 include at least one of titanium nitride, titanium metal, tungsten metal, and doped polysilicon. The following example illustrates that the materials of the bit line structure 210 and the gate structure 212 are both titanium nitride.

[0056] Specifically, the steps of simultaneously filling the bitline trench 108 to form the bitline structure 210 and the gate trench 110 to form the gate structure 212 include: a first step of forming a titanium nitride material layer in the bitline trench 108 and the gate trench 110 through a deposition process. A second step of etching away excess titanium nitride material layer to obtain the bitline structure 210 formed by the titanium nitride material layer remaining in the bitline trench 108 and the gate structure 212 formed by the titanium nitride material layer remaining in the gate trench 110. The gate structure 212 also serves as a wordline structure (WL) in the resistive memory device.

[0057] In one embodiment, the upper surface of the gate structure 212 is flush with the upper surface of the bit line structure 210 .

[0058] like Figure 5 As shown, in one embodiment, the upper surface of the bitline structure 210 is lower than the upper surface of the substrate 102, that is, the bitline structure 210 is a buried bitline. In other embodiments, the upper surface of the bitline structure 210 is flush with the upper surface of the substrate 102 or the upper surface of the bitline structure 210 is higher than the upper surface of the substrate 102.

[0059] Figure 6 for Figure 5 A cross-sectional view of the resistive memory device after the second dielectric layer 112 is formed in a corresponding embodiment. Figure 6In one embodiment, the method for preparing a resistive memory device further includes: forming a protective layer 214 on the bit line structure 210 and the gate structure 212. Furthermore, when the upper surface of the bit line structure 210 is lower than the upper surface of the substrate 102, the upper surface of the protective layer 214 is flush with or higher than the upper surface of the substrate 102. Specifically, first, the bit line trench 108 and the gate trench 110 are filled with a protective material, the upper surface of the protective material is higher than the upper surface of the substrate 102, and the protective material covers the active area 106 and the shallow trench isolation structure 104. Secondly, the protective material above the surface of the substrate 102 is etched away. Thirdly, a chemical planarization treatment is performed to obtain a protective layer 214 composed of the remaining protective material, the upper surface of which is flush with the upper surface of the substrate 102. The constituent materials of the protective layer 214 include one or more of oxides, nitrides, and oxynitrides, wherein the oxides include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), spin-on glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); the nitrides include silicon nitride (SiN); and the oxynitrides include silicon oxynitride (SiON).

[0060] Continue to refer Figure 6 In one embodiment, after forming the protection layer 214 on the bit line structure 210 and the gate structure 212, the method further includes forming a second dielectric layer 112 on the substrate 102, wherein the second dielectric layer 112 is in contact with the protection layer 214. Furthermore, the material constituting the second dielectric layer 112 includes one or more of oxide, nitride, and oxynitride, wherein the oxide includes borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), spin-on glass (SOG), high-density plasma (HDP), or spin-on dielectric (SOD); the nitride includes silicon nitride (SiN); and the oxynitride includes silicon oxynitride (SiON).

[0061] In one embodiment, the second dielectric layer 112 is located on the upper surface of the substrate 102. Typically, the second dielectric layer 112 includes a silicon dioxide layer located on the upper surface of the substrate 102. Furthermore, the second dielectric layer 112 also includes a silicon nitride layer located on the upper surface of the silicon dioxide layer.

[0062] In one embodiment, the second dielectric layer 112 and the protective layer 214 are made of the same material. In this case, the second dielectric layer 112 can be formed simultaneously with the protective layer 214 or separately from the protective layer 214 .

[0063] like Figure 6 As shown, in one embodiment, after forming the second dielectric layer 112 on the substrate 102, the method further includes:

[0064] A source lead-out structure 114 is formed on the source region 202 . The source lead-out structure 114 penetrates the second dielectric layer 112 and contacts the source region 202 .

[0065] Specifically, first, a photoresist layer having a pattern of a source lead-out structure 114 is formed on the upper surface of the second dielectric layer 112. Second, using the photoresist layer as a mask, the second dielectric layer 112 is etched to form a lead-out trench penetrating the second dielectric layer 112. The lead-out trench exposes the source region 202 below the second dielectric layer 112, i.e., the lead-out trench exposes the doped source electrode in the source region 202. Third, a conductive material is filled in the lead-out trench to form the source lead-out structure 114 in contact with the source region 202. Furthermore, the conductive material forming the source lead-out structure 114 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. The metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0066] In one embodiment, the upper surface of the source extraction structure 114 is higher than the upper surface of the second dielectric layer 112 .

[0067] In one embodiment, the lower surface of the source extraction structure 114 is lower than the upper surface of the substrate 102 , and the lower surface of the source extraction structure 114 is not lower than the lower surface of the source.

[0068] In another embodiment, the lower surface of the source extraction structure 114 is flush with the upper surface of the substrate 102 .

[0069] like Figure 6 As shown, in one embodiment, after forming the source lead-out structure 114 on the source region 202 , the process further includes:

[0070] A source metal line layer 116 is formed on the substrate 102 . The source metal line layer 116 is in contact with the source lead-out contact and is used to lead the source to the upper surface of the resistive memory device.

[0071] Figure 7 for Figure 6 The equivalent circuit diagram of the resistive memory device in one embodiment is shown in FIG. Figure 7As shown in the figure, the arrow curve indicates the direction of current flow. The input end of the current is the source metal line layer 116 (SL), and the output end of the current is the bit line structure 210 (BL). The resistive memory device includes a transistor 216 and a variable resistance structure 218. The transistor 216 is composed of a source region 202, a gate structure 212 (i.e., a word line structure WL, where the gate structure 212 and the first dielectric layer 208 serve as the gate of the transistor), and a drain region 204. The variable resistance structure 218 is composed of the drain region 204, a resistive material layer 206 between the drain region 204 and the bit line structure 210, and the bit line structure 210.

[0072] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0073] like Figure 2 、 Figure 5 As shown, the present application also provides a resistive memory device, comprising:

[0074] The substrate 102 includes, specifically, a substrate and different device regions formed on the substrate. The substrate can be made of undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the substrate is made of single crystal silicon.

[0075] A bit line trench 108 is formed in the substrate 102;

[0076] The resistive material layer 206 is located on the sidewalls and bottom of the bitline trench 108. Under the influence of an applied voltage, current, or other electrical signal, the resistive material layer 206 undergoes a reversible transition between different resistance states, typically a high resistance state and a low resistance state. It is understood that the resistive material layer 206 may be a high-k material layer. In one embodiment, the resistive material layer 206 comprises at least one of a hafnium oxide layer or a tantalum oxide layer.

[0077] A bitline structure 210 is filled in the bitline trench 108; the material of the bitline structure 210 can be titanium nitride or metallic tungsten. In this case, the bitline structure 210 on one side of the resistive material layer 206, the substrate 102 on the other side of the resistive material layer 206, and the resistive material layer 206 together constitute a variable resistance structure (MIM structure) in the resistive memory device. Specifically, the bitline structure 210 in this application also serves as an electrode in the MIM structure, and the resistive material layer 206 serves as the resistance conversion layer in the MIM structure. Compared to the typical preparation process of forming a single MIM structure, this simplifies the process flow.

[0078] In the resistive memory device described above, the variable resistance structure includes a bit line structure 210 and a resistive material layer 206, wherein the resistive material layer 206 is located on the sidewalls and bottom of the bit line trench 108, and the bit line structure 210 is filled in the bit line trench 108. In the resistive memory device of the present application, the bit line structure 210 and the resistive material layer 206 on the bit line sidewalls serve as part of the variable resistance structure. The variable resistance structure is formed simultaneously with the formation of the bit line structure 210, thereby simplifying the process flow of the resistive memory device, reducing production costs, and reducing the size of the resistive memory device.

[0079] like Figure 2 As shown, in one embodiment, a shallow trench isolation structure 104 is formed in the substrate 102, and the shallow trench isolation structure 104 isolates the active areas 106 arranged in an array in the substrate 102; the resistive memory device further includes:

[0080] The gate trenches 110, each gate trench 110 and a bit line trench 108, span the same active area 106, and divide the active area 106 into a source region 202 located between the gate trench 110 and the shallow trench isolation structure 104, and a drain region 204 located between the gate trench 110 and the bit line trench 108. That is, a gate trench 110 and a bit line trench 108 pass through an active area 106, dividing the active area 106 into a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110, and a drain region 204 located between the gate trench 110 and the bit line trench 108. Subsequently, the source region 202 and the drain region 204 can be doped as needed to obtain the source and drain of the transistor in the resistive memory device, respectively.

[0081] In one embodiment, the doping depth of the source and drain along the X direction is less than or equal to the depth of the gate trench 110 and the bit line trench 108. The X direction refers to the direction upward from the substrate 102, and the Y direction refers to the direction intersecting the extending direction of the bit line trench 108.

[0082] Continue to refer Figure 2In one embodiment, the bit line trench 108 and the gate trench 110 have the same depth in the X direction and width in the Y direction. In this case, the bit line trench 108 and the gate trench 110 can be formed using lithography equipment with the same overlay error. In other embodiments, the bit line trench 108 and the gate trench 110 have different morphologies. In this case, the bit line trench 108 and the gate trench 110 can be formed using lithography equipment with the same or different overlay errors according to process requirements.

[0083] like Figure 2 As shown, in one embodiment, the bit line trench 108 and the gate trench 110 cross the same active area 106, and an active area 106 exists between the bit line trench 108 and an adjacent shallow trench isolation structure 104 in the Y direction. That is, when both the gate trench 110 and the bit line trench 108 pass through an active area 106, the active area 106 is divided into a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110, a drain region 204 located between the gate trench 110 and the bit line trench 108, and a portion of the active area 106 located between the bit line trench 108 and the adjacent shallow trench isolation structure 104. Furthermore, the width W1 of the portion of the active area 106 located between the bit line trench 108 and the adjacent shallow trench isolation structure 104 along the Y direction is less than or equal to the width W2 of the source region 202 along the Y direction. The method for preparing the resistive memory device in this application is compatible with the method for preparing DRAM devices, that is, at least part of the photomask of the DRAM device can be used to prepare the resistive memory device, so that the process flow of the resistive memory device is simplified while having the density of the DRAM device, reducing the production cost and realizing a high-density array design of the resistive memory device. The size of the resistive memory device can reach 0.004 square microns, which is reduced by nearly 19 times.

[0084] See also Figure 3 In other embodiments, the bit line trench 108 and the gate trench 110 cross the same active area 106 while contacting the adjacent shallow trench isolation structure 104 in the Y direction. That is, when both the gate trench 110 and the bit line trench 108 pass through an active area 106, the active area 106 is divided into two parts: a source region 202 located between the shallow trench isolation structure 104 and the gate trench 110, and a drain region 204 located between the gate trench 110 and the bit line trench 108. This arrangement further reduces the size of the resistive memory device.

[0085] In one embodiment, the variable resistor structure further includes a drain region 204. That is, the substrate 102 on the other side of the resistive material layer 206 in the variable resistor structure is a doped drain. In this case, the drain and the bit line structure 210 serve as two electrodes of the variable resistor structure, and the resistive material layer 206 located between the drain and the bit line structure 210 serves as a resistance conversion layer between the two electrodes of the variable resistor structure.

[0086] In one embodiment, the bit line trenches 108 are formed in the plurality of active regions 106 and in the shallow trench isolation structures 104 between adjacent active regions 106. In other embodiments, the bit line trenches 108 are formed only in the plurality of active regions 106.

[0087] like Figure 4 As shown, in one embodiment, the resistive memory device further includes:

[0088] The first dielectric layer 208 is located between the sidewalls of the gate structure 212 and the gate trench 110 and between the gate structure 212 and the bottom of the gate trench 110. By forming the first dielectric layer 208, the active region 106 can be isolated from the gate structure 212 subsequently formed in the gate trench 110, wherein the active region 106 includes a source formed in the source region 202 and a drain formed in the drain region 204.

[0089] In one embodiment, the first dielectric layer 208 includes at least one of a hafnium oxide material layer, a silicon dioxide layer, or a tantalum oxide material layer.

[0090] In one embodiment, the first dielectric layer 208 and the resistive material layer 206 are made of the same material, for example, hafnium oxide. Furthermore, the first dielectric layer 208 and the resistive material layer 206 are formed simultaneously.

[0091] like Figure 5 As shown, in one embodiment, the resistive memory device further includes a gate structure 212 filled in the gate trench 110. The gate structure 212 also serves as a word line structure (WL) in the resistive memory device. In one embodiment, the material of the bit line structure 210 and the gate structure 212 includes at least one of titanium nitride, titanium metal, tungsten metal, and doped polysilicon.

[0092] In one embodiment, the upper surface of the gate structure 212 is flush with the upper surface of the bit line structure 210 .

[0093] like Figure 5As shown, in one embodiment, the upper surface of the bitline structure 210 is lower than the upper surface of the substrate 102, that is, the bitline structure 210 is a buried bitline. In other embodiments, the upper surface of the bitline structure 210 is flush with the upper surface of the substrate 102 or the upper surface of the bitline structure 210 is higher than the upper surface of the substrate 102.

[0094] like Figure 6 As shown, in one embodiment, the resistive memory device further includes a protective layer 214 located on the bitline structure 210 and the gate structure 212. Furthermore, when the upper surface of the bitline structure 210 is lower than the upper surface of the substrate 102, the upper surface of the protective layer 214 is flush with or higher than the upper surface of the substrate 102. The protective layer 214 is formed of one or more materials selected from oxide, nitride, and oxynitride. The oxide may include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), spin-on glass (SOG), high-density plasma (HDP), or spin-on dielectric (SOD); the nitride may include silicon nitride (SiN); and the oxynitride may include silicon oxynitride (SiON).

[0095] Continue to refer Figure 6 In one embodiment, the resistive memory device further includes:

[0096] The second dielectric layer 112 is located on the substrate 102 and contacts the protective layer 214. Furthermore, the constituent material of the second dielectric layer 112 includes one or more of oxides, nitrides, and oxynitrides, wherein the oxides include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), spin-on glass (SOG), high-density plasma (HDP), or spin-on dielectric (SOD); the nitrides include silicon nitride (SiN); and the oxynitrides include silicon oxynitride (SiON).

[0097] In one embodiment, the second dielectric layer 112 is located on the upper surface of the substrate 102. Typically, the second dielectric layer 112 includes a silicon dioxide layer located on the upper surface of the substrate 102. Furthermore, the second dielectric layer 112 also includes a silicon nitride layer located on the upper surface of the silicon dioxide layer.

[0098] In one embodiment, the second dielectric layer 112 and the protective layer 214 are made of the same material.

[0099] Continue to refer Figure 6In one embodiment, the resistive memory device further includes a source lead-out structure 114 located on the source region 202. The source lead-out structure 114 penetrates the second dielectric layer 112 and contacts the source region 202. Furthermore, the conductive material forming the source lead-out structure 114 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. The metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO 2); and the metal silicide includes titanium silicide (TiSi). The source lead-out structure 114 contacts the doped source electrode in the source region 202.

[0100] In one embodiment, the upper surface of the source extraction structure 114 is higher than the upper surface of the second dielectric layer 112 .

[0101] In one embodiment, the lower surface of the source extraction structure 114 is lower than the upper surface of the substrate 102 , and the lower surface of the source extraction structure 114 is not lower than the lower surface of the source.

[0102] In another embodiment, the lower surface of the source extraction structure 114 is flush with the upper surface of the substrate 102 .

[0103] Continue to refer Figure 6 In one embodiment, the resistive memory device further includes:

[0104] The source metal line layer 116 is located on the substrate 102 and is in contact with the source lead-out contact, and is used to lead the source to the upper surface of the resistive memory device.

[0105] Figure 7 for Figure 6 The equivalent circuit diagram of the resistive memory device in one embodiment is shown in FIG. Figure 7 As shown in the figure, the arrow curve indicates the direction of current flow. The input end of the current is the source metal line layer 116 (SL), and the output end of the current is the bit line structure 210 (BL). The resistive memory device includes a transistor 216 and a variable resistance structure 218. The transistor 216 is composed of a source region 202, a gate structure 212 (i.e., a word line structure WL, where the gate structure 212 and the first dielectric layer 208 serve as the gate of the transistor), and a drain region 204. The variable resistance structure 218 is composed of the drain region 204, a resistive material layer 206 between the drain region 204 and the bit line structure 210, and the bit line structure 210.

[0106] In one embodiment, the resistive memory device is manufactured by using any of the above-mentioned methods for manufacturing a resistive memory device.

[0107] The present application also provides a storage device, which includes any of the resistive memory devices described above.

[0108] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above-described embodiments merely represent several implementation methods of the embodiments of the present application. The descriptions thereof are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for those skilled in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all fall within the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the patent of the embodiments of the present application shall be based on the appended claims.

Claims

1. A method for preparing a resistive memory device, characterized in that: include: Providing a substrate, wherein a shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure isolates active areas arranged in an array in the substrate; forming a bit line trench and a gate trench in the substrate, wherein each gate trench and one bit line trench cross the same active area and divide the active area into a source region located between the gate trench and the shallow trench isolation structure and a drain region located between the gate trench and the bit line trench; forming a resistive material layer on the sidewalls and bottom of the bit line trench; Filling the bit line trench to form a bit line structure, and filling the gate trench to form a gate structure; The variable resistance structure includes the bit line structure, the resistive material layer and the drain region.

2. The preparation method according to claim 1, characterized in that The resistive material layer includes at least one of a hafnium oxide material layer and a tantalum oxide material layer.

3. The preparation method according to claim 1, characterized in that An upper surface of the bit line structure is lower than an upper surface of the substrate.

4. The preparation method according to claim 1, characterized in that While forming the resistive material layer on the sidewall and bottom of the bit line trench, a first dielectric layer is formed on the sidewall and bottom of the gate trench.

5. The preparation method according to claim 4, characterized in that The first dielectric layer and the resistive material layer are made of the same material.

6. The preparation method according to claim 1, characterized in that An upper surface of the gate structure is flush with an upper surface of the bit line structure.

7. The preparation method according to claim 1, characterized in that Also includes: forming a protection layer on the bit line structure and the gate structure, wherein the protection layer is flush with the upper surface of the substrate; A second dielectric layer is formed on the substrate, wherein the second dielectric layer is in contact with the protective layer.

8. The preparation method according to claim 7, characterized in that After forming the second dielectric layer on the substrate, the method further comprises: A source lead-out structure is formed on the source region, wherein the source lead-out structure penetrates the second dielectric layer and contacts the source region.

9. A resistive memory device, characterized in that: include: A substrate having a shallow trench isolation structure formed therein, wherein the shallow trench isolation structure isolates active areas arranged in an array within the substrate; A bit line trench is opened in the substrate; A gate trench, wherein each gate trench and one bit line trench cross the same active area and divide the active area into a source region located between the gate trench and the shallow trench isolation structure and a drain region located between the gate trench and the bit line trench; a resistive material layer, located on the sidewalls and bottom of the bit line trench; A bit line structure filled in the bit line trench; a gate structure filled in the gate trench; The variable resistance structure includes the bit line structure, the resistive material layer, and the drain region.

10. The resistive memory device according to claim 9, wherein: The resistive material layer includes at least one of a hafnium oxide material layer and a tantalum oxide material layer.

11. The resistive memory device according to claim 9, wherein: An upper surface of the bit line structure is lower than an upper surface of the substrate.

12. The resistive memory device according to claim 9, wherein: Also includes: The first dielectric layer is located between the gate structure and the sidewall of the gate trench and between the gate structure and the bottom of the gate trench.

13. The resistive memory device according to claim 12, wherein: The first dielectric layer and the resistive material layer are made of the same material.

14. The resistive memory device according to claim 9, wherein: Also includes: a protective layer, located on the bit line structure and the gate structure, wherein the protective layer is flush with the upper surface of the substrate; a second dielectric layer, located on the substrate and in contact with the protective layer; A source lead-out structure is located on the source region, and the source lead-out structure penetrates the second dielectric layer and contacts the source region.

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