Caching Method, System and Chip

Abstract

The embodiments of the present application provide a caching system, method and chip. The caching method includes: receiving a data reading request, determining the data that needs to be written from the memory to the cache based on the data reading request; obtaining the number of data access requests received per unit time; selecting a first page from the cache based on the number of data access requests; and saving the data that needs to be written from the memory to the cache in the first page. The caching method shown in the embodiments of the present application can improve the data caching efficiency.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of cache technologies, and in particular, to a cache method, system, and chip. Background Art

[0002] With the development of chip process technologies, the implementation media of memory have become increasingly diversified. Die-stacked DRAM is a new technology proposed to solve the memory access bandwidth problem. Among them, through-silicon via (TSV) technology can be used to package a large-capacity storage chip and a processor on the same system-on-chip (SoC) to achieve a large-capacity on-chip memory. Taking 2.5D or 3D packaged DRAM as an example, there is data indicating that the bandwidth of on-chip memory can reach 4 to 8 times that of off-chip double data rate dynamic random access memory (DDR DRAM).

[0003] In the current technology, on-chip memory can be used as ordinary memory or as a cache for off-chip memory (DDR). When on-chip memory is used as a cache, the cache space in the cache is allocated in page granularity. The cache space of the cache can be divided into multiple pages. Similarly, the memory space can also be divided into multiple pages. When storing data in off-chip memory into a cache page, a cache page can be selected in the cache based on a pre-established mapping relationship between the memory page and the cache page for storage. When all cache pages in the cache are already storing data and new data needs to be stored in the cache, the least recently used data replacement method or the first-in first-out data replacement method is usually adopted to select a page from the cache to replace the data previously stored in the selected page. The page selected by the traditional method may store a large amount of dirty data, which is data in the cache that has been rewritten by the processor. When performing page replacement, it needs to be written back to memory. When there is a large amount of dirty data that needs to be written back to memory, it seriously occupies the cache bandwidth, causing data congestion, reducing the data transmission efficiency, and resulting in data access latency.

[0004] Therefore, how to improve the data caching efficiency in the scenario of a large-capacity cache has become a problem to be solved. Summary of the Invention

[0005] The cache method, system, and chip provided by the present application can improve the data caching efficiency.

[0006] To achieve the above object, the present application adopts the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a caching method, which includes: receiving a data reading request, determining data that needs to be written from memory to the cache based on the data reading request; obtaining the number of data access requests received within a unit time; selecting a first page from the cache based on the number of data access requests; and storing the data that needs to be written from memory to the cache in the first page.

[0008] In the caching method provided by the present application, data is stored in each cache page. When the data to be cached needs to overwrite the original data stored in the cache, the usage of the cache bandwidth can be determined by counting the number of access requests sent by the processor within a unit time, and then a cache page is selected based on the usage of the cache bandwidth to store the data to be cached in the selected cache page. In a specific implementation, a cache page with a lower dirty data rate among the stored data can be selected during a period with a high data transfer volume, which can reduce the occupancy rate of the memory access bandwidth and is beneficial to improving the data caching efficiency and the data access efficiency of the processor.

[0009] Based on the first aspect, in a possible implementation manner, selecting a first page from the cache based on the number of data access requests includes: in response to the number of data access requests being greater than or equal to a first threshold, selecting the page with the least amount of dirty data stored in the cache as the first page.

[0010] Based on the first aspect, in a possible implementation manner, selecting a first page from the cache based on the number of data access requests includes: in response to the number of data access requests being less than the first threshold, selecting the first page from the cache based on the priority level information of the data stored in each page of the cache; the priority level includes one of the following: least recently used information, first in first out information, or access frequency information.

[0011] Based on the first aspect, in a possible implementation manner, selecting a first page from the cache based on the number of data access requests includes: in response to the number of data access requests being greater than or equal to the first threshold, selecting the first page based on the cache access volume within a unit time and the memory access volume within a unit time.

[0012] By further introducing the ratio between the cache access volume and the memory access volume to select the first page to store data, the cache hit rate and the bandwidth occupancy rate can be further balanced, thereby further improving the caching efficiency.

[0013] Based on the first aspect, in a possible implementation manner, the cache access volume includes one of the following: the number of cache hits or the data transfer volume between the cache and the processor; the memory access volume includes one of the following: the number of memory accesses or the data transfer volume between the memory and the processor.

[0014] Based on the first aspect, in a possible implementation manner, the selecting of the first page based on the cache access volume per unit time and the memory access volume per unit time includes: determining a ratio between the cache access volume and the memory access volume; and selecting the first page from the cache based on the ratio between the cache access volume and the memory access volume.

[0015] Based on the first aspect, in a possible implementation manner, the selecting of the first page from the cache based on the ratio between the cache access volume and the memory access volume includes: in response to the ratio between the cache access volume and the memory access volume being greater than or equal to a second threshold, selecting the first page from the cache based on the position information of the page in the cache occupied by the data to be written from the memory to the cache and the position information of the dirty data saved in each page in the cache.

[0016] Based on the first aspect, in a possible implementation manner, the selecting of the first page from the cache based on the ratio between the cache access volume and the memory access volume includes: in response to the ratio between the cache access volume and the memory access volume being less than the second threshold, selecting the first page from the cache based on the priority level information of the data saved in each page in the cache; the priority level includes one of the following: least recently used information, first in first out information, or access frequency information.

[0017] Based on the first aspect, in a possible implementation manner, the method further includes: updating first index information saved in the cache, where the first index information is used to index the data to be written from the memory to the cache and saved in the first page.

[0018] Based on the first aspect, in a possible implementation manner, the method further includes: obtaining the position information of free data units in the first page, and updating second index information saved in the cache according to the position information of the free data units, where the second index information is used to index the original data in the data units corresponding to the position information in the first page.

[0019] Second aspect, an embodiment of the present application provides a cache system. The cache system includes a cache for storing data from memory and index information for indexing the data stored in the cache; a storage controller for receiving a data read request, determining data that needs to be written from memory to the cache based on the data read request; obtaining the number of data access requests received per unit time; selecting a first page from the cache based on the number of data access requests; and storing the data that needs to be written from memory to the cache in the first page.

[0020] Based on the second aspect, in a possible implementation, the storage controller is further configured to: in response to the number of data access requests being greater than or equal to a first threshold, select the first page from the cache based on the dirty data stored in the pages of the cache.

[0021] Based on the second aspect, in a possible implementation, the storage controller is further configured to: in response to the number of data access requests being less than the first threshold, select the first page from the cache based on the priority level information of the data saved in each page of the cache; the priority level includes one of the following: least recently used information, first in first out information, or access frequency information.

[0022] Based on the second aspect, in a possible implementation, the storage controller is further configured to: in response to the number of data access requests being greater than or equal to the first threshold, select the first page based on the cache access volume per unit time and the memory access volume per unit time.

[0023] Based on the second aspect, in a possible implementation, the cache access volume includes one of the following: the number of cache hits or the data transfer volume between the cache and the processor; the memory access volume includes one of the following: the number of memory accesses or the data transfer volume between the memory and the processor.

[0024] Based on the second aspect, in a possible implementation, the storage controller is further configured to: determine the ratio between the cache access volume and the memory access volume; select the first page from the cache based on the ratio between the cache access volume and the memory access volume.

[0025] Based on the second aspect, in a possible implementation, the storage controller is further configured to: in response to the ratio between the cache access volume and the memory access volume being greater than or equal to a second threshold, select the first page from the cache based on the location information of the page in the cache occupied by the data that needs to be written from memory to the cache and the location information of the dirty data saved in each page of the cache.

[0026] Based on the second aspect, in a possible implementation, the storage controller is further configured to: in response to a ratio between the cache access volume and the memory access volume being less than the second threshold, select the first page from the cache based on the priority level information of the data saved in each page in the cache; the priority level includes one of the following: least recently used information, first in first out information, or access frequency information.

[0027] Based on the second aspect, in a possible implementation, the cache system further includes a first counter, and the first counter is configured to count the number of data access requests received by the storage controller within a unit time.

[0028] Based on the second aspect, in a possible implementation, the cache system further includes a second counter; the second counter is configured to count the cache access volume of the storage controller within a unit time; wherein, the cache access volume includes one of the following: the number of cache hits or the data transfer volume between the cache and the processor.

[0029] Based on the second aspect, in a possible implementation, the cache system further includes a third counter; the third counter is configured to count the memory access volume of the storage controller within a unit time; wherein, the memory access volume includes one of the following: the number of memory accesses or the data transfer volume between the memory and the processor.

[0030] In a third aspect, an embodiment of the present application provides a chip, and the chip includes the cache system as described in the second aspect.

[0031] Based on the third aspect, in a possible implementation, the chip further includes a processor, configured to access the data stored in the cache system and store the processed data into the cache system. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0033] Figure 1 is a schematic structural diagram of a cache system provided by an embodiment of the present application;

[0034] Figure 2 is a schematic diagram of the mapping relationship between a memory page and a cache page provided by an embodiment of the present application;

[0035] Figure 3It is a schematic structural diagram of a cache provided by an embodiment of the present application;

[0036] Figure 4 It is another schematic structural diagram of a cache provided by an embodiment of the present application;

[0037] Figure 5 It is another schematic structural diagram of a cache provided by an embodiment of the present application;

[0038] Figure 6 It is as provided by an embodiment of the present application Figure 3 A schematic diagram of the data units occupied by the dirty data stored in cache page B as shown;

[0039] Figure 7 It is as provided by an embodiment of the present application Figure 3 A schematic diagram of the data units occupied by the dirty data stored in cache page A as shown;

[0040] Figure 8 A schematic diagram of the data units in the cache page occupied by the data in the memory page to be stored provided by an embodiment of the present application;

[0041] Figure 9 It is a flowchart of a caching method provided by an embodiment of the present application;

[0042] Figure 10 It is another flowchart of a caching method provided by an embodiment of the present application;

[0043] Figure 11 It is a schematic structural diagram of a caching device provided by an embodiment of the present application. Detailed implementation manners

[0044] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0045] The "first", "second" and similar terms mentioned herein do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a" or "one" do not denote a quantity limitation, but mean that there is at least one.

[0046] The "module" mentioned herein generally refers to a functional structure divided according to logic, and the "module" can be implemented by pure hardware, or a combination of software and hardware.

[0047] In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or more advantageous than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" refers to two or more. For example, a plurality of pages refers to two or more pages; a plurality of index information refers to two or more pieces of data information.

[0048] Please refer to Figure 1 , which shows a schematic structural diagram of a cache system applied to the present application.

[0049] In Figure 1 , the cache system 100 includes a processor, a storage controller, a cache, and a memory. Among them, the memory stores the data required for the processor to run. The cache stores some of the data stored in the memory. The processor can initiate a data access request and perform data processing. The storage controller controls the data interaction between the processor and the cache, and between the cache and the memory based on the data access request initiated by the processor. Under the control of the storage controller, the data in the memory can be written into the cache, provided to the processor, or written into the memory.

[0050] After the processor initiates a data access request, the storage controller can detect whether the data exists in the cache based on the data access request. If the data accessed by the processor is stored in the cache, the storage controller controls the cache to provide the data to the processor through the bus; if the data accessed by the processor is not stored in the cache, the storage controller can control the data to be retrieved from the memory and provided to the processor. In addition, after the data is retrieved from the memory, it can also be written into the cache so that the processor can directly obtain the data from the cache next time.

[0051] As Figure 1 shown, the cache may include a multi-level cache structure, such as L1 level, L2 level, and L3 level. When the processor accesses data, it can first access the L1-level cache. When the L1-level cache misses, it can continue to access the L2-level cache. When the L2-level cache misses, it can continue to access the L3-level cache. When the L3-level cache misses, it can obtain data from the memory. That is, for the L1-level cache, the L2-level cache and the L3-level cache are its lower-level caches; for the L2-level cache, the L3-level cache is its lower-level cache. When data needs to be written back, for example, when the data stored in the L1 level needs to be written back, it can be written back to the L2-level cache, the L1-level cache, or the memory; when the data stored in the L3 level needs to be written back, it can only be written back to the memory. The L1-level cache, the L2-level cache, and the L3-level cache can be caches with the same cache structure but different data capacities.Figure 1 The cache shown does not distinguish between L1, L2, and L3 caches.

[0052] As Figure 1 In the cache shown, the cache space in each level of cache is allocated in page granularity. Specifically, the cache space of each level of cache can be divided into multiple pages. In the following description, the pages in the cache are uniformly referred to as cache pages. In some implementations, a cache page can also be understood as a cache line. Based on a logical structure similar to the cache space, the storage space of the memory can also be divided into multiple pages. In the following description, the pages in the memory are uniformly referred to as memory pages. The storage capacity of a memory page can be the same as that of a cache page. The data stored in the same cache page can come from the same memory page or from different memory pages. In addition, there is a mapping relationship between the memory page and the cache page, which is associated through a set. That is to say, the data saved in multiple memory pages can be stored in the cache pages corresponding to the same set in the cache at the same time, and the pages in the same set in the cache have a competitive relationship. To alleviate this competitive relationship, multiple ways can be set for each set. When there is no data stored in the cache pages corresponding to the multiple ways, the data saved in the memory pages mapped to the same set can be stored in the cache pages corresponding to any way in the set. The number of ways in the cache indicates the number of set-associative ways. For example, it can include but is not limited to: two-way set associative, four-way set associative, or eight-way set associative, etc.

[0053] Specifically, as Figure 2 shown, it schematically shows the corresponding relationship diagram between the cache space in the cache and the storage space in the memory. Figure 2 Exemplarily shows the case where the cache is two-way set associative. In Figure 2 it, the cache includes two ways, Way0 and Way1, and two sets of page data can be stored in each way. Based on a logical structure similar to the cache space, the storage space of the memory can be divided into eight memory pages. Among them, the data in memory page 01, memory page 11, memory page 21, and memory page 31 can be respectively stored in the cache pages corresponding to set 0 of the cache, and the data in memory page 02, memory page 12, memory page 22, and memory page 32 can be respectively stored in the cache pages corresponding to set 1 of the cache.

[0054] In addition, a page can be further divided into multiple data units. When storing the data saved in the memory into the cache, data access is usually performed in units of data blocks (Data Block). In the cache, a cache page may store all the data units of a certain memory page, or may store only some of the data units of a certain memory page. That is to say, when writing the data in a certain memory page into the cache, only some of the data units of the memory page can be cached. For example, when the data that can be saved in a page in the cache or memory is 4KB, if a page in the cache or memory is divided into 32 data units, each data unit can save 128B of data. Among them, the cache page can only save the data saved in some data units (such as 5 data units) of a certain memory page.

[0055] As Figures 3 - 5 shown, they respectively show three schematic diagrams of the cache structures as Figure 1 shown.

[0056] In Figure 3 , the cache can include a tag array (Tag Array) and a data array (Data Array).

[0057] The data retrieved from the memory is stored in the cache page of the data array (Data Array), and the index information used to index the data saved in the cache page is stored in the tag array (Tag Array). Among them, both the tag array and the data array are m*n arrays. There is a pre-established mapping relationship between the cache positions in the tag array (Tag Array) and the pages in the data array (Data Array). That is to say, after the storage position of the data in the data array (Data Array) is fixed, the position of the corresponding index information in the tag array (Tag Array) is fixed. In the tag array (Tag Array) and the data array (Data Array), each row represents a set, and each column represents a way. Each element in the tag array (Tag Array) is an index information, and each element in the data array (Data Array) is a cache page. It can be seen from Figure 3 that the elements in the tag array (Tag Array) and the elements in the data array (Data Array) are in one-to-one correspondence, and the index information in the tag array (Tag Array) is the index information of the data stored in the corresponding cache page in the data array (Data Array). In the cache as Figure 3 shown, the data saved in each cache page in the data array (Data Array) comes from the same memory page.

[0058] The following introduces the index information stored in the tag array Tag Array. Each index information may include tag information, valid bits information, dirty bits information, and priority level information. Specifically, the Tag information is used to indicate the physical address information of the memory page from which the data stored in the cache page comes in the memory and the set information corresponding to the cache page to which the data is stored. Among them, the data from the same memory page has the same Tag information. The dirty bits information is used to indicate whether the data in the data unit saved in the cache page is dirty data. If some bits of the Dirty Bits are set to 0, it indicates that the data saved in the corresponding data unit is clean data and can be directly invalidated without being written back to the off-chip memory when replacement occurs. On the contrary, if some bits of the Dirty Bits are set to 1, when replacement occurs, all the data in the data unit where the corresponding dirty data is located needs to be written back to the off-chip memory. Here, the dirty data specifically refers to the data rewritten by the processor saved in the cache. The memory does not save this data. If the dirty data in the cache is overwritten by other data and not written back to the memory, data loss will occur. Therefore, when the dirty data is overwritten, it needs to be written back. The valid bits information is used to indicate whether each data unit in the cache page stores valid data. Usually, if the cache page includes several data units, the valid bit information is represented by several bits. For example, if the cache page includes 32 data units, it is represented by 32 bits. In addition, each bit can include a "0" state and a "1" state. When a certain bit is "1", it means that the data saved in the corresponding data unit is valid; when a certain bit is "0", it means that the data saved in the corresponding data unit is invalid. The priority level information is used to indicate whether it is preferentially replaced when page replacement occurs. The priority level information PRI includes one of the following: least recently used (LRU) information, which is used to indicate the page that has been least recently used among the pages currently stored in the cache. When this priority level is used, the page that has been least recently used is preferentially replaced; Frequency Based Replacement (FBR) information, which is used to indicate the access frequency information among the pages currently stored in the cache. When this priority level is used, the page with the lowest usage frequency is preferentially replaced; First In First Out (FIFO) information, which is used for the sequence information of the pages stored in the cache. When this priority level is used, the page that was first stored in the cache is preferentially replaced. The way of page replacement can be selected according to the needs of the application scenario.

[0059] Please continue to refer to Figure 4 which shows asFigure 1 Another structural schematic diagram of the cache shown.

[0060] In Figure 4 , the cache may include a tag array Tag Array and a data array Data Array. Among them, both the tag array and the data array may be m*n arrays, and there is a pre-established position mapping relationship between the cache positions in the tag array Tag Array and the pages in the data array DataArray. After the storage position of the data in the data array Data Array is fixed, the position of the corresponding index information in the tag array Tag Array is fixed. Different from Figure 3 the cache shown, Figure 4 in the cache shown, the data stored in each cache page in the data array Data Array may come from different memory pages. Correspondingly, multiple index information is stored at the position of the tag array Tag Array that has a mapping relationship with each cache page. Taking Figure 4 as an example, assume that the data stored in cache page A comes from Figure 2 the memory pages 01 and 11 shown, then in the tag array Tag Array, the index information Index01 and the index information Index11 are stored at the storage position that has a mapping relationship with cache page A. Among them, the index information Index01 is used to index the data from memory page 01 stored in cache page A; the index information Index11 is used to index the data from memory page 11 stored in cache page A.

[0061] Please continue to refer to Figure 5 , which shows another structural schematic diagram of the cache as shown in Figure 1 .

[0062] In Figure 5 , the cache may include a tag array Tag Array and a data array Data Array. Different from the cache structures shown in Figure 3 and Figure 4 , in the cache shown in Figure 4 , the tag array is an m*n array, and the data array may be an m*s array, where s is less than or equal to n. That is to say, the number of sets of the tag array Tag Array and the data array Data Array is the same, and the number of ways in the tag array Tag Array is not less than the number of ways in the data array DataArray. Among them, Figure 4 schematically shows that the tag array Tag Array is a 2*4 array and the data array Data Array is a 2*3 array. AsFigure 5 In the cache shown, the data stored in one cache page may come from the same memory page or different memory pages. Figure 5 Among the index information stored in the tag array TagArray shown, in addition to including Figure 2 each piece of information included in the index information stored in the cache shown, it also includes location information, which is used to indicate the location of the cache page where the data indexed by the index information is located in the data array DataArray. This location information can be way information or (set, way) information. Which location information to use is selected according to the needs of the application scenario. It should be noted that when the above location information can be way information, there is a preset mapping relationship between the set in the tag array Tag Array and the set in the data array Data Array at this time. For example, the index information stored in set Set0 in the tag array Tag Array is respectively used to index the data stored in each cache page in set set0 in the data array. When the above location information is (set, way) information, the index information of the data stored in each cache page in the data array can be stored at any position in the tag array Tag Array. When performing Tag information retrieval, it is necessary to compare the Tag information of the data to be accessed with the Tag information in all the index information in the tag array Tag Array one by one.

[0063] Based on Figures 3 - 5The cache structure shown. Assume that the cache is in a full storage state. If the data saved in the memory page is stored in the cache, and the data to be cached comes from a different memory page than the data currently saved in each cache page, at this time, a cache page needs to be selected from the data array Data Array to store the data to be cached, and when the data to be cached is stored in the selected cache page, the original data previously saved in the cache page is usually overwritten. In traditional cache technologies, the cache page for storing the overwritten data is usually selected based on priority information such as the LRU information or FIFO information of the data saved in each cache page. Before storing the data to be cached in the cache, the dirty data in the overwritten data needs to be written back (for example, written back to the memory or the next-level cache). As the cache capacity increases, the amount of valid data and dirty data stored in the cache page may be large. Selecting the overwritten data using LRU information or FIFO information does not consider the amount of dirty data. When the amount of dirty data in the overwritten data is large, a large amount of dirty data needs to be written back to the memory or the next-level cache, seriously occupying the cache bandwidth, thus reducing the data caching efficiency. However, the data stored in some unselected cache pages may include less dirty data. If such a page is selected, only a small amount of dirty data needs to be written back. Take Figure 3 the cache shown as an example. Assume that the original data currently stored in cache page A includes a large amount of dirty data, and the original data currently stored in the remaining cache pages includes less dirty data. Assume that based on the LRU information of the data saved in each cache page, it is determined that the data saved in cache page A is the least recently used data. At this time, a large amount of dirty data in cache page A needs to be written back, seriously occupying the memory access bandwidth. If the data to be cached is stored in cache page B, it may only be necessary to write back less dirty data, thereby reducing the occupation of the memory access bandwidth and improving the data caching efficiency.

[0064] Based on this, in the cache system shown in the embodiments of the present application, when there is data saved in each cache page and the data to be cached needs to overwrite the original data stored in the cache, the usage of the cache bandwidth can be determined by counting the number of access requests sent by the processor per unit time, and then a cache page is selected based on the usage of the cache bandwidth to store the data to be cached in the selected cache page. In a specific implementation, a cache page with less dirty data in the saved data can be selected during a period with a high data transfer volume, thereby reducing the occupancy rate of the memory access bandwidth, which is beneficial to improving the data caching efficiency and the data access efficiency of the processor.

[0065] In Figure 1In the cache system shown, a first counter is further included. The first counter is used to count the number of access requests sent by the processor within a unit time. Here, the unit time can be, for example, 1 s or one clock cycle in the cache system.

[0066] Next, taking Figure 3 the cache structure shown as an example, the caching method of the cache system 100 shown in the embodiments of the present application will be described in detail.

[0067] When it is necessary to store the data saved in Figure 2 the memory page 21 shown into the cache page, assuming that based on Figure 2 the mapping relationship between the memory page and the cache page shown, it is necessary to store the data saved in the memory page 21 into the cache page corresponding to Set0 in the data array Data Array. At this time, the storage controller can query whether the cache page corresponding to Set0 in the data array DataArray is in a full storage state.

[0068] In a specific implementation, the storage controller can query whether index information is stored in each storage location in the tag array Tag Array to determine whether the cache is in a full storage state. In some other implementation manners, the storage controller can also query whether data is stored in each cache page in the data array Data Array to determine whether the cache is in a full storage state. Assume that index information is stored in each storage location in the current tag array Tag Array, as Figure 3 shown. That is, the cache is in a full storage state at this time.

[0069] Then, the storage controller can obtain the number of access requests sent by the processor within a unit time from the first counter. Here, the access requests sent by the processor can include reading data from the cache or the memory, and can also include writing data to the cache or the memory. The storage controller can select a cache page from Figure 2 the cache shown based on the number of access requests sent by the processor within a unit time to save the data to be cached.

[0070] When the number of access requests sent by the processor within a unit time is less than the first threshold, it indicates that the frequency of the processor accessing the memory or the cache is relatively low. At this time, the occupancy rate of the cache bandwidth used for data transmission between the cache and the processor is relatively low, and the amount of data transmitted by the cache bandwidth is within an acceptable range. At this time, in order to improve the memory access hit rate of the processor, the storage controller can select a cache page for saving the data to be cached based on the priority level information.

[0071] Specifically, the storage controller can query the priority level information of each index information Index saved at the storage location corresponding to Set0 in the tag array Tag Array to determine the priority level of the data that each index information can index. Among them, the priority level information can include one of the following: LRU information, FIFO information, or FBR information. Specifically, the LRU information in each index information is pre-calculated by the storage controller through the LRU algorithm. For example, the data usage within a preset time period from the current time can be sorted (usually, the data usage is reflected by the number of accesses of the processor to the cache pages for storing data), and the corresponding LRU information is set for the data saved in each cache page based on the sorting result. In addition, the FIFO information and FBR information can also determine the corresponding information of the data saved in each cache page by using their respective algorithms, which will not be elaborated here. Assume that by querying the index information Index of each page, it is assumed that it is determined that Figure 3 the data saved in the cache page B shown has the lowest priority level. At this time, the storage controller can store the data saved in the memory page 21 to be cached into the cache page B of the data array Data Array, and then update the index information in the tag array Tag Array that is used to index the data saved in the cache page B. That is, update the previously saved index information Index11 to the index information Index21.

[0072] It should be noted that before storing the data saved in the memory page 21 into the cache page B, it is also necessary to write the dirty data in the data previously saved in the cache page B back to the memory or the next-level cache.

[0073] When the number of access requests sent by the processor per unit time is greater than or equal to the first threshold, it indicates that the processor accesses the memory or cache at a relatively high frequency, and the occupancy rate of the cache bandwidth and interface used for data transmission with the processor in the cache is relatively high. If the priority level information selection method is adopted, the data to be overwritten selected is the data in the cache page B. Assume that the cache page B includes 32 data units, and among them, 25 data units currently save valid data. Among these 25 data units, 20 data units save dirty data, such as Figure 6As shown. Before storing the data saved in the memory page 21 to be cached into the cache, it is necessary to write back all the dirty data saved in the above 20 data units. In this case, writing back the dirty data also occupies too much bandwidth resource. Since the amount of data that can be transmitted by the cache bandwidth and the interface per unit time is limited, it may cause data congestion, reduce the data access efficiency of the processor and the storage efficiency of the cache, and further reduce the running speed of the device or system. Assume that there are 20 data units in the current cache page A whose saved data is valid data, and among these 20 data units, 5 data units have saved dirty data. The data storage situation of each data unit in the cache page A is as Figure 7 shown. If the data to be cached is stored in the cache page A, only the dirty data saved in 5 data units needs to be written back, and the bandwidth pressure can be greatly relieved at this time.

[0074] It should be noted that the data units occupied by the data saved in the page are reflected by the valid bit information in the index information. Among them, each bit in the valid bit information represents a data unit, 0 indicates that the data saved in the data unit is valid, and 1 indicates that the data saved in the data unit is invalid. For example, when the cache page includes 32 data units, both the valid bit information and the dirty bit information in the index information can be represented by 32 bits. When the data stored in a certain data unit is valid, the bit indicating this data unit in the valid bit information can be set to valid (for example, set to "1"); when a certain data unit is invalid, the corresponding valid bit of this data unit can be set to invalid (for example, set to "0"). In addition, only when the data saved in a certain data unit is valid and has dirty data, it is necessary to write back the data saved in this data unit.

[0075] Thus, when the processor accesses the memory or the cache at a high frequency, in order to avoid data congestion caused by writing back too much dirty data, the storage controller can select the page with the least amount of dirty data for data storage. Specifically, it can query the dirty bit information in each index information saved in the tag array Tag Array and select the cache page with the least amount of dirty data.

[0076] Assume that Figure 3 the dirty bit information in the index information Index01 used to index the data in the cache page A is: 00000000000000001100110000000000, Figure 3The dirty bit information in the index information Index11 used to index the data in the cache page B is as follows: 00000001111110001100110000000000. Among them, in the dirty bit information, each bit represents a data unit. "0" means that there is no dirty data stored in the data unit, and "1" means that there is dirty data stored in the data unit. By comparing the dirty bit information in the index information Index01 and the dirty bit information in the index information Index11, it can be determined that the cache page A that can be indexed by the index information Index01 stores the least amount of dirty data. At this time, the storage controller can store the data saved in the memory page 21 to be cached into the cache page A, and then update the index information in the tag array Tag Array used to index the data saved in the cache page A. That is, update the previously saved index information Index01 to the index information Index21. It should be noted that before storing the data saved in the memory page 21 into the cache page A, it is also necessary to write back the previously stored dirty data in the cache page A to the memory or the next-level cache.

[0077] It should be noted that the first threshold of the number of access requests sent by the processor per unit time shown in the embodiments of the present application can be determined based on the maximum number of accesses that the cache can handle per unit time. When the maximum number of accesses that the cache can handle is relatively high, the first threshold can be increased; when the maximum number of accesses that the cache can handle is relatively low, the first threshold can be decreased.

[0078] In another possible implementation, when the number of access requests sent by the processor per unit time is greater than or equal to the first threshold, the storage controller can further select a cache page to save data based on the cache access volume per unit time and the memory access volume per unit time.

[0079] The cache system 100 may further include a second counter and a third counter. The second counter is used to count the cache access volume per unit time; the third counter is used to count the memory access volume per unit time. The cache access volume can be the number of cache hits or the data transfer volume between the cache and the processor; the memory access volume can be the number of times the processor accesses the memory or the data transfer volume between the memory and the processor. In addition, when the cache access volume and the memory access volume are the number of cache hits and the number of times the processor accesses the memory respectively, only one second counter can be set above, and the third counter is not set. The second counter is used to count the number of cache hits, and the number of times the processor accesses the memory can be determined by subtracting the number of cache hits from the number of access requests sent by the processor.

[0080] In a specific implementation, when the cache access volume is the number of cache hits and the memory access volume is the number of times the processor accesses the memory, the second threshold can be the ratio of the maximum number of accesses that the cache can handle per unit time to the maximum number of accesses that the memory can handle per unit time; when the cache access volume is the data transfer volume between the cache and the processor and the memory access volume is the data transfer volume between the memory and the processor, the second threshold can be the ratio of the maximum data transfer rate of the cache per unit time to the maximum data transfer rate of the memory.

[0081] The storage controller can obtain the cache access volume per unit time from the second counter and the memory access volume per unit time from the third counter. Then, it determines the ratio of the cache access volume to the memory access volume. When this ratio is less than or equal to the second threshold, it indicates that the hit rate of the processor accessing the cache is relatively low at this time, and a large amount of data needs to be obtained from the memory. At this time, the cache page can be selected based on the priority level information, thereby improving the cache hit rate; when this ratio is greater than the second threshold, it indicates that the cache bandwidth is overloaded, and the cache page with the least amount of dirty data can be selected for data storage.

[0082] In the embodiment of the present application, the storage controller can obtain the number of access requests sent by the processor per unit time from the first counter. When the number of access requests sent by the processor per unit time is less than the first threshold, the cache page can be selected by querying the priority level information in the index information stored in the cache to store the data to be stored. When the number of access requests sent by the processor per unit time is greater than or equal to the first threshold, the storage controller can obtain the cache access volume per unit time from the second counter and the memory access volume per unit time from the third counter, and determine the ratio between the cache access volume and the memory access volume. When the ratio between the cache access volume and the memory access volume is less than the second threshold, the cache page can be selected by querying the priority level information in the index information stored in the cache to store the data to be stored; when the ratio between the cache access volume and the memory access volume is greater than or equal to the second threshold, the page with the least amount of dirty data can be selected for data storage. Thus, the cache hit rate and the bandwidth occupancy rate can be further balanced, thereby further improving the cache efficiency.

[0083] The above elaborates on how the cache system shown in the embodiment of the present application selects a cache page to store the data in the memory into the selected cache page when each cache page in the cache stores data. Among them, the above implementation method can be applied to Figures 3 - 5 any cache structure shown.

[0084] In such as Figure 5In the cache structure shown, since there is a decoupling between the memory pages in the data array Data Array and the storage locations in the tag array Tag Array, it can have different numbers of arrays. In this case, there is a situation where each cache page in the data array Data Array stores data, while there may still be free storage locations in the tag array Tag Array where no tag information is stored, as shown in Figure 5 shown. At this time, it is necessary to store the data stored in different memory pages into the same cache page. For a data unit in the cache page, if the data unit is used to store the data saved in the first memory page, then the data unit cannot be used to store the data saved in the second memory page. Assuming that there is data in the first memory page that needs to be stored in this data unit, then the data saved in other memory pages previously saved in this data unit needs to be overwritten.

[0085] Based on the above scenario, in the embodiments of the present application, when the number of access requests sent by the processor per unit time is greater than or equal to the first threshold, cache pages can be selected to store the data to be cached based on the valid bit information of the data to be cached, the valid bit information of the data saved in the cache page, and the dirty bit information.

[0086] Specifically, when the data saved in memory page 01 needs to be stored in the cache page, assume that there is a mapping relationship between memory page 01 and the cache page corresponding to Set0 in the cache. At this time, the data saved in memory page 01 needs to be stored in the cache page corresponding to Set0 in the data array Data Array. The storage controller can query the cache page corresponding to Set0 in the data array Data Array and the storage location corresponding to Set0 in the tag array Tag Array, and find that the cache pages corresponding to Set0 in the Data Array are all storing data, and there are still idle positions in the storage location corresponding to Set0 in the tag array Tag Array. At this time, the storage controller can determine the valid dirty bit information in the data stored in each cache page based on the valid bit information and dirty bit information of the data stored in each cache page corresponding to Set0 (only the valid dirty data needs to be written back, and it can be not written back when the dirty data is invalid). Then, the storage controller can select the page with the least number of conflicting positions with memory page 01 based on the valid bit information of the data saved in the memory page 01 to be cached and the valid dirty bit information of the data saved in the cache page corresponding to Set0. The conflict here means that when the data saved in the memory page 01 to be cached is stored in cache page A, the data units occupied by the data in cache page A are in conflict with the data units occupied by the valid dirty data currently stored in the cache page. For example, the data units occupied by the data saved in the memory page 01 to be cached are as Figure 8 shown. Correspondingly, its valid bit information is: 0xFF0E410. Assume Figure 5 that in, the valid bit information of the data saved in cache page B is 0xC975A450, and the dirty bit information is 0x00700060, and its valid dirty bit information is 0x00700040; the valid bit information of the data saved in cache page C is 0xFF8DAC20, and the dirty bit information is 0x06980020, and its valid dirty bit information is 0x06880020. Thus, it can be determined that the data units occupied by the data saved in cache page B conflict the least with the data units occupied by the data saved in the memory page 01 to be cached, so the data saved in the memory page 01 to be cached can be stored in cache page B. It should be noted that before storing the data saved in the memory page 01 to be cached in cache page B, the valid dirty data overwritten in cache page B also needs to be written back to the memory or the next-level cache. In addition, the index information Inedx02 stored in the cache also needs to be updated. Specifically, update the valid bit information and dirty bit information in the index information Inedx02.

[0087] In the example of the embodiment of the present application, the cache, the storage controller, and the processor can be integrated on the same chip to form a system on chip (SOC). In addition, the processor and the cache can be integrated on the same chip, and the storage controller is integrated on another chip. In practical applications, the cache can also be integrated with the processor on different chips. The off-chip cache adopts the same storage structure design as the on-chip cache provided in the embodiments of the present application and implements the same functions as the on-chip cache provided in the embodiments of the present application. The off-chip cache should also be regarded as falling within the protection scope of the embodiments of the present application.

[0088] Based on Figure 1 the cache system shown, Figure 2 the mapping relationship between the memory page and the cache page shown, Figures 3 - 5 and the cache structure shown, the embodiment of the present application further provides a cache method, and the cache method is applied to a storage controller as shown in Figure 1 Please continue to refer to Figure 9 , which shows a process 900 of the cache method provided by the embodiment of the present application. The process 900 of the cache method includes the following steps:

[0089] Step 901, receive a data read request, and determine the data that needs to be written from the memory to the cache based on the data read request.

[0090] In this embodiment, the data read request usually carries the address information of the data to be read, and the address information includes tag information Tag, set information Set, etc. The cache controller retrieves the Tag Array using the set information Set based on the instruction issued by the processor, and finds multiple index information within the set of Set. Then, the cache controller can continue to check whether one of the multiple index information includes the Tag information carried in the data read request. Assuming that none of the index information includes the Tag information carried in the data read request, it means that the Tag is not hit. That is, the data that the processor wants to read is not saved in the cache. At this time, the storage controller needs to obtain the data that the processor wants to read from the memory.

[0091] Then, the storage controller can further determine the data that needs to be written from the memory to the cache based on the Tag information carried in the data read request. That is, determine the position information of the memory page for storing the data to be written in the memory. Then, based on the mapping relationship between the memory page and the cache page as shown in Figure 2 , determine multiple cache pages for storing the data to be written.

[0092] Next, it is detected whether data is stored in all of the determined multiple cache pages. When it is detected that data is stored in all of the multiple cache pages, in order to avoid a large amount of dirty data being stored in the cache page selected for storing the data to be written, when the data to be read overwrites the original data stored in the selected cache page, a large amount of dirty data needs to be written back to the memory or the next-level cache, seriously occupying the cache bandwidth and thus reducing the data caching efficiency. At this time, step 902 can be executed.

[0093] Step 902: Obtain the number of data access requests received per unit time.

[0094] The storage controller can determine the number of data access requests received per unit time. Specifically, a first counter as shown can be set in the storage controller. This first counter is used to count the number of data access requests received per unit time. Here, the unit time can also be referred to as a clock cycle. The unit time can be, for example, 1 s or 30 ms, etc., and is not specifically limited. Figure 1 The storage controller can obtain the number of data access requests received per unit time from the first counter. Generally, this data access request is initiated by the processor. It can be a data read request or a data write request. When the processor sends a data access request to the storage controller, the counter can be incremented by 1.

[0095]

[0096] Step 903: Select a first page from the cache based on the number of data access requests received per unit time.

[0097] In the embodiment of the present application, a first threshold can be preset in the storage controller. This first threshold can also be referred to as the maximum access times value per unit time. The maximum access times value per unit time can be set based on the cache bandwidth, cache capacity, etc.

[0098] When the number of data access requests received per unit time is less than the first threshold, it indicates that the frequency of the processor accessing the memory or cache is relatively low. At this time, the occupancy rate of the cache bandwidth used for data transmission between the cache and the processor is relatively low, and the amount of data transmitted by the cache bandwidth is sufficient within an acceptable range. At this time, in order to improve the memory access hit rate of the processor, the storage controller can select a cache page for storing the data to be read based on the priority level information of the data stored in each determined cache page. The priority level information can include one of the following: LRU information, FIFO information, or FBR information.

[0099] ​When the number of data access requests received within a unit time is greater than or equal to the first threshold, it indicates that the processor accesses the memory or cache at a relatively high frequency, and the occupancy rate of the cache bandwidth and interface used for data transfer with the processor in the cache is relatively high. If the priority level information selection method is adopted, a large amount of valid data may exist in the selected overwritten data, and a lot of the valid data includes dirty data. Writing back the dirty data also occupies too much bandwidth resources. Since the amount of data that can be transmitted by the cache bandwidth and interface within a unit time is limited, it may cause data congestion, reduce the data access efficiency of the processor and the storage efficiency of the cache, and further reduce the operating rate of the device or system. At this time, in order to avoid data congestion caused by writing back too much dirty data, the storage controller can select the page with the least amount of dirty data for data storage. Specifically, based on the data dirty bit information saved in each determined cache page, the cache page for saving the data to be read can be selected.

[0100] Step 904, save the data that needs to be written from the memory to the cache in the selected first page.

[0101] The cache method shown in the embodiments of the present application, when data and the original data stored in the cache need to be overwritten with the data to be cached in the cache page, can determine the usage of the cache bandwidth by counting the number of access requests sent by the processor within a unit time, and then select a cache page based on the usage of the cache bandwidth to store the data to be cached in the selected cache page. In a specific implementation, a cache page with a lower dirty data rate among the saved data can be selected during a period with a higher data transfer volume, thereby reducing the occupancy rate of the memory access bandwidth, which is beneficial to improving the data caching efficiency and the data access efficiency of the processor.

[0102] Please continue to refer to Figure 10 , which shows a flowchart of another embodiment of the cache method provided by the present application. The process 1000 of the cache method includes:

[0103] Step 1001, receive a data read request, and determine the data that needs to be written from the memory to the cache based on the data read request.

[0104] Step 1002, obtain the number of data access requests received within a unit time.

[0105] Among them, the specific implementation of step 1001 and step 1002 can refer to Figure 9 the relevant descriptions of step 901 and step 902 shown, and will not be elaborated here.

[0106] Step 1003, determine whether the number of data access requests is greater than or equal to a first threshold. When it is determined that the number of data access requests is less than the first threshold, execute Step 1004; when it is determined that the number of data access requests is greater than or equal to the first threshold, execute Step 1005.

[0107] Step 1004, select a first page for storing the data to be written based on the priority level information of the data stored in each cache page determined.

[0108] Step 1005, determine whether the ratio between the cache access volume per unit time and the memory access volume per unit time is greater than or equal to a second threshold.

[0109] When the number of data access requests received per unit time is greater than or equal to the first threshold, the storage controller also selects a cache page for storing the data to be read based on the cache access volume per unit time and the memory access volume per unit time. The cache access volume includes one of the following: the number of cache hits or the data transfer volume between the cache and the processor; the memory access volume includes one of the following: the number of memory accesses or the data transfer volume between the memory and the processor.

[0110] Specifically, as Figure 1 shown, the cache system 100 further includes a second counter and a third counter. The second counter is used to count the cache access volume per unit time; the third counter is used to count the memory access volume per unit time. In addition, when the cache access volume and the memory access volume are respectively the number of cache hits and the number of times the processor accesses the memory, only one second counter can be set above, without setting the third counter. The second counter is used to count the number of cache hits, and the number of times the processor accesses the memory can be determined by subtracting the number of cache hits from the number of access requests sent by the processor.

[0111] The storage controller can obtain the cache access volume per unit time from the second counter and the memory access volume per unit time from the third counter. Then determine the ratio of the cache access volume and the memory access volume.

[0112] When the cache access volume is the number of cache hits and the memory access volume is the number of times the processor accesses the memory, the second threshold can be the ratio between the maximum number of accesses that the cache can undertake per unit time and the maximum number of accesses that the memory can undertake per unit time; when the cache access volume is the data transfer volume between the cache and the processor and the memory access volume is the data transfer volume between the memory and the processor, the second threshold can be the ratio between the maximum data transfer rate of the cache per unit time and the maximum data transfer rate of the memory.

[0113] When the ratio between the cache access amount and the memory access amount is less than the second threshold, step 1004 is executed; when the ratio between the cache access amount and the memory access amount is greater than or equal to the second threshold, step 1006 is executed.

[0114] When the ratio between the cache access volume and the memory access volume is less than the second threshold, it means that the hit rate of the processor accessing the cache is low and a large amount of data needs to be obtained from the memory. At this time, the replaced page can be determined from the cache based on the above priority information, thereby improving the cache hit rate.

[0115] Step 1006 , based on the location information of the pages in the cache occupied by the data to be written from the memory to the cache and the location information of the dirty data stored in each page in the cache, select a first page for storing the data to be written.

[0116] When the ratio is greater than or equal to the first threshold, it indicates that the cache bandwidth is overloaded. At this time, one cache page can be selected from the determined multiple cache pages according to the valid bit information and dirty bit information of the data stored in the determined multiple cache pages and the position information of the data unit in the cache page occupied by the data to be read, and then the data to be read can be stored in the selected cache page.

[0117] from Figure 10 It can be seen from the illustrated embodiment that by further introducing the ratio between the cache access amount and the memory access amount to select the first page to store data, the cache hit rate and the bandwidth occupancy rate can be further taken into account, thereby further improving the cache efficiency.

[0118] In addition, in a possible implementation of this embodiment, for example, Figure 5 In the cache structure shown in FIG. 1 , when all cache pages store data, and Figure 5 The tag arrays shown in the figure all store index information. When the data to be read is stored in one of the cache pages, the original data previously stored in the cache page is overwritten. However, the tag array Tag Array still stores the index information of the original data previously stored in the cache page. At this time, the index information of the original data previously stored needs to be updated to the index information of the data to be read.

[0119] Further, in a possible implementation of this embodiment, for example, Figure 5 In the cache structure shown in FIG. 1 , when all cache pages store data, and Figure 5There are idle positions in the Tag Array shown that do not store index information. At this time, after storing the data to be read in one of the cache pages and storing the index information of the data to be read in the idle positions in the Tag Array, the position information of the idle data units in the cache page used to store the data to be read can also be obtained. Then, according to the position information of the idle data units, the second index information stored in the cache is updated. This second index information is used to index the original data in the idle data units.

[0120] It can be understood that in order to implement the above functions, the storage controller includes the corresponding hardware and / or software modules for executing each function. Combining the algorithm steps of each example described in the embodiments disclosed in this article, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the present application.

[0121] This embodiment can divide the functional modules of the storage controller according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into a cache control module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is illustrative, only a logical function division, and there can be other division methods in actual implementation.

[0122] In the case of dividing each functional module corresponding to each function, Figure 11 shows a possible schematic composition diagram of the storage controller 1100 involved in the above embodiment, as Figure 11 shown, the storage controller 1100 may include: a receiving module 1101, an obtaining module 1102, a selecting module 1103, and a saving module 1104.

[0123] Among them, the receiving module 1101 is used to receive a data reading request and determine the data that needs to be written from the memory to the cache based on the data reading request; the obtaining module 1102 is used to obtain the number of data access requests received per unit time; the selecting module 1103 is used to select a first page from the cache based on the number of the data access requests; the saving module 1104 is used to save the data that needs to be written from the memory to the cache in the first page.

[0124] In a possible implementation, the selection module 1103 is further configured to: in response to the number of times of the data access request being greater than or equal to a first threshold, select the first page from the cache based on the dirty data stored in the pages in the cache.

[0125] In a possible implementation, the selection module 1103 is further configured to: in response to the number of times of the data access request being greater than or equal to a first threshold, select the first page based on the cache access volume per unit time and the memory access volume per unit time.

[0126] In a possible implementation, the cache access volume includes one of the following: the number of cache hits or the data transfer volume between the cache and the processor; the memory access volume includes one of the following: the number of memory accesses or the data transfer volume between the memory and the processor.

[0127] In a possible implementation, the selection module 1103 is further configured to: determine a ratio between the cache access volume and the memory access volume; select the first page from the cache based on the ratio between the cache access volume and the memory access volume.

[0128] In a possible implementation, the selection module 1103 is further configured to: in response to the ratio between the cache access volume and the memory access volume being greater than or equal to a second threshold, select the first page from the cache based on the location information of the page in the cache occupied by the data to be written from the memory and the location information of the dirty data saved in each page in the cache.

[0129] In a possible implementation, the selection module 1103 is further configured to: in response to the ratio between the cache access volume and the memory access volume being less than the second threshold, select the first page from the cache based on the priority level information of the data saved in each page in the cache; the priority level includes one of the following: least recently used information, first in first out information, or access frequency information.

[0130] In a possible implementation, the storage controller 1100 further includes a first update module (not shown in the figure), and the first update module is configured to update the first index information saved in the cache, and the first index information is used to index the data to be read saved in the first page.

[0131] In a possible implementation, the storage controller 1100 further includes a second update module (not shown in the figure): The second update module is configured to obtain the position information of the free data units in the first page, and update the second index information stored in the cache according to the position information, where the second index information is used to index the original data in the data units corresponding to the position information in the first page.

[0132] The storage controller 1100 provided in this embodiment is configured to execute the caching method executed by the storage controller shown in the caching system 10, and can achieve the same effect as the above implementation method.

[0133] Among them, the storage controller can implement or execute various exemplary logic modules described in combination with the disclosure of the present application. The storage controller can also be a combination that implements computing functions, such as including an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, etc.

[0134] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the above division of each functional module is used as an example for illustration. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0135] In several embodiments provided in the present application, it should be understood that the disclosed caching device and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there can be other division methods. For example, multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device can be in an electrical, mechanical or other form.

[0136] The units described as separate components may or may not be physically separated. The components displayed as units may be one physical unit or multiple physical units, that is, they can be located in one place, or they can be distributed to multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] In addition, in each embodiment of the present application, each functional unit can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0138] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. The software product is stored in a storage medium and includes several instructions to enable a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods of the various embodiments of the present application. The foregoing readable storage medium includes: various media such as USB flash drives, mobile hard disks, read only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0139] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A caching method, characterized in that, including: Receiving a data reading request, and determining data that needs to be written from memory to the cache based on the data reading request; Obtaining the number of data access requests received within a unit time; Selecting a first page from the cache based on the number of the data access requests; Storing the data that needs to be written from memory to the cache in the first page; Wherein, the selecting a first page from the cache based on the number of the data access requests includes: In response to the number of the data access requests being greater than or equal to a first threshold, selecting the first page from the cache based on the dirty data stored in the pages in the cache; In response to the number of the data access requests being less than the first threshold, selecting the first page from the cache based on the priority level information of the data saved in each page in the cache; The priority level includes one of the following: least recently used information, first in first out information, or access frequency information.

2. The caching method according to claim 1, wherein The selecting a first page from the cache based on the number of the data access requests includes: In response to the number of the data access requests being greater than or equal to a first threshold, selecting the first page based on the cache access volume within a unit time and the memory access volume within a unit time.

3. The cache method according to claim 2, wherein The cache access volume includes one of the following: the number of cache hits or the data transfer volume between the cache and the processor; The memory access volume includes one of the following: the number of memory accesses or the data transfer volume between the memory and the processor.

4. The caching method according to claim 2 or 3, wherein The selecting the first page based on the cache access volume within a unit time and the memory access volume within a unit time includes: Determining the ratio between the cache access volume and the memory access volume; Selecting the first page from the cache based on the ratio between the cache access volume and the memory access volume.

5. The caching method according to claim 4, wherein The selecting the first page from the cache based on the ratio between the cache access volume and the memory access volume includes: In response to the ratio between the cache access volume and the memory access volume being greater than or equal to a second threshold, selecting the first page from the cache based on the position information of the page in the cache occupied by the data that needs to be written from memory to the cache and the position information of the dirty data saved in each page in the cache; 6. The caching method according to claim 5, wherein The selecting the first page from the cache based on the ratio between the cache access volume and the memory access volume includes: In response to the ratio between the cache access volume and the memory access volume being less than the second threshold, selecting the first page from the cache based on the priority level information of the data saved in each page in the cache; The priority level includes one of the following: least recently used information, first in first out information, or access frequency information.

7. A caching system, characterized in that, including: A cache, configured to store data from memory and index information for indexing the data stored in the cache; A storage controller, the storage controller being configured to: receive a data reading request, and determine data that needs to be written from memory to the cache based on the data reading request; Obtain the number of data access requests received per unit time; Based on the number of the data access requests, select a first page from the cache; save the data that needs to be written from the memory to the cache in the first page; Wherein, the cache system further includes a first counter; The first counter is used to count the number of data access requests received by the storage controller per unit time; The selecting a first page from the cache based on the number of the data access requests includes: In response to the number of the data access requests being greater than or equal to a first threshold, select the first page from the cache based on the dirty data stored in the pages in the cache; In response to the number of the data access requests being less than the first threshold, select the first page from the cache based on the priority level information of the data saved in each page in the cache; The priority level includes one of the following: least recently used information, first in first out information, or access frequency information.

8. The cache system according to claim 7, wherein The cache system further includes a second counter; The second counter is used to count the cache access volume of the storage controller per unit time; Wherein, the cache access volume includes one of the following: cache hit times or data transfer volume between the cache and the processor.

9. The cache system according to claim 8, wherein The cache system further includes a third counter; The third counter is used to count the memory access volume of the storage controller per unit time; Wherein, the memory access volume includes one of the following: memory access times or data transfer volume between the memory and the processor.

10. A chip, characterized in that, The chip includes the cache system according to any one of claims 7-9.

11. The chip according to claim 10, characterized in that, Further includes: A processor, configured to access the data stored in the cache system and store the processed data to the cache system.

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