Shift register, driving method, gate driving circuit and display device

Abstract

A shift register, a driving method, a gate driving circuit and a display device, wherein the shift register comprises: an input circuit (10), a first transistor (M1), a cascade output circuit (20), and a driving output circuit (30). The first transistor (M1) is a dual-gate transistor; wherein the first gate of the first transistor (M1) is configured to be coupled to a first reference signal terminal (VREF), the second gate of the first transistor (M1) is configured to receive a first threshold control signal (VS1), the cascade output circuit (20) is configured to enable a cascade signal output terminal (GP) to output a cascade signal according to a signal from a first clock signal terminal (CK1) and a control terminal of the cascade output circuit (20); and the driving output circuit (30) is configured to enable a driving signal output terminal (OP) to output a driving signal according to a cascade signal from the cascade signal output terminal (GP).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a driving method, a gate driving circuit and a display device. Background Art

[0002] With the rapid development of display technology, display devices are increasingly developing towards high integration and low cost. Among them, GOA (Gate Driver on Array) technology integrates TFT (Thin Film Transistor) gate drive circuits on the array substrate of the display device to form a scan drive for the display device. Among them, the gate drive circuit is usually composed of multiple cascaded shift registers. However, the output of the shift register is unstable, which will cause display abnormality. Summary of the invention

[0003] The shift register provided by the embodiment of the present disclosure includes:

[0004] An input circuit is configured to be coupled to an input signal terminal, a second clock signal terminal and a first electrode of the first transistor respectively; and the input circuit is configured to provide the signal of the input signal terminal to the first electrode of the first transistor in response to a signal of the second clock signal terminal;

[0005] The first transistor is a dual-gate transistor; wherein the first gate of the first transistor is configured to be coupled to a first reference signal terminal, and the second gate of the first transistor is configured to receive a first threshold control signal;

[0006] A cascade output circuit is configured to be coupled to a first clock signal terminal and a cascade signal output terminal respectively, and a control terminal of the cascade output circuit is coupled to the second electrode of the first transistor; the cascade output circuit is configured to enable the cascade signal output terminal to output a cascade signal according to signals of the first clock signal terminal and the control terminal of the cascade output circuit;

[0007] The driving output circuit is configured to be coupled to the cascade signal output terminal and the driving signal output terminal respectively, and the driving output circuit is configured to enable the driving signal output terminal to output a driving signal according to the cascade signal of the cascade signal output terminal.

[0008] Optionally, in the embodiment of the present disclosure, the input circuit comprises: a second transistor of a dual-gate type;

[0009] The first gate of the second transistor is configured to be coupled to the second clock signal terminal, the second gate of the second transistor is configured to receive a second threshold control signal, the first electrode of the second transistor is configured to be coupled to the input signal terminal, and the second electrode of the second transistor is coupled to the first electrode of the first transistor.

[0010] Optionally, in the embodiment of the present disclosure, the shift register further includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first capacitor;

[0011] The first gate of the third transistor is configured to be coupled to the first clock signal terminal, the first electrode of the third transistor is coupled to the first electrode of the first transistor, and the second electrode of the third transistor is coupled to the first electrode of the fourth transistor;

[0012] The first gate of the fourth transistor is coupled to the first gate of the seventh transistor, and the second electrode of the fourth transistor is configured to be coupled to the second reference signal terminal;

[0013] The first gate of the fifth transistor is configured to be coupled to the second clock signal terminal, the first electrode of the fifth transistor is configured to be coupled to the first reference signal terminal, and the second electrode of the fifth transistor is coupled to the first gate of the seventh transistor;

[0014] The first gate of the sixth transistor is coupled to the first electrode of the first transistor, the first electrode of the sixth transistor is configured to be coupled to the second clock signal terminal, and the second electrode of the sixth transistor is coupled to the first gate of the seventh transistor;

[0015] The first electrode of the seventh transistor is configured to be coupled to the second reference signal terminal, and the second electrode of the seventh transistor is coupled to the cascade signal output terminal;

[0016] A first terminal of the first capacitor is coupled to the first gate of the seventh transistor, and a second terminal of the first capacitor is configured to be coupled to the second reference signal terminal.

[0017] Optionally, in the embodiment of the present disclosure, at least one of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor is a dual-gate transistor;

[0018] For the transistor configured as the dual-gate transistor, the second gate of the transistor is configured to receive a first control signal.

[0019] Optionally, in the embodiment of the present disclosure, the first control signal includes: a third threshold control signal, a fourth threshold control signal, a fifth threshold control signal, a sixth threshold control signal and a seventh threshold control signal;

[0020] The third transistor is a dual-gate transistor; wherein the first gate of the third transistor is configured to be coupled to the first clock signal terminal, and the second gate of the third transistor is configured to receive the third threshold control signal;

[0021] The fourth transistor is a dual-gate transistor; wherein the first gate of the fourth transistor is coupled to the first gate of the seventh transistor, and the second gate of the fourth transistor is configured to receive the fourth threshold control signal;

[0022] The fifth transistor is a dual-gate transistor; wherein a first gate of the fifth transistor is coupled to the second clock signal terminal, and a second gate of the fifth transistor is configured to receive the fifth threshold control signal;

[0023] The sixth transistor is a dual-gate transistor; wherein the first gate of the sixth transistor is coupled to the first electrode of the first transistor, and the second gate of the sixth transistor is configured to receive the sixth threshold control signal;

[0024] The seventh transistor is a dual-gate transistor; wherein a first gate of the seventh transistor is coupled to a first gate of the fourth transistor, and a second gate of the seventh transistor is configured to receive the seventh threshold control signal.

[0025] Optionally, in an embodiment of the present disclosure, the cascade output circuit includes: an eighth transistor and a second capacitor;

[0026] The first gate of the eighth transistor is coupled to the second electrode of the first transistor, the first electrode of the eighth transistor is configured to be coupled to the first clock signal terminal, and the second electrode of the eighth transistor is coupled to the cascade signal output terminal;

[0027] A first terminal of the second capacitor is coupled to the second electrode of the first transistor, and a second terminal of the second capacitor is coupled to the cascade signal output terminal.

[0028] Optionally, in the embodiment of the present disclosure, the eighth transistor is a dual-gate transistor, wherein the first gate of the eighth transistor is coupled to the second electrode of the first transistor, and the second gate of the eighth transistor is configured to receive an eighth threshold control signal.

[0029] Optionally, in the embodiment of the present disclosure, the driving output circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a third capacitor and a fourth capacitor;

[0030] The first gate of the ninth transistor is coupled to the cascade signal output terminal, the first electrode of the ninth transistor is coupled to the second reference signal terminal, and the second electrode of the ninth transistor is coupled to the first gate of the twelfth transistor;

[0031] The first gate of the tenth transistor is coupled to the first control signal terminal, the first electrode of the tenth transistor is coupled to the first reference signal terminal, and the second electrode of the tenth transistor is coupled to the first gate of the twelfth transistor;

[0032] The first gate of the eleventh transistor is coupled to the cascade signal output terminal, the first electrode of the eleventh transistor is coupled to the second reference signal terminal, and the second electrode of the eleventh transistor is coupled to the drive signal output terminal;

[0033] A first electrode of the twelfth transistor is coupled to the first reference signal terminal, and a second electrode of the twelfth transistor is coupled to the driving signal output terminal;

[0034] A first terminal of the third capacitor is coupled to the second control signal terminal, and a second terminal of the third capacitor is coupled to the first gate of the twelfth transistor;

[0035] A first terminal of the fourth capacitor is coupled to the first gate of the twelfth transistor, and a second terminal of the fourth capacitor is coupled to the driving signal output terminal.

[0036] Optionally, in the embodiment of the present disclosure, at least one of the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor is a dual-gate transistor;

[0037] For the transistor configured as the dual-gate transistor, the second gate of the transistor is configured to receive a second control signal.

[0038] Optionally, in the embodiment of the present disclosure, the second control signal includes: a ninth threshold control signal, a tenth threshold control signal, an eleventh threshold control signal and a twelfth threshold control signal;

[0039] The ninth transistor is a dual-gate transistor, wherein a first gate of the ninth transistor is coupled to the cascade signal output terminal, and a second gate of the ninth transistor is configured to receive the ninth threshold control signal;

[0040] The tenth transistor is a dual-gate transistor, wherein a first gate of the tenth transistor is coupled to the first control signal terminal, and a second gate of the tenth transistor is configured to receive the tenth threshold control signal;

[0041] The eleventh transistor is a dual-gate transistor, wherein a first gate of the eleventh transistor is coupled to the cascade signal output terminal, and a second gate of the eleventh transistor is configured to receive the eleventh threshold control signal;

[0042] The twelfth transistor is a dual-gate transistor, wherein a first gate of the twelfth transistor is coupled to a second electrode of the tenth transistor, and a second gate of the twelfth transistor is configured to receive the twelfth threshold control signal.

[0043] Optionally, in an embodiment of the present disclosure, at least two of the first threshold control signal, the second threshold control signal, the third threshold control signal, the fourth threshold control signal, the fifth threshold control signal, the sixth threshold control signal, the seventh threshold control signal, the eighth threshold control signal, the ninth threshold control signal, the tenth threshold control signal, the eleventh threshold control signal and the twelfth threshold control signal use the same adjustment signal terminal input signal.

[0044] Optionally, in the embodiment of the present disclosure, the first threshold control signal, the second threshold control signal, the third threshold control signal, the fourth threshold control signal, the fifth threshold control signal, the sixth threshold control signal, the ninth threshold control signal, the tenth threshold control signal and the eleventh threshold control signal use the same input signal of the adjustment signal terminal;

[0045] The first gate and the second gate of the seventh transistor are coupled;

[0046] The first gate and the second gate of the eighth transistor are coupled;

[0047] The first gate and the second gate of the twelfth transistor are coupled.

[0048] Optionally, in the embodiment of the present disclosure, the ninth threshold control signal and the eleventh threshold control signal adopt the same input signal of the adjustment signal terminal;

[0049] A first gate of at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the tenth transistor and the twelfth transistor is coupled to the second gate.

[0050] Optionally, in an embodiment of the present disclosure, the adjustment signal terminal outputs a second adjustment signal, and the second adjustment signal is a fixed voltage signal.

[0051] Optionally, in an embodiment of the present disclosure, the first threshold control signal, the second threshold control signal and the fourth threshold control signal use the same input signal of the adjustment signal terminal; wherein the adjustment signal terminal outputs a first adjustment signal, and the first adjustment signal is a clock signal;

[0052] A first gate of at least one of the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor is coupled to the second gate.

[0053] Optionally, in an embodiment of the present disclosure, the first adjustment signal has the same timing as the signal at the second clock signal end.

[0054] The gate driving circuit provided by the embodiment of the present disclosure comprises a plurality of cascaded shift registers as described above;

[0055] The input signal terminal of the first stage shift register is configured to be coupled to the frame trigger signal terminal;

[0056] In every two adjacent shift registers, the input signal terminal of the next-stage shift register is configured to be coupled to the cascade signal output terminal of the previous-stage shift register.

[0057] The display device provided by the embodiment of the present disclosure includes the above-mentioned gate driving circuit.

[0058] The driving method of the shift register provided in the embodiment of the present disclosure includes:

[0059] In the input stage, the input circuit controls the level of the signal at the first electrode of the first transistor according to the signal at the input signal terminal and the signal at the second clock signal terminal; the first transistor is turned on; the cascade output circuit provides the signal at the first clock signal terminal to the cascade signal output terminal in response to the signal at the second electrode of the first transistor; the drive output circuit enables the drive signal output terminal to output a drive signal according to the cascade signal at the cascade signal output terminal;

[0060] In the output stage, the threshold voltage of the first transistor moves in response to the signal of the first threshold control signal terminal, and the first transistor is cut off; the cascade output circuit responds to the signal of the second electrode of the first transistor and provides the signal of the first clock signal terminal to the cascade signal output terminal; the drive output circuit enables the drive signal output terminal to output a drive signal according to the cascade signal of the cascade signal output terminal.

[0061] Optionally, in the embodiment of the present disclosure, after the output stage, the driving method further includes:

[0062] In the reset stage, the input circuit controls the level of the signal at the first electrode of the first transistor according to the signal at the input signal terminal and the signal at the second clock signal terminal; the first transistor is turned on; the cascade output circuit responds to the signal at the control terminal of the cascade output circuit and provides the signal at the second reference signal terminal to the cascade signal output terminal; the drive output circuit causes the drive signal output terminal to output a drive signal according to the cascade signal at the cascade signal output terminal;

[0063] In the holding stage, the cascade output circuit responds to the signal of the control end of the cascade output circuit to provide the signal of the second reference signal end to the cascade signal output end; the drive output circuit enables the drive signal output end to output the drive signal according to the cascade signal of the cascade signal output end. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 is a schematic diagram of the structure of a shift register in the related art;

[0065] Figure 2 for Figure 1 The signal timing diagram of the shift register shown;

[0066] Figure 3 Some structural schematic diagrams of shift registers provided in the embodiments of the present disclosure;

[0067] Figure 4 Some other structural schematic diagrams of the shift register provided by the embodiments of the present disclosure;

[0068] Figure 5a Some signal timing diagrams provided for embodiments of the present disclosure;

[0069] Figure 5b For the corresponding Figure 4 A simulation diagram of a driving signal output terminal of the shift register shown;

[0070] Figure 5c Other signal timing diagrams provided for embodiments of the present disclosure;

[0071] Figure 6a Some further structural schematic diagrams of shift registers provided in the embodiments of the present disclosure;

[0072] Figure 6b Some further structural schematic diagrams of shift registers provided in the embodiments of the present disclosure;

[0073] Figure 7a Some further signal timing diagrams provided for embodiments of the present disclosure;

[0074] Figure 7b For the corresponding Figure 6bA simulation diagram of a driving signal output terminal of the shift register shown;

[0075] Figure 8 Some further structural schematic diagrams of shift registers provided in the embodiments of the present disclosure;

[0076] Fig. 9 Some further structural schematic diagrams of shift registers provided in the embodiments of the present disclosure;

[0077] Fig.10 A flowchart of a driving method provided by an embodiment of the present disclosure;

[0078] Fig.11 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present disclosure;

[0079] Fig.12 Some structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0080] Fig.13a Some other structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0081] Fig.13b Some further structural schematic diagrams of the display device provided in the embodiments of the present disclosure. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0083] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0084] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0085] like Figure 1 As shown, the shift register may include transistors M01 ˜ M012 and capacitors C01 ˜ C04 . Figure 1 The signal timing diagram corresponding to the shift register shown in Figure 2 shown.

[0086] Specifically, in the input stage t01, transistors M02, transistors M05, and transistors M010 are turned on under the control of the low-level signal of the clock signal terminal CK. The turned-on transistor M05 provides the low-level signal of the signal terminal VSS to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal, so as to control the conduction of transistors M04 and transistor M07, and transistor M03 is cut off under the control of the signal of the clock signal terminal CKB. The turned-on transistor M07 provides the high-level signal of the signal terminal VDD to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level signal. In addition, the turned-on transistor M02 provides the low-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a low-level signal. Transistor M06 is turned on under the control of the signal of the second pull-up node PU_2 to provide the low-level signal of the clock signal terminal CK to the pull-down node PD. Since transistor M01 satisfies V gs01 <V th01 , so that the transistor M01 is turned on; wherein, at this time, the electrode of the transistor M01 connected to the first pull-up node PU_1 is used as the source, V gs01 represents the voltage difference between the gate and source of transistor M01, V th01Represents the threshold voltage of transistor M01. The turned-on transistor M01 turns on the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the first pull-up node PU_1 is a low-level signal to control the transistor M08 to turn on. The turned-on transistor M08 provides the high-level signal of the clock signal terminal CKB to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level signal. Since the cascade signal output terminal GP outputs a high-level signal, the transistor M09 and the transistor M011 can be controlled to be cut off. Since the transistor M010 is turned on, the low-level signal of the signal terminal VSS can be provided to the gate of the transistor M012 to control the transistor M012 to turn on, thereby providing the low-level signal of the signal terminal VSS to the drive signal output terminal OP0P, so that the drive signal output terminal OP0P outputs a low-level signal. It should be noted that, in actual applications, the voltage of the low-level signal of the first pull-up node PU_1 can be the same as the voltage of the signal of the signal terminal VSS. Due to the threshold voltage of the transistor M01, the voltage of the low-level signal of the first pull-up node PU_1 can be less than the voltage of the low-level signal of the second pull-up node PU_2. Of course, the specific voltage can be designed and determined according to the actual application environment, and is not limited here.

[0087] In the output stage t02, transistors M02, transistors M05, and transistors M010 are turned off under the control of the high-level signal of the clock signal terminal CK, and the first pull-up node PU_1 is kept as a low-level signal under the action of capacitor C01 to control the transistor M08 to be turned on, so as to provide the low-level signal of the clock signal terminal CKB to the cascade signal output terminal GP. Due to the action of capacitor C01, the level of the first pull-up node PU_1 is further lowered to control the transistor M08 to be turned on as fully as possible, so as to provide the low-level signal of the clock signal terminal CKB to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a low-level signal. Since the cascade signal output terminal GP outputs a low-level signal, both transistors M09 and transistors M011 can be controlled to be turned on. The turned-on transistor M09 can provide the high-level signal of the signal terminal VDD to the gate of the transistor M012, so as to control the transistor M012 to be turned off. The turned-on transistor M011 can provide the high-level signal of the signal terminal VDD to the drive signal output terminal OP, so that the drive signal output terminal OP outputs a high-level signal.

[0088] Afterwards, it enters the reset phase t03 and the hold phase t04. In these two phases, the cascade signal output terminal GP outputs a high-level signal, and the drive signal output terminal OP outputs a low-level signal.

[0089] However, in the output stage t2, due to the long-term leakage accumulation of transistor M01, the level of the first pull-up node PU_1 that is further pulled down will leak, causing the level of the first pull-up node PU_1 to rise, resulting in insufficient opening of transistor M08, and the leakage current problem of transistor M07, which will cause the signal output by the cascade signal output terminal GP to be pulled up, and then cause the transistors M09 and M011 to be insufficiently turned on, and then cause the drive signal output terminal OP to be pulled down, resulting in an abnormal signal output by the drive signal output terminal OP. Affecting the normal charging and discharging of pixels. Especially when the display device adopts a driving condition with a lower refresh frequency (such as 1Hz), due to the long-term leakage accumulation of the transistor, the signal output by the drive signal output terminal OP will be abnormal.

[0090] Based on this, the embodiments of the present disclosure provide some shift registers, such as Figure 3 As shown, it may include:

[0091] The input circuit 10 is configured to be coupled to the input signal terminal IP, the second clock signal terminal CK2 and the first electrode of the first transistor M1 respectively; and the input circuit 10 is configured to provide the signal of the input signal terminal IP to the first electrode of the first transistor M1 in response to the signal of the second clock signal terminal CK2;

[0092] The first transistor M1 is a dual-gate transistor; wherein the first gate of the first transistor M1 is configured to be coupled to the first reference signal terminal VREF1, and the second gate of the first transistor M1 is configured to receive the first threshold control signal VS1;

[0093] The cascade output circuit 20 is configured to be coupled to the first clock signal terminal CK1 and the cascade signal output terminal GP respectively, and the control terminal of the cascade output circuit 20 is coupled to the second electrode of the first transistor M1; the cascade output circuit 20 is configured to make the cascade signal output terminal GP output the cascade signal according to the signal of the first clock signal terminal CK1 and the control terminal of the cascade output circuit 20;

[0094] The driving output circuit 30 is configured to be coupled to the cascade signal output terminal GP and the driving signal output terminal OP respectively, and the driving output circuit 30 is configured to enable the driving signal output terminal OP to output a driving signal according to the cascade signal of the cascade signal output terminal GP.

[0095] The shift register provided by the embodiment of the present disclosure sets the first transistor M1 as a dual-gate transistor, wherein the first gate of the first transistor M1 is coupled to the first reference signal terminal VREF1, and the second gate of the first transistor M1 receives the first threshold control signal VS1, and the threshold voltage V of the first transistor M1 can be controlled by the first threshold control signal VS1. th1, so that the threshold voltage V of the first transistor M1 th1 The first transistor M1 is moved so that it is cut off as much as possible in the output stage, which can keep the level of the signal of the first pull-up node stable, improve the influence of leakage on the signal of the first pull-up node, so as to improve the stability of the signal output by the cascade signal output terminal GP, thereby improving the output stability of the drive signal output terminal OP, which is beneficial to be applied to the display device with low frequency drive and is beneficial to reduce power consumption.

[0096] In specific implementation, Figure 3 and Figure 4 As shown, the first pull-up node PU_1 is between the control end of the cascade output circuit 20 and the second electrode of the first transistor M1. The second pull-up node PU_2 is between the output end of the input circuit 10 and the first electrode of the first transistor M1. The pull-down node PD is coupled between the second electrode of the fifth transistor M5 and the first gate of the seventh transistor M7. It should be noted that the first pull-up node PU_1 and the second pull-up node PU_2 are virtual nodes in the shift register. These two nodes are only for the convenience of describing the structure of the shift register and the transmission of signals. The specific structure of the shift register and the transmission of signals can be determined according to the coupling method between each transistor and capacitor in the shift register.

[0097] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4 As shown, the first electrode of the first transistor M1 is coupled to the second pull-up node PU_2, and the second electrode of the first transistor M1 is coupled to the first pull-up node PU_1.

[0098] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4 As shown, the input circuit 10 may include: a dual-gate second transistor M2; wherein the first gate of the second transistor M2 is configured to be coupled to the second clock signal terminal CK2, the second gate of the second transistor M2 is configured to receive the second threshold control signal VS2, the first electrode of the second transistor M2 is configured to be coupled to the input signal terminal IP, and the second electrode of the second transistor M2 is coupled to the first electrode of the first transistor M1.

[0099] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4 As shown, the shift register may further include: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a first capacitor C1;

[0100] A first gate of the third transistor M3 is configured to be coupled to the first clock signal terminal CK1, a first electrode of the third transistor M3 is coupled to the first electrode of the first transistor M1, and a second electrode of the third transistor M3 is coupled to the first electrode of the fourth transistor M4;

[0101] A first gate of the fourth transistor M4 is coupled to a first gate of the seventh transistor M7, and a second electrode of the fourth transistor M4 is configured to be coupled to a second reference signal terminal VREF2;

[0102] The first gate of the fifth transistor M5 is configured to be coupled to the second clock signal terminal CK2, the first electrode of the fifth transistor M5 is configured to be coupled to the first reference signal terminal VREF1, and the second electrode of the fifth transistor M5 is coupled to the first gate of the seventh transistor M7;

[0103] A first gate of the sixth transistor M6 is coupled to the first electrode of the first transistor M1, the first electrode of the sixth transistor M6 is configured to be coupled to the second clock signal terminal CK2, and a second electrode of the sixth transistor M6 is coupled to the first gate of the seventh transistor M7;

[0104] A first electrode of the seventh transistor M7 is configured to be coupled to the second reference signal terminal VREF2, and a second electrode of the seventh transistor M7 is coupled to the cascade signal output terminal GP;

[0105] A first terminal of the first capacitor C1 is coupled to the first gate of the seventh transistor M7 , and a second terminal of the first capacitor C1 is configured to be coupled to the second reference signal terminal VREF2 .

[0106] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4 As shown, the cascade output circuit 20 may include: an eighth transistor M8 and a second capacitor C2;

[0107] A first gate of the eighth transistor M8 is coupled to the second electrode of the first transistor M1, a first electrode of the eighth transistor M8 is configured to be coupled to the first clock signal terminal CK1, and a second electrode of the eighth transistor M8 is coupled to the cascade signal output terminal GP;

[0108] A first terminal of the second capacitor C2 is coupled to the second electrode of the first transistor M1 , and a second terminal of the second capacitor C2 is coupled to the cascade signal output terminal GP.

[0109] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4 As shown, the eighth transistor M8 is a dual-gate transistor, wherein the first gate of the eighth transistor M8 is coupled to the second electrode of the first transistor M1, and the second gate of the eighth transistor M8 is configured to receive the eighth threshold control signal VS8. Figure 3and Figure 4 As shown, the first gate of the eighth transistor M8 is coupled to the second gate. In this way, the signal of the first pull-up node PU_1 can be used as the eighth threshold control signal VS8, thereby improving the driving capability of the eighth transistor M8, reducing the signal line settings, and reducing the wiring space.

[0110] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4 As shown, the driving output circuit 30 may include: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a third capacitor C3 and a fourth capacitor C4;

[0111] A first gate of the ninth transistor M9 is coupled to the cascade signal output terminal GP, a first electrode of the ninth transistor M9 is coupled to the second reference signal terminal VREF2, and a second electrode of the ninth transistor M9 is coupled to a first gate of the twelfth transistor M12;

[0112] A first gate of the tenth transistor M10 is coupled to the first control signal terminal, a first electrode of the tenth transistor M10 is coupled to the first reference signal terminal VREF1, and a second electrode of the tenth transistor M10 is coupled to a first gate of the twelfth transistor M12;

[0113] A first gate of the eleventh transistor M11 is coupled to the cascade signal output terminal GP, a first electrode of the eleventh transistor M11 is coupled to the second reference signal terminal VREF2, and a second electrode of the eleventh transistor M11 is coupled to the drive signal output terminal OP;

[0114] A first electrode of the twelfth transistor M12 is coupled to the first reference signal terminal VREF1, and a second electrode of the twelfth transistor M12 is coupled to the driving signal output terminal OP;

[0115] A first terminal of the third capacitor C3 is coupled to the second control signal terminal, and a second terminal of the third capacitor C3 is coupled to the first gate of the twelfth transistor M12;

[0116] A first terminal of the fourth capacitor C4 is coupled to the first gate of the twelfth transistor M12 , and a second terminal of the fourth capacitor C4 is coupled to the driving signal output terminal OP.

[0117] In a specific implementation, in the embodiment of the present disclosure, at least one of the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor is a dual-gate transistor. And, for a transistor configured as a dual-gate transistor, the second gate of the transistor is configured to receive a second control signal. Exemplarily, the second control signal may include: a ninth threshold control signal VS9 and an eleventh threshold control signal VS11. Figure 3 and Figure 4As shown, the ninth transistor M9 is a dual-gate transistor, wherein the first gate of the ninth transistor M9 is coupled to the cascade signal output terminal GP, and the second gate of the ninth transistor M9 is configured to receive the ninth threshold control signal VS9. Figure 3 and Figure 4 As shown, the first gate and the second gate of the ninth transistor M9 are coupled. In this way, the cascade signal can be used as the eighth threshold control signal VS8, thereby improving the driving capability of the ninth transistor M9, reducing the signal line settings, and reducing the wiring space.

[0118] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4 As shown, the eleventh transistor M11 is a dual-gate transistor, wherein the first gate of the eleventh transistor M11 is coupled to the cascade signal output terminal GP, and the second gate of the eleventh transistor M11 is configured to receive the eleventh threshold control signal VS11. Figure 3 and Figure 4 As shown, the first gate and the second gate of the eleventh transistor M11 are coupled. In this way, the cascade signal can be used as the eleventh threshold control signal VS11, thereby improving the driving capability of the eleventh transistor M11, reducing the signal line settings, and reducing the wiring space.

[0119] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4 As shown, the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 , the sixth transistor M6 , the seventh transistor M7 , the tenth transistor M10 , and the twelfth transistor M12 may all be configured as single-gate transistors.

[0120] In a specific implementation, according to the direction of signal flow, the first electrode of the transistor can be used as its source and the second electrode can be used as its drain; or, the first electrode can be used as its drain and the second electrode can be used as its source, without making a specific distinction here.

[0121] It should be noted that the transistors mentioned in the above embodiments of the present disclosure may be TFTs or metal oxide semiconductor field effect transistors (MOS), which are not limited here.

[0122] In order to simplify the preparation process, in the specific implementation, in the embodiment of the present disclosure, as Figure 3 and Figure 4 As shown, all transistors can be P-type transistors. The voltage difference V between the gate and the source of the P-type transistor is gs With its threshold voltage V th Satisfy the relationship Vgs <V th For example, the first transistor M1 may be a P-type transistor, and the voltage difference V between the gate and the source of the first transistor M1 is gs1 With its threshold voltage V th1 The relationship between satisfies the formula: V gs1 <V th1 Of course, in the embodiment of the present disclosure, the transistor is a P-type transistor for example. For the case where the transistor is an N-type transistor, the design principle is the same as that of the present disclosure and also falls within the scope of protection of the present disclosure. In addition, the voltage difference V between the gate and the source of the N-type transistor is gs With its threshold voltage V th Satisfy the relationship V gs >V th For example, the first transistor M1 may be an N-type transistor, and the voltage difference V between the gate and the source of the first transistor M1 is gs1 With its threshold voltage V th1 The relationship between satisfies the formula: V gs1 >V th1 When turned on.

[0123] Generally, a gate insulating layer is provided between the gate and the active layer of a transistor. In a specific implementation, the dominant gate in the dual-gate transistor can be determined by adjusting the thickness of the gate insulating layer. For example, in the embodiment of the present disclosure, the thickness of the gate insulating layer can be adjusted so that the first gate of the transistor is dominant, so that the on or off state of the transistor can be controlled by loading a signal to the first gate. In addition, the threshold voltage of the transistor can be adjusted by loading a signal to the second gate. For example, the first gate of the first transistor M1 can be dominant so that the on and off state of the first transistor can be controlled by loading a signal to the first gate. For example, the second gate is the voltage difference V between the first gate and the source of the first transistor M1. gs1 With its threshold voltage V th1 The relationship between them satisfies the formula V gs1 <V th1 When the second gate is loaded with a signal, the threshold voltage of the first transistor is adjusted. gs1 The voltage difference between the first gate and the source of the first transistor M1 is taken as an example for description.

[0124] In order to reduce the number of signal lines and reduce the wiring space, in the specific implementation, in the embodiment of the present disclosure, as Figure 4 As shown, the first threshold control signal VS1, the second threshold control signal VS2 and the fourth threshold control signal VS4 can use the same adjustment signal terminal CKD input signal. Figure 5aAs shown, the adjustment signal terminal CKD can output a first adjustment signal CKD1, and the first adjustment signal CKD1 can be a clock signal. Figure 5a The CKD1 shown represents the clock signal output by the adjustment signal terminal CKD, so that the clock signal can be loaded to the second gate of the first transistor M1, the second gate of the second transistor M2 and the second gate of the fourth transistor M4, so that the threshold voltages of the first transistor M1, the second transistor M2 and the fourth transistor M4 can be controlled to move.

[0125] For example, Figure 5a As shown, the timing of the first adjustment signal CKD1 output by the adjustment signal terminal CKD and the signal of the second clock signal terminal CK2 can be made the same. In other words, the first adjustment signal CKD1 and the second clock signal terminal CK2 can be triggered at the same time. Furthermore, the adjustment signal terminal CKD and the second clock signal terminal CK2 can use the same signal terminal to input the clock signal, which can further reduce the signal line settings and reduce the wiring space.

[0126] For example, Figure 5a As shown, the signals of the first control signal terminal and the second control signal terminal can be set as clock signals. For example, the periods of the signals of the first control signal terminal and the second control signal terminal are the same. Further, the periods of the signals of the first control signal terminal and the second control signal terminal are the same as the period of the signal of the first clock signal terminal. The falling edge of the signal of the first control signal terminal is aligned with the rising edge of the signal of the first clock signal terminal CK1. The falling edge of the signal of the second control signal terminal is aligned with the rising edge of the signal of the second clock signal terminal CK2. Alternatively, the signal of the first control signal terminal can be made the same as the signal of the second clock signal terminal CK2. For example, the timing and level of the signal of the first control signal terminal can be made the same as the signal of the second clock signal terminal CK2. And the signal of the second control signal terminal can also be made the same as the signal of the first clock signal terminal CK1. For example, the timing and level of the signal of the second control signal terminal can be made the same as the signal of the first clock signal terminal CK1. In this way, the signal line setting can be further reduced and the wiring space occupied can be reduced.

[0127] In a specific implementation, in the embodiment of the present disclosure, when the valid pulse signal at the input signal terminal IP is a low level signal, the signal at the first reference signal terminal VREF1 is a low level signal, and the signal at the second reference signal terminal VREF2 is a high level signal. Alternatively, in a specific implementation, in the embodiment of the present disclosure, when the valid pulse signal at the input signal terminal IP is a high level signal, the signal at the first reference signal terminal VREF1 is a high level signal, and the signal at the second reference signal terminal VREF2 is a low level signal. It should be noted that, in combination with Figure 5aAs shown, the effective pulse signal of the input signal terminal IP refers to a low level signal input to the second transistor M2 within a frame time to control the second transistor M2 to be turned on, thereby enabling the shift register to work.

[0128] Furthermore, in a specific implementation, the P-type transistor is turned off under the action of a high-level signal and turned on under the action of a low-level signal, and the N-type transistor is turned on under the action of a high-level signal and turned off under the action of a low-level signal.

[0129] The above is only an example to illustrate the specific structure of the shift register provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above circuits is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.

[0130] Below Figure 4 Take the shift register shown in the figure as an example, combined with Figure 5a The signal timing diagram shown describes the working process of the above-mentioned shift register provided by the embodiment of the present disclosure. In the following description, 1 represents a high-level signal and 0 represents a low-level signal. It should be noted that 1 and 0 are logic levels, which are only for better explanation of the specific working process of the embodiment of the present disclosure, rather than the voltage applied to the gate of each transistor during specific implementation.

[0131] Specifically, select Figure 5a The signal timing diagram shown in FIG. 1 includes four stages: input stage T1, output stage T2, reset stage T3, and reset hold stage T4. It should be noted that: Figure 5a The signal timing diagram shown is only the working process of a certain shift register in the current frame. The working process of the shift register in other frames is basically the same as the working process in the current frame, and will not be described in detail here.

[0132] In the input phase T1, IP=0, CK1=1, CK2=0, CS1=0, CS2=1, CKD1=0.

[0133] Since CK1=1, the third transistor M3 is turned off. Since CK2=0, the fifth transistor M5 is turned on to provide the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal, so as to control the seventh transistor M7 to be turned on. The turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level signal. Since CK2=0, CKD1=0, the threshold voltage V th2It can be shifted right to make the second transistor M2 fully conductive as much as possible, so as to accelerate the charging process of providing the low level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a low level signal as quickly as possible. The sixth transistor M6 is turned on under the control of the signal of the second pull-up node PU_2 to provide the low level signal of the second clock signal terminal CK2 to the pull-down node PD, further making the signal of the pull-down node PD a low level signal. Since CKD1=0, the V of the first transistor M1 can be th1 right, so that the first transistor M1 satisfies V gs1 <V th1 , so that the first transistor M1 is fully turned on as much as possible. The turned-on first transistor M1 turns on the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the first pull-up node PU_1 can be timely made a low-level signal to control the eighth transistor M8 to be turned on. In addition, the first gate and the second gate of the eighth transistor M8 are electrically connected to each other, and their signals are the same. Thus, the eighth transistor M8 can be turned on as much as possible. The turned-on eighth transistor M8 provides the high-level signal of the first clock signal terminal CK1 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level cascade signal. Since the cascade signal output terminal GP outputs a high-level signal, the ninth transistor M9 and the eleventh transistor M11 can be controlled to be turned off. Since the first gate and the second gate of the ninth transistor M9 and the eleventh transistor M11 are electrically connected to each other, their signals are the same. Thus, it can also be turned off as much as possible to reduce leakage current. Since CS1=0, the tenth transistor M10 is turned on, so that the low level signal of the first reference signal terminal VREF1 can be provided to the first gate of the twelfth transistor M12, thereby controlling the twelfth transistor M12 to be turned on, so as to provide the low level signal of the first reference signal terminal VREF1 to the driving signal output terminal OP, so that the driving signal output terminal OP outputs a low level driving signal.

[0134] In the output stage T2, IP=1, CK1=0, CK2=1, CS1=1, CS2=0, CKD1=1.

[0135] Since CK2=1, the fifth transistor M5 is turned off. The first pull-up node PU_1 is maintained as a low-level signal under the action of the second capacitor C2 to control the eighth transistor M8 to turn on, thereby providing the low-level signal of the first clock signal terminal CK1 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a low-level cascade signal. Due to the action of the second capacitor C2, the level of the first pull-up node PU_1 is further lowered to control the eighth transistor M8 to be turned on as fully as possible, so as to provide the low-level signal of the first clock signal terminal CK1 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a low-level cascade signal. In addition, since the threshold voltage V th1 Therefore, the voltage of the low level signal of the first pull-up node PU_1 can be lower than the voltage of the low level signal of the second pull-up node PU_2. Therefore, in this stage, the first transistor M1 is electrically connected to the second pull-up node PU_2 as its source. Since CKD1 = 1, the V th1 The first gate of the first transistor M1 is at the voltage of the low-level signal, and the source voltage of the first transistor M1 is at the voltage of the low-level signal, so that the first transistor M1 cannot meet V gs1 <V th1, so that the first transistor M1 is turned off, so that the level of the first pull-up node PU_1 can be kept stable, and the level of the first pull-up node PU_1 is prevented from rising due to leakage, which causes the cascade signal output terminal GP to output unstable. In addition, since CK2=1 and CKD1=1, the threshold voltage of the second transistor M2 can be shifted to the left, so that the second transistor M2 can be turned off as much as possible to avoid the leakage of the second transistor M2 on the leakage of the second pull-up node PU_2, and extend the holding time of the low-level signal of the second pull-up node PU_2. In addition, since CKD1=1 and the signal of the pull-down node PD is a high-level signal, the threshold voltage of the fourth transistor M4 can be shifted to the left, so that the fourth transistor M4 can be turned off as much as possible to avoid the leakage of the fourth transistor M4 on the leakage of the second pull-up node PU_2, and extend the holding time of the low-level signal of the second pull-up node PU_2. The sixth transistor M6 provides the high level signal of the second clock signal terminal CK2 to the pull-down node PD under the control of the signal of the second pull-up node PU_2, so as to control the seventh transistor M7 to be turned off, so as to avoid adversely affecting the signal output by the cascade signal output terminal GP. Since CS1=1, the tenth transistor M10 is turned off. Since the cascade signal output terminal GP outputs a low level signal, the ninth transistor M9 and the eleventh transistor M11 can be controlled to be turned on. Since the first gate and the second gate of the ninth transistor M9 and the eleventh transistor M11 are electrically connected to each other, their signals are the same. Thus, it can be turned on as fully as possible to improve the driving capability. The turned-on ninth transistor M9 can provide the high level signal of the second reference signal terminal VREF2 to the first gate of the twelfth transistor M12, thereby controlling the twelfth transistor M12 to be turned off. The turned-on eleventh transistor M11 can provide the high level signal of the second reference signal terminal VREF2 to the drive signal output terminal OP, so that the drive signal output terminal OP outputs a high level drive signal.

[0136] After the output stage T2 and before the reset stage T3, since CK1=1, the third transistor M3 is turned off. Since CK2=1, the fifth transistor M5 is turned off. The first pull-up node PU_1 is maintained as a low-level signal under the action of the second capacitor C2 to control the eighth transistor M8 to turn on, thereby providing the high-level signal of the first clock signal terminal CK1 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level cascade signal to control the ninth transistor M9 and the eleventh transistor M11 to be turned off. Since CS1 changes from a high level to a low level, the tenth transistor M10 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the first gate of the twelfth transistor M12, thereby controlling the twelfth transistor M12 to turn on, so as to provide the low-level signal of the first reference signal terminal VREF1 to the drive signal output terminal OP, so that the drive signal output terminal OP outputs a low-level drive signal.

[0137] In the reset phase T3, IP=1, CK1=1, CK2=0, CS1=0, CS2=1, CKD1=0.

[0138] Since CK1 = 1, the third transistor M3 is turned off. Since CK2 = 0, CKD1 = 0, the threshold voltage V th2 It can be shifted right so that the second transistor M2 is fully turned on as much as possible to accelerate the charging process of providing the high-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a high-level signal as quickly as possible to control the sixth transistor M6 to be turned off. Since CKD1=0 and the first reference signal terminal VREF1 is a low-level signal, the first transistor M1 can be turned on in time to provide the high-level signal of the second pull-up node PU_2 to the first pull-up node PU_1 to control the eighth transistor M8 to be turned off. Since CK2=0, the fifth transistor M5 is turned on to provide the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the seventh transistor M7 to be turned on. The turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level signal to control the ninth transistor M9 and the eleventh transistor M11 to be turned off. Since CS1=0, the tenth transistor M10 is turned on, so that the low level signal of the first reference signal terminal VREF1 can be provided to the first gate of the twelfth transistor M12, and then the twelfth transistor M12 is controlled to be turned on, so as to provide the low level signal of the first reference signal terminal VREF1 to the drive signal output terminal OP, so that the drive signal output terminal OP outputs a low level drive signal. In addition, the voltage difference between the two ends is kept stable through the third capacitor C3 and the fourth capacitor C4.

[0139] In the reset holding phase T4, IP=1, CK1=0, CK2=1, CS1=1, CS2=0, CKD1=1.

[0140] Since CK2=1, the second transistor M2 and the fifth transistor M5 are both turned off. Due to the effect of the first capacitor C1C1, the signal of the pull-down node PD can be kept as a low-level signal, and the seventh transistor M7 is controlled to be turned on to provide the high-level signal of the second reference signal terminal VREF2 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level signal, so as to control the ninth transistor M9 and the eleventh transistor M11 to be turned off. Since CS1=0, the tenth transistor M10 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the first gate of the twelfth transistor M12, and then the twelfth transistor M12 is controlled to be turned on to provide the low-level signal of the first reference signal terminal VREF1 to the drive signal output terminal OP, so that the drive signal output terminal OP outputs a low-level drive signal. In addition, although CKD1=1, the V of the fourth transistor M4 can be made th4 However, the first gate of the fourth transistor M4 is the voltage of the low level signal, and the source voltage of the fourth transistor M4 is the voltage of the high level signal, so that the fourth transistor M4 can satisfy V gs4 <V th4 Since CK1=0, the third transistor M3 is turned on. The turned-on third transistor M3 and the fourth transistor M4 can timely provide the high level signal of the second reference signal terminal VREF2 to the second pull-up node PU_2, so as to timely control the signal of the second pull-up node PU_2 to be high level, and control the sixth transistor M6 to be turned off. In addition, the voltage difference between the two ends of the third capacitor C3 and the fourth capacitor C4 is kept stable.

[0141] After the reset and hold phase T4, the working processes of the reset phase T3 and the reset and hold phase T4 are repeatedly executed until the level of the signal at the input signal terminal IP becomes a high level again.

[0142] Furthermore, according to Figure 5a The signal timing diagram shown is Figure 4 The signal output from the driving signal output terminal OP of the shift register shown in the figure is simulated, and the simulation diagram is as shown in FIG. Figure 5b As shown. The horizontal axis represents time and the vertical axis represents voltage. S1 represents the voltage Figure 2 The signal timing diagram shown is Figure 1 The driving signal output terminal OP of the shift register shown in the figure is used to simulate the signal. Figure 5a The signal timing diagram shown is Figure 4The driving signal output terminal OP of the shift register shown in the figure is used to simulate the signal. Figure 5b It can be seen that the driving signal output terminal GP can output a signal stably, thereby improving the instability problem caused by leakage.

[0143] It should be noted that there are buffer stages between the input stage T1 and the output stage T2, between the output stage T2 and the reset stage T3, and between the reset stage T3 and the reset holding stage T4. In the buffer stage, the characteristics of the transistors in the shift register can be stabilized so as to enter the next working stage after stabilization. In addition, this can also avoid the alignment of the rising edge of the signal at the first clock signal terminal CK1 and the falling edge of the signal at the second clock signal terminal CK2, and avoid the alignment of the falling edge of the signal at the first clock signal terminal CK1 and the rising edge of the signal at the second clock signal terminal CK2, thereby improving the stability of the shift register.

[0144] It should be noted that, in practical applications, the specific voltage values ​​of the above-mentioned signals can be designed and determined according to the actual application environment and are not limited here.

[0145] It should be noted that in actual applications, a general display device may be in a static image display state or standby state for a long time. In order to reduce power consumption, the display device can be operated at a lower refresh rate (such as 1Hz, 30Hz). Of course, the display device can also display video images. In order to improve the display effect of the video images, the display device can be operated at a higher refresh rate (such as 60Hz, 120Hz).

[0146] The disclosed embodiment also provides some other signal timing diagrams of the shift register, such as Figure 5c As shown, the above-mentioned implementation mode is modified. The following only describes the differences between this embodiment and the above-mentioned embodiment, and the similarities are not repeated here.

[0147] Generally, a display device may be in a static image display state or standby state for a long time. In order to reduce power consumption, the display device can be operated at a lower refresh rate (such as 1Hz, 30Hz). Figure 5c, the shift register may include a data refresh phase T10 and a data retention phase T20 within one frame time. The working process of the shift register in the data refresh phase T10 may refer to the above embodiment. In the data retention phase T20, the signal of the first clock signal terminal CK1, the signal of the second clock signal terminal CK2, the signal of the first control signal terminal CS1, the signal of the second control signal terminal CS2, the signal of the input signal terminal IP, and the first adjustment signal CKD1 of the adjustment signal terminal CKD are all set to high-level signals, so that the second transistor M2, the third transistor M3, the fifth transistor M5 and the tenth transistor M10 in the shift register are all turned off, thereby reducing power consumption, which can further facilitate the shift register in the present application to be applied to a display device with a lower refresh frequency.

[0148] The present disclosure also provides some other structural diagrams of the shift register, such as Figure 6a and Figure 6b As shown, the above-mentioned implementation mode is modified. The following only describes the differences between this embodiment and the above-mentioned embodiment, and the similarities are not repeated here.

[0149] In the specific implementation, in the embodiment of the present disclosure, if Figure 6a As shown, the first transistor M1 can be set as a dual-gate transistor; wherein the first gate of the first transistor M1 is configured to be coupled to the first reference signal terminal VREF1, and the second gate of the first transistor M1 is configured to receive the first threshold control signal VS1. Exemplarily, the first threshold control signal VS1 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the first threshold control signal VS1 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0150] For example, in a specific implementation, in order to reduce leakage, when the first transistor M1 is set as a P-type transistor, the voltage of the first threshold control signal VS1 can be set to a negative voltage. When the first transistor M1 is set as an N-type transistor, the voltage of the first threshold control signal VS1 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0151] In the specific implementation, in the embodiment of the present disclosure, if Figure 6aAs shown, the second transistor M2 can be set as a dual-gate transistor; wherein the first gate of the second transistor M2 is configured to be coupled to the second clock signal terminal CK2, and the second gate of the second transistor M2 is configured to receive the second threshold control signal VS2. Exemplarily, the second threshold control signal VS2 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the second threshold control signal VS2 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0152] For example, in a specific implementation, in order to reduce leakage, when the second transistor M2 is set as a P-type transistor, the voltage of the second threshold control signal VS2 can be set to a negative voltage. When the second transistor M2 is set as an N-type transistor, the voltage of the second threshold control signal VS2 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0153] In a specific implementation, in the embodiment of the present disclosure, at least one of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor can be set as a dual-gate transistor. And, for the transistor set as a dual-gate transistor, the second gate of the transistor is configured to receive the first control signal. Exemplarily, the first control signal may include: a third threshold control signal, a fourth threshold control signal, a fifth threshold control signal, a sixth threshold control signal, and a seventh threshold control signal. Figure 6a As shown, the third transistor M3 can be set as a dual-gate transistor; wherein the first gate of the third transistor M3 is configured to be coupled to the first clock signal terminal CK1, and the second gate of the third transistor M3 is configured to receive the third threshold control signal VS3. Exemplarily, the third threshold control signal VS3 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the third threshold control signal VS3 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0154] For example, in a specific implementation, in order to reduce leakage, when the third transistor M3 is set as a P-type transistor, the voltage of the third threshold control signal VS3 can be set to a negative voltage. When the third transistor M3 is set as an N-type transistor, the voltage of the third threshold control signal VS3 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0155] In the specific implementation, in the embodiment of the present disclosure, if Figure 6a As shown, the fourth transistor M4 can be set as a dual-gate transistor; wherein the first gate of the fourth transistor M4 is coupled to the first gate of the seventh transistor M7 (i.e., the pull-down node PD), and the second gate of the fourth transistor M4 is configured to receive the fourth threshold control signal VS4. Exemplarily, the fourth threshold control signal VS4 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the fourth threshold control signal VS4 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0156] For example, in a specific implementation, in order to reduce leakage, when the fourth transistor M4 is set as a P-type transistor, the voltage of the fourth threshold control signal VS4 can be set to a negative voltage. When the fourth transistor M4 is set as an N-type transistor, the voltage of the fourth threshold control signal VS4 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0157] In the specific implementation, in the embodiment of the present disclosure, if Figure 6a As shown, the fifth transistor M5 can be set as a dual-gate transistor; wherein the first gate of the fifth transistor M5 is coupled to the second clock signal terminal CK2, and the second gate of the fifth transistor M5 is configured to receive the fifth threshold control signal VS5. Exemplarily, the fifth threshold control signal VS5 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the fifth threshold control signal VS5 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0158] For example, in a specific implementation, in order to reduce leakage, when the fifth transistor M5 is set as a P-type transistor, the voltage of the fifth threshold control signal VS5 can be set to a negative voltage. When the fifth transistor M5 is set as an N-type transistor, the voltage of the fifth threshold control signal VS5 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0159] In the specific implementation, in the embodiment of the present disclosure, if Figure 6aAs shown, the sixth transistor M6 can be set as a dual-gate transistor; wherein the first gate of the sixth transistor M6 is coupled to the first electrode of the first transistor M1, and the second gate of the sixth transistor M6 is configured to receive the sixth threshold control signal VS6. Exemplarily, the sixth threshold control signal VS6 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the sixth threshold control signal VS6 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0160] For example, in a specific implementation, in order to reduce leakage, when the sixth transistor M6 is set as a P-type transistor, the voltage of the sixth threshold control signal VS6 can be set to a negative voltage. When the sixth transistor M6 is set as an N-type transistor, the voltage of the sixth threshold control signal VS6 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0161] In the specific implementation, in the embodiment of the present disclosure, if Figure 6a As shown, the seventh transistor M7 can be a dual-gate transistor; wherein the first gate of the seventh transistor M7 is coupled to the first gate of the fourth transistor M4, and the second gate of the seventh transistor M7 is configured to receive the seventh threshold control signal VS7. Exemplarily, the seventh threshold control signal VS7 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the seventh threshold control signal VS7 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0162] For example, in a specific implementation, in order to reduce leakage, when the seventh transistor M7 is set as a P-type transistor, the voltage of the seventh threshold control signal VS7 can be set to a negative voltage. When the seventh transistor M7 is set as an N-type transistor, the voltage of the seventh threshold control signal VS7 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0163] In the specific implementation, in the embodiment of the present disclosure, if Figure 6aAs shown, the eighth transistor M8 can be set as a dual-gate transistor, wherein the first gate of the eighth transistor M8 is coupled to the second electrode of the first transistor M1, and the second gate of the eighth transistor M8 is configured to receive the eighth threshold control signal VS8. Exemplarily, the eighth threshold control signal VS8 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the eighth threshold control signal VS8 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0164] For example, in a specific implementation, in order to reduce leakage, when the eighth transistor M8 is set as a P-type transistor, the voltage of the eighth threshold control signal VS8 can be set to a negative voltage. When the eighth transistor M8 is set as an N-type transistor, the voltage of the eighth threshold control signal VS8 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0165] In a specific implementation, in the embodiment of the present disclosure, at least one of the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor may be configured as a dual-gate transistor. Moreover, for the transistor configured as a dual-gate transistor, the second gate of the transistor is configured to receive a second control signal. Exemplarily, the second control signal may include: a ninth threshold control signal, a tenth threshold control signal, an eleventh threshold control signal, and a twelfth threshold control signal. Figure 6a As shown, the ninth transistor M9 can be set as a dual-gate transistor, wherein the first gate of the ninth transistor M9 is coupled to the cascade signal output terminal GP, and the second gate of the ninth transistor M9 is configured to receive the ninth threshold control signal VS9. Exemplarily, the ninth threshold control signal VS9 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the ninth threshold control signal VS9 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0166] For example, in a specific implementation, in order to reduce leakage, when the ninth transistor M9 is set as a P-type transistor, the voltage of the ninth threshold control signal VS9 can be set to a negative voltage. When the ninth transistor M9 is set as an N-type transistor, the voltage of the ninth threshold control signal VS9 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0167] In the specific implementation, in the embodiment of the present disclosure, if Figure 6a As shown, the tenth transistor M10 can be set as a dual-gate transistor, wherein the first gate of the tenth transistor M10 is coupled to the first control signal terminal, and the second gate of the tenth transistor M10 is configured to receive the tenth threshold control signal VS10. Exemplarily, the tenth threshold control signal VS10 can be set as a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the tenth threshold control signal VS10 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0168] For example, in a specific implementation, in order to reduce leakage, when the tenth transistor M10 is set as a P-type transistor, the voltage of the tenth threshold control signal VS10 can be set to a negative voltage. When the tenth transistor M10 is set as an N-type transistor, the voltage of the tenth threshold control signal VS10 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0169] In the specific implementation, in the embodiment of the present disclosure, if Figure 6a As shown, the eleventh transistor M11 can be set as a dual-gate transistor, wherein the first gate of the eleventh transistor M11 is coupled to the cascade signal output terminal GP, and the second gate of the eleventh transistor M11 is configured to receive the eleventh threshold control signal VS11. Exemplarily, the eleventh threshold control signal VS11 can be set as a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the eleventh threshold control signal VS11 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0170] For example, in a specific implementation, in order to reduce leakage, when the eleventh transistor M11 is set as a P-type transistor, the voltage of the eleventh threshold control signal VS11 can be set to a negative voltage. When the eleventh transistor M11 is set as an N-type transistor, the voltage of the eleventh threshold control signal VS11 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0171] In the specific implementation, in the embodiment of the present disclosure, if Figure 6aAs shown, the twelfth transistor M12 can be set as a dual-gate transistor, wherein the first gate of the twelfth transistor M12 is coupled to the second electrode of the tenth transistor M10, and the second gate of the twelfth transistor M12 is configured to receive the twelfth threshold control signal VS12. Exemplarily, the twelfth threshold control signal VS12 can be set to a fixed voltage signal. Exemplarily, the voltage value range of the fixed voltage signal can be -30V to +30V. For example, the voltage value of the twelfth threshold control signal VS12 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0172] For example, in a specific implementation, in order to reduce leakage, when the twelfth transistor M12 is set as a P-type transistor, the voltage of the twelfth threshold control signal VS12 can be set to a negative voltage. When the twelfth transistor M12 is set as an N-type transistor, the voltage of the twelfth threshold control signal VS12 can be set to a positive voltage. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0173] In a specific implementation, at least two of the first threshold control signal VS1, the second threshold control signal VS2, the third threshold control signal VS3, the fourth threshold control signal VS4, the fifth threshold control signal VS5, the sixth threshold control signal VS6, the seventh threshold control signal VS7, the eighth threshold control signal VS8, the ninth threshold control signal VS9, the tenth threshold control signal VS10, the eleventh threshold control signal VS11 and the twelfth threshold control signal VS12 can use the same adjustment signal terminal input signal. For example, Figure 6b As shown, the first threshold control signal VS1 to the twelfth threshold control signal VS12 can all use the same adjustment signal terminal CKD to load the signal, that is, the second gates of the first transistor M1 to the twelfth transistor M12 are all coupled to the adjustment signal terminal CKD. In this way, the number of signal lines can be reduced as much as possible, and the wiring space occupied can be reduced. Of course, the first threshold control signal VS1 to the twelfth threshold control signal VS12 can also use different signal terminals to load signals. In this way, the voltages of the first threshold control signal VS1 to the twelfth threshold control signal VS12 can be adjusted independently, so that the threshold voltage of each transistor can be flexibly adjusted.

[0174] For example, Figure 7a As shown, the adjustment signal terminal CKD may output the second adjustment signal CKD2, and the second adjustment signal CKD2 may be a fixed voltage signal. Figure 7aThe CKD2 shown represents the fixed voltage signal output by the adjustment signal terminal CKD. Exemplarily, the voltage value range of the second adjustment signal CKD2 can be -30V to +30V. For example, the voltage value of the second adjustment signal CKD2 can be set to -30V, -15V, -5V, 5V, 15V, 30V. Of course, in actual applications, the design can be determined according to the needs of the actual application, and is not limited here.

[0175] Below Figure 6b Take the shift register shown in the figure as an example, combined with Figure 7a The signal timing diagram shown describes the working process of the above-mentioned shift register provided by the embodiment of the present disclosure. In the following description, 1 represents a high-level signal and 0 represents a low-level signal. It should be noted that 1 and 0 are logic levels, which are only for better explanation of the specific working process of the embodiment of the present disclosure, rather than the voltage applied to the gate of each transistor during specific implementation.

[0176] Specifically, the voltage value of the second adjustment signal CKD2 outputted from the adjustment signal terminal is a positive voltage, and all transistors are P-type transistors. Figure 7a The signal timing diagram shown in FIG. 1 includes four stages: input stage T1, output stage T2, reset stage T3, and reset hold stage T4. It should be noted that: Figure 7a The signal timing diagram shown is only the working process of a certain shift register in the current frame. The working process of the shift register in other frames is basically the same as the working process in the current frame, and will not be described in detail here.

[0177] In the input phase T1, IP=0, CK1=1, CK2=0, CS1=0, CS2=1.

[0178] Since CK1=1, the third transistor M3 is turned off. Since CK2=0, the fifth transistor M5 is turned on to provide the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal, so as to control the seventh transistor M7 to be turned on. The turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level signal. Since CK2=0, the second transistor M2 is turned on to provide the low-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a low-level signal. The sixth transistor M6 is turned on under the control of the signal of the second pull-up node PU_2 to provide the low-level signal of the second clock signal terminal CK2 to the pull-down node PD, further making the signal of the pull-down node PD a low-level signal. And, the first transistor M1 is turned on. The turned-on first transistor M1 turns on the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the first pull-up node PU_1 can be timely made a low-level signal to control the eighth transistor M8 to turn on. The turned-on eighth transistor M8 provides the high-level signal of the first clock signal terminal CK1 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level cascade signal. Since the cascade signal output terminal GP outputs a high-level signal, the ninth transistor M9 and the eleventh transistor M11 can be controlled to be cut off. Since CS1=0, the tenth transistor M10 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the first gate of the twelfth transistor M12, and then the twelfth transistor M12 is controlled to turn on, so as to provide the low-level signal of the first reference signal terminal VREF1 to the drive signal output terminal OP, so that the drive signal output terminal OP outputs a low-level drive signal.

[0179] In the output stage T2, IP=1, CK1=0, CK2=1, CS1=1, CS2=0.

[0180] Since CK2=1, the fifth transistor M5 is turned off. The first pull-up node PU_1 is maintained as a low-level signal under the action of the second capacitor C2 to control the eighth transistor M8 to turn on, thereby providing the low-level signal of the first clock signal terminal CK1 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a low-level cascade signal. Due to the action of the second capacitor C2, the level of the first pull-up node PU_1 is further lowered to control the eighth transistor M8 to be turned on as fully as possible, so as to provide the low-level signal of the first clock signal terminal CK1 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a low-level cascade signal. In addition, since the threshold voltage V th1Therefore, the voltage of the low level signal of the first pull-up node PU_1 can be lower than the voltage of the low level signal of the second pull-up node PU_2. Therefore, in this stage, the first transistor M1 is electrically connected to the second pull-up node PU_2 as its source. Since CKD2 = 1, the V th1 The first gate of the first transistor M1 is at the voltage of the low-level signal, and the source voltage of the first transistor M1 is at the voltage of the low-level signal, so that the first transistor M1 cannot meet V gs1 <V th1 , so that the first transistor M1 is cut off as fully as possible, so that the level of the first pull-up node PU_1 can be kept stable, and the level of the first pull-up node PU_1 is prevented from increasing due to leakage, which causes the cascade signal output terminal GP to output unstable. In addition, since CK2=1 and CKD2=1, the threshold voltage of the second transistor M2 can be shifted to the left, so that the second transistor M2 can be cut off as fully as possible, so as to avoid the leakage of the second transistor M2 on the leakage of the second pull-up node PU_2, and extend the holding time of the low-level signal of the second pull-up node PU_2. In addition, since CKD2=1 and the signal of the pull-down node PD is a high-level signal, the threshold voltage of the fourth transistor M4 can be shifted to the left, so that the fourth transistor M4 is cut off as fully as possible, so as to avoid the leakage of the fourth transistor M4 on the leakage of the second pull-up node PU_2, and extend the holding time of the low-level signal of the second pull-up node PU_2. The sixth transistor M6 provides the high level signal of the second clock signal terminal CK2 to the pull-down node PD under the control of the signal of the second pull-up node PU_2, so as to control the seventh transistor M7 to be turned off, so as to avoid adversely affecting the signal output by the cascade signal output terminal GP. Since CS1=1, the tenth transistor M10 is turned off. Since the cascade signal output terminal GP outputs a low level signal, the ninth transistor M9 and the eleventh transistor M11 can be controlled to be turned on. The turned-on ninth transistor M9 can provide the high level signal of the second reference signal terminal VREF2 to the first gate of the twelfth transistor M12, thereby controlling the twelfth transistor M12 to be turned off. The turned-on eleventh transistor M11 can provide the high level signal of the second reference signal terminal VREF2 to the drive signal output terminal OP, so that the drive signal output terminal OP outputs a high level drive signal.

[0181] It should be noted that, in this stage, the second gates of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the tenth transistor M10 and the twelfth transistor M12 are all electrically connected to the adjustment signal terminal CKD, and the voltage value of the second adjustment signal CKD2 output by the adjustment signal terminal CKD is a positive voltage, so that the threshold voltages of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the tenth transistor M10 and the twelfth transistor M12 can be shifted to the left, thereby reducing the leakage current of these transistors and improving stability.

[0182] In the reset phase T3, IP=1, CK1=1, CK2=0, CS1=0, CS2=1.

[0183] Since CK1=1, the third transistor M3 is turned off. Since CK2=0, the second transistor M2 is turned on to provide the high-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a high-level signal to control the sixth transistor M6 to be turned off. In addition, the first transistor M1 is turned on to provide the high-level signal of the second pull-up node PU_2 to the first pull-up node PU_1 to control the eighth transistor M8 to be turned off. Since CK2=0, the fifth transistor M5 is turned on to provide the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the seventh transistor M7 to be turned on. The turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level signal to control the ninth transistor M9 and the eleventh transistor M11 to be turned off. Since CS1=0, the tenth transistor M10 is turned on, so that the low level signal of the first reference signal terminal VREF1 can be provided to the first gate of the twelfth transistor M12, thereby controlling the twelfth transistor M12 to be turned on, so as to provide the low level signal of the first reference signal terminal VREF1 to the driving signal output terminal OP, so that the driving signal output terminal OP outputs a low level driving signal.

[0184] In the reset holding phase T4, IP=1, CK1=0, CK2=1, CS1=1, CS2=0.

[0185] Since CK2=1, the second transistor M2 and the fifth transistor M5 are both turned off. Due to the effect of the first capacitor C1C1, the signal of the pull-down node PD can be kept as a low-level signal, and the seventh transistor M7 is controlled to be turned on to provide the high-level signal of the second reference signal terminal VREF2 to the cascade signal output terminal GP, so that the cascade signal output terminal GP outputs a high-level signal, so as to control the ninth transistor M9 and the eleventh transistor M11 to be turned off. Since CS1=0, the tenth transistor M10 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the first gate of the twelfth transistor M12, and then the twelfth transistor M12 is controlled to be turned on to provide the low-level signal of the first reference signal terminal VREF1 to the drive signal output terminal OP, so that the drive signal output terminal OP outputs a low-level drive signal. In addition, although CKD2=1, the V of the fourth transistor M4 can be made th4 However, the first gate of the fourth transistor M4 is the voltage of the low level signal, and the source voltage of the fourth transistor M4 is the voltage of the high level signal, so that the fourth transistor M4 can satisfy V gs4 <V th4 Since CK1=0, the third transistor M3 is turned on. The turned-on third transistor M3 and fourth transistor M4 can timely provide the high level signal of the second reference signal terminal VREF2 to the second pull-up node PU_2, so as to timely control the signal of the second pull-up node PU_2 to be high level and control the sixth transistor M6 to be turned off.

[0186] It should be noted that, in this stage, the second gates of the ninth transistor M9 and the eleventh transistor M11 are electrically connected to the adjustment signal terminal CKD, and the voltage value of the second adjustment signal CKD2 output by the adjustment signal terminal CKD is a positive voltage, so that the threshold voltages of the ninth transistor M9 and the eleventh transistor M11 can be shifted to the left, thereby reducing the leakage current of these transistors and improving stability.

[0187] After the reset and hold phase T4, the working processes of the reset phase T3 and the reset and hold phase T4 are repeatedly executed until the level of the signal at the input signal terminal IP becomes a high level again.

[0188] Furthermore, according to Figure 7a The signal timing diagram shown is Figure 6b The signal output from the driving signal output terminal OP of the shift register shown in the figure is simulated, and the simulation diagram is as shown in FIG. Figure 7b As shown. The horizontal axis represents time and the vertical axis represents voltage. S1 represents the voltage Figure 2 The signal timing diagram shown is Figure 1 The driving signal output terminal OP of the shift register shown in the figure is used to simulate the signal. Figure 7a The signal timing diagram shown is Figure 6b The driving signal output terminal OP of the shift register shown in the figure is used to simulate the signal. Figure 7b It can be seen that the driving signal output terminal GP can output a signal stably, thereby improving the instability problem caused by leakage.

[0189] The present disclosure also provides some other structural diagrams of the shift register, such as Figure 8 As shown, the above-mentioned implementation mode is modified. The following only describes the differences between this embodiment and the above-mentioned embodiment, and the similarities are not repeated here.

[0190] In the specific implementation, in the embodiment of the present disclosure, if Figure 8 As shown, the first gate and the second gate of the seventh transistor M7 can be coupled. In this way, the signal of the pull-down node PD can be used as the seventh threshold control signal VS7, thereby improving the driving capability of the seventh transistor M7, reducing the signal line settings, and reducing the wiring space.

[0191] In the specific implementation, in the embodiment of the present disclosure, if Figure 8 As shown, the first gate and the second gate of the eighth transistor M8 can be coupled. In this way, the signal of the first pull-up node PU_1 can be used as the eighth threshold control signal VS8, thereby improving the driving capability of the eighth transistor M8, reducing the signal line settings, and reducing the wiring space.

[0192] In the specific implementation, in the embodiment of the present disclosure, if Figure 8 As shown, the first gate of the twelfth transistor M12 can be coupled to the second gate. In this way, the signal of the first gate of the twelfth transistor M12 can be used as the twelfth threshold control signal VS12, thereby improving the driving capability of the twelfth transistor M12, reducing the signal line setting, and reducing the wiring space.

[0193] In the specific implementation, in the embodiment of the present disclosure, if Figure 8 As shown, the second gates of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 can be coupled to the adjustment signal terminal CKD. Exemplarily, the adjustment signal terminal CKD can output the second adjustment signal CKD2, and the second adjustment signal CKD2 is a fixed voltage signal.

[0194] In specific implementation, Figure 8 The working process of the shift register shown is similar to Figure 6bThe working process of the shift register shown is roughly the same, and only the differences are described below.

[0195] In the input stage, the reset stage, and the hold stage, since the first gate and the second gate of the seventh transistor M7 are electrically connected to each other, their signals are the same. Thus, the seventh transistor M7 can be turned on as fully as possible to improve the driving capability. In the output stage, since the first gate and the second gate of the seventh transistor M7 are electrically connected to each other, their signals are the same. Thus, the seventh transistor M7 can be turned off as fully as possible to reduce the leakage current.

[0196] In the input stage and the output stage, since the first gate and the second gate of the eighth transistor M8 are electrically connected to each other, their signals are the same. Therefore, it can be turned on as fully as possible to improve the driving capability. In the reset stage and the holding stage, since the first gate and the second gate of the eighth transistor M8 are electrically connected to each other, their signals are the same. Therefore, it can be turned off as fully as possible to reduce the leakage current.

[0197] In the input stage, the reset stage, and the hold stage, since the first gate and the second gate of the twelfth transistor M12 are electrically connected to each other, their signals are the same. Thus, it can be turned on as fully as possible to improve the driving capability. In the output stage, since the first gate and the second gate of the twelfth transistor M12 are electrically connected to each other, their signals are the same. Thus, it can be turned off as fully as possible to reduce the leakage current.

[0198] It should be noted that, in practical applications, a general display device may be in a static image display state or a standby state for a long time. In order to reduce power consumption, the display device can be operated at a lower refresh frequency (e.g., 1 Hz, 30 Hz). In this way, the shift register can be operated at a lower refresh frequency. In the image retention stage, the voltage at the adjustment signal end can be set to a positive voltage to reduce leakage and ensure the output stability of the shift register, so that the shift register will not work abnormally. Alternatively, the display device can also display video images. In order to improve the display effect of the video image, the display device can be operated at a higher refresh frequency (e.g., 60 Hz, 120 Hz). In this way, the shift register can be operated at a higher refresh frequency, so that the voltage at the adjustment signal end can be set to 0V or a negative voltage to ensure the response speed of the shift register. Of course, the voltage at the adjustment signal end can be designed and determined according to the actual application environment, and is not limited here.

[0199] The present disclosure also provides some other structural diagrams of the shift register, such as Fig. 9 As shown, the above-mentioned implementation mode is modified. The following only describes the differences between this embodiment and the above-mentioned embodiment, and the similarities are not repeated here.

[0200] In a specific implementation, in the embodiment of the present disclosure, the first gate of at least one transistor among the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10 and the twelfth transistor M12 is coupled to the second gate.

[0201] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate and the second gate of the first transistor M1 can be coupled. In this way, the signal of the first reference signal terminal VREF1 can be used as the first threshold control signal VS1, thereby improving the driving capability of the first transistor M1, reducing the signal line settings, and reducing the wiring space.

[0202] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate and the second gate of the second transistor M2 can be coupled. In this way, the signal of the second clock signal terminal CK2 can be used as the second threshold control signal VS2, thereby improving the driving capability of the second transistor M2, reducing the signal line settings, and reducing the wiring space.

[0203] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate of the third transistor M3 can be coupled to the second gate. In this way, the signal of the first clock signal terminal CK1 can be used as the third threshold control signal VS3, thereby improving the driving capability of the third transistor M3, reducing the signal line settings, and reducing the wiring space.

[0204] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate and the second gate of the fourth transistor M4 can be coupled. In this way, the signal in the pull-down stage can be used as the fourth threshold control signal VS4, thereby improving the driving capability of the fourth transistor M4, reducing the signal line settings, and reducing the wiring space.

[0205] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate of the fifth transistor M5 can be coupled to the second gate. In this way, the signal of the second clock signal terminal CK2 can be used as the fifth threshold control signal VS5, thereby improving the driving capability of the fifth transistor M5, reducing the signal line settings, and reducing the wiring space.

[0206] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9As shown, the first gate and the second gate of the sixth transistor M6 can be coupled. In this way, the signal of the second pull-up node PU_2 can be used as the sixth threshold control signal VS6, thereby improving the driving capability of the sixth transistor M6, reducing the signal line settings, and reducing the wiring space.

[0207] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate and the second gate of the seventh transistor M7 can be coupled. In this way, the signal of the pull-down node can be used as the seventh threshold control signal VS7, thereby improving the driving capability of the seventh transistor M7, reducing the signal line settings, and reducing the wiring space.

[0208] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate of the eighth transistor M8 can be coupled to the second gate. In this way, the signal of the first pull-up node can be used as the eighth threshold control signal VS8, thereby improving the driving capability of the eighth transistor M8, reducing the signal line settings, and reducing the wiring space.

[0209] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate and the second gate of the tenth transistor M10 can be coupled. In this way, the signal of the first control signal terminal can be used as the tenth threshold control signal VS10, thereby improving the driving capability of the tenth transistor M10, reducing the signal line settings, and reducing the wiring space.

[0210] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the first gate of the twelfth transistor M12 can be coupled to the second gate. In this way, the signal of the first gate of the twelfth transistor M12 can be used as the twelfth threshold control signal VS12, thereby improving the driving capability of the twelfth transistor M12, reducing the signal line setting, and reducing the wiring space.

[0211] For example, in a specific implementation, in the embodiments of the present disclosure, if Fig. 9 As shown, the second gate of the ninth transistor M9 and the second gate of the eleventh transistor M11 can be coupled to the adjustment signal terminal CKD. Exemplarily, the adjustment signal terminal CKD can output the second adjustment signal CKD2, and the second adjustment signal CKD2 is a fixed voltage signal.

[0212] In specific implementation, Fig. 9 The working process of the shift register shown is similar to Figure 6b The working process of the shift register shown is roughly the same, and only the differences are described below.

[0213] Since the first gate of each of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10 and the twelfth transistor M12 is coupled to the second gate, when these transistors are turned on by the control of the signal of the first gate, since the signal of the first gate is the same as that of the second gate, they can be turned on as fully as possible to improve the driving capability. When these transistors are turned off by the control of the signal of the first gate, since the signal of the first gate is the same as that of the second gate, they can be turned off as fully as possible to reduce the leakage current.

[0214] Based on the same inventive concept, the embodiment of the present disclosure also provides a driving method of the above-mentioned shift register, wherein: Fig.10 As shown, it may include:

[0215] S100, input stage, the input circuit 10 controls the level of the signal at the first electrode of the first transistor M1 according to the signal at the input signal terminal IP and the signal at the second clock signal terminal CK2; the first transistor M1 is turned on; the cascade output circuit 20 responds to the signal at the second electrode of the first transistor M1 and provides the signal at the first clock signal terminal CK1 to the cascade signal output terminal GP; the drive output circuit 30 enables the drive signal output terminal OP to output the drive signal according to the cascade signal at the cascade signal output terminal GP;

[0216] S200, in the output stage, the threshold voltage of the first transistor M1 moves in response to the signal at the first threshold control signal VS1 end, and the first transistor M1 is turned off; the cascade output circuit 20 responds to the signal at the second electrode of the first transistor M1, and provides the signal of the first clock signal end CK1 to the cascade signal output end GP; the drive output circuit 30 enables the drive signal output end OP to output the drive signal according to the cascade signal of the cascade signal output end GP.

[0217] In specific implementation, in the embodiment of the present disclosure, after the output stage S200, the driving method may further include: a reset stage and a holding stage; wherein,

[0218] In the reset stage, the input circuit controls the level of the signal at the first electrode of the first transistor according to the signals at the input signal terminal and the second clock signal terminal; the first transistor is turned on; the cascade output circuit responds to the signal at the control terminal of the cascade output circuit and provides the signal at the second reference signal terminal to the cascade signal output terminal; the drive output circuit causes the drive signal output terminal to output a drive signal according to the cascade signal at the cascade signal output terminal.

[0219] In the holding stage, the first capacitor holds the signal of the pull-down node; the cascade output circuit provides the signal of the second reference signal terminal to the cascade signal output terminal in response to the signal of the control terminal of the cascade output circuit; the drive output circuit causes the drive signal output terminal to output the drive signal according to the cascade signal of the cascade signal output terminal.

[0220] The driving principle and specific implementation of the driving method are the same as those of the shift register in the above embodiment. Therefore, the driving method can be implemented with reference to the specific implementation of the shift register in the above embodiment, which will not be described in detail here.

[0221] Based on the same inventive concept, the disclosed embodiment also provides a gate driving circuit, such as Fig.11 As shown, it includes a plurality of cascaded shift registers SR(1), SR(2) ... SR(n-1), SR(n) ... SR(N-1), SR(N) (a total of N shift registers, 1≤n≤N, n is an integer) provided in the embodiments of the present disclosure; wherein the input signal terminal IP of the first stage shift register SR(1) is configured to be coupled to the frame trigger signal terminal STV;

[0222] In every two adjacent shift registers, the input signal terminal IP of the next-stage shift register SR(n) is configured to be coupled to the cascade signal output terminal GP of the previous-stage shift register SR(n-1).

[0223] Specifically, the specific structure of each shift register in the above-mentioned gate drive circuit is the same as the above-mentioned shift register in the present disclosure in terms of function and structure, and the repeated parts are not repeated. The gate drive circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, which is not limited here.

[0224] Specifically, in the above-mentioned gate driving circuit provided in the embodiment of the present disclosure, if Fig.11 As shown, the first reference signal terminal VREF1 of each stage of the shift register SR(n) is coupled to the same DC signal terminal vdd, and the second reference signal terminal VREF2 of each stage of the shift register SR(n) is coupled to the same DC signal terminal vss.

[0225] Specifically, in the above-mentioned gate driving circuit provided in the embodiment of the present disclosure, if Fig.11 As shown, the first clock signal terminal CK1 of the 2k-1th level shift register and the second clock signal terminal CK2 of the 2kth level shift register are both coupled to the same clock terminal, i.e., the first clock terminal ck1; the second clock signal terminal CK2 of the 2k-1th level shift register and the first clock signal terminal CK1 of the 2kth level shift register are both coupled to the same clock terminal, i.e., the second clock terminal ck2; wherein k is a positive integer.

[0226] Specifically, when the first threshold control signal VS1, the second threshold control signal VS2 and the third threshold control signal VS3 are configured to receive a clock signal with the same timing as the second clock signal terminal CK2 signal, the first threshold control signal VS1, the second threshold control signal VS2 and the third threshold control signal VS3 of the 2k-1 level shift register and the 2k level shift register are all input signals from the same clock terminal, i.e., the third clock terminal ck3; the first threshold control signal VS1, the second threshold control signal VS2 and the third threshold control signal VS3 of the 2k-1 level shift register and the 2k level shift register are all coupled by the same clock terminal, i.e., the fourth clock terminal ck4.

[0227] Specifically, when the signals at the first control signal terminal and the second control signal terminal are clock signals, the first control signal terminal of the 2k-1th level shift register and the second control signal terminal of the 2kth level shift register are both coupled to the same clock terminal, i.e., the fifth clock terminal ck5; the second control signal terminal of the 2k-1th level shift register and the first control signal terminal of the 2kth level shift register are both coupled to the same clock terminal, i.e., the sixth clock terminal ck6.

[0228] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including the above-mentioned gate driving circuit provided by the embodiment of the present disclosure. The principle of solving the problem by the display device is similar to that of the above-mentioned shift register, so the implementation of the display device can refer to the implementation of the above-mentioned shift register, and the repeated parts will not be repeated here.

[0229] In a specific implementation, the display device provided in the embodiment of the present disclosure may be as follows: Fig.12 Of course, the display device provided in the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be described here, nor should they be used as a limitation to the present disclosure.

[0230] In a specific implementation, the display device may include multiple pixel units, multiple gate lines and data lines, and each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels. The above-mentioned display device provided in the embodiment of the present disclosure may be an organic light-emitting display device, or may also be a liquid crystal display device, which is not limited here.

[0231] In a liquid crystal display device, such as Fig.13aAs shown, a row of sub-pixels spx is electrically connected to a gate line GA, and a column of sub-pixels spx is electrically connected to a data line DA. The sub-pixel spx may include a scanning transistor N00 and a pixel electrode 200. Among them, the gate of the scanning transistor N00 may be electrically connected to the gate line GA, the source of the scanning transistor N00 is electrically connected to the data line DA, and the drain of the scanning transistor N00 is electrically connected to the pixel electrode 200. In addition, a driving signal output terminal OP of a shift register is electrically connected to a gate line GA, so that the driving signal output terminal OP of the shift register can provide a signal to the gate of the scanning transistor N00 in the sub-pixel, and the cascade signal output terminal GP of the shift register is used to transmit a start signal to the next-level shift register. In this way, when the above-mentioned display device provided in the embodiment of the present disclosure is a liquid crystal display device, the above-mentioned driving circuit can be used as a gate driving circuit, which is applied to provide a gate scanning signal of the scanning transistor N00. It should be noted that the scanning transistor N00 can be an N-type transistor or a P-type transistor, which is not limited here.

[0232] Furthermore, two different types of transistors may be provided in a sub-pixel. Fig.13b As shown, the display device may include a plurality of first gate lines GA1 and a plurality of second gate lines GA2. A row of sub-pixels is electrically connected to a first gate line GA1 and a second gate line GA2. The sub-pixel spx may include a first scanning transistor N01, a second scanning transistor P01 and a pixel electrode 200. Among them, the first scanning transistor N01 is an N-type transistor, and the second scanning transistor P01 is a P-type transistor. The gate of the first scanning transistor N01 is electrically connected to the first gate line GA1, and the second scanning transistor P01 is electrically connected to the second gate line GA2. The source of the second scanning transistor P01 is electrically connected to the data line DA, the drain of the second scanning transistor P01 is electrically connected to the source of the first scanning transistor N01, and the drain of the first scanning transistor N01 is electrically connected to the pixel electrode 200. In addition, the drive signal output terminal OP of a shift register is electrically connected to a first gate line GA1, and the cascade signal output terminal GP of a shift register is electrically connected to a second gate line GA2. In this way, the drive signal output terminal OP of the shift register can provide a signal to the gate of the N-type transistor in the sub-pixel. The cascade signal output terminal GP of the shift register provides a signal to the gate of the P-type transistor in the sub-pixel, and the cascade signal output terminal GP is also used to transmit a start signal to the next-stage shift register. In this way, when the display device provided in the embodiment of the present disclosure is a liquid crystal display device, the drive circuit can be used as a gate drive circuit to provide a gate scanning signal.

[0233] In an organic light-emitting display device, a plurality of organic light-emitting diodes and a pixel circuit connected to each organic light-emitting diode are generally provided. A light-emitting control transistor for controlling the light emission of the organic light-emitting diode and a scan control transistor for controlling the input of a data signal are generally provided in the pixel circuit. In a specific implementation, when the above-mentioned display device provided in the embodiment of the present disclosure is an organic light-emitting display device, the organic light-emitting display device may include the above-mentioned driving circuit provided in the embodiment of the present disclosure, and the driving circuit may be used as a light-emitting driving circuit, applied to provide a light-emitting control signal of the light-emitting control transistor; or, the driving circuit may also be used as a gate driving circuit, applied to provide a gate scanning signal of the scanning control transistor. Of course, the organic light-emitting display device may also include two of the above-mentioned driving control circuits provided in the embodiment of the present disclosure, one of which may be used as a light-emitting driving circuit, applied to provide a light-emitting control signal of the light-emitting control transistor; and the other driving circuit may be used as a gate driving circuit, applied to provide a gate scanning signal of the scanning control transistor, which is not limited here.

[0234] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0235] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A shift register, wherein: include: An input circuit is configured to be coupled to an input signal terminal, a second clock signal terminal and a first electrode of the first transistor respectively; and the input circuit is configured to provide the signal of the input signal terminal to the first electrode of the first transistor in response to a signal of the second clock signal terminal; The first transistor is a dual-gate transistor; wherein the first gate of the first transistor is configured to be coupled to a first reference signal terminal, and the second gate of the first transistor is configured to receive a first threshold control signal; A cascade output circuit is configured to be coupled to a first clock signal terminal and a cascade signal output terminal respectively, and a control terminal of the cascade output circuit is coupled to the second electrode of the first transistor; the cascade output circuit is configured to enable the cascade signal output terminal to output a cascade signal according to signals of the first clock signal terminal and the control terminal of the cascade output circuit; The driving output circuit is configured to be coupled to the cascade signal output terminal and the driving signal output terminal respectively, and the driving output circuit is configured to enable the driving signal output terminal to output a driving signal according to the cascade signal of the cascade signal output terminal.

2. The shift register as claimed in claim 1, wherein: The input circuit comprises: a second dual-gate transistor; The first gate of the second transistor is configured to be coupled to the second clock signal terminal, the second gate of the second transistor is configured to receive a second threshold control signal, the first electrode of the second transistor is configured to be coupled to the input signal terminal, and the second electrode of the second transistor is coupled to the first electrode of the first transistor.

3. The shift register as claimed in claim 2, wherein: The shift register further includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first capacitor; The first gate of the third transistor is configured to be coupled to the first clock signal terminal, the first electrode of the third transistor is coupled to the first electrode of the first transistor, and the second electrode of the third transistor is coupled to the first electrode of the fourth transistor; The first gate of the fourth transistor is coupled to the first gate of the seventh transistor, and the second electrode of the fourth transistor is configured to be coupled to the second reference signal terminal; The first gate of the fifth transistor is configured to be coupled to the second clock signal terminal, the first electrode of the fifth transistor is configured to be coupled to the first reference signal terminal, and the second electrode of the fifth transistor is coupled to the first gate of the seventh transistor; The first gate of the sixth transistor is coupled to the first electrode of the first transistor, the first electrode of the sixth transistor is configured to be coupled to the second clock signal terminal, and the second electrode of the sixth transistor is coupled to the first gate of the seventh transistor; The first electrode of the seventh transistor is configured to be coupled to the second reference signal terminal, and the second electrode of the seventh transistor is coupled to the cascade signal output terminal; A first terminal of the first capacitor is coupled to the first gate of the seventh transistor, and a second terminal of the first capacitor is configured to be coupled to the second reference signal terminal.

4. The shift register as claimed in claim 3, wherein: At least one of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor is a dual-gate transistor; For the transistor configured as the dual-gate transistor, the second gate of the transistor is configured to receive a first control signal.

5. The shift register as claimed in claim 4, wherein: The first control signal includes: a third threshold control signal, a fourth threshold control signal, a fifth threshold control signal, a sixth threshold control signal and a seventh threshold control signal; The third transistor is a dual-gate transistor; wherein the first gate of the third transistor is configured to be coupled to the first clock signal terminal, and the second gate of the third transistor is configured to receive the third threshold control signal; The fourth transistor is a dual-gate transistor; wherein the first gate of the fourth transistor is coupled to the first gate of the seventh transistor, and the second gate of the fourth transistor is configured to receive the fourth threshold control signal; The fifth transistor is a dual-gate transistor; wherein a first gate of the fifth transistor is coupled to the second clock signal terminal, and a second gate of the fifth transistor is configured to receive the fifth threshold control signal; The sixth transistor is a dual-gate transistor; wherein the first gate of the sixth transistor is coupled to the first electrode of the first transistor, and the second gate of the sixth transistor is configured to receive the sixth threshold control signal; The seventh transistor is a dual-gate transistor; wherein a first gate of the seventh transistor is coupled to a first gate of the fourth transistor, and a second gate of the seventh transistor is configured to receive the seventh threshold control signal.

6. The shift register as claimed in claim 5, wherein: The cascade output circuit comprises: an eighth transistor and a second capacitor; The first gate of the eighth transistor is coupled to the second electrode of the first transistor, the first electrode of the eighth transistor is configured to be coupled to the first clock signal terminal, and the second electrode of the eighth transistor is coupled to the cascade signal output terminal; A first terminal of the second capacitor is coupled to the second electrode of the first transistor, and a second terminal of the second capacitor is coupled to the cascade signal output terminal.

7. The shift register as claimed in claim 6, wherein: The eighth transistor is a dual-gate transistor, wherein a first gate of the eighth transistor is coupled to a second gate of the first transistor, and a second gate of the eighth transistor is configured to receive an eighth threshold control signal.

8. The shift register as claimed in claim 7, wherein: The driving output circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a third capacitor and a fourth capacitor; The first gate of the ninth transistor is coupled to the cascade signal output terminal, the first electrode of the ninth transistor is coupled to the second reference signal terminal, and the second electrode of the ninth transistor is coupled to the first gate of the twelfth transistor; The first gate of the tenth transistor is coupled to the first control signal terminal, the first electrode of the tenth transistor is coupled to the first reference signal terminal, and the second electrode of the tenth transistor is coupled to the first gate of the twelfth transistor; The first gate of the eleventh transistor is coupled to the cascade signal output terminal, the first electrode of the eleventh transistor is coupled to the second reference signal terminal, and the second electrode of the eleventh transistor is coupled to the drive signal output terminal; A first electrode of the twelfth transistor is coupled to the first reference signal terminal, and a second electrode of the twelfth transistor is coupled to the driving signal output terminal; A first terminal of the third capacitor is coupled to the second control signal terminal, and a second terminal of the third capacitor is coupled to the first gate of the twelfth transistor; A first terminal of the fourth capacitor is coupled to the first gate of the twelfth transistor, and a second terminal of the fourth capacitor is coupled to the driving signal output terminal.

9. The shift register as claimed in claim 8, wherein: At least one of the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor is a dual-gate transistor; For the transistor configured as the dual-gate transistor, the second gate of the transistor is configured to receive a second control signal.

10. The shift register as claimed in claim 9, wherein: The second control signal includes: a ninth threshold control signal, a tenth threshold control signal, an eleventh threshold control signal and a twelfth threshold control signal; The ninth transistor is a dual-gate transistor, wherein a first gate of the ninth transistor is coupled to the cascade signal output terminal, and a second gate of the ninth transistor is configured to receive the ninth threshold control signal; The tenth transistor is a dual-gate transistor, wherein a first gate of the tenth transistor is coupled to the first control signal terminal, and a second gate of the tenth transistor is configured to receive the tenth threshold control signal; The eleventh transistor is a dual-gate transistor, wherein a first gate of the eleventh transistor is coupled to the cascade signal output terminal, and a second gate of the eleventh transistor is configured to receive the eleventh threshold control signal; The twelfth transistor is a dual-gate transistor, wherein a first gate of the twelfth transistor is coupled to a second electrode of the tenth transistor, and a second gate of the twelfth transistor is configured to receive the twelfth threshold control signal.

11. The shift register according to claim 10, wherein: At least two of the first threshold control signal, the second threshold control signal, the third threshold control signal, the fourth threshold control signal, the fifth threshold control signal, the sixth threshold control signal, the seventh threshold control signal, the eighth threshold control signal, the ninth threshold control signal, the tenth threshold control signal, the eleventh threshold control signal and the twelfth threshold control signal use the same adjustment signal terminal input signal.

12. The shift register according to claim 11, wherein: The first threshold control signal, the second threshold control signal, the third threshold control signal, the fourth threshold control signal, the fifth threshold control signal, the sixth threshold control signal, the ninth threshold control signal, the tenth threshold control signal and the eleventh threshold control signal use the same input signal of the adjustment signal terminal; The first gate and the second gate of the seventh transistor are coupled; The first gate and the second gate of the eighth transistor are coupled; The first gate and the second gate of the twelfth transistor are coupled.

13. The shift register according to claim 11, wherein: The ninth threshold control signal and the eleventh threshold control signal use the same input signal of the adjustment signal terminal; A first gate of at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the tenth transistor and the twelfth transistor is coupled to the second gate.

14. The shift register according to any one of claims 11 to 13, wherein: The adjustment signal terminal outputs a second adjustment signal, and the second adjustment signal is a fixed voltage signal.

15. The shift register according to claim 11, wherein: The first threshold control signal, the second threshold control signal and the fourth threshold control signal use the same input signal of the adjustment signal terminal; wherein the adjustment signal terminal outputs a first adjustment signal, and the first adjustment signal is a clock signal; A first gate of at least one of the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor is coupled to the second gate.

16. The shift register as claimed in claim 15, wherein: The first adjustment signal has the same timing as the signal at the second clock signal end.

17. A method for driving a shift register according to any one of claims 3 to 16, wherein: include: In the input stage, the input circuit controls the level of the signal at the first electrode of the first transistor according to the signal at the input signal terminal and the signal at the second clock signal terminal; The first transistor is turned on; The cascade output circuit provides the signal of the first clock signal terminal to the cascade signal output terminal in response to the signal of the second electrode of the first transistor; The driving output circuit enables the driving signal output terminal to output a driving signal according to the cascade signal of the cascade signal output terminal; In the output stage, the threshold voltage of the first transistor moves in response to the signal at the first threshold control signal terminal, and the first transistor is turned off; The cascade output circuit provides the signal of the first clock signal terminal to the cascade signal output terminal in response to the signal of the second electrode of the first transistor; the drive output circuit enables the drive signal output terminal to output a drive signal according to the cascade signal of the cascade signal output terminal.

18. The driving method according to claim 17, wherein: After the output stage, the driving method further includes: In the reset stage, the input circuit controls the level of the signal at the first electrode of the first transistor according to the signal at the input signal terminal and the signal at the second clock signal terminal; the first transistor is turned on; the cascade output circuit responds to the signal at the control terminal of the cascade output circuit and provides the signal at the second reference signal terminal to the cascade signal output terminal; the drive output circuit causes the drive signal output terminal to output a drive signal according to the cascade signal at the cascade signal output terminal; In the holding stage, the cascade output circuit responds to the signal of the control end of the cascade output circuit to provide the signal of the second reference signal end to the cascade signal output end; the drive output circuit enables the drive signal output end to output the drive signal according to the cascade signal of the cascade signal output end.

19. A gate drive circuit, wherein: A shift register comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 16; The input signal terminal of the first stage shift register is configured to be coupled to the frame trigger signal terminal; In every two adjacent shift registers, the input signal terminal of the next-stage shift register is configured to be coupled to the cascade signal output terminal of the previous-stage shift register.

20. A display device, wherein: Comprising the gate drive circuit as claimed in claim 19.

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