Clock calibration device and measuring equipment

Abstract

A clock calibration device for a measuring device and the measuring device itself are disclosed. The clock calibration device includes a GPS receiver module, a programmable array logic unit, and a calibration module. The GPS receiver module generates a second pulse synchronization signal. The programmable array logic unit delays the rising edge of the second pulse synchronization signal to obtain a third synchronization signal. Based on the second pulse synchronization signal and the third synchronization signal, a synchronization pulse signal is generated. The time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal is calculated. Based on this time difference and the period of the third synchronization signal, the period of the second pulse synchronization signal is determined. Finally, based on the difference between the period of the second pulse synchronization signal and the target period, a calibration control signal is output. The calibration module calibrates the frequency of the measuring device's operating clock signal based on the calibration control signal to ensure that the measuring device's operating clock signal is synchronized with the clock of the satellite positioning system.

Description

Technical Field

[0001] This invention relates to the field of measurement technology, and more specifically to a clock calibration device and a measuring device. Background Technology

[0002] People's daily lives, businesses, production, and scientific research all require accurate time, and a unified time standard is becoming increasingly important to all sectors of modern society. Currently, the internationally accepted time standards are: Atomic Time (TAI), Universal Time (UT), and Coordinated Universal Time (UTC).

[0003] Given that the atomic clocks used in global positioning systems such as GPS and BeiDou are highly accurate, GPS time signals are currently widely used in wireless communication base stations, power systems, and geological exploration. For example, communication base stations primarily receive 1PPS (Pulses Per 1 Second) and TOD (Time of Day) signals from GPS satellites.

[0004] The 1PPS (1 second pulse) signal is emitted by the satellite's atomic clock, and its rising edge, known as the punctual edge, has extremely high edge accuracy. However, because GPS communication contains other data packets, the pulse width of the 1PPS signal is not uniform, typically ranging from 20ms to 200ms. Figure 1 The waveform of the 1PPS signal is shown below.

[0005] GPS satellites use atomic clocks with very high frequencies, exceeding 9 GHz. The principle of synchronizing the local clock using the 1PPS signal is essentially clock synchronization frequency locking, locking the frequency of the local clock source, such as an OCXO, TCXO, or VCXO, to the frequency equivalent to that of the GPS satellite. For example, if the 1PPS pulse time interval in the GPS satellite is divided into 10^7 equal parts, and a local 10MHz clock source is used to lock the "10MHz" clock of the GPS satellite, since the rising edge of the "10MHz" clock on the GPS satellite is exactly the same as the edge of the 1PPS clock, the "10MHz" clock derived from the 1PPS is highly accurate. However, the clock frequency of the local clock source, such as an OCXO, TCXO, or VCXO, has an error compared to the standard "10MHz" clock frequency. By modifying the output frequency of the local clock source, the 10MHz output from the local clock source can be made infinitely close to the "10MHz" frequency derived from the 1PPS signal from the satellite, reducing the error and achieving synchronization between the local clock frequency and the clock frequency derived from the 1PPS of the satellite positioning system.

[0006] Clock synchronization is a crucial technology in numerous fields, including communications, geological exploration, and power. Its purpose is to align clocks distributed around the world, ensuring that clocks everywhere are synchronized with a standard clock. Currently, the mainstream architecture uses a numerically controlled phase-locked loop (PLL), employing high-real-time processor chips such as DSPs and FPGAs to perform second pulse edge interception and clock synchronization. This solution is expensive and technologically closed, with different manufacturers implementing 1PPS clock synchronization modules using varying principles.

[0007] Measurement equipment, such as oscilloscopes, spectrum analyzers, and network analyzers, all use local operating clocks. Over long-term use, clock frequency drift can occur, leading to errors between the measured signal frequency values ​​and the actual values. Returning the equipment to the factory for frequency accuracy calibration increases usage costs. Furthermore, when using measurement equipment to test signals from base stations and communication devices, the operating clock frequency of most current measurement equipment cannot be synchronized to the clock domain of the device under test, increasing testing difficulty. Finally, current techniques for disciplining operating clocks based on satellite positioning systems suffer from insufficient synchronization accuracy between the docile operating clock source frequency and the clock frequency of the positioning satellite, resulting in a certain frequency difference. Summary of the Invention

[0008] The main technical problem solved by this invention is how to make the working clock signal of the measuring device synchronized with the clock of the satellite positioning system.

[0009] According to a first aspect, one embodiment provides a clock calibration device for a measuring apparatus, comprising:

[0010] The GPS receiver module is used to generate a second pulse synchronization signal based on the timing information from the satellite positioning system.

[0011] Programmable array logic, including synchronous pulse extension circuit, digital TDC circuit and control unit;

[0012] The synchronization pulse extension circuit is used to acquire the second pulse synchronization signal and the counting clock signal, and to delay the rising edge of the second pulse synchronization signal to obtain a third synchronization signal, wherein the rising edge of the third synchronization signal is synchronized with the clock edge of the counting clock signal; the synchronization pulse extension circuit is also used to generate a synchronization pulse signal based on the rising edge of the second pulse synchronization signal and the rising edge of the third synchronization signal, wherein the rising edge of the synchronization pulse signal is the rising edge of the second pulse synchronization signal, and the falling edge of the synchronization pulse signal is the rising edge of the third synchronization signal;

[0013] The digital TDC circuit is used to acquire the synchronization pulse signal, calculate the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal, and then determine the period of the second pulse synchronization signal based on the period of the third synchronization signal and the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal.

[0014] The control unit is used to acquire the period and target period of the second pulse synchronization signal, and output a calibration control signal based on the difference between the period and target period of the second pulse synchronization signal.

[0015] The calibration module is used to calibrate the frequency of the operating clock signal of the measuring device based on the calibration control signal, so as to synchronize the operating clock of the measuring device with the second pulse synchronization signal.

[0016] According to a second aspect, one embodiment provides a measuring device, comprising:

[0017] The main measurement module is used to acquire and process signals based on the operating clock signal of the measurement device;

[0018] A clock calibration device, wherein the clock calibration device is the clock calibration device described in any of the above embodiments, is used to calibrate the working clock signal of the measuring device after receiving an externally input calibration command.

[0019] According to the above embodiments, the clock calibration device and the measuring device include a GPS receiver module, a programmable array logic unit, and a calibration module. The GPS receiver module generates a second pulse synchronization signal. The programmable array logic unit delays the rising edge of the second pulse synchronization signal to obtain a third synchronization signal. Based on the second pulse synchronization signal and the third synchronization signal, a synchronization pulse signal is generated. The time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal is calculated. Based on the time difference and the period of the third synchronization signal, the period of the second pulse synchronization signal is determined. Finally, based on the difference between the period of the second pulse synchronization signal and the target period, a calibration control signal is output. The calibration module calibrates the frequency of the measuring device's operating clock signal based on the calibration control signal to make the measuring device's operating clock signal synchronized with the clock of the satellite positioning system. Attached Figure Description

[0020] Figure 1 A waveform diagram of a 1PPS signal;

[0021] Figure 2 This is a schematic diagram illustrating the principle of time interval measurement.

[0022] Figure 3 A schematic diagram illustrating the principle of digital phase-shift counting measurement;

[0023] Figure 4 A schematic diagram illustrating the principle of the clock signal for PID discipline.

[0024] Figure 5 This is a schematic diagram of the structure of a clock calibration device for a measuring apparatus according to one embodiment;

[0025] Figure 6 This is a timing diagram of the counting clock signal CLK, the second pulse synchronization signal W, the first synchronization signal W1, the second synchronization signal W2, the third synchronization signal W3, and the synchronization pulse signal P;

[0026] Figure 7 This is a schematic diagram of the structure of a digital TDC circuit according to one embodiment;

[0027] Figure 8 This is a schematic diagram illustrating the principle of metastable state.

[0028] Figure 9 This is a schematic diagram of the structure of a digital TDC circuit according to another embodiment;

[0029] Figure 10 This is the decoding timing diagram;

[0030] Figure 11 This is a schematic diagram of the counting clock signal, the signals of each delay tap, and the valid signal valid1;

[0031] Figure 12 This is a schematic diagram of the counting clock signal, the signals of each delay tap, and the valid signal valid2;

[0032] Figure 13 This is the control block diagram of a PID controller;

[0033] Figure 14 The flowchart shows the implementation of a PID controller.

[0034] Figure 15 This is a simulation diagram showing the change of the error signal e(k) over time.

[0035] Figure 16 This is a schematic diagram of the structure of a measuring device according to one embodiment. Detailed Implementation

[0036] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0037] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0038] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0039] Please refer to Figure 2 , Figure 2 A schematic diagram illustrating the principle of time interval measurement is shown; the period of the second pulse (1PPS) synchronization signal is... Figure 2 In this context, T is obtained by adding the "coarse measurement" time to the "fine measurement" time, as shown in the following expression:

[0040] T = N * T C +Δt1-Δt2

[0041] Wherein N*T C Let Δt1-Δt2 be the coarse measurement time, Δt1-Δt2 be the fine measurement time, and Tc be the period of the counting clock signal CLK. Because the pulse-per-second (1PPS) synchronization signal and the counting clock signal CLK are asynchronous signals, Δt1-Δt2 represents the measurement error caused by a non-integer number of counting clock signals CLK. Therefore, due to the asynchrony between the counting clock signal CLK and the pulse-per-second (1PPS) synchronization signal, there exists a measurement error term Δt1-Δt2. This error term can be up to ±1 counting clock pulse width, i.e., -Tc to +Tc.

[0042] In addition, the period T of the counting clock signal CLK C This determines the minimum accuracy of the measurement method, i.e., the minimum time resolution. In test methods based on the time interval measurement principle, the higher the frequency of the counting clock signal CLK, the more accurate the measurement. However, relying on increasing the frequency of the counting clock signal to achieve high measurement accuracy places high demands on chip performance and is therefore less feasible.

[0043] As can be seen from the above description, in order to reduce measurement errors and improve the measurement accuracy of time intervals, it is necessary to reduce or even ignore the influence of Δt1-Δt2. The most direct way is to increase the frequency of the counting clock signal. However, due to the limitations of chip performance, if it is not convenient to increase the frequency of the counting clock signal, digital phase-shift counting can also be used to improve measurement accuracy.

[0044] like Figure 3 As shown, the DCM module on the FPGA (Programmable Array Logic Controller) chip is used to shift the counting clock signals CLK1 to CLK4 by 90° intervals. Each CLKx (x = 1, 2, 3, 4) has the same frequency, and the pulse width of the time interval is counted on both the rising and falling edges of CLKx. After using an equivalent counting clock to count the pulse width, the counting period is equivalent to Tc / 8 of the original clock. The equivalent clock frequency is increased to 8 times the original, so the counting error becomes -1 / 8Tc to +1 / 8Tc. However, this method depends on the frequency of the operating clock signal of the measuring device; the higher the frequency of the operating clock signal, the more accurate the measurement.

[0045] This embodiment also provides a method for PID control of a clock signal. A PID controller is a linear regulator that calculates the control quantity based on the deviation between a given input value and the actual output value, according to the P (proportional), integral (I), and derivative (D) functional relationship, so that the output tracks the input signal well. PID control algorithms are relatively mature, have a simple structure, and are easy to implement.

[0046] Figure 4 In this context, X(S) is the input signal, corresponding to a 1PPS signal; Y(S) is the output signal, corresponding to the frequency of the locally tamed clock source; E(S) is the error signal; and U(S) is the control signal. P It is a proportional element, capable of generating timely adjustments proportional to the deviation to reduce it. K P / (T I S) is the integral term, used to eliminate the static error of the system and improve the system's accuracy. T I Let T be the integration time constant. I The larger the value of K, the stronger its integral effect. P T DS is the differential element, which controls the change in deviation and helps to reduce overshoot and overcome oscillation. T... D It is the differential time constant.

[0047] PID controllers are a control method based on negative feedback, which is beneficial for improving system stability and is suitable for use in high-precision control systems. Currently, the method of using digital PID controllers for local clock discipline has an accuracy error greater than one cycle of the counting clock signal CLK.

[0048] To address the aforementioned issues, this embodiment of the invention converts the second pulse synchronization signal into a synchronization pulse signal using a synchronization pulse extension circuit. The time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal is calculated to obtain the fine measurement time. Combined with the coarse measurement time, the period of the second pulse synchronization signal is determined. Based on the difference between the period of the second pulse synchronization signal and the target period, the frequency of the working clock signal is calibrated to ensure that the working clock signal of the measuring device is synchronized with the clock of the satellite positioning system.

[0049] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of a clock calibration device for a measuring device according to an embodiment, hereinafter referred to as the clock calibration device. The clock calibration device includes: a GPS receiver module 101, a programmable array logic unit 102, and a calibration module 103. The programmable array logic unit 102 includes a synchronous pulse extension circuit 1021, a digital TDC circuit 1022, a control unit 1023, and a frequency divider module 1024. The calibration module 103 includes a digital-to-analog converter 1031, a voltage-controlled oscillator 1032, and a phase-locked loop 1033. These will be described in detail below.

[0050] The GPS receiver module 101 is used to generate a pulse-per-second synchronization signal, or 1PPS synchronization signal, based on the timing information from the satellite positioning system.

[0051] The synchronous pulse extension circuit 1021 in the programmable array logic 102 is used to acquire the second pulse synchronization signal and the counting clock signal, and to delay the rising edge of the second pulse synchronization signal to obtain a third synchronization signal, wherein the rising edge of the third synchronization signal is synchronized with the clock edge of the counting clock signal.

[0052] In one embodiment, the rising edge of the second pulse synchronization signal is delayed to obtain a third synchronization signal, which includes:

[0053] Obtain the period of the counting clock signal at which the rising edge of the second pulse synchronization signal occurs, and use the counting clock signal corresponding to the period of the obtained counting clock signal as the synchronous counting clock signal.

[0054] A first synchronization signal is generated based on the synchronous counting clock signal, wherein the rising edge of the first synchronization signal is synchronized with the clock edge of the synchronous counting clock signal.

[0055] Based on the first synchronization signal, a second synchronization signal is generated, wherein the rising edge of the second synchronization signal is delayed by one period of a counting clock signal relative to the rising edge of the first synchronization signal.

[0056] A third synchronization signal is generated based on the second synchronization signal, wherein the rising edge of the third synchronization signal is delayed by one counting clock signal period relative to the rising edge of the second synchronization signal.

[0057] Therefore, the first synchronization signal, the second synchronization signal, and the third synchronization signal have the same period. The second synchronization signal differs from the first synchronization signal by one counting clock signal period, and the third synchronization signal differs from the second synchronization signal by one counting clock signal period. Thus, the third synchronization signal and the first synchronization signal differ by two counting clock signal periods.

[0058] It should be noted that the period of the first, second, or third synchronization signal is the coarse measurement time N*T. C .

[0059] The synchronization pulse extension circuit 1021 is also used to generate a synchronization pulse signal based on the rising edge of the second pulse synchronization signal and the rising edge of the third synchronization signal, wherein the rising edge of the synchronization pulse signal is the rising edge of the second pulse synchronization signal, and the falling edge of the synchronization pulse signal is the rising edge of the third synchronization signal.

[0060] It should be noted that the synchronization pulse extension circuit 1021 provided in this embodiment can be implemented by digital circuits, for example, by three D flip-flops. The first synchronization signal is the signal output through one D flip-flop, the second synchronization signal is the signal output through two D flip-flops, and the third synchronization signal is the signal output through three D flip-flops.

[0061] The digital TDC circuit 1022 is used to acquire the synchronization pulse signal, calculate the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal, and then determine the period of the second pulse synchronization signal based on the period of the third synchronization signal and the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal.

[0062] Please refer to Figure 6 , Figure 6This is a timing diagram of the counting clock signal CLK, the second pulse synchronization signal W, the first synchronization signal W1, the second synchronization signal W2, the third synchronization signal W3, and the synchronization pulse signal P. Since the second pulse synchronization signal W and the counting clock signal CLK are asynchronous, this embodiment first synchronizes the second pulse synchronization signal W asynchronously by generating the first synchronization signal W1, the second synchronization signal W2, and the third synchronization signal W3 sequentially, so that the resulting third synchronization signal W3 is synchronized with the clock edge of the clock signal. Then, the rising edge of the second pulse synchronization signal W is taken as the rising edge of the synchronization pulse signal P, and the rising edge of the third synchronization signal W3 is taken as the falling edge of the synchronization pulse signal P, forming the synchronization pulse signal P. The expression for the synchronization pulse signal P is P = ! W3 & W, where & represents logical AND and ! represents logical NOT.

[0063] In this embodiment, the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal is calculated. The time differences Δt1 and Δt2 between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal are calculated respectively, and the fine measurement time Δt1-Δt2 can be obtained.

[0064] The control unit 1023 is used to acquire the period and target period of the second pulse synchronization signal, and outputs a calibration control signal based on the difference between the period and the target period. In this embodiment, the control unit is a PID control unit, which uses a PID control method to determine the calibration control signal based on the difference between the period and the target period of the second pulse synchronization signal.

[0065] The frequency divider module 1024 is used to receive the working clock signal of the measuring equipment, divide the working clock signal to obtain the counting clock signal.

[0066] In this embodiment, the second pulse synchronization signal generated by the GPS receiver module 101 is equivalent to an external trigger signal. After the synchronization pulse extension circuit 1021 performs a coarse measurement of the time interval, the coarse measurement time N*T is obtained. C The coarse measurement time can be directly obtained. A synchronization pulse signal P is then generated and input into the digital TDC circuit 1022 to calculate the fine measurement time Δt1-Δt2. After measurement, the period of the second pulse synchronization signal is obtained as T = N*T. C +Δt1-Δt2, and then send the period T into the control unit 1023.

[0067] The calibration module 103 is used to calibrate the frequency of the operating clock signal of the measuring device based on the calibration control signal, so as to synchronize the operating clock of the measuring device with the second pulse synchronization signal.

[0068] In one embodiment, the calibration module 103 includes a digital-to-analog converter (D / A converter) 1031, a voltage-controlled oscillator (VCXO) 1032, and a phase-locked loop (PLL) 1033. The D / A converter 1031 converts the calibration control signal into an analog control voltage. The VCXO 1032 generates a reference clock frequency value corresponding to the analog control voltage. In this embodiment, the VCXO 1032 is a local clock reference source with good short-term stability, good phase noise performance, and low jitter. The VCXO 1032 adjusts its output reference clock frequency value according to the analog control voltage received at its input. The PLL 1033 generates a working clock signal for the measuring device that is several times higher than the reference clock frequency, based on the reference clock frequency value output by the VCXO 1032.

[0069] In one embodiment, please refer to Figure 7 The digital TDC circuit 1022 includes a delay chain 201, multiple D flip-flops 202, and a first thermometer code decoder 203, which are described in detail below.

[0070] The input terminal of the delay chain 201 is connected to the output terminal of the synchronous pulse extension circuit 1021, and is used to receive the signal output by the synchronous pulse extension circuit 1021.

[0071] The delay chain 201 includes multiple delay taps, each corresponding one-to-one with a D flip-flop 202. Each delay tap is connected to the input pin of its corresponding D flip-flop 202. Each delay tap is used to delay the signal received by the delay chain 201 for different time intervals.

[0072] Delay tap 1 is used to delay the signal received by delay chain 201 for a delay time t;

[0073] Delay tap 2 is used to delay the signal received by delay chain 201 for a delay time of 2t;

[0074] …

[0075] The delay tap n is used to delay the signal received by the delay chain 201 for a delay time nt.

[0076] Each D flip-flop 202 receives the signal output from the corresponding delay tap and outputs a valid level signal when the signal received by the delay chain 201 is a synchronization pulse signal; otherwise, it outputs an invalid level signal. That is, when the delay chain 201 does not receive a synchronization pulse signal, all D flip-flops output invalid level signals. After the delay chain 201 receives a synchronization pulse signal, because the pulse width of the synchronization pulse signal is finite, some D flip-flops will output valid level signals.

[0077] The first thermometer code decoder 203 receives the level signals output by each D flip-flop and outputs the corresponding first decoded value sequence. The first decoded value sequence includes multiple first decoded values, and each first decoded value corresponds one-to-one with the level signal output by each D flip-flop. The first thermometer code decoding module synchronizes the time difference between the two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal according to the number of valid decoded values ​​in the first decoded value sequence. It should be noted that this time difference is the initial time difference.

[0078] Please refer to Figure 8 Due to the existence of metastability, when the second pulse synchronization signal falls within the hold time window of the clock edge, the synchronization trigger signal may be synchronized to synchronization signal 1 by the current clock edge, or it may be synchronized to synchronization signal 2 by the next clock edge. That is, when the synchronization pulse extension circuit 1021 adjusts the delay of the rising edge of the second pulse synchronization signal, the resulting third synchronization signal may contain two counting clock signal cycles or three counting clock signal cycles between it and the second pulse synchronization signal. Therefore, to avoid the existence of metastability, this embodiment... Figure 7 The digital TDC circuit shown has been improved; please refer to [reference needed]. Figure 9 The digital TDC circuit also includes: a second thermometer code decoder 204, an AND gate logic circuit 205, and a counter 206.

[0079] The first thermometer code decoder 203 is also used to receive the signals output from each delay tap of the delay chain, and pulls the valid signal valid1 high when the first non-zero data is detected, outputting the first decoded value. The second thermometer code decoder 204 is used to receive the inverse code signals of the signals output from each delay tap of the delay chain, and pulls the valid signal valid2 high when the first data in the inverse code signal to transition from 0 to 1 is detected, outputting the second decoded value. Please refer to [reference needed]. Figure 10 , Figure 10 For the decoding timing, data1 is the original code signal output by the delay chain, and data2 is the inverse code signal of the original code signal.

[0080] The AND gate logic circuit 205 is used to obtain the inverse code values ​​of the first decoded value and the second decoded value, and to perform an AND operation on the inverse code values ​​of the first decoded value and the second decoded value to obtain the first signal.

[0081] Counter 206 is used to receive the first signal and count the first signal to obtain a count value. The count value is the number of counting clock signal cycles contained in the pulse width of the synchronization pulse signal.

[0082] In this embodiment, the first signal is m, then m = ! valid2 & valid1. The first signal m is counted, and the count value is b. Therefore: Δt1 = (b - 2) * T C+T D1 Δt2=(b-2)*T C +T D2 , among which, T D1 and T D2 Δt1 and Δt2 represent the initial time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal, respectively; Δt1 and Δt2 represent the time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal, respectively.

[0083] Please refer to Figure 11 If a synchronous pulse signal is input to the delay chain, then D(0), D(1)……D(n-1) represent the signals of each delay tap. Each clock signal samples the signals on the delay chain. After the first non-zero value is detected on the tap, the valid signal valid1 is pulled high and the value is output. No further detection is performed after that.

[0084] Please refer to Figure 12 If a synchronization pulse signal is input to the delay chain, then D(0)', D(1)'……D(n-1)' represent the inverse code signals of each delay tap. Each counting clock signal samples the signals on the delay chain. When the first data in the inverse code signal that jumps from 0 to 1 is detected at the tap, the valid signal valid2 is pulled high and the value is output. No further detection is performed after that.

[0085] from Figure 11 and Figure 12 The comparison shows that the inverse code detection timing converts the falling edge of the synchronization pulse signal P into a rising edge for detection. The original second pulse synchronization signal W is metastable, while the third synchronization signal W3 after three beats is already a stable signal. Logically, there are at least two complete counting clock cycles between the rising and falling edges of the synchronization pulse signal P. Therefore, using the formula Δt1=(b-2)*T C +T D1 Δt2=(b-2)*T C +T D2 This allows us to calculate the time difference between the rising edge of the second pulse synchronization signal W and the clock edge of the counting clock signal.

[0086] In this embodiment of the invention, the edge of the second pulse synchronization signal is widened into a pulse and then subtracted. This conversion calculation can eliminate metastability. It avoids detecting the specific tap position of the edge of the second pulse synchronization signal in the delay chain. By detecting the relative position, when metastability occurs, the relative position of the edge of the second pulse synchronization signal does not change, but belongs to different counting clock signal periods. The occurrence of metastability can be calculated by subtraction.

[0087] Through the above coarse and fine measurements, the period T = N*T of the second pulse synchronization signal is obtained. C +Δt1-Δt2, then subtract the measured period T from the target period T' to obtain the deviation value e(k)=ΔT, and output ΔT to the control unit.

[0088] In one embodiment, the control unit employs a PID (Proportional-Integral-Derivative) controller to tame the reference clock of the voltage-controlled oscillator, such as... Figure 13 As shown, although the control input of the PID controller undergoes a series of transformations, it ultimately controls the voltage-controlled oscillator. The PID controller model in this embodiment is K. P +K L / S+K D *S, where K P K is the proportionality coefficient. L K is the integral coefficient. D is the differential coefficient.

[0089] Discretization yields the following digital difference equation for the PID:

[0090] U(k)=K P e(k)+K I ∑ k j＝0 e(j)+K D [e(k)-e(k-1)]

[0091] Where k is the sampling sequence number, u(k) is the regulator output control quantity at the k-th sampling time, e(k) is the deviation value at the k-th sampling time, and e(k-1) is the deviation value at the (k-1)-th sampling time. K P It is a proportional element that can promptly generate a proportional adjustment effect to reduce deviation. K I It is an integral term used to eliminate the static error of the system and improve the system's error-free performance. K D It is the differential element, which controls the changes in deviation and helps to reduce overshoot and overcome oscillation.

[0092] The transfer function G(S) of the voltage-controlled oscillator tamped by the second pulse synchronization signal is calculated as follows:

[0093] Y(s)=(K P +K I / S+K D *S)*K F *1 / S*(Y(s)-X(s))G(S)=Y(s) / X(s)

[0094] This embodiment assumes that there is a proportionality coefficient K between the control quantity and the output frequency of the voltage-controlled oscillator. FThe frequency divider module can be viewed as an integral element, denoted as 1 / S. A suitable coefficient K is selected in the PID controller. P K I K D This allows for adjustment of the output frequency of the clock source voltage-controlled oscillator based on the input error signal e(k). The programmable array logic unit (PLA) judges the value of the error signal e(k), and if it is less than a certain value, the calibration is considered successful and the calibration ends. Figure 14 As shown, Figure 14 The implementation flowchart of the PID controller is shown.

[0095] like Figure 15 As shown, Figure 15 The simulation diagram shows the change of the error signal e(k) of the programmable array logic as input value over time. It can be seen that the error signal e(k) becomes smaller and smaller after calibration.

[0096] Please refer to Figure 16 The present invention also provides a measuring device, which includes a main measuring module 301 and a clock calibration device 302. The main measuring module 301 is used to acquire and process signals based on the working clock signal of the measuring device; the clock calibration device 302 is used to calibrate the working clock signal of the measuring device after receiving an externally input calibration command.

[0097] The measuring device provided in this invention firstly improves the accuracy of measuring the time interval of the second pulse synchronization signal, with an accuracy better than one counting clock signal cycle. Secondly, the measuring device uses a satellite positioning system to tame the local clock source, improving the clock source frequency accuracy of the measuring device and thus enhancing the overall accuracy of the measuring device. Thirdly, for measuring devices that have already left the factory, the clock source frequency can be calibrated in real time on-site, eliminating the need for periodic factory returns for calibration and reducing calibration costs. Finally, when using the measuring device to test signals from base stations, communication equipment, etc., the testing difficulty is reduced because both the clock of the object under test and the clock source of the testing measuring instrument are synchronized to the clock domain on the satellite positioning system.

[0098] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A clock calibration device for a measuring instrument, characterized in that, include: The GPS receiver module is used to generate a second pulse synchronization signal based on the timing information from the satellite positioning system. Programmable array logic, including synchronous pulse extension circuit, digital TDC circuit and control unit; The synchronization pulse extension circuit is used to acquire the second pulse synchronization signal and the counting clock signal, and to delay the rising edge of the second pulse synchronization signal to obtain a third synchronization signal, wherein the rising edge of the third synchronization signal is synchronized with the clock edge of the counting clock signal; the synchronization pulse extension circuit is also used to generate a synchronization pulse signal based on the rising edge of the second pulse synchronization signal and the rising edge of the third synchronization signal, wherein the rising edge of the synchronization pulse signal is the rising edge of the second pulse synchronization signal, and the falling edge of the synchronization pulse signal is the rising edge of the third synchronization signal; The digital TDC circuit is used to acquire the synchronization pulse signal, calculate the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal, and then determine the period of the second pulse synchronization signal based on the period of the third synchronization signal and the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal. The control unit is used to acquire the period and target period of the second pulse synchronization signal, and output a calibration control signal based on the difference between the period and target period of the second pulse synchronization signal. The calibration module is used to calibrate the frequency of the operating clock signal of the measuring device based on the calibration control signal, so as to synchronize the operating clock of the measuring device with the second pulse synchronization signal.

2. The clock calibration device as described in claim 1, characterized in that, The rising edge of the second pulse synchronization signal is delayed to obtain the third synchronization signal, which includes: Obtain the period of the counting clock signal at which the rising edge of the second pulse synchronization signal is located, and use the counting clock signal corresponding to the period of the obtained counting clock signal as the synchronous counting clock signal. Based on the synchronous counting clock signal, a first synchronization signal is generated, wherein the rising edge of the first synchronization signal is synchronized with the clock edge of the synchronous counting clock signal; Based on the first synchronization signal, a second synchronization signal is generated, wherein the rising edge of the second synchronization signal is delayed by one counting clock signal period relative to the rising edge of the first synchronization signal. Based on the second synchronization signal, a third synchronization signal is generated, wherein the rising edge of the third synchronization signal is delayed by one counting clock signal period relative to the rising edge of the second synchronization signal.

3. The clock calibration device as described in claim 1, characterized in that, The period of the second pulse synchronization signal is determined based on the period of the third synchronization signal and the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal, including: Calculate the time difference between two consecutive rising edges of the synchronization pulse signal and the clock edge of the counting clock signal; Obtain the period of the third synchronization signal; The period of the second pulse synchronization signal is calculated according to the following expression: T=N*T C +Δt1-Δt2 Where T is the period of the second pulse synchronization signal, and N is the number of counting clock signal periods contained within the period of the third synchronization signal. C The period of the counting clock signal is denoted by Δt1 and Δt2, which represent the time difference between the two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal, respectively.

4. The clock calibration device as described in claim 3, characterized in that, The digital TDC circuit includes: a delay chain, multiple D flip-flops, and a first thermometer code decoder; The delay chain includes multiple delay taps, each corresponding one-to-one with a D flip-flop, and each delay tap is connected to the input pin of its corresponding D flip-flop. Each delay tap is used to delay the received signal by the delay chain for different time intervals, wherein: Delay tap 1 is used to delay the signal received by the delay link for a delay time t; Delay tap 2 is used to delay the signal received by the delay link for a time of 2t; … The delay tap n is used to delay the signal received by the delay link by a delay time nt. Each of the D flip-flops is used to receive the signal output by the corresponding delay tap, and outputs a valid level signal when the received signal is the synchronization pulse signal; otherwise, it outputs an invalid level signal. The first thermometer code decoder is used to receive the level signals output by each of the D flip-flops and output the corresponding first decoded value sequence. The first decoded value sequence includes multiple first decoded values, and each first decoded value corresponds one-to-one with the level signal output by each D flip-flop. The first thermometer code decoder determines the initial time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal based on the number of valid decoded values ​​in the first decoded value sequence.

5. The clock calibration device as described in claim 4, characterized in that, The digital TDC circuit also includes: a second thermometer code decoder, an AND gate logic circuit, and a counter; The first thermometer code decoder is also used to receive the signals output by each delay tap of the delay chain, and output the first decoded value when the first non-zero signal is detected; The second thermometer code decoder is used to receive the inverse code signals of the signals output by each delay tap of the delay chain, and outputs the second decoded value when the first data that jumps from 0 to 1 is detected. The AND gate logic circuit is used to obtain the inverse code values ​​of the first decoded value and the second decoded value, and to perform an AND operation on the inverse code values ​​of the first decoded value and the second decoded value to obtain the first signal; The counter is used to receive the first signal and count the first signal to obtain a count value. The count value is the number of counting clock signal cycles contained in the pulse width of the synchronization pulse signal.

6. The clock calibration device as described in claim 5, characterized in that, Calculating the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal includes: The time difference between two consecutive rising edges of the synchronization pulse signal and the clock edge of the counting clock signal is calculated using the following expression: Δt1=(b-2)*T C +T D1 Δt2=(b-2)*T C +T D2 Where Δt1 and Δt2 represent the time differences between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal, respectively, and T D1 and T D2 b represents the initial time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal, and b represents the number of counting clock signal cycles contained in the pulse width of the synchronization pulse signal.

7. The clock calibration device as described in claim 1, characterized in that, The programmable array logic unit further includes: The frequency divider module is used to receive the working clock signal of the measuring device, divide the working clock signal to obtain the counting clock signal.

8. The clock calibration device as described in claim 1, characterized in that, The control unit is a PID control unit, which is used to determine the calibration control signal based on the difference between the period of the second pulse synchronization signal and the target period using a PID control method.

9. The clock calibration device as claimed in claim 1, characterized in that, The correction module includes: A digital-to-analog converter is used to convert the calibration control signal into an analog control voltage; A voltage-controlled oscillator is used to generate a reference clock frequency value corresponding to the analog control voltage based on the analog control voltage; A phase-locked loop is used to generate the operating clock signal of the measuring device based on the reference clock frequency value.

10. A measuring device, characterized in that, include: The main measurement module is used to acquire and process signals based on the operating clock signal of the measurement device; A clock calibration device, wherein the clock calibration device is as described in any one of claims 1 to 9, is used to calibrate the working clock signal of the measuring device after receiving an externally input calibration command.

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