Data processing method and device, electronic equipment and medium

Abstract

The application provides a data processing method and device, electronic equipment and medium. By executing a BL jump instruction, a first address of a first data segment adjacent to the BL jump instruction is saved to a first register, and a jump is made to execute a code. According to the first address in the first register, a processing instruction required first data in the first data segment is loaded into a second register by executing a corresponding loading instruction of the processing instruction. The scheme uses the characteristics of the BL instruction to passively save the first address of the first data segment to the first register, realizes the effect of obtaining the first address of the first data segment through only one BL instruction, and enables the loading of the to-be-processed data when the storage address of the to-be-processed data is unknown, and further realizes the processing of the to-be-processed data.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data processing method, apparatus, electronic device and medium. Background Technology

[0002] Data processing is the core of computer operation, and typically includes: loading the data to be processed from memory into the target register in the CPU to improve the CPU's processing speed, and then executing the corresponding processing instructions through the CPU's arithmetic unit to process the data in the target register.

[0003] In related technologies, when loading data to be processed, it is necessary to obtain the storage address of the data to be processed in the memory, load the data to be processed into the target register according to the storage address, and then process the data to be processed in the target register.

[0004] However, in some scenarios, the storage address of the data to be processed is unknown, which makes it impossible to load the data and thus impossible to process it. Summary of the Invention

[0005] This application provides a data processing method, apparatus, electronic device, and medium, aiming to solve the problem that the storage address of the data to be processed is unknown, making it impossible to load the data and thus impossible to process it.

[0006] In a first aspect, this application provides a data processing method, comprising: initializing a jump instruction (BL) and using adjacent code following the jump instruction as a first data segment; wherein the jump instruction is used to jump to the address of the code to be executed in memory; the code to be executed includes a processing instruction and a load instruction corresponding to the processing instruction; the first data segment includes data to be processed corresponding to the processing instruction; executing the jump instruction, saving the starting address of the first data segment in memory to a first register and jumping to the code to be executed; the first register is used to save the address of the jump instruction before the jump; reading the starting address from the first register, executing the load instruction according to the starting address, loading the data to be processed associated with the load instruction to a second register, and processing the data to be processed by executing the processing instruction.

[0007] Optionally, when there are multiple processing instructions, and the first data segment includes the data to be processed required by the multiple processing instructions, then: for each processing instruction in the code to be executed, the data to be processed required by the processing instruction is loaded into the second register respectively, and the data to be processed is processed respectively by executing the processing instruction.

[0008] Optionally, the code to be executed may contain multiple first processing instructions corresponding to the same loading instruction, and the data to be processed corresponding to the multiple first processing instructions may be the same.

[0009] Optionally, the code to be executed further includes a transfer instruction corresponding to the load instruction; loading the data to be processed associated with the load instruction into the second register includes: transferring the starting address to a third register for caching by executing the transfer instruction; wherein the third register is a general-purpose register; extracting the starting address from the third register, and loading the data to be processed into the second register by executing the load instruction.

[0010] Optionally, when the number of data to be processed in the first data segment is one; loading the data to be processed associated with the loading instruction into the second register includes: loading the data to be processed required by the processing instruction into the second register by executing the loading instruction corresponding to the processing instruction; wherein, the source address of the loading instruction includes the starting address and offset in the first register, and the offset is zero.

[0011] Optionally, when there are multiple data to be processed in the first data segment; loading the data to be processed associated with the loading instruction into the second register includes: loading the data to be processed required by the processing instruction into the second register by executing the loading instruction corresponding to the processing instruction; wherein, the source address of the loading instruction includes the starting address and offset in the first register, and the offset is the offset value of the data to be processed relative to the starting address.

[0012] Secondly, this application provides a data processing apparatus, comprising: an initialization module, configured to initialize a BL jump instruction and use adjacent code following the BL jump instruction as a first data segment; wherein the BL jump instruction is used to jump to the address of the code to be executed in memory; the code to be executed includes a processing instruction and a loading instruction corresponding to the processing instruction; the first data segment includes data to be processed corresponding to the processing instruction; a jump module, configured to execute the BL jump instruction, save the starting address of the first data segment in memory to a first register and jump to the code to be executed; the first register is used to save the address of the BL jump instruction before the jump; and a processing module, configured to read the starting address from the first register, execute the loading instruction according to the starting address, load the data to be processed associated with the loading instruction into a second register, and process the data to be processed by executing the processing instruction.

[0013] Optionally, when there are multiple processing instructions, the first data segment includes the data to be processed required by the multiple processing instructions; the processing module is specifically used to read the starting address from the first register for each processing instruction in the code to be executed, execute the loading instruction according to the starting address, load the data to be processed associated with the loading instruction into the second register, and process the data to be processed by executing the processing instruction.

[0014] Optionally, the code to be executed may contain multiple first processing instructions corresponding to the same loading instruction, and the data to be processed corresponding to the multiple first processing instructions may be the same.

[0015] Optionally, the code to be executed further includes a transfer instruction corresponding to the load instruction; the processing module is specifically used to transfer the starting address to a third register for caching by executing the transfer instruction; wherein the third register is a general-purpose register; the processing module is further used to extract the starting address from the third register and load the data to be processed into the second register by executing the load instruction.

[0016] Optionally, when the number of data to be processed in the first data segment is one, the processing module is specifically used to load the data to be processed required by the processing instruction into the second register by executing the loading instruction corresponding to the processing instruction; wherein, the source address of the loading instruction includes the starting address and offset in the first register, and the offset is zero.

[0017] Thirdly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor.

[0018] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method described above.

[0019] In the data processing method, apparatus, electronic device, and medium provided in this application, by executing a BL jump instruction, the starting address of the adjacent first data segment after the BL jump instruction is saved to a first register, and the execution code is jumped to. Based on the starting address in the first register, the load instruction corresponding to the processing instruction is executed to load the data to be processed in the first data segment required by the processing instruction into a second register. The processing instruction is then executed to process the data to be processed in the second register. This embodiment utilizes the characteristic that the BL jump instruction can save the next address of the current instruction (BL jump instruction) to a specific register, passively saving the starting address of the first data segment after the BL jump instruction to the first register. Therefore, the address corresponding to the data to be processed in the first data segment can be obtained through the starting address. Thus, even if the data storage address to be processed is unknown before executing the BL jump instruction, the loading of the data to be processed can be achieved, thereby enabling the processing of the data to be processed. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with those of this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0021] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the embodiments of this application in any way, but rather to illustrate the concepts of the embodiments of this application to those skilled in the art through reference to specific embodiments.

[0022] Figure 1 A flowchart illustrating a data processing method provided in Embodiment 1 of this application;

[0023] Figure 2 This is a schematic diagram of a data structure according to Embodiment 1 of this application;

[0024] Figure 3 This is a schematic diagram of another data structure in Embodiment 1 of this application;

[0025] Figure 4 This is a schematic diagram of another data structure in Embodiment 1 of this application;

[0026] Figure 5 This is a schematic diagram of another data structure in Embodiment 1 of this application;

[0027] Figure 6 This is a schematic diagram of another data structure in Embodiment 1 of this application;

[0028] Figure 7 This is a schematic diagram of the structure of a data processing device provided in Embodiment 2 of this application;

[0029] Figure 8 This is a schematic diagram of the structure of the electronic device provided in Embodiment 3 of this application.

[0030] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0032] Data processing is the core of computer operation, and typically includes: the CPU loading the data to be processed from memory into the target register, and the CPU's arithmetic unit executing the corresponding processing instructions to process the data in the target register.

[0033] In related technologies, when loading data to be processed, it is necessary to obtain the storage address of the data to be processed in the memory, load the data to be processed into the target register according to the storage address, and then process the data to be processed in the target register.

[0034] However, in some scenarios, the storage address of the data to be processed is unknown, making it impossible to load the data and thus impossible to process it. The technical solutions of this application are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. In the description of this application, unless otherwise expressly specified and limited, the terms should be broadly understood within the art. The embodiments of this application will now be described with reference to the accompanying drawings.

[0035] Example 1

[0036] Figure 1 This is a flowchart illustrating a data processing method provided in Embodiment 1 of this application, as shown below. Figure 1 As shown, the data processing method provided in this embodiment includes:

[0037] S101: Initialize the BL jump instruction, and use the adjacent code after the BL jump instruction as the first data segment; wherein, the BL jump instruction is used to jump to the address in memory of the code to be executed; the code to be executed includes a processing instruction and a load instruction corresponding to the processing instruction; the first data segment includes the data to be processed corresponding to the processing instruction;

[0038] S102: Execute the BL jump instruction, save the starting address of the first data segment in memory to the first register and jump to the code to be executed; the first register is used to save the address of the BL jump instruction before the jump;

[0039] S103: Read the starting address from the first register, execute the load instruction according to the starting address, load the data to be processed corresponding to the load instruction into the second register, and process the data to be processed by executing the processing instruction.

[0040] Branch with Link (BL) jump instructions are jump instructions with a return function, used in program call scenarios. During program execution, before jumping, the BL jump instruction saves the address of the next instruction to the current instruction in a specific register, and then jumps to the jump address and executes from there. In practice, the CPU's Program Counter (PC) register stores the address of the currently executing instruction; therefore, when the BL jump instruction is being executed, its address is stored in the PC register. Before jumping, the BL jump instruction stores the address PC+4 (the BL jump instruction occupies 4 bytes) in a specific register. When returning, the address (PC+4) in the specific register can be directly assigned to the PC register, allowing the program to return to the original program and continue execution. This achieves the return from the jump address to the instruction following the BL jump instruction.

[0041] In this embodiment, after configuring the runtime environment and initializing the development tools, the code adjacent to the BL jump instruction is the first data segment, which includes the data to be processed. Before jumping, the BL jump instruction stores the starting address of the adjacent first data segment (equivalent to the address of the next instruction) in the first register. Since the first data segment contains the data to be processed, and these data are interconnected, knowing the starting address of the first data segment is sufficient to obtain the address of the data to be processed. After storing the starting address of the first data segment, the BL jump instruction jumps to the code to be executed and continues execution from there. Thus, the BL jump instruction effectively obtains the address of the data to be processed, enabling subsequent loading instructions to load the data.

[0042] In this embodiment, a BL jump instruction, a first data segment, and a piece of code to be executed constitute a data structure. The jump process of the BL jump instruction will be illustrated below using this data structure as an example: Figure 2 This is a schematic diagram of a data structure provided in Embodiment 1 of this application, as shown below. Figure 2 As shown, a first data segment 22 is set after the BL jump instruction 21. The BL jump instruction includes a flag instr, and a flag instr is also set at the code to be executed 23. The flag instr is used to indicate the jump address of the BL jump instruction. That is, when the BL jump instruction 21 is executed, according to the flag instr, the execution jumps to the code to be executed 23, and then the subsequent instructions are executed.

[0043] In this embodiment, the first register is a specific register that stores the address according to the BL jump instruction; for example, the first register is the Return Address (Ra). The code to be executed includes processing instructions and corresponding load instructions. The processing instructions can be arithmetic instructions; for example, addition or subtraction instructions. The load instructions are used to load the data to be processed from the source address to the target address for processing by the processing instructions. The number of load instructions is related to the number of data items to be processed required by the processing instructions. For example, if a processing instruction requires 3 data items to be processed, then the corresponding number of load instructions is also 3.

[0044] It is understood that in this embodiment, the BL jump instruction is used to save the next address of the current instruction to a specific register, thereby passively saving the starting address of the first data segment to the first register. The starting address of the first data segment can be obtained with just one BL jump instruction. The address of the data to be processed in the first data segment is related to the starting address; that is, the address of the data to be processed can be obtained through the starting address.

[0045] Subsequently, based on the starting address in the first register, the load instruction corresponding to the processing instruction is executed to load the data to be processed into the second register. The second register is a general-purpose register; for example, registers r12-r20. Then, the processing instruction is executed to process the data in the second register, thus completing the processing of the data.

[0046] It should be noted that a data structure may contain multiple processing instructions within the code to be executed, in which case one BL jump instruction corresponds to multiple processing instructions. Alternatively, the code to be executed may contain only one processing instruction, in which case one BL jump instruction corresponds to one instruction to be processed. The following will provide an illustrative explanation of S103 combining these two cases.

[0047] In one example, when the number of processing instructions is multiple, S103 includes:

[0048] For each processing instruction in the code to be executed, the starting address is read from the first register, the loading instruction is executed according to the starting address, the data to be processed associated with the loading instruction is loaded into the second register, and the data to be processed is processed by executing the processing instruction.

[0049] In this example, a data structure contains multiple processing instructions. For each instruction, based on the starting address in the first memory, the required data is loaded into the second register using a corresponding load instruction. Each instruction may require one or more data items. The data required by different instructions may be the same or different. In some examples, the required data differs between instructions; in this case, each instruction corresponds to a different load instruction. By executing the corresponding load instruction, the data is loaded into the second register. Then, by executing the corresponding processing instruction, the data in the second register is processed.

[0050] The following will illustrate this solution with examples from real-world scenarios: For instance... Figure 2 As shown, the data structure includes a BL jump instruction 21, a first data segment 22, and code to be executed 23. The code to be executed 23 includes two processing instructions: an addition instruction 233, associated with the data to be processed in the first data segment 22 (data1 and data2), and the corresponding loading instructions are the first loading instruction 231 and the second loading instruction 232. The other processing instruction is a subtraction instruction 236, associated with the data to be processed in the first data segment 22 (data3 and data4), and the corresponding loading instructions are the third loading instruction 234 and the fourth loading instruction 235. In the first data segment 22, data1, data2, data3, and data4 are placed consecutively, each data byte being 4 bytes and occupying 4 consecutive addresses. It can be understood that the starting address of the first data segment is the address of data1; adding 4 to the starting address gives the address of data2; adding 8 to the starting address gives the address of data3; and adding 12 to the starting address gives the address of data4.

[0051] The specific execution process is as follows: Execute the BL jump instruction 21 to save the starting address of the adjacent code, i.e., the first data segment 22, to the Ra register. Then, jump to the instr register according to the flag. Based on the starting address in Ra, load data1 corresponding to the starting address into the r13 register using the first load instruction 231. Similarly, load data2 into the r14 register using the second load instruction 232. Execute the addition instruction 233 to sum data1 in r14 and data2 in r13, and store the result in the r4 register. Then, load data3 into the r13 register using the third load instruction 234, and load data4 into the r15 register using the fourth load instruction 235. Execute the subtraction instruction 236 to calculate the difference between data8 in r13 and data4 in r15, and store the result in the r5 register.

[0052] In this example, the code to be executed includes multiple processing instructions, and each processing instruction corresponds to a BL jump instruction, which reduces the number of times the BL jump instruction is executed, thereby improving the efficiency of data processing.

[0053] Based on the above, in one example, the code to be executed contains multiple first processing instructions corresponding to the same loading instruction, and the multiple first processing instructions require the same data to be processed.

[0054] In this example, multiple first processing instructions require the same data to be processed, and these multiple first processing instructions correspond to the same load instruction. It can be understood that when multiple first processing instructions require the same data to be processed, only one load instruction needs to be executed, instead of executing the same load instruction before each first processing instruction.

[0055] It's worth noting that the data to be processed for the first processing instruction can be one or more. In this example, the term "same load instruction" doesn't mean there's only one load instruction, but rather that the same load instruction can be executed only once.

[0056] As an example, Figure 3 This is a schematic diagram of another data structure in Embodiment 1 of this application, as shown below. Figure 3As shown, the data structure includes a BL jump instruction 31, a first data segment 32, and code to be executed 33. The code to be executed 33 includes two first processing instructions: an addition instruction 333 and a subtraction instruction 334, both associated with data1 and data2. The addition instruction 333 and the subtraction instruction 334 each correspond to the first load instruction 331 and the second load instruction 332. Non-addition instructions 333 and 334 correspond to their respective load instructions. Thus, after executing the BL jump instruction, only the first load instruction 331 and the second load instruction 332 are executed once to load the associated data of the addition instruction 333 and the subtraction instruction 334.

[0057] In this example, when multiple first processing instructions require the same data to be processed, the multiple first processing instructions are assigned to the same loading instruction, which reduces the number of loading instructions and thus improves the efficiency of data processing.

[0058] In another example, the number of processing instructions is one, and the first data segment includes the data to be processed required by that one processing instruction.

[0059] In this example, a data structure contains only one processing instruction, but this does not mean that the entire program involves only one processing instruction. It can be understood that when the entire program includes multiple processing instructions, it corresponds to multiple data structures. The first data segment instruction of each data structure contains only the data to be processed required by one processing instruction, which can require one or more pieces of data. The number of loaded instructions corresponds to the number of pieces of data to be processed.

[0060] The following will further illustrate this example with a real-world scenario:

[0061] Figure 4 This is a schematic diagram of another data structure in Embodiment 1 of this application, as shown below. Figure 4 As shown. The data structure includes a BL jump instruction 41, a first data segment 42, and code to be executed 43. The code to be executed 43 includes an addition instruction 433. The data to be processed associated with the addition instruction 433 are data1 and data2 in the first data segment 42, where data1 and data2 are placed consecutively, each data byte is 4 bytes, and occupies 4 consecutive addresses. The loading instructions corresponding to the addition instruction 433 are the first loading instruction 431 and the second loading instruction 432.

[0062] The specific execution process is as follows: The BL jump instruction 41 is executed, automatically saving the starting address of the first data segment 42 to the Ra register. Then, a jump to the instr address is executed, followed by the first load instruction 431. Based on the starting address in the Ra register, data1 is loaded into the r13 register. Similarly, the first load instruction 431 is executed, and based on the starting address in the Ra register, data2 is loaded into the r14 register. The addition instruction 433 is then executed, summing data1 in r14 and data2 in r13, and storing the sum in the r4 register. This completes the processing of data1 and data2.

[0063] In a scenario where a processing instruction is associated with a large amount of unprocessed data, if the data structure includes multiple such instructions, it may correspond to even more unprocessed data, potentially exceeding the jump range of the Black-Blank (BL) jump instruction. Therefore, in this example, the number of processing instructions in the code to be executed is one, and the first data segment includes the unprocessed data associated with one processing instruction. This avoids the risk of excessive unprocessed data exceeding the jump range of the BL jump instruction, thereby ensuring effective data processing.

[0064] In the example above where there are one or more instructions to be processed, the data to be processed in the first data segment can be one or more. The following will provide an exemplary description of the specific loading process of the data to be processed in S103 for a scenario where there are one or more data to be processed in the first data segment.

[0065] In one example, when the number of data to be processed in the first data segment is one, step S103 includes:

[0066] By executing the load instruction corresponding to the processing instruction, the data to be processed required by the processing instruction is loaded into the second register; wherein, the source address of the load instruction includes the starting address and offset in the first register, and the offset is zero.

[0067] In practical applications, the load instruction includes a source address and a target address. During execution, the load instruction loads the data to be processed from the source address to the target address. In this example, the source address includes the starting address of the first data segment and an offset, where the offset is zero. It can be understood that in this example, the first data segment contains only one piece of data to be processed, and the starting address of the first data segment is the address of the data to be processed in memory.

[0068] It's worth noting that when a data structure contains multiple processing instructions, and the first data segment contains a single piece of data to be processed, then the multiple processing instructions correspond to the same piece of data to be processed. For example, Figure 5 This is a schematic diagram of another data structure in Embodiment 1 of this application, as shown below. Figure 5 As shown. The data structure includes a BL jump instruction 51, a first data segment 52, and code to be executed 53. The code to be executed 53 includes an addition instruction 532 and a multiplication instruction 533, where the data associated with the addition instruction 532 and the multiplication instruction 533 is data1, corresponding to a load instruction 531.

[0069] The specific execution process is as follows: After executing the BL jump instruction 51, the starting address of the first data segment 52 is automatically saved to the Ra register, and the process jumps to the load instruction 531. Since the first data segment 52 only contains data1, there is no need to obtain the offset (which is always zero). The starting address of the first data segment 52 is the address of data1. Therefore, the source address of the load instruction 531 includes the starting address in Ra and 0 (offset), and the target address is r13. The load instruction 531 loads data1 into r13. Then, the addition instruction 532 adds data1 in r13 and stores the sum in the r4 register. Finally, the multiplication instruction 533 adds data1 in r13 and stores the product in the r5 register to process the data to be processed.

[0070] In this example, the number of data items to be processed in the first data segment is one. The source address in the load instruction includes the starting address and an offset with a value of zero. During the loading process, there is no need to obtain the offset separately. The data to be processed can be loaded directly based on the starting address, thereby improving the loading efficiency of the data to be processed.

[0071] In another example, when there are multiple data items to be processed in the first data segment, then S103 includes:

[0072] By executing the load instruction corresponding to the processing instruction, the data to be processed required by the processing instruction is loaded into the second register; wherein, the source address of the load instruction includes the starting address and offset in the first register, and the offset is the offset value of the data to be processed relative to the starting address.

[0073] In this example, there are multiple data to be processed in the first data segment. During the loading process, the loading instruction loads the data to be processed associated with the processing instruction into the second register according to the source address. The source address includes the starting address and offset in the first register. The offset is the offset value of the data to be processed relative to the starting address.

[0074] It's worth noting that this example can be applied to scenarios where the data structure includes multiple processing instructions. This means that the multiple data items required by these instructions are all located in the first data segment, and all the data items are loaded from the same starting address. Of course, this example can also be applied to scenarios where the data structure includes only one processing instruction, in which case the instruction requires multiple data items.

[0075] In both scenarios described above, the loading method for the data to be processed is the same. The following example illustrates this solution using a scenario where the data structure includes multiple processing instructions.

[0076] like Figure 2 As shown, the data structure includes a BL jump instruction 21, a first data segment 22, and code to be executed 23. The code to be executed 23 includes an addition instruction 233 and a subtraction instruction 236. The first data segment 22 includes data1, data2, data3, and data4 associated with the addition and subtraction instructions 233 and 236. Each piece of data to be processed consists of 4 bytes and is stored contiguously. It can be understood that the offset of data1 relative to the starting address is zero, the offset of data2 relative to the starting address is 4, the offset of data3 relative to the starting address is 8, and the offset of data4 relative to the starting address is 12.

[0077] The specific execution process is as follows: After executing the BL jump instruction 21, the starting address of the first data segment 22 is automatically saved to the Ra register. The source address of the first load instruction 231 includes the starting address in Ra and 0 (offset), and the target address is r13. The first load instruction 231 loads data1 into r13. The source address of the second load instruction 232 includes the starting address in Ra and 4 (offset), and the target address is r14. The second load instruction 232 then loads data2 into the r14 register, and the addition instruction 233 sums the data1 in r13 and the data2 in r14, storing the result in the r4 register, which is the second register.

[0078] Similarly, the source address of the third load instruction 234 includes the starting address and offset 8 in Ra, and the target address is r13. The third load instruction 234 loads data3 into register r13, overwriting any previously stored data in r13. The source address of the fourth load instruction 235 includes the starting address and offset 12 in Ra, and the target address is r15. The fourth load instruction 235 loads data4 into register r15. The subtraction instruction 236 calculates the difference between the sum of data1 in R13 and data2 in r15, and stores the result in register r5. This completes the data processing for data1, data2, data3, and data4.

[0079] In this example, there are multiple pieces of data to be processed in the first data segment. For each piece of data, based on the same starting address and corresponding offset, it is loaded into the corresponding second register using the corresponding load instruction. Since there are multiple pieces of data to be processed in the first data segment, all corresponding to the same starting address, only one BL jump instruction is needed to load the corresponding data, thereby improving the processing efficiency of the data.

[0080] Based on any of the above examples, in one example, the code to be executed further includes a transfer instruction corresponding to the load instruction; in S103, loading the data to be processed associated with the load instruction into the second register includes:

[0081] By executing the transfer instruction, the starting address is transferred to a third register for caching; wherein, the third register is a general-purpose register;

[0082] The starting address is extracted from the third register, and the data to be processed is loaded into the second register by executing the load instruction.

[0083] In this example, after executing the BL jump instruction and saving the starting address of the first data segment to the first register, the first register is a special register that is difficult to replace if damaged, thus affecting data processing. However, the first register is easily damaged during multiple reads. Therefore, the code to be executed in this example also includes a jump instruction, which transfers the starting address in the first register to the third register. The third register is a general-purpose register and is replaceable.

[0084] Subsequently, based on the starting address in the third register, a load instruction is executed to load the data to be processed into the second register. It can be understood that this example uses a transfer instruction to move the starting address of the first register to the third register. Thus, in scenarios where there are multiple data items to be processed in the first data segment, when loading data through multiple load instructions, the third register can be read directly without reading the first register, thereby significantly reducing the number of times the first memory is used and minimizing the risk of damage to it. The second register is a general-purpose register, and even if damaged, it can be replaced.

[0085] The following will provide an example of this solution in a specific scenario: Figure 6 This is a schematic diagram of another data structure in Embodiment 1 of this application, as shown below. Figure 6 As shown, the data structure includes a BL jump instruction 61, a first data segment 62, and code to be executed 63. The code to be executed 63 includes a transfer instruction 631, a load instruction 632, and an addition instruction 633.

[0086] The specific execution process is as follows: After executing the BL jump instruction 61, the starting address of the data to be processed in the first data segment 62 is automatically stored in the Ra register, and a jump to the branch instruction 631 is initiated based on the flag instr. The branch instruction 631 transfers the starting address in the Ra register to the r12 register. Subsequently, based on the starting address in the r12 register, the load instruction 632 loads data2 from the source address r12,4 (offset) into the r13 register. Then, the addition instruction 633 performs an addition operation on data2, thus completing the processing of the data to be processed.

[0087] In this example, a jump instruction is used to transfer the starting address in a specific first register to a general-purpose third register. Subsequently, the starting address in the third register is read to load the data to be processed, which reduces the number of times the first register is used, thereby reducing the risk of damage to the first register.

[0088] In the data processing method provided in this application, by executing the BL jump instruction, the starting address of the adjacent first data segment after the BL jump instruction is saved to the first register, and the execution code is jumped to. Based on the starting address in the first register, the load instruction corresponding to the processing instruction is executed to load the data to be processed in the first data segment required by the processing instruction into the second register. Then, the processing instruction is executed to process the data to be processed in the second register. This embodiment utilizes the characteristic of the BL jump instruction that it can save the next address of the current instruction (BL jump instruction) to a specific register. The starting address of the first data segment after the BL jump instruction is passively saved to the first register, and thus the address corresponding to the data to be processed in the first data segment can be obtained through the starting address. In this way, even if the data storage address to be processed is unknown before executing the BL jump instruction, the loading of the data to be processed can be achieved, thereby realizing the processing of the data to be processed.

[0089] Example 2

[0090] Figure 7 This is a schematic diagram of the structure of a data processing device provided in Embodiment 2 of this application, as shown below. Figure 7 As shown, the data processing apparatus provided in this embodiment includes:

[0091] Initialization module 71 is used to initialize the BL jump instruction and take the adjacent code after the BL jump instruction as the first data segment; wherein, the BL jump instruction is used to jump to the address in memory of the code to be executed; the code to be executed includes a processing instruction and a load instruction corresponding to the processing instruction; the first data segment includes the data to be processed corresponding to the processing instruction;

[0092] Jump module 72 is used to execute the BL jump instruction, save the starting address of the first data segment in memory to the first register and jump to the code to be executed; the first register is used to save the address of the BL jump instruction before the jump;

[0093] The processing module 73 is configured to read the starting address from the first register, execute the load instruction according to the starting address, load the data to be processed corresponding to the load instruction into the second register, and process the data to be processed by executing the processing instruction.

[0094] Branch with Link (BL) jump instructions are jump instructions with a return function, used in program call scenarios. During program execution, before jumping, the BL jump instruction saves the address of the next instruction to the current instruction in a specific register, and then jumps to the jump address and executes from there. In practice, the CPU's Program Counter (PC) register stores the address of the currently executing instruction; therefore, when the BL jump instruction is being executed, its address is stored in the PC register. Before jumping, the BL jump instruction stores the address PC+4 (the BL jump instruction occupies 4 bytes) in a specific register. When returning, the address (PC+4) in the specific register can be directly assigned to the PC register, allowing the program to return to the original program and continue execution. This achieves the return from the jump address to the instruction following the BL jump instruction.

[0095] In this embodiment, the initialization module 71 initializes the BL jump instruction. The adjacent code after the BL jump instruction is the first data segment, which includes the data to be processed. Thus, before the jump, the BL jump instruction stores the starting address of the adjacent first data segment (equivalent to the address of the next instruction) in the first register. Since the first data segment includes the data to be processed, and these data are related, the address of the data to be processed can be obtained given the starting address of the first data segment.

[0096] After saving the starting address of the first data segment, the BL jump instruction jumps to the code to be executed and continues execution from there. In this way, the BL jump instruction is equivalent to obtaining the address of the data to be processed, enabling subsequent loading of the data using load instructions. In this embodiment, a BL jump instruction, a first data segment, and a piece of code to be executed constitute a data structure.

[0097] In this embodiment, the first register is a specific register that stores the address according to the BL jump instruction; for example, the first register is the Return Address (Ra). The code to be executed includes processing instructions and corresponding load instructions. The processing instructions can be arithmetic instructions; for example, addition or subtraction instructions. The load instructions are used to load the data to be processed from the source address to the target address for processing by the processing instructions. The number of load instructions is related to the number of data items to be processed required by the processing instructions. For example, if a processing instruction requires 3 data items to be processed, then the corresponding number of load instructions is also 3.

[0098] It is understandable that this embodiment utilizes the characteristic of the BL jump instruction to save the next address of the current instruction to a specific register, thus passively saving the starting address of the first data segment to the first register. The starting address of the first data segment can be obtained with just one BL jump instruction. The address of the data to be processed in the first data segment is related to the starting address; that is, the address of the data to be processed can be obtained through the starting address.

[0099] The subsequent processing module 73 loads the data to be processed required by the processing instruction into the second register by executing the load instruction corresponding to the processing instruction, based on the starting address in the first register. The second register is a general-purpose register; for example, it is registers r12-r20. Then, by executing the processing instruction, the data to be processed in the second register is processed, thus completing the processing of the data.

[0100] It should be noted that a data structure may contain multiple processing instructions within the code to be executed, in which case one BL jump instruction corresponds to multiple processing instructions. Alternatively, the code to be executed may contain only one processing instruction, in which case one BL jump instruction corresponds to one instruction to be processed. The following will provide an exemplary description of the processing module 73 combining these two scenarios.

[0101] In one example, when the number of processing instructions is multiple,

[0102] The processing module 73 is specifically used to read the starting address from the first register for each processing instruction in the code to be executed, execute the loading instruction according to the starting address, load the data to be processed associated with the loading instruction into the second register, and process the data to be processed by executing the processing instruction.

[0103] In this example, a data structure contains multiple processing instructions. For each processing instruction, the processing module 73 loads the data to be processed required by the processing instruction into the second register according to the starting address in the first memory and through the corresponding load instruction. Each processing instruction may require one or more data items to be processed. The data required by different processing instructions may be the same or different.

[0104] In some examples, the data to be processed differs between processing instructions. In such cases, each processing instruction corresponds to a different load instruction. By executing the corresponding load instruction, the data to be processed is loaded into the second register. Then, by executing the processing instruction, the data in the second register is processed.

[0105] In this example, the code to be executed includes multiple processing instructions, and each processing instruction corresponds to a BL jump instruction, which reduces the number of times the BL jump instruction is executed, thereby improving the efficiency of data processing.

[0106] Based on the above, in one example, the code to be executed contains multiple first processing instructions corresponding to the same loading instruction, and the multiple first processing instructions require the same data to be processed.

[0107] In this scenario, multiple first processing instructions require the same data to be processed, and these multiple first processing instructions correspond to the same load instruction. It can be understood that when multiple first processing instructions require the same data to be processed, only one load instruction needs to be executed, instead of executing the same load instruction before each first processing instruction.

[0108] It's worth noting that the data to be processed for the first processing instruction can be one or more. In this example, the term "same load instruction" doesn't mean there's only one load instruction, but rather that the same load instruction can be executed only once.

[0109] In this example, when multiple first processing instructions require the same data to be processed, the multiple first processing instructions are assigned to the same loading instruction, which reduces the number of loading instructions and thus improves the efficiency of data processing.

[0110] In another example, the number of processing instructions is one, and the first data segment includes the data to be processed required by that one processing instruction.

[0111] In this example, a data structure contains only one processing instruction, but this does not mean that the entire program involves only one processing instruction. It can be understood that when the entire program includes multiple processing instructions, it corresponds to multiple data structures. The first data segment of each data structure contains only the data to be processed required by one processing instruction. This data can contain one or more data items. The number of loaded instructions corresponds to the number of data items to be processed.

[0112] In a scenario where a processing instruction is associated with a large amount of unprocessed data, if the data structure includes multiple such instructions, it may correspond to even more unprocessed data, potentially exceeding the jump range of the Black-Blank (BL) jump instruction. Therefore, in this example, the number of processing instructions in the code to be executed is one, and the first data segment includes the unprocessed data associated with one processing instruction. This avoids the risk of excessive unprocessed data exceeding the jump range of the BL jump instruction, thereby ensuring effective data processing.

[0113] In the example above where there are one or more instructions to be processed, the data to be processed in the first data segment can be one or more. The processing module 73 will be described below as an example for scenarios where there are one or more data to be processed in the first data segment.

[0114] In one example, when the number of data to be processed in the first data segment is one, the processing module 73 is specifically used to load the data to be processed required by the processing instruction into the second register by executing the loading instruction corresponding to the processing instruction; wherein, the source address of the loading instruction includes the starting address and offset in the first register, and the offset is zero.

[0115] In practical applications, the load instruction includes a source address and a target address. During execution, the load instruction loads the data to be processed from the source address to the target address. In this example, the source address includes the starting address of the first data segment and an offset, where the offset is zero. It can be understood that in this example, the first data segment contains only one piece of data to be processed, and the starting address of the first data segment is the address of the data to be processed in memory.

[0116] In this example, the number of data items to be processed in the first data segment is one. The source address in the load instruction includes the starting address and an offset with a value of zero. During the loading process, there is no need to obtain the offset separately. The data to be processed can be loaded directly based on the starting address, thereby improving the loading efficiency of the data to be processed.

[0117] In another example, when there are multiple data to be processed in the first data segment, the processing module 73 is specifically used to load the data to be processed required by the processing instruction into the second register by executing the loading instruction corresponding to the processing instruction; wherein, the source address of the loading instruction includes the starting address and offset in the first register, and the offset is the offset value of the data to be processed relative to the starting address.

[0118] In this example, there are multiple data to be processed in the first data segment. During the loading process, the processing module 73 loads the data to be processed associated with the processing instruction into the second register according to the source address. The source address includes the starting address and offset in the first register. The offset is the offset value of the data to be processed relative to the starting address.

[0119] It's worth noting that this example can be applied to scenarios where the data structure includes multiple processing instructions. This means that the multiple data items required by these instructions are all located in the first data segment, and all the data items are loaded from the same starting address. Of course, this example can also be applied to scenarios where the data structure includes only one processing instruction, in which case the instruction requires multiple data items.

[0120] In this example, there are multiple pieces of data to be processed in the first data segment. For each piece of data, based on the same starting address and corresponding offset, it is loaded into the corresponding second register using the corresponding load instruction. Since there are multiple pieces of data to be processed in the first data segment, all corresponding to the same starting address, only one BL jump instruction is needed to load the corresponding data, thereby improving the processing efficiency of the data.

[0121] Based on any of the above examples, in one example,

[0122] Processing module 73 is specifically used to execute the transfer instruction to transfer the starting address to a third register for caching; wherein, the third register is a general-purpose register;

[0123] The processing module 73 is further configured to extract the starting address from the third register and load the data to be processed into the second register by executing the load instruction.

[0124] In this example, after executing the BL jump instruction, the jump module 72 saves the starting address of the first data segment to the first register. Since the first register is a special register, it is difficult to replace if damaged, thus affecting data processing. However, the first register is easily damaged during multiple reads. Therefore, the code to be executed in this example also includes a transfer instruction, which transfers the starting address in the first register to the third register. The third register is a general-purpose register and is replaceable.

[0125] Subsequently, processing module 73 loads the data to be processed into the second register by executing a load instruction based on the starting address in the third register. It can be understood that this example uses a transfer instruction to move the starting address of the first register to the third register. Thus, in scenarios where there are multiple data items to be processed in the first data segment, when loading data through multiple load instructions, the third register can be read directly without reading the first register, thereby greatly reducing the number of times the first memory is used and minimizing the risk of damage to the first register. The second register is a general-purpose register, and even if damaged, it can be replaced.

[0126] In this example, the processing module 73 uses a transfer instruction to transfer the starting address in a specific first register to a general-purpose third register. Subsequently, by reading the starting address in the third register, the data to be processed is loaded, which reduces the number of times the first register is used, thereby reducing the risk of damage to the first register.

[0127] In the data processing apparatus provided in this application, the jump module executes the BL jump instruction, saves the starting address of the adjacent first data segment after the BL jump instruction to the first register, and jumps to the execution code. The processing module, based on the starting address in the first register, executes the load instruction corresponding to the processing instruction to load the data to be processed from the first data segment required by the processing instruction into the second register, and processes the data to be processed in the second register by executing the processing instruction. This embodiment utilizes the characteristic that the BL jump instruction can save the next address of the current instruction (BL jump instruction) to a specific register, passively saving the starting address of the first data segment after the BL jump instruction to the first register. Therefore, the address corresponding to the data to be processed in the first data segment can be obtained through the starting address. Thus, even if the data storage address to be processed is unknown before executing the BL jump instruction, the loading of the data to be processed can still be achieved, thereby enabling the processing of the data to be processed.

[0128] Example 3

[0129] Figure 8 This is a schematic diagram of the structure of the electronic device provided in Embodiment 3 of this application, as shown below. Figure 8 As shown, the electronic device includes:

[0130] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can invoke logical instructions stored in the memory 292 to execute the methods of the above embodiments.

[0131] Furthermore, the logic instructions in the aforementioned memory 292 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0132] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, thereby implementing the methods in the above-described method embodiments.

[0133] The memory 292 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 292 may include high-speed random access memory and may also include non-volatile memory.

[0134] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods described in any of the embodiments.

[0135] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0136] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A data processing method, characterized in that, include: The BL jump instruction is initialized, and the adjacent code following the BL jump instruction is used as the first data segment; wherein, the BL jump instruction is used to jump to the address in memory of the code to be executed; the code to be executed includes processing instructions and load instructions corresponding to the processing instructions; the first data segment includes the data to be processed corresponding to the processing instructions; Execute the BL jump instruction to save the starting address of the first data segment in memory to the first register and jump to the code to be executed; the starting address is the address of the next instruction after the BL jump instruction, and the first register is used to save the address of the BL jump instruction before the jump; The starting address is read from the first register, the loading instruction is executed according to the starting address, the data to be processed associated with the loading instruction is loaded into the second register, and the data to be processed is processed by executing the processing instruction.

2. The method according to claim 1, characterized in that, When the number of processing instructions is multiple, and the first data segment includes the data to be processed required by the multiple processing instructions, then the method further includes: For each processing instruction in the code to be executed, the starting address is read from the first register, the loading instruction is executed according to the starting address, the data to be processed associated with the loading instruction is loaded into the second register, and the data to be processed is processed by executing the processing instruction.

3. The method according to claim 2, characterized in that, The code to be executed contains multiple first processing instructions that correspond to the same loading instruction, and the data to be processed corresponding to the multiple first processing instructions is the same.

4. The method according to claim 1, characterized in that, The code to be executed also includes a transfer instruction corresponding to the load instruction; loading the data to be processed associated with the load instruction into the second register includes: By executing the transfer instruction, the starting address is transferred to a third register for caching; wherein, the third register is a general-purpose register; The starting address is extracted from the third register, and the data to be processed is loaded into the second register by executing the load instruction.

5. The method according to any one of claims 1-4, characterized in that, When the number of data to be processed in the first data segment is one; loading the data to be processed associated with the load instruction into the second register includes: By executing the load instruction corresponding to the processing instruction, the data to be processed required by the processing instruction is loaded into the second register; wherein, the source address of the load instruction includes the starting address and offset in the first register, and the offset is zero.

6. The method according to any one of claims 1-4, characterized in that, When there are multiple pieces of data to be processed in the first data segment; loading the data to be processed associated with the load instruction into the second register includes: By executing the load instruction corresponding to the processing instruction, the data to be processed required by the processing instruction is loaded into the second register; wherein, the source address of the load instruction includes the starting address and offset in the first register, and the offset is the offset value of the data to be processed relative to the starting address.

7. A data processing apparatus, characterized in that, include: An initialization module is used to initialize the BL jump instruction and take the adjacent code after the BL jump instruction as the first data segment; wherein, the BL jump instruction is used to jump to the address in memory of the code to be executed; the code to be executed includes processing instructions and loading instructions corresponding to the processing instructions; the first data segment includes the data to be processed corresponding to the processing instructions; The jump module is used to execute the BL jump instruction, save the starting address of the first data segment in memory to the first register and jump to the code to be executed; the starting address is the address of the next instruction of the BL jump instruction, and the first register is used to save the address of the BL jump instruction before the jump; The processing module is configured to read the starting address from the first register, execute the load instruction according to the starting address, load the data to be processed associated with the load instruction into the second register, and process the data to be processed by executing the processing instruction.

8. The apparatus according to claim 7, characterized in that, When there are multiple processing instructions, the first data segment includes the data to be processed required by the multiple processing instructions; The processing module is specifically configured to read the starting address from the first register for each processing instruction in the code to be executed, execute the loading instruction according to the starting address, load the data to be processed associated with the loading instruction into the second register, and process the data to be processed by executing the processing instruction.

9. The apparatus according to claim 8, characterized in that, The code to be executed contains multiple first processing instructions that correspond to the same loading instruction, and the data to be processed corresponding to the multiple first processing instructions is the same.

10. The apparatus according to claim 7, characterized in that, The code to be executed also includes the transfer instruction corresponding to the load instruction; The processing module is specifically used to execute the transfer instruction to transfer the starting address to a third register for caching; wherein, the third register is a general-purpose register; The processing module is further configured to extract the starting address from the third register and load the data to be processed into the second register by executing the load instruction.

11. The apparatus according to any one of claims 7-10, characterized in that, When the number of data to be processed in the first data segment is one; The processing module is specifically used to load the data to be processed required by the processing instruction into the second register by executing the loading instruction corresponding to the processing instruction; wherein the source address of the loading instruction includes the starting address and offset in the first register, and the offset is zero.

12. The apparatus according to any one of claims 7-10, characterized in that, When there are multiple data items to be processed in the first data segment; The processing module is specifically used to load the data to be processed required by the processing instruction into the second register by executing the loading instruction corresponding to the processing instruction; wherein, the source address of the loading instruction includes the starting address and offset in the first register, and the offset is the offset value of the data to be processed relative to the starting address.

13. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-6.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.

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