A memory SPD information recovery method, device and computing equipment

Abstract

The application discloses a memory SPD information recovery method and device and a computing device, and relates to the technical field of computers.The method comprises the following steps: acquiring serial presence detect (SPD) information of each memory, each memory having identification information for representing the specifications of the memory, and the identification information and the SPD information of the memory of the same specifications being the same; when a fault memory with erroneous SPD information exists, recording first identification information of the fault memory, and determining target identification information from second identification information corresponding to the memory with non-erroneous SPD information, the target identification information being the same as the first identification information of the fault memory; and re-determining target SPD information corresponding to the target identification information as the SPD information of the fault memory. In this way, after the information of the fault memory with the SPD information variation is recovered, the fault memory can still be normally used because the hardware of the memory itself is not faulty, and the normal start of the system is no longer affected, so that the fault tolerance performance of the system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a memory SPD information recovery method and device and a computing device. BACKGROUND

[0002] The memory stick is the most used and the highest value device in the server and other computing devices, and the state of the memory stick is closely related to the system running stability of the computing device. Therefore, the system will monitor the memory stick to find the risk memory in advance and isolate and process it in time to reduce the system downtime risk.

[0003] Generally, in the computing device, the timing parameters of the memory stick are stored through a serial presence detect (SPD) chip, which is a storage chip arranged on the memory stick, and the system will configure the memory by detecting the information in the SPD chip when starting. However, in the use process of the memory stick, the information in the SPD chip may be changed or lost, at this time, the corresponding memory stick will be isolated as a risk memory by the system whether it has a fault or not. In this way, it will adversely affect the system running, and even cause the system to fail to start normally. SUMMARY

[0004] The present application provides a memory SPD information recovery method and device, a computing device, a computer storage medium and a computer program product, which can improve the system fault tolerance.

[0005] In a first aspect, the present application provides a memory SPD information recovery method, which is applied to a computing device including a plurality of memory sticks, and the method includes: acquiring serial presence detect (SPD) information of each memory stick, wherein each memory stick has identification information for representing its specifications, and the identification information and the SPD information of the memory sticks of the same specifications are the same; when there is a fault memory stick with erroneous SPD information in the plurality of memory sticks, recording first identification information of the fault memory stick; determining target identification information from second identification information corresponding to the memory sticks with no erroneous SPD information, the target identification information being the same as the first identification information of the fault memory stick; and re-determining target SPD information corresponding to the target identification information as the SPD information of the fault memory stick.

[0006] The computing device in the embodiment can be a workstation, a server, a super terminal, etc., but is not limited thereto. The internal memory in the computing device is also referred to as a memory (Memory) and is used to support the processor of the computing device to run various programs. In the embodiment, the computing device includes a plurality of memories, and to ensure the stability of the system, the specifications of the memories can be the same, and the memories of the same specification have the same identification information and SPD information.

[0007] In this way, when the SPD information of a certain memory (i.e., a faulty memory) is erroneous, such as being changed or lost, a normal memory (i.e., a memory whose SPD information is not erroneous) of the same specification can be found according to the same identification information, and the SPD information of the normal memory is used as the SPD information of the faulty memory, so that the SPD information of the faulty memory is recovered, and the initialization of the faulty memory can continue. Furthermore, after the information of the memory whose SPD information is changed is recovered, the memory itself is not faulty, and thus can still be normally used, and does not affect the normal start of the system, which is beneficial to improving the fault tolerance performance of the system.

[0008] In some possible implementation manners, when the SPD information of each memory is acquired, the SPD information is acquired in sequence according to the slot order corresponding to the plurality of memory, and when the faulty memory is the n th memory in the slot order, the target identification information is determined from the second identification information corresponding to the memory whose SPD information is not erroneous, including: starting from the (n+1) th memory in the slot order, the target memory whose SPD information is not erroneous is determined in sequence; after each target memory is determined, the second identification information of the target memory is compared with the first identification information of the faulty memory until the second identification information identical to the first identification information of the faulty memory is determined, and the second identification information is determined as the target identification information.

[0009] In this way, after the faulty memory is determined, the target identification information is queried from the remaining normal memories (i.e., memories whose SPD information is not erroneous) after the faulty memory in the slot order, so that the SPD information recovery of the faulty memory can be implemented, and the running efficiency of the memory initialization program is also improved.

[0010] In some possible implementation manners, when the serial presence detect (SPD) information of each memory is acquired, the SPD information is acquired in sequence according to a slot order corresponding to the plurality of memories, and when the faulty memory is the n th memory in the slot order, the target identification information is determined from second identification information corresponding to the memory whose SPD information is correct, including: determining, from the first memory to the n-1 th memory, a target memory whose SPD information is correct; comparing the second identification information of the target memory with the first identification information to obtain second identification information that is the same as the first identification information; and determining the second identification information that is the same as the first identification information as the target identification information.

[0011] In this way, if the slot order of the faulty memory is relatively late, the target identification information can also be queried from the normal memory (i.e., the memory whose SPD information is correct) determined previously, so as to facilitate recovery of the SPD information of the faulty memory.

[0012] In some possible implementation manners, after the serial presence detect (SPD) information of each memory is acquired, the method includes: verifying each piece of SPD information; when SPD information verification fails, reporting corresponding alarm information, the alarm information being used to represent that the SPD information is incorrect, and performing corresponding timing parameter configuration on the memory whose SPD information passes the verification.

[0013] In the implementation manner, the SPD information is used to configure various timing parameters of the memory, and therefore, verification of each piece of acquired SPD information can guarantee the reliability of subsequent configuration of the timing of the memory. When the SPD information of a certain memory fails the verification, an alarm is given in time, and initialization of the memory is temporarily suspended, so as to wait for subsequent recovery of the SPD information of the memory. The SPD information that passes the verification is used to configure the memory, which facilitates the system to reach an optimal running state.

[0014] In a second aspect, the present application provides a memory SPD information recovery apparatus, the apparatus being applied to a computing device, the computing device including a plurality of memories, and the apparatus including: an acquisition module, configured to acquire serial presence detect (SPD) information of each memory, wherein each memory has identification information used to represent a specification of the memory, and the identification information and the SPD information of memories of the same specification are the same; a processing module, configured to, when a faulty memory whose SPD information is incorrect exists in the plurality of memories, record first identification information of the faulty memory; the processing module is further configured to determine target identification information from second identification information corresponding to a memory whose SPD information is correct, the target identification information being the same as the first identification information of the faulty memory; and the processing module is further configured to re-determine target SPD information corresponding to the target identification information as the SPD information of the faulty memory.

[0015] In some possible implementation manners, the serial presence detect (SPD) information of each memory is acquired according to a preset slot order of the plurality of memories, and when the faulty memory is an nth memory in the slot order, the processing apparatus is specifically configured to: start from an (n+1)th memory in the slot order, and sequentially determine a target memory whose SPD information is correct; after determining each target memory, compare second identification information of the target memory with first identification information of the faulty memory until the second identification information identical to the first identification information is found, and determine the second identification information as the target identification information.

[0016] In some possible implementation manners, the plurality of memories correspond to a preset slot order, and when the faulty memory is an nth memory in the slot order, the processing apparatus is specifically configured to: determine, from the first to the (n-1)th memory, a target memory whose SPD information is correct; compare second identification information of the target memory with the first identification information, and obtain the second identification information identical to the first identification information; and determine the second identification information identical to the first identification information as the target identification information.

[0017] In some possible implementation manners, the processing apparatus is further configured to: check each piece of SPD information; when there is SPD information that fails the check, report corresponding alarm information, the alarm information being used to indicate that the SPD information is incorrect; and perform corresponding timing parameter configuration on the memory whose SPD information passes the check.

[0018] In a third aspect, the present application provides a computing device, which includes a plurality of memories, and further includes: at least one memory configured to store a program; and at least one processor configured to execute the program stored in the memory, wherein when the program stored in the memory is executed, the processor is configured to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0019] In a fourth aspect, the present application provides a computer readable storage medium, which stores a computer program, and when the computer program is executed on a processor, the processor is caused to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0020] In a fifth aspect, the present application provides a computer program product, which is characterized by, when the computer program product is executed on a processor, the processor is caused to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0021] In a sixth aspect, the present application provides a chip, characterized by comprising at least one processor and an interface; the at least one processor acquires program instructions or data through the interface; and the at least one processor executes the program instructions to implement the method described in the first aspect or any possible implementation manner of the first aspect.

[0022] It can be understood that the beneficial effects of the second aspect to the sixth aspect described above can be referred to the related description in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 Fig. 1 is a schematic diagram of a hardware structure of a computing device according to an embodiment of the present application;

[0024] Figure 2 Fig. 1 is a schematic diagram of a hardware structure of a computing device according to an embodiment of the present application;

[0025] Figure 3 Fig. 1 is a schematic diagram of a hardware structure of a computing device according to an embodiment of the present application;

[0026] Figure 4 Fig. 1 is a schematic diagram of a hardware structure of a computing device according to an embodiment of the present application;

[0027] Figure 5 Fig. 1 is a schematic diagram of a hardware structure of a computing device according to an embodiment of the present application;

[0028] Figure 6 Fig. 1 is a schematic diagram of a hardware structure of a computing device according to an embodiment of the present application; DETAILED DESCRIPTION

[0029] The term "and / or" in the present document is a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The symbol " / " in the present document represents the relationship of or, for example, A / B represents A or B.

[0030] The terms "first" and "second" and the like in the specification and claims of the present document are used to distinguish different objects, and are not used to describe a specific order of the objects. For example, the first response message and the second response message are used to distinguish different response messages, and are not used to describe a specific order of the response messages.

[0031] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0032] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0033] To facilitate understanding of the technical solutions of this application, the technical terms used in this document are explained below.

[0034] CPU (Central Processing Unit): As the core of a computer system for computation and control, it is the final execution unit for information processing and program execution.

[0035] Memory (RAM): Internal memory (also known as "RAM") is a computer component that the CPU can address and read / write through the bus. All programs in a computer run in RAM, and the operation of RAM determines the stable operation of the computer system. Memory modules are mostly random access memory (RAM).

[0036] SPD (Serial Presence Detection) is a set of configuration information for a memory module, including various key operation timings (such as the latency (CL) of the column address controller before memory read / write operations, the row-to-column addressing delay (tRCD), the precharge time (tRP) of the memory row address controller, and the shortest cycle (tRAS) from row activation to precharge), the number of row / column addresses, and bit width. This SPD information is stored in an SPD chip, which can be an electrically erasable programmable read-only memory (EEPROM).

[0037] BIOS (basic input output system): basic input output system. It is a set of programs fixed to a ROM (read-only memory) chip on the motherboard of a computer, also known as "BIOS firmware", which stores the most important basic input and output programs, self-checking programs after startup, and system startup programs. The main function of BIOS is to provide the lowest and most direct hardware settings and control for the computer.

[0038] In a computing device, the memory stick is a passive device that cannot determine its own state, and the system needs to monitor the memory stick to identify risky memory in advance and isolate it, thereby achieving system protection. However, this protection mechanism still has some drawbacks:

[0039] Generally, when the computing device starts, the CPU will configure the timing parameters of the memory in the memory initialization process by reading the SPD information to achieve the best running state, wherein the SPD information is stored on an SPD chip integrated on the memory stick. And to ensure the reliability of memory configuration, the CPU will first verify the read SPD information. However, the SPD chip itself is a storage device, and the SPD information stored therein may be subject to variation and loss. When the SPD information varies or is lost, the CPU verification of the SPD information will not be consistent with the expected value, and the memory stick corresponding to the slot will be considered as a fault by the system, thereby being alarmed and isolated by the system. However, at this time, the memory stick itself is not actually faulty, and after being isolated, it may still adversely affect the system operation, or even cause the system to stop starting. Therefore, in this case, the memory monitoring and isolation method affects the normal startup of the computer system due to the low fault tolerance of the system.

[0040] In order to improve the fault tolerance performance of the system, the present application provides a memory SPD information recovery method, device and electronic equipment, which mainly recovers the SPD information of the current memory using the SPD information of other memory of the same specification when the SPD information of some memory varies or is lost, thereby avoiding the system from mistakenly isolating the memory stick due to the variation or loss of the SPD information, and affecting the normal startup of the system.

[0041] In order to facilitate the understanding of the technical solutions of the present application, the computing device provided by the embodiments of the present application will be described first.

[0042] Exemplarily, Figure 1 A hardware structure schematic diagram of a computing device is shown. The computing device 100 can be a hardware device capable of providing data processing functions, operation functions, and storage functions, such as a computer, a workstation, a server, or a super terminal, but is not limited thereto. As shown in the figure, Figure 1As shown, the computing device 100 provided by the embodiments of the present application can include a processing system 101, a memory 102, and a communication interface 103, wherein the processing system 101, the memory 102, and the communication interface 103 can be integrated on a mainboard and connected through a bus 110 to complete communication among each other.

[0043] The processing system 101 can include various processing devices, for example, can be a central processing unit (CPU), a system on chip (SOC), a processor integrated on an SOC, a separate processor chip, or a controller, etc. The processing system 101 can also include special-purpose processing devices, for example, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), etc. The processing system 101 can be a processor group composed of multiple processors, and the multiple processors are coupled with each other through one or more buses.

[0044] The memory 102 can be coupled to the processing system 101. Specifically, the memory 102 can be coupled to the processing system 101 via one or more memory controllers. The memory 102 can be used to store computer program instructions, including a computer operating system (OS), BIOS firmware, and various programs. The memory 102 can be a non-volatile memory, such as an embedded multi media card (EMMC), universal flash storage (UFS), or read-only memory (ROM), or other type of static storage device that can store static information and instructions, or a volatile memory, such as a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magneto-optical disk, a magnetic disk storage or other magnetic storage devices, or any other computer readable storage medium that can be used to carry or store program codes in the form of instructions or data structures and that can be accessed by a computer, but not limited to. The memory 102 can exist independently, or the memory 102 can be integrated with the processing system 101.

[0045] In some examples, the memory 102 can include multiple memory banks. For example, referring to Figure 2As shown, in the computing device 100, one CPU 101a can be mounted with multiple memory sticks (1021a, 1021b, …, 1021n), and each memory stick (1021a, 1021b, …, 1021n) is provided with a corresponding SPD chip (1022a, 1022b, …, 1022n). The SPD chip (1022a, 1022b, …, 1022n) stores the SPD information and identification information of the memory stick where the SPD chip is located. The SPD information is data information written by the manufacturer according to the performance characteristics of different specifications of memory sticks. The SPD information of the memory sticks of the same specification is the same. The identification information can include part number (PN) information, serial number (SN) information, etc., but is not limited thereto. The PN information is a combination of numbers or numbers and letters, etc. formulated by the manufacturer of the memory stick for unique identification. The PN information of the memory sticks of the same specification is the same, in other words, the PN information and the SPD information have a one-to-one correspondence.

[0046] In this way, since the CPU 101a can be mounted with multiple memory sticks, when the SPD information of one or several memory sticks is reported as an error, the normal SPD information of other memory sticks with the same identification information can be used to initialize these error memory sticks, thereby ensuring that the entire system is not affected by the variation of the SPD information of part of the memory.

[0047] The communication interface 103 is mainly used to realize the communication between the modules, devices, units and / or equipment in the embodiments of the application.

[0048] The bus 110 includes a bus of one or more communication protocols. Moreover, the bus 110 includes hardware, software, or both, that couples the components of the server 100 to each other. By way of example, and not limitation, the bus 110 can include an accelerated graphics port (AGP) or other graphics bus, an enhanced industry standard architecture (EISA) bus, a front-side bus (FSB), a hyper transport (HT) interconnect, an industry standard architecture (ISA) bus, an infiniband interconnect, a low pin count (LPC) bus, a memory bus, a microchannel architecture (MCA) bus, a peripheral component interconnect (PCI) bus, a PCI-Express (PCIE) bus, a serial advanced technology attachment (SATA) bus, a video electronics standards association local (VLB) bus, or another suitable bus or combination of two or more of these. It should be understood that, although this embodiment describes and shows a particular bus, this application contemplates any suitable bus or interconnect.

[0049] It can be understood that the structure of the embodiment of the present application does not constitute a specific limitation of the server 100. In other embodiments of the present application, the server 100 can include more or fewer components than shown, or combine certain components, or split certain components, or different arrangement of components. The components shown can be implemented in hardware, software or a combination of software and hardware.

[0050] Also, it can be understood that in the present scheme, the exemplary embodiments of the computing device 100 include but are not limited to electronic devices running iOS, android, Windows, Harmony OS or other operating systems. The present scheme does not specifically limit the type of computing device 100.

[0051] Next, based on the above description, a memory SPD information recovery method provided by the embodiments of the present application is introduced. It can be understood that the method is based on the above description, and part or all of the contents in the method can be referred to the description above.

[0052] Please refer to Figure 3 , Figure 3 is a flowchart of a memory SPD information recovery method provided by the embodiments of the present application. It can be understood that the method can be executed by the computing device shown in the above Figure 1 or Figure 2 , or other devices or apparatuses with computing, processing and storage capabilities. As shown in Figure 3 , the memory SPD information recovery method can include S301-S304:

[0053] S301, obtaining serial presence detection SPD information and identification information corresponding to each memory, wherein each memory has identification information for representing its specifications, and the identification information and SPD information of the same specification memory are the same.

[0054] In the present embodiment, in combination with Figure 1 and Figure 2 , when the computing device 100 starts, the processor 101 runs BIOS, and the BIOS automatically reads the SPD information of the memory 1021a-1021n connected to each slot of the motherboard (i.e. memory stick) to perform memory initialization. Wherein the SPD information of each memory stick 1021a-1021n is stored in the SPD chip 1022a-1022n respectively. It can be understood that the SPD information is data information written by the manufacturer according to the performance characteristics of different specifications of memory sticks, and the SPD information of the same specification memory is the same.

[0055] Further, the SPD chips 1022a-1022n also store identification information of the memory sticks 1021a-1021n, such as part number (PN) information, serial number (SN) information, etc. The present example does not list them one by one. The PN information is a combination of numbers or numbers and letters, etc. formulated by the manufacturer of the memory stick to represent a unique identification. The PN information of the memory sticks of the same specification is the same, in other words, the PN information and the SPD information have a one-to-one correspondence.

[0056] For example, continuing to refer to Figure 2 As shown, in order to facilitate stable operation of the computing device 100, the specifications of the plurality of memory sticks 1021a-1021n in the computing device 100 can be the same, for example, all are ECC (error checking and correcting) memory with part number “xx…xx72”. Alternatively, in some specific examples, the specification of at least one of the memory sticks in the computing device 100 is the same as that of any other memory stick. Then, for any one of the memory sticks in the computing device 100, the SPD information of at least one of the memory sticks is the same.

[0057] In the present embodiment, when the BIOS reads the SPD information, it can also read the PN and other identification information of the memory sticks 1021a-1021n. The SPD information is used for memory initialization, and the identification information can be recorded for subsequent query when recovering the SPD information of the memory itself or other memories, which facilitates reducing the complexity of the system execution logic and improving the efficiency.

[0058] In some possible implementations, the BIOS can first read the SPD information for memory initialization, and then read the PN and other identification information of the relevant memory sticks for query when necessary, such as when recovering the SPD information.

[0059] It can be understood that each of the memory sticks in the computing device 100 is initialized separately. The processor 101 can read the SPD information (which can also include the identification information, etc.) of each of the memory sticks in a preset memory slot order for initialization, that is, the processor 101 first reads the SPD information of the first memory stick in the slot order, and after completing the checksum and timing configuration, it reads the SPD information of the next memory stick, checks the checksum and configures the timing, and so on, until all the memory sticks are initialized. In some other examples, the processor 101 can also randomly read the SPD information of each of the memory sticks for initialization.

[0060] For example, in order to ensure the reliability of the subsequent configuration of the memory timing by using the SPD information, referring to Figure 4As shown, after obtaining each SPD information through S301, the following S1 to S2 can also be performed:

[0061] S1, checking each detected SPD information;

[0062] S2, when there is SPD information checking failure, reporting corresponding alarm information, the alarm information is used to represent that the SPD information has error.

[0063] In this embodiment, after the CPU (i.e. the processor) 101a obtains the SPD information of one memory bar in sequence, it can also check each SPD information through the above S1. For example, the cyclic redundancy check (CRC) algorithm can be used for checking, but it is not limited to this.

[0064] For example, the principle of checking SPD information by using the CRC algorithm can be that a check code d1 is generated based on the CRC algorithm for the SPD information in the SPD chip in advance and stored in a fixed position of the SPD chip. During the memory initialization process, after the CPU 101a obtains the SPD information, it also generates a check code d2 based on the CRC algorithm, and then compares d2 and d1. If d2 and d1 are consistent, the checking is passed, and the timing parameter configuration for the SPD information passed by the checking can be continued to be performed on the memory, and the initialization is completed. If d2 and d1 are inconsistent, the checking fails, it can be determined that the SPD information has error (i.e. information content variation or loss), and the alarm information that the SPD information has error is reported through the above S2.

[0065] When a certain SPD information has error after checking, i.e. checking failure, the following S302-S304 can be continued to be performed:

[0066] In S302, when there is a fault memory in which the SPD information has error in all memory, the first identification information of the fault memory is recorded.

[0067] In this embodiment, when it is determined that there is SPD information checking failure after checking, it means that the SPD information has variation or loss error, so the memory corresponding to the SPD information with checking failure will be determined as a fault memory (i.e. a fault memory, which can also be called "error memory"). The CPU 101a will temporarily suspend the initialization of the fault memory, and record the identification information (i.e. the first identification information) representing the specifications of the SPD chip on the fault memory. For example, the identification information can be the PN information of the fault memory.

[0068] S303, determining the target identification information from the second identification information of the memory in which the SPD information checking is successful, the target identification information is the same as the first identification information of the fault memory.

[0069] In this embodiment, after the CPU101a terminates the initialization of the faulty memory where the SPD information is incorrect, it continues to read the SPD information of the next memory module in sequence for initialization. If the SPD information of the memory module after the faulty memory passes the verification, the PN information (i.e., the second identification information) of the memory module that passes the verification is recorded and compared with the PN information of the faulty memory until a target identification information (i.e., the target PN information) that is the same as the PN information of the faulty memory is found.

[0070] For example, combined with Figure 2 As shown, if CPU 101a detects the SPD information d1 of memory module 1021a through the aforementioned S301-S302 and confirms that the SPD information d1 is erroneous, it suspends the initialization configuration of memory module 1021a and records the PN information k1 of the faulty memory module 1021a read from SPD chip 1022a. Next, it continues to read the SPD information d2 and PN information k2 of memory module 1021b through the aforementioned S301, and first verifies the SPD information d2 of memory module 1021b. If the verification passes, it compares the PN information k2 and PN information k1. If k2 and k1 are the same, then the PN information k2 can be used as the target identification information. If k2 and k1 are different, continue reading the SPD information d3 and PN information k3 of memory module 1021c. Similarly, first verify the SPD information d3, and after the verification is passed, compare the PN information k3 and PN information k1. If k3 and k1 are the same, then the PN information k3 can be used as the target identification information.

[0071] Additionally, if an error occurs while verifying the SPD information d2 of memory module 1021b, the SPD information of memory modules 1021c to 1021n is retrieved and verified one by one. Among the memory modules that pass verification, a target PN information that matches the PN information k1 of memory module 1021a and another target PN information that matches the PN information k2 of memory module 1021b are searched. It can be understood that when the SPD information of two or more memory modules is incorrect, the PN information of these erroneous memory modules can be the same.

[0072] In this way, after identifying the faulty memory, querying the target identification information from the remaining normal memory (i.e., memory where the SPD information has not been erroneous) whose slot sequence is after the faulty memory can help restore the SPD information of the faulty memory while ensuring the running efficiency of the memory initialization program.

[0073] In some possible implementation manners, if the slot sequence of the faulty memory is relatively late, for example, the SPD information of the memory bar of the last slot is changed, the PN information of all the memory bars that have passed the SPD information checking can still be read one by one according to the preset slot sequence (or in a random sequence) to match the PN information of the faulty memory, until the target PN information is found.

[0074] In some possible implementation manners, because the probability of memory failure is relatively low, in order to improve the memory initialization efficiency, the corresponding PN information is not recorded during the initialization process of reading the SPD information (at this time, the PN information can be read together with the SPD information but not recorded), and the PN information of the faulty memory is recorded only when the memory bar fails. Then, when initializing the memory bar after the faulty memory, the PN information of each memory bar is also recorded and compared with the PN information of the faulty memory, so as to find the target PN information. If the faulty memory is the last slot memory bar in the current initialization process, the PN information of the memory bar that has passed the checking can be read according to the slot sequence or in a random sequence, so as to find the target PN information by comparison.

[0075] After the target identification information is determined through S303, the following S304 can be performed.

[0076] In S304, the target SPD information corresponding to the target identification information is determined as the SPD information of the faulty memory again, to continue the initialization of the faulty memory.

[0077] In this embodiment, after the target identification information that is consistent with the PN information of the faulty memory is matched, the SPD information of the memory bar corresponding to the target identification information (that is, the target SPD information) can be directly called, and the target SPD information is used as the SPD information of the faulty memory, to recheck and configure the timing parameters of the faulty memory, so as to continue the initialization process, and all the memories work normally, to ensure the normal startup of the system.

[0078] For example, if the SPD information d1 of the memory bar 1021a fails to pass the checking, and the PN information k2 of the memory bar 1021b can be used as the target identification information after comparison, the SPD information d2 of the memory bar 1021b is the target SPD information, that is, the SPD information d2 is used as the SPD information of the memory bar 1021a. Then, the memory bar 1021a can be reinitialized and configured by using the SPD information d2, so that the memory bar 1021a works normally.

[0079] Thus, in the embodiment, in view of the same PN information and SPD information of the memory of the same specification, when it is verified that the SPD information of a certain memory changes or is lost, the PN information (i.e., target PN information) of a normal memory of the same specification as the faulty memory is detected, and the SPD information (i.e., target SPD information) of the normal memory is used as the SPD information of the faulty memory, so as to realize the recovery of the changed SPD information of the faulty memory. Thus, since the memory with abnormal SPD information does not actually have a fault in the hardware itself, the memory can still be normally used after the SPD information is recovered, and thus the system fault tolerance is improved, and the entire system is protected from the influence of the changed SPD information of the partial memory.

[0080] Based on the method in the above embodiment, an embodiment of the present application provides a memory SPD information recovery device. Please refer to Figure 5 , Figure 5 FIG. 1 is a structural schematic diagram of a memory SPD information recovery device provided by an embodiment of the present application.

[0081] As shown in Figure 5 , the memory SPD information recovery device 500 can include an acquisition module 501 and a processing module 502. The acquisition module 501 can be configured to acquire the serial presence detect (SPD) information and identification information of each memory. Each piece of SPD information has corresponding identification information, and the identification information is used to represent the specification of the corresponding memory. The processing module 502 can be configured to, when there is a faulty memory with changed SPD information in a plurality of memories, record the first identification information of the faulty memory, and determine target identification information from the second identification information of the memory with unchanged SPD information, the target identification information being the same as the first identification information of the faulty memory. In addition, the processing module 502 can be further configured to re-determine the target SPD information corresponding to the target identification information as the SPD information of the faulty memory.

[0082] In some embodiments, when the SPD information of each memory is acquired, the SPD information is acquired in sequence according to the slot order corresponding to the plurality of memories. When the faulty memory is the nth memory in the slot order, the processing module 502 is specifically configured to start from the (n+1)th memory in the slot order, sequentially determine the target memory with unchanged SPD information, and compare the second identification information of each target memory with the first identification information of the faulty memory after the target memory is determined, until the second identification information that is the same as the first identification information of the faulty memory is determined, and the second identification information is determined as the target identification information.

[0083] In some possible implementation manners, the plurality of internal memories correspond to a preset slot order, and when the faulty internal memory is an n th slot in the slot order, the processing apparatus 502 is specifically configured to: from the first to the (n-1) th internal memory, determine a target internal memory in which the SPD information does not have an error; compare the second identification information of the target internal memory with the first identification information to obtain second identification information that is the same as the first identification information; and determine the second identification information that is the same as the first identification information as the target identification information.

[0084] In some embodiments, the processing apparatus 502 is further configured to verify each piece of detected SPD information, and when there is SPD information that fails verification, report corresponding alarm information, the alarm information being used to represent that the SPD information has an error. The processing apparatus 502 is further configured to perform corresponding timing parameter configuration on the internal memory in which the SPD information passes verification.

[0085] It should be understood that the apparatus is used to execute the method in the above embodiments, the corresponding program modules in the apparatus have similar implementation principles and technical effects to those described in the above method, and the working process of the apparatus can refer to the corresponding process in the above method, which will not be described here again.

[0086] Based on the method in the above embodiments, an embodiment of the present application provides a computing device. The computing device includes a plurality of internal memories and comprises: at least one memory for storing a program; and at least one processor for executing the program stored in the memory; wherein when the program stored in the memory is executed, the processor is configured to execute the method in the above embodiments.

[0087] Based on the method in the above embodiments, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and when the computer program runs on a processor, the processor executes the method in the above embodiments.

[0088] Based on the method in the above embodiments, an embodiment of the present application provides a computer program product, and when the computer program product runs on a processor, the processor executes the method in the above embodiments.

[0089] Based on the method in the above embodiments, an embodiment of the present application provides an electronic device. The electronic device can include: at least one memory for storing a program; and at least one processor for executing the program stored in the memory; wherein when the program stored in the memory is executed, the processor is configured to execute the method in the above embodiments.

[0090] Based on the method in the above embodiments, an embodiment of the present application further provides a chip. Please refer to Figure 6 , Figure 6 FIG. 1 is a structural schematic diagram of a chip provided by an embodiment of the present application. As shown in FIG. 1, the chip includes a plurality of internal memories and comprises: at least one memory for storing a program; and at least one processor for executing the program stored in the memory; wherein when the program stored in the memory is executed, the processor is configured to execute the method in the above embodiments.Figure 6 As shown in FIG. 6, the chip 600 includes one or more processors 601 and interface circuits 602. Optionally, the chip 600 can also include a bus 603. Among them:

[0091] The processor 601 can be an integrated circuit chip with processing capability. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 601 or the instruction in the form of software. The above processor 601 can be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. Each method and step disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor.

[0092] The interface circuit 602 can be used for sending or receiving data, instructions or information. The processor 601 can process the data, instructions or other information received by the interface circuit 602, and can send the processed information out through the interface circuit 602.

[0093] Optionally, the chip 600 also includes a memory, which can include a read-only memory and a random access memory, and provides operation instructions and data for the processor. Part of the memory can also include a non-volatile random access memory (NVRAM).

[0094] Optionally, the memory stores executable software modules or data structures, and the processor can execute corresponding operations by calling the operation instructions stored in the memory (which can be stored in an operating system).

[0095] Optionally, the interface circuit 602 can be used to output the execution result of the processor 601.

[0096] It should be noted that the functions of the processor 601 and the interface circuit 602 respectively can be realized by hardware design, software design or combination of hardware and software, which is not limited here.

[0097] It should be understood that each step of the above method embodiment can be completed by the logic circuit in the form of hardware or the instruction in the form of software in the processor.

[0098] It can be understood that the size of the serial number of each step in the above-mentioned embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. In addition, in some possible implementations, each step in the above-mentioned embodiments can be selectively executed, partially executed, or fully executed according to actual conditions, which is not limited here.

[0099] It can be understood that the method steps in the embodiments of the present application can be realized by hardware or by the processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC.

[0100] In the above-mentioned embodiments, all or part can be realized by software, hardware, firmware, or any combination thereof. When realized by software, all or part can be realized in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted by the computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

[0101] It can be understood that various digital numbers involved in the embodiments of the present application are only distinguished for convenience of description, and are not used to limit the scope of the embodiments of the present application.

Claims

1. A method for recovering SPD information from an internal memory, characterized in that, The method is applied to a computing device including a plurality of internal memories, and the method comprises: obtaining serial presence detect (SPD) information of each internal memory, wherein each internal memory has identification information for representing a specification thereof, and the identification information and the SPD information of internal memories of the same specification are the same; when there is a fault internal memory with erroneous SPD information in the plurality of internal memories, obtaining first identification information of the fault internal memory; determining target identification information from second identification information of internal memories with non-erroneous SPD information, the target identification information being the same as the first identification information; using target SPD information corresponding to the target identification information as the SPD information of the fault internal memory, re-performing checksum and timing parameter configuration on the fault internal memory to continue the initialization process.

2. The method of claim 1, wherein, The SPD information of each internal memory is obtained in sequence according to a slot order corresponding to the plurality of internal memories; when the fault internal memory is the nth internal memory in the slot order, the target identification information is determined from the second identification information of the internal memories with non-erroneous SPD information, comprising: starting from the (n+1)th internal memory in the slot order, sequentially determining target internal memories with non-erroneous SPD information; after determining each target internal memory, obtaining second identification information corresponding to each target internal memory, and comparing the second identification information of the target internal memory with the first identification information until the same second identification information as the first identification information is determined, and the second identification information is determined as the target identification information.

3. The method of claim 1, wherein, The SPD information of each internal memory is obtained in sequence according to a slot order corresponding to the plurality of internal memories; when the fault internal memory is the nth internal memory in the slot order, the target identification information is determined from the second identification information of the internal memories with non-erroneous SPD information, comprising: from the 1st to the (n-1)th internal memory, determining target internal memories with non-erroneous SPD information, and obtaining second identification information corresponding to each target internal memory; comparing the second identification information of the target internal memory with the first identification information to obtain the same second identification information as the first identification information; determining the same second identification information as the first identification information as the target identification information.

4. The method according to any of claims 1 to 3, characterized in that, After obtaining the SPD information of each internal memory, the method comprises: verifying each piece of SPD information; when there is SPD information verification failure, reporting corresponding alarm information, the alarm information representing that the SPD information is erroneous; performing corresponding timing parameter configuration on the internal memory with SPD information passing the verification.

5. An in-memory SPD information recovery apparatus, characterized by, The device is applied to a computing device including a plurality of internal memories, and the device comprises: The acquisition module is configured to acquire serial presence detect (SPD) information of each of the memory modules, wherein each of the memory modules has identification information for representing a specification of the memory module, and the identification information and the SPD information of memory modules of the same specification are the same; The processing module is configured to, when there is a faulty memory module with erroneous SPD information in the plurality of memory modules, record first identification information of the faulty memory module; The processing module is further configured to determine target identification information from second identification information of memory modules with correct SPD information, the target identification information being the same as the first identification information; The processing module is further configured to use target SPD information corresponding to the target identification information as the SPD information of the faulty memory module, and re-perform checksum and timing parameter configuration on the faulty memory module to continue the initialization process.

6. The apparatus of claim 5, wherein, The acquisition of the SPD information of each of the memory modules is performed according to a slot order corresponding to the plurality of memory modules, and when the faulty memory module is an nth memory module in the slot order, the processing apparatus is specifically configured to: start from an (n+1)th memory module in the slot order, and sequentially determine target memory modules with correct SPD information; after each of the target memory modules is determined, compare second identification information of the target memory module with the first identification information until the target identification information that is the same as the first identification information is determined.

7. The apparatus of claim 5, wherein, The acquisition of the SPD information of each of the memory modules is performed according to a slot order corresponding to the plurality of memory modules, and when the faulty memory module is an nth memory module in the slot order, the processing apparatus is specifically configured to: from the 1st to the (n-1)th memory modules, determine target memory modules with correct SPD information, and acquire second identification information corresponding to each of the target memory modules; compare the second identification information of the target memory module with the first identification information to obtain second identification information that is the same as the first identification information; determine the second identification information that is the same as the first identification information as the target identification information.

8. The apparatus of any of claims 5-7, wherein, The processing apparatus is further configured to: verify each of the SPD information; when there is SPD information that fails the verification, report corresponding alarm information, the alarm information being used to represent that the SPD information is erroneous; perform corresponding timing parameter configuration on the memory module with the SPD information that passes the verification.

9. A computing device, comprising: The computing device includes a plurality of memory modules, and further includes: at least one memory configured to store a program; at least one processor configured to execute the program stored in the memory; wherein, when the program stored in the memory is executed, the processor is configured to perform the method of any one of claims 1-4.

10. A computer-readable storage medium storing a computer program, when the computer program is executed on a processor, causing the processor to perform the method of any one of claims 1-4.

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