Gold finger connector and memory storage device

Abstract

The present application provides a kind of gold finger connector and memory storage device.The gold finger connector includes connector body, pin carrier, a plurality of first pins, a plurality of second pins and at least one signal shielding structure.The pin carrier protrudes from the connector body.The first pins are disposed on a first surface of the pin carrier.The second pins are disposed on the first surface and at least partially interleaved with the first pins.The at least one signal shielding structure is disposed on the pin carrier and is used to connect at least one target pin in the second pins with at least one ground layer.Thus, the electrical interference between some pins on the gold finger connector can be suppressed.

Description

Technical Field

[0001] This invention relates to a connector structure, and more particularly to a gold finger connector and a memory storage device. Background Technology

[0002] Some types of memory storage devices are equipped with gold finger connectors to communicate with the host system via the pins on these connectors. However, the pins on the gold finger connectors are very close together, making them prone to interference during signal transmission. Summary of the Invention

[0003] The present invention provides a gold finger connector and a memory storage device, which can suppress electrical interference between some pins on the gold finger connector.

[0004] An exemplary embodiment of the present invention provides a gold finger connector, comprising a connector body, a pin carrier, a plurality of first pins, a plurality of second pins, and at least one signal shielding structure. The pin carrier protrudes from the connector body. The plurality of first pins are disposed on a first surface of the pin carrier. The plurality of second pins are disposed on the first surface and are at least partially staggered with the plurality of first pins. The at least one signal shielding structure is disposed on the pin carrier and serves to conduct electricity between at least one target pin of the plurality of second pins and at least one ground layer.

[0005] In one exemplary embodiment of the present invention, the plurality of first pins are used to transmit data signals.

[0006] In one exemplary embodiment of the invention, the plurality of second pins are used to provide a reference ground voltage.

[0007] In one exemplary embodiment of the present invention, the at least one signal shielding structure is disposed below the at least one target pin.

[0008] In an exemplary embodiment of the present invention, the gold finger connector further includes at least one through hole that penetrates at least the at least one target pin and the at least one ground layer below the at least one target pin and is used to accommodate the at least one signal shielding structure.

[0009] In one exemplary embodiment of the present invention, a plurality of first through holes in the at least one through hole penetrate the first target pin in the at least one target pin.

[0010] In one exemplary embodiment of the present invention, the at least one signal shielding structure includes at least one metal layer covering the second surface of the pin carrier.

[0011] In one exemplary embodiment of the present invention, the at least one signal shielding structure does not occupy the vertical projection area below the plurality of first pins.

[0012] An exemplary embodiment of the present invention provides a memory storage device, comprising a gold finger connector, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is connected to the gold finger connector and the rewritable non-volatile memory module. The gold finger connector includes a connector body, a pin carrier, a plurality of first pins, a plurality of second pins, and at least one signal shielding structure. The pin carrier protrudes from the connector body. The plurality of first pins are disposed on a first surface of the pin carrier. The plurality of second pins are disposed on the first surface and are at least partially interleaved with the plurality of first pins. The at least one signal shielding structure is disposed on the pin carrier and serves to conduct at least one target pin of the plurality of second pins to at least one ground layer.

[0013] Based on the above, multiple pins can be disposed in a pin carrier protruding from the connector body of the gold finger connector. In particular, by further providing a signal shielding structure on the pin carrier to conduct at least one target pin among the pins to at least one ground layer, electrical interference between some pins on the gold finger connector can be effectively suppressed. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the appearance of a gold finger connector according to an exemplary embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of multiple pins in a pin group as shown in an exemplary embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of a signal shielding structure disposed on a pin carrier according to an exemplary embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of a signal shielding structure disposed on a pin carrier according to an exemplary embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of a memory storage device and a host system according to an exemplary embodiment of the present invention. Detailed Implementation

[0019] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0020] Figure 1This is a schematic diagram of the appearance of a gold finger connector according to an exemplary embodiment of the present invention.

[0021] Please refer to Figure 1 The gold finger connector 10 includes a connector body 11, a pin carrier 12, and a pin assembly 13. The connector body 11 can be used to house, for example, a control chip, a circuit board, and various electronic circuits for performing signal processing.

[0022] The pin carrier 12 protrudes beyond the connector body 11. Thus, the pin carrier 12 is adapted to be inserted into a mating slot in a host system (not shown) for communication with the host system via said slot. Furthermore, the shape of the pin carrier 12 can be adjusted according to practical requirements, and the present invention is not limited thereto.

[0023] Pin assembly 13 is disposed on the surface 101 (also referred to as the first surface) of pin carrier 12. Pin assembly 13 includes multiple pins. These pins can be made of metal or any conductive material. Furthermore, the pins in pin assembly 13 can be arranged side-by-side on surface 101, such as... Figure 1 As shown. For example, the pins in pin group 13 can conform to the configuration specifications of various connection interfaces such as M.2.

[0024] In one exemplary embodiment, after the surface 102 of the pin carrier 12 (also referred to as the second surface) is inserted as the foremost end into a matching slot in the host system, at least some of the pins in the pin assembly 13 can be electrically connected to each other with at least some of the pins in the slot. In this state, these electrically connected pins can be used to transmit signals between the connected host system and the connector body 11. It should be noted that the total number and configuration of the pins in the pin assembly 13 can be adjusted according to practical needs, and the present invention is not limited thereto.

[0025] Figure 2 This is a schematic diagram of multiple pins in a pin group as shown in an exemplary embodiment of the present invention.

[0026] Please refer to Figure 1 and Figure 2 The lead assembly 13 may include leads (also referred to as first leads) 21(1) to 21(8) and leads (also referred to as second leads) 22(1) to 22(9). Leads 21(1) to 21(8) and 22(1) to 22(9) are arranged side by side on surface 101. In particular, leads 21(1) to 21(8) may be at least partially staggered with leads 22(1) to 22(9), such as Figure 2 As shown. However, the total number and arrangement of the first and second pins can be adjusted according to practical needs, and this invention does not impose any limitations.

[0027] In one exemplary embodiment, pins 21(1) to 21(8) are used to transmit data signals. For example, pins 21(1) to 21(8) may be electrically connected to a control chip and / or various electronic circuits for performing signal processing in the connector body 11. After the pin carrier 12 is inserted into a matching slot in the host system, at least one of pins 21(1) to 21(8) may be used to transmit data signals to or receive data signals from the host system. In one embodiment, the data signal may carry bit data that the host system intends to store in a memory storage device and / or bit data that the host system reads from the memory storage device. In one exemplary embodiment, pins 21(1) to 21(8) are also referred to as data pins.

[0028] In one exemplary embodiment, pins 22(1) to 22(9) are used to provide a reference ground voltage. For example, pins 22(1) to 22(9) may be electrically connected to one or more ground planes in a circuit board inside the connector body 11 and the pin carrier 12. In one exemplary embodiment, after the pin carrier 12 is inserted into a matching slot in the host system, at least one of pins 22(1) to 22(9) may be used to provide a reference ground voltage to or receive a reference ground voltage from the host system. In one exemplary embodiment, pins 22(1) to 22(9) are also referred to as ground pins.

[0029] Traditionally, pins 21(1) to 21(8) are easily susceptible to electrical interference due to their close proximity. This electrical interference can severely affect the signal quality of the transmitted data signal. However, in an exemplary embodiment, by additionally providing at least one signal shielding structure on the pin carrier 12, electrical interference between pins 21(1) to 21(8) can be assisted in suppressing. In particular, the signal shielding structure can be provided on the pin carrier 12 and used to connect at least one of the pins 22(1) to 22(9) (also referred to as the target pin) to at least one ground plane below the target pin.

[0030] Figure 3 This is a schematic diagram of a signal shielding structure disposed on a pin carrier, as shown in an exemplary embodiment of the present invention.

[0031] Please refer to Figure 3In one exemplary embodiment, assuming the target pin includes pin 22(1) (also referred to as the first target pin), the signal shielding structure can be accommodated inside at least one of the vias 31(1) to 31(5). For example, the signal shielding structure can be formed by plating metal inside at least one of the vias 31(1) to 31(5). The vias 31(1) to 31(5) are all located below the pin 22(1). For example, the vias 31(1), 31(2), 31(4) and 31(5) can penetrate the pin 22(1) and the ground layers 301 and 302 below the pin 22(1). Thus, the signal shielding structure in the vias 31(1), 31(2), 31(4) and 31(5) can conduct electricity to the pin 22(1) and the ground layers 301 and 302 below the pin 22(1). Meanwhile, vias 31(1), 31(2), 31(4) and 31(5) can also penetrate the dielectric layer (not shown) between the first surface and the ground layer 301, and the dielectric layer (not shown) between ground layers 301 and 302. In addition, via 31(3) can penetrate the ground layers 302 and 303 below the pin 22(1) and the dielectric layer (not shown) between the ground layers 302 and 303, so as to conduct the ground layers 302 and 303 below the pin 22(1).

[0032] In one embodiment, assuming the target pin includes pin 22(2) (also referred to as the second target pin), the signal shielding structure can be accommodated inside at least one of the vias 32(1) to 32(3). For example, the signal shielding structure can be formed by plating metal inside at least one of the vias 32(1) to 32(3). The vias 32(1) to 32(3) can be disposed below the pin 22(2). For example, the via 32(1) can penetrate the ground layers 302 and 303 below the pin 22(2) and the dielectric layer between the ground layers 302 and 303 to conduct electricity to the ground layers 302 and 303 below the pin 22(2). In addition, the vias 32(2) and 32(3) can penetrate the pin 22(2), the ground layers 301 and 302 below the pin 22(2), the interface layer between the first surface and the ground layer 301, and the dielectric layer between the ground layers 301 and 302. Therefore, the signal shielding structure in the through holes 32(2) and 32(3) can conduct the connection to the pin 22(2) and the ground layers 301 and 302 below the pin 22(2).

[0033] It should be noted that, Figure 3 In the exemplary embodiment, the total number and location of vias 31(1) to 31(5) and 32(1) to 32(3) can be adjusted according to practical needs, as long as the location of the signal shielding structure is within the vertical projection range below the target pin. Thus, the signal shielding structure can be used to help suppress electrical interference between pins 21(1) to 21(8). Figure 3For example, the signal shielding structure formed by the through holes 32(1) to 32(3) can be used to suppress electrical interference between pin 21(1) and pin 21(2).

[0034] Figure 4 This is a schematic diagram of a signal shielding structure disposed on a pin carrier, as shown in an exemplary embodiment of the present invention.

[0035] Please refer to Figure 1 , Figure 2 and Figure 4 In one embodiment, assuming the target pin includes pin 22(1), the signal shielding structure may include a metal layer 41. The metal layer 41 covers the surface 102 (i.e., the second surface) of the pin carrier 12. For example, the metal layer 41 may be electroplated onto the surface 102 of the pin carrier 12. Thus, the metal layer 41 can be used to conduct electricity between pin 22(1) and at least one of the ground layers 301-303 below pin 22(1). Furthermore, assuming the target pin includes pin 22(2), the signal shielding structure may include a metal layer 42. The metal layer 42 also covers the surface 102 of the pin carrier 12. Thus, the metal layer 42 can be used to conduct electricity between pin 22(2) and at least one of the ground layers 301-303 below pin 22(2).

[0036] It should be noted that, in Figure 4 In exemplary embodiments, metal layer 41 (or 42) may provide the same or similar Figure 3 The signal shielding structure formed by the through holes 31(1) to 31(5) (or through holes 32(1) to 32(3)) in the exemplary embodiment provides effective shielding of the signal to help suppress electrical interference between multiple data pins. In addition, the target pin may also include the remaining pins of pins 22(1) to 22(9), which is not limited by the present invention.

[0037] In one exemplary embodiment, the signal shielding structure is disposed below the target pin, which can be considered as the signal shielding structure being located within the vertical projection range below the target pin. This vertical projection range is also referred to as the projection range in the normal vector direction. Figure 3 and Figure 4 For example, the through holes 31(1) to 31(5) and the metal layer 41 can both be considered as being within the vertical projection range below the pin 22(1).

[0038] In one exemplary embodiment, the area where the signal shielding structure is located may not occupy the vertical projection area below the first pin. This limitation can be applied to... Figure 3 Through holes 31(1)~31(5) and 32(1)~32(3) and Figure 4Metal layers 41 and 42. This prevents the additional signal shielding structure from accidentally affecting the original performance of the gold finger connector 10.

[0039] In one exemplary embodiment, Figure 1 The gold finger connector 10 can be coupled to a memory storage device. The memory storage device can communicate with a host system through the gold finger connector 10. For example, through the gold finger connector 10, the host system can write data to or read data from the memory storage device.

[0040] Figure 5 This is a schematic diagram of a memory storage device and a host system according to an exemplary embodiment of the present invention.

[0041] Please refer to Figure 5 The memory storage device 50 includes a connection interface unit 501, a memory control circuit unit 502, and a rewritable non-volatile memory module 503.

[0042] The connection interface unit 501 is used to connect the memory storage device 50 to the host system 51. For example, the connection interface unit 501 may include... Figure 1The gold finger connector 10. The memory storage device 50 can communicate with the host system 51 through the connection interface unit 501. For example, the connection interface unit 501 can be compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 501 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 501 may be packaged in a chip with the memory control circuit unit 502, or the connection interface unit 501 may be disposed outside a chip containing the memory control circuit unit 502.

[0043] The memory control circuit unit 502 is connected to the connection interface unit 501 and the rewritable non-volatile memory module 503. The memory control circuit unit 502 executes multiple logic gates or control instructions implemented in hardware or firmware, and performs operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 503 according to instructions from the host system 51. In an exemplary embodiment, the memory control circuit unit 502 may include a flash memory controller.

[0044] The rewritable non-volatile memory module 503 is used to store data written by the host system 51. For example, the rewritable non-volatile memory module 503 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same or similar characteristics.

[0045] In summary, by setting a signal shielding structure on the pin carrier of the gold finger connector to conduct specific pins to at least one ground plane, electrical interference between some pins on the pin carrier can be effectively suppressed.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gold finger connector, characterized in that, include: Connector body; The pin carrier protrudes from the connector body; Multiple first pins are disposed on the first surface of the pin carrier; A plurality of second pins are disposed on the first surface and are at least partially staggered with the plurality of first pins; as well as At least one signal shielding structure is disposed on the pin carrier and used to connect at least one target pin among the plurality of second pins to a portion of the plurality of grounding layers.

2. The gold finger connector according to claim 1, wherein the plurality of first pins are used for transmitting data signals.

3. The gold finger connector of claim 1, wherein the plurality of second pins are used to provide a reference ground voltage.

4. The gold finger connector according to claim 1, wherein the at least one signal shielding structure is disposed below the at least one target pin.

5. The gold finger connector according to claim 4, further comprising: At least one through-hole extends below the at least one target pin and at least part of the ground layer to accommodate the at least one signal shielding structure.

6. The gold finger connector according to claim 5, wherein a plurality of first through holes in the at least one through hole penetrate a first target pin in the at least one target pin.

7. The gold finger connector according to claim 1, wherein the at least one signal shielding structure comprises at least one metal layer covering the second surface of the pin carrier.

8. The gold finger connector according to claim 1, wherein the at least one signal shielding structure does not occupy the vertical projection range below the plurality of first pins.

9. A memory storage device, characterized in that, include: Gold finger connector; Rewritable non-volatile memory module; as well as The memory control circuit unit is connected to the gold finger connector and the rewritable non-volatile memory module. The gold finger connector includes: Connector body; The pin carrier protrudes from the connector body; Multiple first pins are disposed on the first surface of the pin carrier; A plurality of second pins are disposed on the first surface and are at least partially staggered with the plurality of first pins; and At least one signal shielding structure is disposed on the pin carrier and used to connect at least one target pin among the plurality of second pins to a portion of the plurality of grounding layers.

10. The memory storage device of claim 9, wherein the plurality of first pins are used for transmitting data signals.

11. The memory storage device of claim 9, wherein the plurality of second pins are used to provide a reference ground voltage.

12. The memory storage device according to claim 9, wherein the at least one signal shielding structure is disposed below the at least one target pin.

13. The memory storage device of claim 12, wherein the gold finger connector further comprises: At least one through-hole extends below the at least one target pin and at least part of the ground layer to accommodate the at least one signal shielding structure.

14. The memory storage device of claim 13, wherein a plurality of first through holes in the at least one through hole penetrate a first target pin in the at least one target pin.

15. The memory storage device of claim 9, wherein the at least one signal shielding structure comprises at least one metal layer covering the second surface of the pin carrier.

16. The memory storage device of claim 9, wherein the at least one signal shielding structure does not occupy the vertical projection area below the plurality of first pins.

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