An FPGA that uses built-in local serial modules to realize module signal sharing

Abstract

The present application discloses an FPGA that utilizes a built-in local series module to realize module signal sharing, and relates to the field of FPGA. The built-in local series module in the FPGA includes at least one local interconnect line connected in series with a local control switch, each local interconnect line is respectively connected to multiple shared ports belonging to the same signal sharing group, and a local control switch is included between two adjacent shared ports, and each shared port is a port of a predetermined resource module; the local control switch on the local interconnect line is controlled to be turned on by a configuration bit, and multiple shared ports in the same signal sharing group realize signal transmission through the local interconnect line. In this FPGA, multiple shared ports that need to be connected in series can directly realize signal transmission through the local series module for signal sharing, without having to go through a winding architecture, thereby reducing wiring congestion, increasing wiring flexibility, improving routing rate, and effectively reducing latency.

Description

Technical Field

[0001] The present invention relates to the field of FPGA, and in particular to an FPGA which utilizes built-in local series modules to realize module signal sharing. Background Art

[0002] FPGA (Field Programmable Gate Array) contains a large number of resource modules such as CLB, BRAM, DSP, IOB, etc. These resource modules are interconnected through a winding architecture to achieve the required user design.

[0003] When implementing user designs, there is often a need for signal sharing between resource modules, that is, the signal generated by the same signal source needs to be fanned out to multiple resource modules. At this time, the signal generated by the signal source needs to be connected to each resource module separately through different winding paths in the winding architecture. This places a large demand on wiring resources, easily leads to wiring congestion, and reduces the routing rate. Summary of the Invention

[0004] In response to the above-mentioned problems and technical requirements, the applicant has proposed an FPGA that uses built-in local serial modules to achieve module signal sharing. The technical solution of this application is as follows:

[0005] An FPGA that implements module signal sharing using a built-in local series module. The FPGA includes a built-in local series module, which includes at least one local interconnect line connected in series with a local control switch. Each local interconnect line connects multiple shared ports belonging to the same signal sharing group, and a local control switch is included between two adjacent shared ports. Each shared port is a port of a predetermined resource module.

[0006] By controlling the local control switch on the local interconnect line through the configuration bit, multiple shared ports in the same signal sharing group can realize signal transmission through the local interconnect line; or, by controlling the local control switch on the local interconnect line through the configuration bit, multiple shared ports in the same signal sharing group can realize their own signal transmission through the winding structure respectively.

[0007] A further technical solution is that the multiple shared ports in the same signal sharing group belong to multiple predetermined resource modules respectively, and the distance between the layout positions of the multiple predetermined resource modules does not exceed the predetermined distance.

[0008] A further technical solution is that when the local control switch on the local interconnection line is turned on by controlling the configuration bit, the same signal is input to the local series module and shared to other shared ports through the local interconnection line.

[0009] Its further technical solution is that multiple shared ports of the same signal sharing group belong to multiple BRAM modules respectively. When the local control switch on the local interconnection line in the local series module is turned on by controlling the configuration bit, multiple BRAM modules realize width expansion function or depth expansion function through the local series module.

[0010] A further technical solution is that the address ports of multiple BRAM modules form a signal sharing group and are connected to a first local interconnect line, the enable ports of multiple BRAM modules form a signal sharing group and are connected to a second local interconnect line, and the control ports of multiple BRAM modules form a signal sharing group and are connected to a third local interconnect line;

[0011] The local control switches on the three local interconnection lines connected to multiple BRAM modules are all turned on by configuration bit control, and the address signal is shared to the address port of each BRAM module through the first local interconnection line; the enable signal is input through the connection between the winding structure and one of the enable ports and is shared to the enable port of each BRAM module through the second local interconnection line; the control signal is shared to the control port of each BRAM module through the third local interconnection line; the data ports of multiple BRAM modules respectively obtain data signals through the winding structure, and multiple BRAM modules realize the width expansion function.

[0012] A further technical solution is that the data ports of the multiple BRAM modules form a signal sharing group and are connected to the fourth local interconnect line, the address ports of the multiple BRAM modules form a signal sharing group and are connected to the fifth local interconnect line, and the control ports of the multiple BRAM modules form a signal sharing group and are connected to the sixth local interconnect line;

[0013] The local control switches on the three local interconnection lines connected to the multiple BRAM modules are all turned on through configuration bit control. The data signal is input through the connection between the winding structure and one of the control ports and is shared to the data ports of each BRAM module through the fourth local interconnection line; the control signal is shared to the control ports of each BRAM module through the sixth local interconnection line; part of the signal bits of the address signal are shared to the address ports of each BRAM module through the fifth local interconnection line, and the enable ports of the multiple BRAM modules respectively obtain the remaining signal bits of the address signal through the winding structure, so that the multiple BRAM modules realize the depth expansion function.

[0014] A further technical solution is that the address signals and control signals shared to each BRAM module via the local interconnection lines are input by the winding structure; or, the address signals and control signals shared to each BRAM module via the local interconnection lines are input by the FIFO controller.

[0015] A further technical solution is that when the number of shared ports in the same signal sharing group is less than a predetermined threshold, the local control switch on the local interconnect line connected to the shared ports in the signal sharing group is implemented using an NMOS transistor, a transmission gate or a bidirectional tri-state buffer;

[0016] When the number of shared ports in the same signal sharing group reaches a predetermined threshold, the local control switches on the local interconnection lines connected to the shared ports in the signal sharing group are implemented using bidirectional tri-state buffers.

[0017] Its further technical solution is that one or more local series modules are built into the FPGA, and each local series module is respectively arranged between its corresponding predetermined resource module and winding structure; each local series module includes one or more local interconnection lines, and each local interconnection line is used to connect different signal sharing groups.

[0018] Its further technical solution is that when the FPGA is used, it controls all local control switches on the local interconnection line to be turned on through the configuration bit, so that all shared ports in the same signal sharing group realize signal transmission through the local interconnection line; or it controls some local control switches on the local interconnection line to be turned on and other local control switches to be turned off through the configuration bit, so that some shared ports in the same signal sharing group realize signal transmission through the local interconnection line, and other shared ports realize signal transmission through the winding structure respectively.

[0019] The beneficial technical effects of this application are:

[0020] The present application discloses an FPGA that utilizes a built-in local series module to implement module signal sharing. The FPGA has a built-in local series module through hardware resources. Signal transmission between multiple shared ports that need to be connected in series can be directly achieved through the local series module for signal sharing, without the need to go through a winding architecture. This can reduce the signal transmitted through the winding architecture, thereby reducing wiring congestion, increasing wiring flexibility, improving routing rate, and effectively reducing latency.

[0021] Moreover, the newly added local series module does not affect the connection relationship between the resource module and the winding structure. When the local series module is disconnected by configuration, the resource module can still be connected to its corresponding signal source through the winding structure, which does not affect the normal operation of the original function of the resource module.

[0022] The built-in local serial module of the FPGA can be used to easily and quickly implement width expansion and depth expansion of multiple BRAM modules, and can be expanded to form a FIFO function. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1This is a schematic diagram of the signal transmission path of the address signal Addr in a conventional FPGA fanned out to two BRAM modules via the winding architecture.

[0024] Figure 2 This is a schematic diagram of the signal transmission path of the address signal Addr in the FPGA in one embodiment of the present application, which is fanned out to two BRAM modules for achieving width expansion via a built-in local series module.

[0025] Figure 3 This is a schematic diagram of the signal transmission path of the data signal Data in the FPGA in one embodiment of the present application, which is fanned out to four BRAM modules for achieving depth expansion via the built-in local series module.

[0026] Figure 4 This is a schematic diagram of a signal transmission path of a FIFO formed by a FIFO controller in one embodiment of the present application using a built-in local series module and two BRAM modules for achieving width expansion. DETAILED DESCRIPTION

[0027] The specific implementation of this application will be further described below with reference to the accompanying drawings.

[0028] The present application discloses an FPGA that utilizes built-in local series modules to achieve module signal sharing. The FPGA has the same architecture as a conventional FPGA and includes various resource modules and a winding architecture. The resource modules can be arranged in a common manner according to a matrix architecture. Each resource module includes several ports, and each port of the resource module is connected to the winding architecture to achieve communication interconnection.

[0029] On this basis, the FPGA of the present application also has a built-in local series module (BOX module) through the newly added hardware resources. The local series module includes at least one local interconnect line connected in series with a local control switch. Each local interconnect line is connected to multiple shared ports belonging to the same signal sharing group, and a local control switch N1 is included between two adjacent shared ports. Each shared port is a port of a predetermined resource module. The predetermined resource module is a resource module in the FPGA that needs to implement module signal sharing. In one embodiment, there are multiple shared ports in the same signal sharing group that belong to the same predetermined resource module, but more commonly in another embodiment, multiple shared ports in the same signal sharing group belong to multiple predetermined resource modules, and further, these multiple predetermined resource modules are exactly the same. The same ports in multiple identical predetermined resource modules are respectively used as shared ports to form a signal sharing group. For example, the enable ports EN in multiple identical BRAM modules are respectively used as shared ports to form a signal sharing group. The signal sharing group includes enable ports EN belonging to different BRAM modules. This is because multiple identical resource modules are generally copied from the same resource module during design and have the same layout design. Therefore, the same ports in these multiple identical resource modules will occupy the metal wire Track at the same position. In this case, the implementation of the local series module only requires adding a local control switch N1 between two adjacent shared ports, which is relatively low in implementation cost.

[0030] Based on this architecture, the local control switch on the local interconnect line is controlled by the configuration bit to be turned on, so that multiple shared ports in the same signal sharing group can realize signal transmission through the local interconnect line without going through the winding structure, thereby reducing wiring congestion and improving routing efficiency. In one embodiment, the signal transmission realized by multiple shared ports in the same signal sharing group through the local interconnect line includes that the same signal is input into the local series module and shared to other shared ports through the local interconnect line, that is, the same signal is simultaneously fanned out to the shared ports in multiple predetermined resource modules through the local series module, realizing the sharing of the same signal by multiple predetermined resource modules. This is a common application scenario in the FPGA application process. A typical example is when multiple BRAM modules are expanded in width or depth to form a large-capacity RAM, some of the same ports of these multiple BRAM modules need to share the same signal. In other scenarios, the signal transmission realized by multiple shared ports in the signal sharing group through the local interconnect line also includes that a shared port in the signal sharing group transmits a signal to other shared ports in the signal sharing group through the local interconnect line.

[0031] For example, if we implement width expansion for two BRAM modules with a maximum capacity of 1024x32 and obtain a RAM with a capacity of 1024x64, please compare Figure 1 and Figure 2 This embodiment compares a conventional FPGA implementation method with the implementation method of the present application using a local serial module as follows. Since the read and write ends of a BRAM module are similar, this example only uses the write end of the BRAM module as an example. When implementing the width expansion function, it is necessary to simultaneously fan out the clock signal to the clock port WCLK of the two BRAM modules, simultaneously fan out the enable signal to the enable port EN of the two BRAM modules, simultaneously fan out the control signal to the control port WEN of the two BRAM modules, and simultaneously fan out the address signal to the address ports WA[9:0] of the two BRAM modules. The lower 32 bits of the data signal are fanned out to the data port of one of the BRAM modules to form the lower 32-bit data port WD[0:31] of the width-expanded RAM, and the upper 32 bits of the data signal are fanned out to the data port of the other BRAM module to form the upper 32-bit data port WD[63:32] of the width-expanded RAM. In order to achieve the width expansion function, the clock signal, enable signal, control signal and address signal need to be fanned out to the two BRAM modules. Among them, the clock signal is relatively special. It is generally fanned out to the two BRAM modules through the same clock tree to reduce clock skew. Therefore, the clock signal is generally not connected through the winding structure. Therefore, this application will not consider the clock signal in the future.

[0032] For other enable signals, control signals, and address signals that need to be fanned out to two BRAM modules, take the address signal Addr as an example, such as Figure 1 As shown, in a conventional FPGA, the signal source of the address signal Addr needs to be fanned out to IP1 and IP2 of the winding structure at the same time through the winding structure. Figure 1 The address signal Addr is fanned out to IP1 and IP2 in a dotted line, which is not the case in practice. Figure 1 The straight line shown is usually a more complex line structure, whereby the address signal Addr can be connected to the address port WA[9:0] of BRAM1 through IP1 of INT1 and to the address port WA[9:0] of BRAM2 through IP2 of INT2. The signal transmission path is as follows Figure 1As shown by the arrows in . In addition to the address signal Addr, the enable signal and the control signal need to be fanned out to two BRAMs through the winding architecture. In actual situations, more BRAMs will be used for expansion. The same signal needs to be fanned out to more BRAMs through the winding architecture. As described in the background technology section, this will occupy a large demand for wiring resources, easily lead to wiring congestion, and reduce the routing rate. In addition, the distance between IP1 and IP2 of the winding architecture may be large, especially when more BRAM modules are used to form a larger RAM. Since BRAM modules are usually arranged in a row inside the FPGA, these multiple BRAM modules are arranged up and down, occupying a large height, which will cause the signal connection to occupy more wiring resources and take a longer winding path, which not only increases the pressure on wiring resources, but also causes the path delay to increase.

[0033] Based on the FPGA of this application, Figure 2 As shown, the address port WA[9:0] of BRAM1 and the address port WA[9:0] of BRAM2 are also connected through the local interconnect line L1. The local control switch N1 between the two BRAM modules on the local interconnect line L1 is turned on by the configuration bit, thereby only the address signal Addr needs to be fanned out to IP1 or IP2 of the winding structure. Figure 1 Taking the fan-out to IP1 as an example, the address signal Addr is connected to the address port WA[9:0] of BRAM1 and can also be connected to the address port WA[9:0] of BRAM through the local interconnection line and the turned-on local control switch N1. The signal transmission path is as follows: Figure 2 As shown by the arrows in . Other signals that need to be shared by BRAM1 and BRAM2 are similar, and the same is true when more BRAM modules are used for expansion. Since there is no need to connect to BRAM2 through IP2, the wiring requirements are reduced, the wiring flexibility is increased, the wiring process is more convenient, and the path delay is reduced. When more BRAM modules are used for functional expansion, this optimization effect is more obvious, such as Figure 4 The figure shows a connection diagram of another example in which four BRAM modules are expanded to form a large-capacity RAM. In a conventional FPGA, the data signal Data needs to be connected to INT1, INT2, INT3, and INT4 respectively and then input into the data ports WD[31:0] of the four BRAM modules. In the FPGA of the present application, the data signal Data is connected to the data port WD[31:0] of BRAM1 through INT1 and is transmitted to the data ports WD[31:0] of BRAM2, BRAM3, and BRAM4 through the local interconnect line L4. The signal transmission path is shown as follows: Figure 3 As shown by the arrow in .

[0034] When signal sharing is not required, the local control switch on the local interconnect line is turned off by configuring the bit, and multiple shared ports in the same signal sharing group realize their own signal transmission through the winding structure. Figure 2 When there is no RAM expansion requirement, the local control switch N1 is turned off, and the two BRAM modules are connected to the winding structure and used independently without being connected to each other, which does not affect the normal use of the two BRAM modules.

[0035] Based on the architecture and functionality of local series modules, an FPGA has one or more built-in local series modules, each located between its corresponding predetermined resource modules and the wiring architecture. Each local series module includes one or more local interconnect lines, each used to connect different signal sharing groups.

[0036] Based on the above examples, it can be seen that each predetermined resource module can have only one port as a shared port connected to the local interconnection line corresponding to the signal sharing group to which it belongs, or each predetermined resource module can have multiple ports as shared ports in different signal sharing groups connected to their respective corresponding local interconnection lines, for example Figure 2 In the example, the control port address port WA[9:0] in each BRAM module belongs to a signal sharing group connected to the local interconnect line L1, the enable port EN in each BRAM module belongs to a signal sharing group connected to the second local interconnect line L2, and the control port WEN in each BRAM module belongs to a signal sharing group connected to the third local interconnect line L3. In actual implementation, the different local interconnect lines connected to different ports of a predetermined resource module may belong to different local series modules or to the same local series module. A more common practice is that the multiple local interconnect lines connected to different ports of a predetermined resource module belong to the same local series module, and the local series module is set between the corresponding multiple predetermined resource modules and the winding structure, such as Figure 2 In the example, local interconnect lines L1, L2, and L3 belong to the same local series module.

[0037] The above example uses a local interconnect line connecting two shared ports. However, in actual implementation, there is no such limitation. A local interconnect line can connect multiple shared ports, with a local control switch N1 positioned between any two adjacent shared ports. Therefore, when a local interconnect line connects shared ports in multiple predetermined resource modules, the distance between the layout locations of these predetermined resource modules does not exceed a predetermined distance. For example, these predetermined resource modules are typically positioned adjacent to each other or at diagonal locations. In this way, the local interconnect line achieves a shorter distance in the local series connection, thus minimizing the space occupied by the local interconnect line.

[0038] When the number of shared ports in the same signal sharing group is less than a predetermined threshold, the local control switch N1 on the local interconnect line connected to the shared ports in the signal sharing group is implemented using an NMOS transistor, a transmission gate, or a bidirectional tri-state buffer. When the number of shared ports in the same signal sharing group reaches a predetermined threshold, the local control switch on the local interconnect line connected to the shared ports in the signal sharing group is implemented using a bidirectional tri-state buffer. This can avoid the problem of increased delay when signal sharing via the local interconnect line.

[0039] When more than two shared ports are connected to a local interconnect line, all local control switches on the same local interconnect line can be turned on through configuration bits, so that all shared ports in the same signal sharing group can achieve signal transmission through the local interconnect line. Alternatively, some local control switches on the local interconnect line can be turned on and other local control switches can be turned off through configuration bits, so that some shared ports in the same signal sharing group can achieve signal transmission through the local interconnect line and other shared ports can achieve signal transmission through the winding structure. For example Figure 3 In the example shown, the local interconnect line L4 connects the data ports WD[31:0] of the four BRAM modules. In application, the three local control switches N1 can be controlled to be turned on through the configuration bit. In this way, the data ports WD[31:0] of the four BRAM modules can all be transmitted through the local interconnect line L4, and these four BRAM modules can be used to expand into a large-capacity RAM. Alternatively, the local control switch N1 between BRAM1 and BRAM2 can be controlled to be turned on through the configuration bit, while the local control switches N1 between BRAM2 and BRAM3 and between BRAM3 and BRAM4 are kept off. In this case, only the data ports WD[31:0] of BRAM1 and BRAM2 can be transmitted through the local interconnect line L4, while BRAM3 and BRAM4 still use the winding structure to transmit signals. Only BRAM1 and BRAM2 can be used to expand into a large-capacity RAM, while BRAM3 and BRAM4 can still be used independently.

[0040] As mentioned above Figure 2 and Figure 3 For example, when using the local series module built into the FPGA of this application to realize module signal sharing, a common application is to use it to realize the capacity expansion of the BRAM module, that is, multiple shared ports of the same signal sharing group belong to multiple BRAM modules respectively, and when the local control switch on the local interconnection line within the local series module is controlled by the configuration bit to be turned on, when multiple BRAM modules realize width expansion function or depth expansion function through the local series module.

[0041] 1. Realize the width expansion function of multiple BRAM modules, that is, use multiple BRAM modules with small data bit width to realize RAM with large data bit width.

[0042] In this case, the address ports of the multiple BRAM modules form a signal sharing group and are connected to the first local interconnect line L1, the enable ports of the multiple BRAM modules form a signal sharing group and are connected to the second local interconnect line L2, and the control ports of the multiple BRAM modules form a signal sharing group and are connected to the third local interconnect line L3. Figure 2 shown.

[0043] Configuration bits control the local control switches on the three local interconnect lines connecting multiple BRAM modules, turning them on. Address signals are shared to the address ports of each BRAM module via the first local interconnect line L1. An enable signal is input via a connection between the wiring structure and one of the enable ports and shared to the enable ports of each BRAM module via the second local interconnect line. Control signals are shared to the control ports of each BRAM module via the third local interconnect line. The data ports of multiple BRAM modules receive data signals via the wiring structure.

[0044] That is, the address signal, enable signal, control signal and clock signal are all shared, while the data signal is separate and independent. Thus, these multiple BRAM modules realize the width expansion function, which is applicable to both the write end and the read end.

[0045] 2. Realize the depth expansion function of multiple BRAM modules, that is, use multiple BRAM modules with small address width to realize RAM with large address width.

[0046] In this case, the data ports of the multiple BRAM modules form a signal sharing group and are connected to the fourth local interconnect line L4, the address ports of the multiple BRAM modules form a signal sharing group and are connected to the fifth local interconnect line L5, and the control ports of the multiple BRAM modules form a signal sharing group and are connected to the sixth local interconnect line L6. Figure 3 shown.

[0047] Configuration bits control the conduction of local control switches on the three local interconnects connecting multiple BRAM modules. Data signals are input via a connection between the wiring structure and one of the control ports and shared to the data ports of each BRAM module via the fourth local interconnect line L4. Control signals are shared to the control ports of each BRAM module via the sixth local interconnect line L6. Partial address signal bits are shared to the address ports of each BRAM module via the fifth local interconnect line L5. The enable ports of the multiple BRAM modules receive the remaining address signal bits via the wiring structure.

[0048] That is, some signal bits of the address signal, control signal, data signal and clock signal are shared, and the enable signal is separated and independent. In this way, these multiple BRAM modules realize the depth expansion function, which is applicable to both the write end and the read end. For example, taking two BRAM modules to realize depth expansion as an example, the lower 10 bits of the address signal Addr[9:0] are shared to BRAM1 and BRAM2, and the highest bit of the address signal Addr

[10] is used as the enable signal. When Addr

[10] =0, the enable signal of BRAM1 is valid; when Addr

[10] =1, the enable signal of BRAM2 is valid. In this way, two BRAM modules with a capacity of 1024x32 can be used for depth expansion to form a RAM with a capacity of 2048x32.

[0049] Regardless of the above-mentioned width expansion or depth expansion function, the address signals and control signals shared to each BRAM module via the local interconnection line have two sources: (1) The address signals and control signals shared to each BRAM module via the local interconnection line are input by the winding structure, such as Figure 2 and 3 Alternatively, (2) the address signals and control signals shared to each BRAM module via the local interconnection line are input by the FIFO controller.

[0050] Configuring a BRAM module as a FIFO is another common application. This requires a FIFO controller, which can output the control and address signals required to read and write the corresponding BRAM module in FIFO mode, thereby implementing the FIFO function. However, in conventional FPGAs, a FIFO controller can only correspond to one BRAM module, so the capacity that the FIFO can achieve cannot exceed the maximum capacity that a BRAM module can provide. Based on the architecture of this application, the address and control signals generated by a FIFO controller can be fanned out to multiple BRAMs via local interconnects, which can be expanded in width or depth. This allows a FIFO controller to be combined with multiple BRAM modules to achieve a larger capacity FIFO.

[0051] like Figure 4 As shown, the winding frame and FIFO controller are connected to the two input terminals of MUX1, and the output terminal of MUX1 is connected to the first local interconnect line L1. The winding frame and FIFO controller are connected to the two input terminals of MUX2, and the output terminal of MUX2 is connected to the third local interconnect line L3. By controlling MUX1 and MUX2, the address signals and control signals from the winding frame can be selected and shared with BRAM1 and BRAM2. Alternatively, by controlling MUX1 and MUX2, the address signals and control signals from the FIFO controller can be selected and shared with BRAM1 and BRAM2, thereby achieving a larger FIFO capacity.

Claims

1. An FPGA that uses built-in local serial modules to achieve module signal sharing, characterized in that: The FPGA has a built-in local series module, the local series module including at least one local interconnect line connected in series with a local control switch, each local interconnect line is connected to multiple shared ports belonging to the same signal sharing group, and a local control switch is included between two adjacent shared ports, and each shared port is a port of a predetermined resource module; The local control switch on the local interconnect line is controlled to be turned on by the configuration bit, so that multiple shared ports in the same signal sharing group realize signal transmission through the local interconnect line; or the local control switch on the local interconnect line is controlled to be turned off by the configuration bit, so that multiple shared ports in the same signal sharing group realize their own signal transmission through the winding structure respectively; Multiple shared ports of the same signal sharing group belong to multiple BRAM modules respectively. When local control switches on local interconnect lines in the local series modules are controlled to be turned on by configuration bits, the multiple BRAM modules implement a width expansion function or a depth expansion function through the local series modules. The address ports of multiple BRAM modules form a signal sharing group and are connected to a first local interconnect line; the enable ports of the multiple BRAM modules form a signal sharing group and are connected to a second local interconnect line; the control ports of the multiple BRAM modules form a signal sharing group and are connected to a third local interconnect line; local control switches on three local interconnect lines connected to the multiple BRAM modules are all turned on by controlling the configuration bits, and the address signal is shared to the address ports of each BRAM module through the first local interconnect line; the enable signal is input through the connection between the winding structure and one of the enable ports and is shared to the enable ports of each BRAM module through the second local interconnect line; the control signal is shared to the control ports of each BRAM module through the third local interconnect line; the data ports of the multiple BRAM modules respectively obtain data signals through the winding structure, and the multiple BRAM modules implement a width expansion function; The data ports of the multiple BRAM modules form a signal sharing group and are connected to a fourth local interconnect line, the address ports of the multiple BRAM modules form a signal sharing group and are connected to a fifth local interconnect line, and the control ports of the multiple BRAM modules form a signal sharing group and are connected to a sixth local interconnect line. Local control switches on three local interconnect lines connected to the multiple BRAM modules are all turned on by controlling the configuration bits, a data signal is input via a connection between a winding structure and one of the control ports and is shared to the data ports of each BRAM module via the fourth local interconnect line; a control signal is shared to the control ports of each BRAM module via the sixth local interconnect line; part of the signal bits of the address signal are shared to the address ports of each BRAM module via the fifth local interconnect line, and the enable ports of the multiple BRAM modules respectively obtain the remaining signal bits of the address signal via the winding structure, so that the multiple BRAM modules realize a depth expansion function.

2. The FPGA according to claim 1, wherein The multiple shared ports in the same signal sharing group belong to multiple predetermined resource modules respectively, and the distance between the layout positions of the multiple predetermined resource modules does not exceed the predetermined distance.

3. The FPGA according to claim 1, wherein: When the local control switch on the local interconnection line is turned on by controlling the configuration bit, the same signal is input into the local series module and is shared to other shared ports through the local interconnection line.

4. The FPGA according to claim 1, wherein: The address signals and control signals shared to each BRAM module via the local interconnection lines are input by the winding structure; or, the address signals and control signals shared to each BRAM module via the local interconnection lines are input by the FIFO controller.

5. The FPGA according to claim 1, wherein: When the number of shared ports in the same signal sharing group is less than a predetermined threshold, the local control switch on the local interconnection line connected to the shared ports in the signal sharing group is implemented using an NMOS transistor, a transmission gate or a bidirectional tri-state buffer; When the number of shared ports in the same signal sharing group reaches the predetermined threshold, the local control switches on the local interconnection lines connected to the shared ports in the signal sharing group are implemented using bidirectional tri-state buffers.

6. The FPGA according to claim 1, wherein: The FPGA has one or more built-in local series modules, each of which is arranged between its corresponding predetermined resource module and winding structure; each of the local series modules includes one or more local interconnection lines, and each local interconnection line is used to connect different signal sharing groups.

7. The FPGA according to claim 1, wherein: When the FPGA is used, all local control switches on the local interconnection lines are controlled to be turned on through configuration bits, so that all shared ports in the same signal sharing group realize signal transmission through the local interconnection lines; or some local control switches on the local interconnection lines are controlled to be turned on and other local control switches are turned off through configuration bits, so that some shared ports in the same signal sharing group realize signal transmission through the local interconnection lines and other shared ports realize signal transmission through winding structures.

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