Pixel circuit and driving method thereof, and display panel

Abstract

A pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes a driving circuit, a data writing circuit, a storage circuit, and a first reset circuit; the driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal; the data writing circuit is configured to write a data signal to the control terminal of the driving circuit under the control of a first scanning signal; the storage circuit is configured to store the data signal; the first reset circuit is configured to apply a first initialization voltage to the control terminal of the driving circuit under the control of a first reset control signal; the pixel circuit also includes a third reset circuit, the third reset circuit is configured to apply a holding voltage to the first terminal of the driving circuit under the control of a third reset control signal; the driving circuit is turned on under the control of the first reset control signal, and the turn-on duration of the driving circuit is greater than the effective duration of the third reset control signal.

Description

[0001] This application is a divisional application of Chinese patent application No. 202110898671.4 filed on August 5, 2021, with the invention name being “Pixel circuit, driving method thereof, and display panel”. Technical Field

[0002] Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display panel. Background Art

[0003] Organic Light-Emitting Diode (OLED) display panels have the advantages of being thin, light, having a wide viewing angle, active luminescence, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, high luminous efficiency and flexible display. They are increasingly used in display fields such as mobile phones, tablet computers, and digital cameras. Summary of the Invention

[0004] At least some embodiments of the present disclosure provide a pixel circuit, comprising a driving circuit, a data writing circuit, a storage circuit and a first reset circuit; wherein the driving circuit comprises a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving a light-emitting element to emit light; the data writing circuit is configured to write a data signal to the control terminal of the driving circuit under the control of a first scanning signal; the storage circuit is configured to store the data signal; the first reset circuit is configured to apply a first initialization voltage to the control terminal of the driving circuit under the control of a first reset control signal; the first reset circuit comprises an N-type oxide thin film transistor, and the pixel circuit further comprises: a third reset circuit, the third reset circuit is configured to apply a holding voltage to the first terminal of the driving circuit under the control of a third reset control signal, the driving circuit is turned on under the control of the first reset control signal, and the turn-on time of the driving circuit is greater than the effective time of the third reset control signal.

[0005] For example, in the pixel circuit provided in some embodiments of the present disclosure, the driving circuit includes a first transistor; the gate of the first transistor serves as the control end of the driving circuit, the first electrode of the first transistor serves as the first end of the driving circuit, and the second electrode of the first transistor serves as the second end of the driving circuit.

[0006] For example, in the pixel circuit provided in some embodiments of the present disclosure, the data writing circuit includes a second transistor; the gate of the second transistor is connected to the first scanning signal end to receive the first scanning signal, the first electrode of the second transistor is connected to the data signal end to receive the data signal, and the second electrode of the second transistor is connected to the control end of the driving circuit.

[0007] For example, in the pixel circuit provided in some embodiments of the present disclosure, the storage circuit includes a storage capacitor, a first electrode of the storage capacitor is connected to the control end of the driving circuit, and a second electrode of the storage capacitor is connected to the second end of the driving circuit.

[0008] For example, in the pixel circuit provided in some embodiments of the present disclosure, the N-type oxide thin film transistor included in the first reset circuit is a third transistor; the gate of the third transistor is connected to the first reset control signal terminal to receive the first reset control signal, the first electrode of the third transistor is connected to the first initialization voltage terminal to receive the first initialization voltage, and the second electrode of the seventh transistor is connected to the control terminal of the driving circuit.

[0009] For example, in some embodiments of the present disclosure, the pixel circuit further includes a second reset circuit, wherein the second reset circuit is configured to apply a second initialization voltage to the anode of the light-emitting element under the control of a second reset control signal.

[0010] For example, in the pixel circuit provided in some embodiments of the present disclosure, the second reset circuit includes a fourth transistor, which is an N-type thin film transistor, the gate of the fourth transistor and the second reset control signal terminal are connected to receive the second reset control signal, the first electrode of the fourth transistor and the second initialization voltage terminal are connected to receive the second initialization voltage, and the second electrode of the fourth transistor and the anode of the light-emitting element.

[0011] For example, in some embodiments of the present disclosure, the pixel circuit further includes a first light-emitting control circuit, wherein the first light-emitting control circuit is configured to apply a first power supply voltage to the first end of the driving circuit under the control of a first light-emitting control signal.

[0012] For example, in the pixel circuit provided in some embodiments of the present disclosure, the first light-emitting control circuit includes a fifth transistor, the gate of the fifth transistor is connected to the first light-emitting control terminal to receive the first light-emitting control signal, the first electrode of the fifth transistor is connected to the first power supply terminal to receive the first power supply voltage, and the second electrode of the fifth transistor is connected to the first end of the driving circuit.

[0013] For example, in the pixel circuit provided in some embodiments of the present disclosure, the third reset circuit includes a sixth transistor, the gate of the sixth transistor is connected to the third reset control signal terminal to receive the third reset control signal, the first electrode of the sixth transistor is connected to the holding voltage terminal to receive the holding voltage, and the second electrode of the sixth transistor is connected to the first terminal of the driving circuit.

[0014] For example, in the pixel circuit provided in some embodiments of the present disclosure, the maintenance voltage is greater than the first voltage, wherein the first voltage is provided by a first power supply terminal, the first power supply terminal is connected to the first end of the driving circuit, and the first voltage is higher than the second power supply voltage connected to the cathode of the light-emitting element.

[0015] For example, in the pixel circuit provided in some embodiments of the present disclosure, the first reset circuit is turned on earlier than the third reset circuit.

[0016] For example, in some embodiments of the present disclosure, the pixel circuit further includes a second light-emitting control circuit, wherein the second light-emitting control circuit is configured to apply the driving current to the first pole of the light-emitting element under the control of a second light-emitting control signal.

[0017] For example, in the pixel circuit provided in some embodiments of the present disclosure, the second light-emitting control circuit includes a seventh transistor, the gate of the seventh transistor is connected to the second light-emitting control end to receive the second light-emitting control signal, the first electrode of the seventh transistor is connected to the second end of the driving circuit, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting element.

[0018] For example, in the pixel circuit provided in some embodiments of the present disclosure, the first initialization voltage is greater than the first voltage, wherein the first voltage is provided by a first power supply terminal, the first power supply terminal is connected to the first end of the driving circuit, and the first voltage is higher than the second power supply voltage connected to the cathode of the light-emitting element.

[0019] For example, in the pixel circuits provided in some embodiments of the present disclosure, the maintaining voltage is respectively greater than the first voltage, the first voltage is provided by the first power supply terminal, the first power supply terminal is connected to the first end of the driving circuit, and the first voltage is higher than the second power supply voltage connected to the cathode of the light-emitting element.

[0020] At least some embodiments of the present disclosure provide a display panel comprising a plurality of pixel units arranged in an array; wherein each of the pixel units comprises a pixel circuit according to any one of the above descriptions.

[0021] At least some embodiments of the present disclosure provide a method for driving a pixel circuit, including an initialization stage, a threshold voltage compensation stage, a data writing and mobility compensation stage, and a light-emitting stage, wherein, in the initialization stage, the first reset control signal and the second reset control signal are input, the first reset circuit and the second reset circuit are turned on, the first initialization voltage is applied to the control end of the driving circuit through the first reset circuit to reset the control end of the driving circuit, and the second initialization voltage is applied to the second end of the driving circuit through the second reset circuit to reset the second end of the driving circuit; in the threshold voltage compensation stage, the first reset control signal is input, the first reset circuit is turned on, the first initialization voltage is applied to the control end of the driving circuit through the first reset circuit to turn on the driving circuit, and the second reset circuit is turned on. Stop inputting the second reset control signal, turn off the second reset circuit, perform threshold compensation through the turned-on drive circuit and the storage circuit, input the third reset control signal, turn on the third reset circuit, and apply the holding voltage to the first end of the drive circuit through the third reset circuit; in the data writing phase, input the gate scan signal, turn on the data writing circuit, write the data signal into the control end of the drive circuit through the data writing circuit, and store the written data signal through the storage circuit; in the light-emitting phase, stop inputting the gate scan signal, turn off the data writing circuit, so that the drive circuit will generate a driving current under the control of the data signal stored in the storage circuit to drive the light-emitting element to emit light, and the on time length of the drive circuit is greater than the effective time length of the third reset control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0023] Figure 1A is a schematic diagram of a 2T1C pixel circuit;

[0024] Figure 1B is a schematic diagram of another 2T1C pixel circuit;

[0025] Figure 2A A schematic block diagram of a pixel circuit provided for at least some embodiments of the present disclosure;

[0026] Figure 2B for Figure 2A A circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG;

[0027] Figure 2C for Figure 2B A signal timing diagram of a driving method for a pixel circuit shown in FIG.

[0028] Figure 3A A schematic block diagram of a pixel circuit provided for at least some embodiments of the present disclosure;

[0029] Figure 3B for Figure 3A A circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG;

[0030] Figure 3C for Figure 3B A signal timing diagram of a driving method for a pixel circuit shown in FIG.

[0031] Figure 4A A schematic block diagram of a pixel circuit provided for at least some embodiments of the present disclosure;

[0032] Figure 4B for Figure 4A A circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG;

[0033] Figure 4C for Figure 4B A signal timing diagram of a driving method for a pixel circuit shown in FIG.

[0034] Figure 5A A schematic block diagram of a pixel circuit provided for at least some embodiments of the present disclosure;

[0035] Figure 5B for Figure 5A A circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG;

[0036] Figure 5C for Figure 5B A signal timing diagram of a driving method for a pixel circuit shown in ;

[0037] Figure 5D for Figure 5B Another signal timing diagram of the driving method of the pixel circuit shown in;

[0038] Figure 6A A schematic block diagram of a pixel circuit provided for at least some embodiments of the present disclosure;

[0039] Figure 6B for Figure 6A A circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG;

[0040] Figure 6C for Figure 6B A signal timing diagram of a driving method for a pixel circuit shown in FIG.

[0041] Figure 7A A schematic block diagram of a pixel circuit provided for at least some embodiments of the present disclosure;

[0042] Figure 7B for Figure 7A A circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG;

[0043] Figure 7C for Figure 7B A signal timing diagram of a driving method for a pixel circuit shown in FIG.

[0044] Figure 8A A schematic block diagram of a pixel circuit provided for at least some embodiments of the present disclosure;

[0045] Figure 8B for Figure 8A A circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG;

[0046] Figure 8C for Figure 8B A signal timing diagram of a driving method of a pixel circuit shown in ; and

[0047] 9A to 9F Each of them is a schematic diagram of a display panel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0049] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0050] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0051] The pixel circuit in the OLED display panel generally adopts a matrix drive mode, which is divided into active matrix (AM) drive and passive matrix (PM) drive according to whether switching components are introduced in each pixel unit. Among them, the AMOLED display panel integrates a group of thin-film transistors and storage capacitors in the pixel circuit of each pixel. By controlling the drive of the thin-film transistors and storage capacitors, the drive current flowing through the OLED is controlled, so that the OLED can emit light as needed. Therefore, the AMOLED display panel requires a small drive current, low power consumption, and a longer lifespan, which can meet the needs of large-size displays with high resolution and multiple grayscales. At the same time, AMOLED display panels have obvious advantages in viewing angle, color reproduction, power consumption, and response time, and are suitable for display devices with high information content and high resolution.

[0052] The basic pixel circuit used in the AMOLED display panel may be a 2T1C pixel circuit, that is, using two TFTs (Thin-film transistors) and a storage capacitor Cs to realize the basic function of driving the OLED to emit light.

[0053] Figure 1A and Figure 1B Schematic diagrams of two 2T1C pixel circuits are shown respectively.

[0054] like Figure 1A As shown, a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs. For example, the gate of the switching transistor T0 is connected to a scan line to receive a scan signal Scan1, the source is connected to a data signal line to receive a data signal Vdata, and the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected to a first voltage terminal to receive a first voltage VDD (high voltage), and the drain is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and the first voltage terminal; the negative terminal of the OLED is connected to a second voltage terminal to receive a second voltage Vss (low voltage, such as a ground voltage). The driving method of the 2T1C pixel circuit is to control the brightness (grayscale) of the pixel via two TFTs and the storage capacitor Cs. When the scan signal Scan1 is applied through the scan line to turn on the switch transistor T0, the data signal Vdata sent by the data driving circuit through the data signal line will charge the storage capacitor Cs through the switch transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs. The stored data signal Vdata controls the conduction degree of the drive transistor N0, thereby controlling the current flowing through the drive transistor to drive the OLED to emit light. That is, this current determines the grayscale of the pixel. Figure 1A In the 2T1C pixel circuit shown, the switch transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.

[0055] like Figure 1B As shown, another 2T1C pixel circuit also includes a switch transistor T0, a driving transistor N0 and a storage capacitor Cs, but the connection method thereof is slightly changed, and the driving transistor N0 is an N-type transistor. Figure 1B The pixel circuit is relative to Figure 1A The changes include: the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage VDD (high voltage), and the negative terminal is connected to the drain of the driving transistor N0, and the source of the driving transistor N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage). One end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and the second voltage terminal. The working method of the 2T1C pixel circuit is basically the same as Figure 1A The pixel circuits shown are basically the same and will not be described again here.

[0056] In addition, for Figure 1A and Figure 1BIn the pixel circuit shown, the switch transistor T0 is not limited to an N-type transistor, but may also be a P-type transistor, whereby the polarity of the scanning signal Scan1 that controls its conduction or cutoff can be changed accordingly.

[0057] OLED display panels often experience screen flickering when switching between high and low frequencies. This flickering affects high-quality images and therefore requires improvement. The reason for this is that in these OLED display panels, the driver transistor (DTFT) in the pixel circuit is made of a low-temperature polycrystalline silicon semiconductor as the active layer. Due to the high number of defect states in its channel, it exhibits a significant hysteresis effect. The hysteresis effect of a TFT device refers to the uncertainty in the device's electrical characteristics under a certain bias voltage. That is, the magnitude of the TFT device's current depends not only on the current bias voltage but also on the state of the TFT device at the previous moment. The hysteresis effect of TFTs has already posed a threat to current flat-panel display technology. For example, images from one moment in time often remain in the image displayed at the next moment, resulting in display errors. The hysteresis effect of TFT devices is related to traps in the gate dielectric, semiconductor material, and the interface states between them. These traps capture and release charge, causing changes in the TFT device's threshold voltage. This, in turn, causes changes in the channel carrier concentration under the same bias voltage, thereby altering the TFT's electrical characteristics.

[0058] Therefore, based on the above-mentioned 2T1C basic pixel circuit, an active layer with a weaker hysteresis effect is used to prepare the DTFT, and the DTFT is further reset during the reset or programming stage so that the DTFT characteristics can return to the initial state as quickly as possible, thereby reducing afterimages, flickering and other phenomena at low frequencies, and thus improving image quality.

[0059] At least some embodiments of the present disclosure provide a pixel circuit. The pixel circuit includes a drive circuit, a data write circuit, a storage circuit, and a first reset circuit; wherein the drive circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control a drive current flowing through the first terminal and the second terminal for driving a light-emitting element to emit light; the data write circuit is configured to write a data signal to the control terminal of the drive circuit under the control of a gate scan signal; the storage circuit is configured to store the data signal; the first reset circuit is configured to apply a first initialization voltage to the control terminal of the drive circuit under the control of a first reset control signal; wherein the drive circuit and the data write circuit include N-type thin-film transistors. The first reset circuit includes an N-type oxide thin-film transistor.

[0060] Some embodiments of the present disclosure also provide a driving method and a display panel corresponding to the above-mentioned pixel circuit.

[0061] In the pixel circuit provided by the embodiments of the present disclosure, the drive circuit and data write circuit include N-type thin-film transistors. The first reset circuit includes an N-type oxide thin-film transistor, which can reduce low-frequency leakage, maintain the voltage at the control terminal of the drive circuit to prevent flickering, and improve TFT device hysteresis, reducing low-frequency afterimages.

[0062] Some embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0063] Figure 2A A schematic block diagram of a pixel circuit provided in at least some embodiments of the present disclosure. Figure 2A As shown, the pixel circuit 10 includes a driving circuit 100 , a data writing circuit 200 , a storage circuit 300 , a first reset circuit 410 and a light emitting element 700 .

[0064] For example, the driving circuit 100 includes a first terminal 110, a second terminal 120 and a control terminal 130, and is configured to control a driving current flowing through the first terminal 110 and the second terminal 120 for driving the light-emitting element 700 to emit light. For example, the driving circuit 100 includes an N-type thin film transistor, such as an N-type oxide thin film transistor. For example, in some embodiments, during the light-emitting stage, the driving circuit 100 can provide a driving current to the light-emitting element 700 to drive the light-emitting element 700 to emit light, and can provide a corresponding driving current to emit light according to the grayscale to be displayed (different grayscales correspond to different data signals). For example, the light-emitting element 700 can adopt an organic light-emitting diode (OLED), a mini light-emitting diode (Mini LED), a micro light-emitting diode (MicroLED), a quantum dot light-emitting diode (QLED), an inorganic light-emitting diode, etc. The embodiments of the present disclosure include but are not limited to the above.

[0065] For example, the first reset circuit 410 is configured to apply a first initialization voltage Vinit1 to the control terminal 130 of the driver circuit 100 in response to a first reset control signal RST1. For example, the first reset circuit 410 may be an N-type oxide thin film transistor. For example, in some embodiments, during the initialization phase, the first reset circuit 410 is turned on in response to the first reset control signal RST1, thereby applying the first initialization voltage Vinit1 to the control terminal 130 of the driver circuit 100 to initialize the driver circuit 100. N-type oxide thin film transistors may use IGZO (Indium Gallium Zinc Oxide) or the like as the active layer of the thin film transistor. Compared to using LTPS (Low Temperature Polysilicon) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin film transistor, this can effectively reduce the size of the transistor and reduce leakage current, thereby making the pixel circuit suitable for low-frequency driving while also increasing the resolution of the display panel.

[0066] For example, the data write circuit 200 is configured to write the data signal Vdata transmitted by the data line into the control terminal 130 of the driver circuit 100 in response to the gate scan signal GN. For example, the data write circuit 200 includes an N-type thin film transistor, such as an N-type oxide thin film transistor. For example, in some embodiments, during the data write phase, the data write circuit 200 is turned on in response to the gate scan signal GN, thereby writing the data signal Vdata transmitted by the data line into the control terminal 130 of the driver circuit 100 and storing it in the storage circuit 300. In this way, during the light-emitting phase, the driver circuit 100 generates a driving current to drive the light-emitting element 700 to emit light according to the data signal Vdata.

[0067] For example, the storage circuit 300 is configured to store the written data signal Vdata and electrically connects the control terminal 130 and the second terminal 120 of the driving circuit 100. For example, in some embodiments, the storage circuit 300 includes a storage capacitor. During the data writing and storage phase, the storage capacitor can receive and store the data signal Vdata written by the data writing circuit 200. The storage circuit 300 electrically connects the control terminal 130 and the second terminal 120 of the driving circuit 100, so that information related to the threshold voltage Vth of the driving circuit is also stored in the storage capacitor.

[0068] For example, in at least some embodiments of the present disclosure, Figure 2A Based on the circuit structure shown, as Figure 3AAs shown, the pixel circuit 10 may further include a second reset circuit 420, which is configured to apply a second initialization voltage Vinit2 to the second terminal 120 of the driving circuit 100 under the control of a second reset control signal RST2. For example, the second reset circuit 420 may include an N-type thin film transistor, such as an N-type oxide thin film transistor. For example, in some embodiments, during the initialization phase, the second reset circuit 420 is turned on in response to the second reset control signal RST2, thereby applying the second initialization voltage Vinit2 to the second terminal 120 of the driving circuit 100, so that the potential of the second terminal 120 of the driving circuit 100 is initialized to the second initialization voltage Vinit2 according to the second initialization voltage Vinit2, thereby performing an initialization operation on the second terminal of the driving circuit 100 and eliminating the influence of the previous light-emitting phase.

[0069] For example, in at least some embodiments of the present disclosure, Figure 3A Based on the circuit structure shown, as Figure 4A As shown, the pixel circuit 10 may further include a first light-emitting control circuit 500. For example, in some embodiments, the first light-emitting control circuit 500 may be an N-type thin-film transistor, such as an N-type oxide thin-film transistor. For example, in some embodiments, the first light-emitting control circuit 500 is configured to apply a first power supply voltage VDD to the first terminal 110 of the driver circuit 100 in response to a first light-emitting control signal EM1, thereby causing the driver circuit 100 to generate a drive current. For example, during a light-emitting phase, the first light-emitting control circuit 500 is turned on in response to the first light-emitting control signal EM1 and applies the first power supply voltage VDD to the first terminal 110 of the driver circuit 100. As a result, the driver circuit 100 generates a drive current due to the combined action of the voltages at its control terminal and the first terminal. During a non-light-emitting phase, the first light-emitting control circuit 500 is turned off in response to the first light-emitting control signal EM1, thereby preventing the driver circuit 100 from generating a drive current. This prevents the light-emitting element 700 from emitting light, thereby improving the contrast of the corresponding display device.

[0070] For example, in at least some embodiments of the present disclosure, Figure 4A Based on the circuit structure shown, as Figure 5A As shown, the pixel circuit 10 may further include a third reset circuit 430. For example, in some embodiments, the third reset circuit 430 may be an N-type thin film transistor, such as an N-type oxide thin film transistor, which is configured to apply a hold voltage Vhold to the first terminal 110 of the driver circuit 100 under the control of the third reset control signal RST3 to reduce characteristic drift of the driver circuit 100. For example, in some embodiments, the third reset control signal RST3 and the first reset control signal RST1 are both on signals for at least part of the time period.

[0071] For example, in at least some embodiments of the present disclosure, Figure 5D As shown, the third reset control signal RST3 and the first reset control signal RST1 can be the same control signal, that is, they can use the same timing to achieve the effect of reducing the hysteresis of the driving circuit 100.

[0072] It should be noted that, in the embodiments of the present disclosure, the first reset control signal RST1, the second reset control signal RST2 and the third reset control signal RST3 are intended to distinguish three control signals (e.g., reset control signals) with different timings. For example, in some embodiments, when the pixel circuits 10 of multiple pixel units in the display panel are arranged in an array, the second reset control signal RST2 and the third reset control signal RST3 can be in a superior-subordinate relationship with each other. For example, for a row of pixel units, the second reset control signal RST2 for controlling the second reset circuit 420 in the pixel circuit 10 of the pixel units in this row can also be used to control the third reset circuit 430 in the pixel circuit 10 of the pixel units in the previous row, that is, as the third reset control signal RST3 in the pixel circuit 10 of the pixel units in the previous row; similarly, the third reset control signal RST3 for controlling the third reset circuit 430 in the pixel circuit 10 of the pixel units in this row can also be used to control the second reset circuit 420 in the pixel circuit 10 of the pixel units in the next row, that is, as the second reset control signal RST2 in the pixel circuit 10 of the pixel units in the next row. In this way, the second reset control signal RST2 and the third reset control signal RST3 can be provided by the same GOA (Gate Driver On Array), which is beneficial to simplifying display wiring, improving resolution, and achieving narrow borders.

[0073] For example, in at least some embodiments of the present disclosure, Figure 3A Based on the circuit structure shown, as Figure 6A As shown, the pixel circuit 10 may further include a second light-emitting control circuit 600. For example, in some embodiments, the second light-emitting control circuit 600 may be an N-type thin film transistor, such as an N-type oxide thin film transistor. For example, in some embodiments, the second light-emitting control circuit 600 is configured to apply a driving current to the first electrode of the light-emitting element 700 under the control of the second light-emitting control signal EM2, so as to cause the light-emitting element 700 to emit light. For example, in the light-emitting phase, the second light-emitting control circuit 600 is turned on in response to the second light-emitting control signal EM2, so that the driving circuit 100 can apply a driving current to the light-emitting element 700 through the second light-emitting control circuit 600 to cause it to emit light; while in the non-light-emitting phase, the second light-emitting control circuit 600 is turned off in response to the second light-emitting control signal EM2, preventing the light-emitting element 700 from emitting light, thereby improving the contrast of the corresponding display device.

[0074] For example, in at least some embodiments of the present disclosure, Figure 2A Based on the circuit structure shown, as Figure 7A As shown, the pixel circuit 10 may further include a voltage transmission circuit 800. For example, in some embodiments, the voltage transmission circuit 800 may be an N-type thin film transistor, such as an N-type oxide thin film transistor, which is configured to, under the control of the voltage transmission control signal Vtc, transmit a second power supply voltage, such as VSS, to the first terminal 110 of the driving circuit 100 during a first time period, and transmit a first power supply voltage, such as VDD, which is different from the second power supply voltage, to the first terminal 110 of the driving circuit 100 during a second time period, such as after t2.

[0075] For example, in at least some embodiments of the present disclosure, Figure 3A Based on the circuit structure shown, as Figure 8A As shown, the pixel circuit 10 may further include a second reset circuit 420 while excluding the first reset circuit 410. For example, in some embodiments, the data signal terminal transmits a reference voltage Vref, such as the first initialization voltage Vinit1, to the first terminal of the data write circuit 200 during a first time period, such as t1, t2, and t3, to complete an initialization operation on the control terminal 130 of the driving circuit 100, and the data signal terminal transmits a data signal Vdata to the first terminal of the data write circuit 200 during a second time period, such as t3, t4, and t5, to write and store the data signal Vdata in the storage circuit 300, so that the driving circuit 100 generates a driving current for driving the light-emitting element 700 to emit light according to the data signal Vdata during the light-emitting phase.

[0076] Figure 2B for Figure 2A A circuit structure diagram of a specific example of a pixel circuit is shown in FIG. Figure 2B As shown, the pixel circuit 10 includes first to third transistors T1, T2, and T3, a storage capacitor C1, and a light-emitting element LE. For example, the first transistor T1 is used as a driving transistor, and the second and third transistors T2 and T3 are used as switching transistors. For example, the light-emitting element LE can be an OLED. The embodiments of the present disclosure include but are not limited to this. The following embodiments are described using OLED as an example and will not be repeated here.

[0077] The OLED can be of various types, such as top-emitting or bottom-emitting, and can emit red, green, blue, or white light, etc., and the embodiments of the present disclosure are not limited thereto. Furthermore, it should be noted that the following embodiments are described using N-type transistors as an example, but this does not constitute a limitation of the embodiments of the present disclosure.

[0078] For example, the first to third transistors T1, T2, and T3 may all be N-type thin film transistors, wherein the first to third transistors T1, T2, and T3 may all be N-type oxide thin film transistors. When using N-type oxide thin film transistors, indium gallium zinc oxide (IGZO) may be used as the active layer of the thin film transistor. Compared with using low temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0079] For example, Figure 2B As shown, the driving circuit 100 can be implemented as a first transistor T1, where the first transistor T1 can be an N-type thin film transistor, such as an N-type oxide thin film transistor. The gate of the first transistor T1 serves as the control terminal 130 of the driving circuit 100 and is connected to the first node N1. The first electrode of the first transistor T1 serves as the first terminal 110 of the driving circuit 100 and is connected to the first power supply terminal VDD via the third node N3 to receive the first power supply voltage VDD. The second electrode of the first transistor T1 serves as the second terminal 120 of the driving circuit 100 and is connected to the second node N2. For example, the first power supply voltage VDD can be a driving voltage, such as a high voltage (relative to the second power supply voltage VSS connected to the light-emitting element, which will be described in detail below).

[0080] For example, Figure 2B As shown, the data writing circuit 200 can be implemented as a second transistor T2, wherein the second transistor T2 can be an N-type thin film transistor, such as an N-type oxide thin film transistor. The gate of the second transistor T2 is connected to the gate scan signal terminal to receive the gate scan signal GN. The first electrode of the second transistor T2 is connected to the data signal terminal to receive the data signal Vdata, and the second electrode of the second transistor T2 is connected to the first node N1 (the control terminal 130 of the driving circuit 100).

[0081] For example, Figure 2B As shown, the storage circuit 300 can be implemented as a storage capacitor C1, the first end of the storage capacitor C1 is connected to the first node N1 (the control end 130 of the driving circuit 100), and the second end of the storage capacitor C1 is connected to the second node N2 (the second end 120 of the driving circuit 100).

[0082] For example, Figure 2BAs shown, the first reset circuit 410 can be implemented as a third transistor T3, wherein the third transistor T3 is an N-type oxide thin film transistor. The gate of the third transistor T3 is connected to the first reset control signal terminal to receive the first reset control signal RST1, the first electrode of the third transistor T3 is connected to the first initialization voltage terminal to receive the first initialization voltage Vinit1, and the second electrode of the third transistor T3 is connected to the first node N1 (the control terminal 130 of the driving circuit 100).

[0083] Figure 3B for Figure 3A A circuit structure diagram of a specific example of a pixel circuit is shown in FIG. Figure 3B As shown, the pixel circuit 10 includes: first to fourth transistors T1, T2, T3, T4, a storage capacitor C1 and a light emitting element LE. Figure 3B The pixel circuit 10 shown is compared Figure 2B The differences of the pixel circuit 10 shown are: Figure 3B The pixel circuit 10 shown further includes a fourth transistor T4 for implementing a second reset circuit 420 . Figure 3B The rest of the pixel circuit 10 shown is similar to Figure 2B The pixel circuit 10 shown is the same and will not be described again here.

[0084] For example, the first to fourth transistors T1, T2, T3, and T4 may all be N-type thin film transistors, wherein the first to fourth transistors T1, T2, T3, and T4 may all be N-type oxide thin film transistors. When using N-type oxide thin film transistors, indium gallium zinc oxide (IGZO) may be used as the active layer of the thin film transistor. Compared with using low temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0085] For example, Figure 3B As shown, the second reset circuit 420 can be implemented as a fourth transistor T4, wherein the fourth transistor T4 can be an N-type thin film transistor, such as an N-type oxide thin film transistor. The gate of the fourth transistor T4 is connected to the second reset control signal terminal to receive the second reset control signal RST2, the first electrode of the fourth transistor T4 is connected to the second initialization voltage terminal to receive the second initialization voltage Vinit2, and the second electrode of the fourth transistor T4 is connected to the second node N2 (the second terminal 120 of the driving circuit 100).

[0086] Figure 4B for Figure 4AA circuit structure diagram of a specific example of a pixel circuit is shown in FIG. Figure 4B As shown, the pixel circuit 10 includes: first to fifth transistors T1, T2, T3, T4, T5, a storage capacitor C1 and a light emitting element LE. Figure 4B The pixel circuit 10 shown is compared Figure 3B The differences of the pixel circuit 10 shown are: Figure 4B The pixel circuit 10 shown further includes a fifth transistor T5 for implementing the first light emission control circuit 500 . Figure 4B The rest of the pixel circuit 10 shown is similar to Figure 3B The pixel circuit 10 shown is the same and will not be described again here.

[0087] For example, the first to fifth transistors T1, T2, T3, T4, and T5 may all be N-type thin film transistors, wherein the first to fifth transistors T1, T2, T3, T4, and T5 may all be N-type oxide thin film transistors. When N-type oxide thin film transistors are used, indium gallium zinc oxide (IGZO) may be used as the active layer of the thin film transistor. Compared with using low temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0088] For example, Figure 4B As shown, the first light-emitting control circuit 500 can be implemented as a fifth transistor T5, wherein the fifth transistor T5 can be an N-type thin film transistor, such as an N-type oxide thin film transistor, the gate of the fifth transistor T5 is connected to the first light-emitting control terminal to receive the first light-emitting control signal EM1, the first electrode of the fifth transistor T5 is connected to the first power supply terminal to receive the first power supply voltage VDD, and the second electrode of the fifth transistor is connected to the third node N3 (the first terminal 110 of the driving circuit 100).

[0089] Figure 5B for Figure 5A A circuit structure diagram of a specific example of a pixel circuit is shown in FIG. Figure 5B As shown, the pixel circuit 10 includes: first to sixth transistors T1, T2, T3, T4, T5, T6, a storage capacitor C1 and a light emitting element LE. Figure 5B The pixel circuit 10 shown is compared Figure 4B The differences of the pixel circuit 10 shown are: Figure 5B The pixel circuit 10 shown further includes a sixth transistor T6 for implementing a third reset circuit 430 . Figure 5B The rest of the pixel circuit 10 shown is similar to Figure 4B The pixel circuit 10 shown is the same and will not be described again here.

[0090] For example, the first to sixth transistors T1, T2, T3, T4, T5, and T6 may all be N-type thin film transistors, wherein the first to sixth transistors T1, T2, T3, T4, T5, and T6 may all be N-type oxide thin film transistors. When using N-type oxide thin film transistors, indium gallium zinc oxide (IGZO) may be used as the active layer of the thin film transistor. Compared with using low temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0091] For example, Figure 5B As shown, the third reset circuit 430 can be implemented as a sixth transistor T6, wherein the sixth transistor T6 can be an N-type thin film transistor, such as an N-type oxide thin film transistor. The gate of the sixth transistor T6 is connected to the third reset control signal terminal to receive the third reset control signal RST3, the first electrode of the sixth transistor T6 is connected to the hold voltage terminal to receive the hold voltage Vhold, and the second electrode of the sixth transistor T6 is connected to the third node N3 (the first terminal 110 of the driving circuit 100).

[0092] Figure 6B for Figure 6A A circuit structure diagram of a specific example of a pixel circuit is shown in FIG. Figure 6B As shown, the pixel circuit 10 includes transistors T1 , T2 , T3 , T4 , T7 , a storage capacitor C1 and a light emitting element LE. Figure 6B The pixel circuit 10 shown is compared Figure 3B The differences of the pixel circuit 10 shown are: Figure 6B The pixel circuit 10 shown further includes a seventh transistor T7 for implementing the second light emitting control circuit 600 . Figure 6B The rest of the pixel circuit 10 shown is similar to Figure 3B The pixel circuit 10 shown is the same and will not be described again here.

[0093] For example, the transistors T1, T2, T3, T4, and T7 can all be N-type thin film transistors, wherein the transistors T1, T2, T3, T4, and T7 can all be N-type oxide thin film transistors. When using N-type oxide thin film transistors, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin film transistor. Compared with using low-temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0094] For example, Figure 6B As shown, the second light emitting control circuit 600 can be implemented as a seventh transistor T7, wherein the seventh transistor T7 is an N-type thin film transistor, such as an N-type oxide thin film transistor. The gate of the seventh transistor T7 is connected to the second light emitting control terminal to receive the second light emitting control signal EM2, the first electrode of the seventh transistor T7 is connected to the second node N2 (the second terminal 120 of the driving circuit 100), and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element EL.

[0095] Figure 7B for Figure 7A A circuit structure diagram of a specific example of a pixel circuit is shown in FIG. Figure 7B As shown, the pixel circuit 10 includes transistors T1 , T2 , T3 , T8 , a storage capacitor C1 and a light emitting element LE. Figure 7B The pixel circuit 10 shown is compared Figure 2B The differences of the pixel circuit 10 shown are: Figure 7B The pixel circuit 10 shown further includes an eighth transistor T8 for implementing the voltage transfer circuit 800 . Figure 7B The rest of the pixel circuit 10 shown is similar to Figure 2B The pixel circuit 10 shown is the same and will not be described again here.

[0096] For example, the transistors T1, T2, T3, T4, and T7 can all be N-type thin film transistors, wherein the transistors T1, T2, T3, T4, and T7 can all be N-type oxide thin film transistors. When using N-type oxide thin film transistors, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin film transistor. Compared with using low-temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0097] For example, Figure 7B As shown, the second light-emitting control circuit 600 can be implemented as an eighth transistor T8, wherein the eighth transistor T8 is an N-type thin-film transistor, such as an N-type oxide thin-film transistor. The gate of the eighth transistor T8 is connected to the voltage transmission control signal terminal to receive the voltage transmission control signal Vtc. The first electrode of the eighth transistor T8 is connected to the first power supply terminal, and the second electrode of the eighth transistor T8 is connected to the third node N3 (the first terminal 110 of the driver circuit 100). The first power supply terminal is configured to transmit a second power supply voltage, such as VSS, to the first terminal 110 of the driver circuit 100 during a first time period, and to transmit a first power supply voltage, such as VDD, which is different from the second power supply voltage, to the first terminal 110 of the driver circuit 100 during a second time period.

[0098] Figure 8B for Figure 8A A circuit structure diagram of a specific example of a pixel circuit is shown in FIG. Figure 8B As shown, the pixel circuit 10 includes transistors T1 , T2 , T4 , T5 , a storage capacitor C1 and a light emitting element LE. Figure 8B The pixel circuit 10 shown is compared Figure 3B The differences of the pixel circuit 10 shown are: Figure 8B The pixel circuit 10 shown does not include the third transistor T3 for implementing the first reset circuit 410 . Figure 8B The rest of the pixel circuit 10 shown is similar to Figure 3B The pixel circuit 10 shown is the same and will not be described again here.

[0099] For example, the transistors T1 , T2 , T4 , and T5 may all be N-type thin film transistors, such as N-type oxide thin film transistors.

[0100] For example, Figure 8A and 8B As shown, in some embodiments, the data signal terminal transmits a reference voltage Vref, for example, a first initialization voltage Vinit1, to the first terminal of the second transistor T2 during a first time period, and after the second transistor T2 is turned on in response to the gate scan signal GN, transmits the first initialization voltage Vinit1 to the control terminal 130 of the driving circuit 100 to complete the initialization operation of the control terminal 130 of the driving circuit 100, and, during a second time period, the data signal terminal transmits a data signal Vdata to the first terminal of the data writing circuit 200, and after the second transistor T2 is turned on in response to the gate scan signal GN, writes the data signal Vdata into the control terminal 130 of the driving circuit 100 and stores it in the storage circuit 300, so that during the light-emitting stage, the driving circuit 100 generates a corresponding driving current according to the intensity of the data signal Vdata to drive the light-emitting element 700 to emit light.

[0101] It should be noted that in the embodiments of the present disclosure, the storage capacitor C1 can be at least partially a capacitor device manufactured by a process, for example, by making a special capacitor electrode to realize the capacitor device, and the various electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc., and the capacitor can also be at least partially a parasitic capacitance between various devices, which can be realized by the transistor itself and other devices and circuits. The connection method of the capacitor is not limited to the method described above, and can also be other applicable connection methods, as long as the voltage of the corresponding node can be stored.

[0102] It should be noted that, in the description of the embodiments of the present disclosure, the first node N1 , the second node N2 and the third node N3 do not represent components that must actually exist, but represent junction points of related electrical connections in a circuit diagram.

[0103] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0104] In addition, the transistors in the embodiments of the present disclosure are all described using N-type transistors as an example. In this case, the first electrode of the transistor is the drain electrode, and the second electrode is the source electrode. When using N-type oxide thin-film transistors, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin-film transistor. Compared with using low-temperature polysilicon (LTPS) or amorphous silicon (such as hydrogenated amorphous silicon) as the active layer of the thin-film transistor, it can effectively reduce the size of the transistor and prevent leakage current.

[0105] It should be noted that in the embodiments of the present disclosure, the cathode of the light emitting element LE (for example, the common cathode of multiple light emitting elements) is connected to the second power supply voltage VSS (low voltage) as an example for description, and the embodiments of the present disclosure include but are not limited to this. For example, the anode of the light emitting element LE can also be connected to the first power supply voltage VDD (high voltage), and its cathode can be directly or indirectly connected to the driving circuit, for example, refer to Figure 1B The 2T1C pixel circuit shown.

[0106] It should be noted that, in the pixel circuit provided in the embodiment of the present disclosure, the “effective voltage” refers to the voltage that can turn on the operated transistor included therein, and accordingly, the “invalid voltage” refers to the voltage that cannot turn on the operated transistor included therein (that is, the transistor is cut off). Depending on factors such as the type of transistor (e.g., N-type) in the circuit structure of the shift register unit, the effective voltage may be higher or lower than the invalid voltage. For example, in the embodiment of the present disclosure, when all transistors are N-type transistors, the effective voltage is a high voltage and the invalid voltage is a low voltage.

[0107] At least some embodiments of the present disclosure also provide a method for driving a pixel circuit. Figure 2C The signal timing diagram of a driving method of a pixel circuit provided by at least some embodiments of the present disclosure is as follows. Figure 2C The signal timing diagram shown in Figure 2A The pixel circuit shown is specifically implemented as Figure 2B As an example, the pixel circuit structure shown in FIG. Figure 2A The working principle of the pixel circuit shown in FIG. Figure 2C The voltage levels of the signal timing diagram shown in the figure are only schematic and do not represent the actual voltage values ​​or relative proportions. In the embodiment of the present disclosure, the high voltage signal corresponds to the turn-on signal of the N-type transistor, and the low voltage signal corresponds to the turn-off signal of the N-type transistor.

[0108] For example, Figure 2C As shown, the driving method provided in this embodiment may include three stages, namely, an initialization stage p1, a data writing stage p2, and a light emitting stage p3. Figure 2C The timing waveforms of each signal in each stage are shown in FIG.

[0109] During the initialization phase p1, a first reset control signal RST1 is input, turning on (i.e., conducting) the first reset circuit 410, and resetting the control terminal 130 of the driver circuit 100 via the first reset circuit 410. For example, during the initialization phase p1, the third transistor T3 is turned on by the high voltage of the first reset control signal RST1, initializing the first node N1 to Vinit1. For example, Vinit1 is a low voltage (e.g., grounded or another low voltage), and the voltage of the gate of the first transistor T1 (i.e., the first node N1) becomes Vinit1, thereby turning off the first transistor T1 and rendering the light-emitting device EL non-luminous. For example, the third transistor T3 can be an oxide thin film transistor to reduce low-frequency leakage, thereby maintaining a low voltage at the first node N1. This keeps the first transistor T1 in the off state for a long time, thereby rendering the light-emitting device EL non-luminous for a long time, and thus eliminating flicker. Simultaneously, the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.

[0110] During the data write phase p2, the gate scan signal GN is input, turning on the data write circuit 200. The data signal Vdata is written into the control terminal 130 of the drive circuit 100 via the data write circuit 200, and the written data signal Vdata is stored via the storage circuit 300. For example, during the data write phase, the first reset control signal RST1 becomes a low voltage, thereby turning off the third transistor T3, while the gate scan signal GN becomes a high voltage, turning on the second transistor T2. At this time, the voltage of the first node N1 changes from the first initialization voltage Vinit1 to a higher voltage, namely, the data voltage Vdata (the voltage of the data signal Vdata), thereby turning on the first transistor T1. At the same time, since the voltage of the first node N1 becomes the data voltage Vdata, the storage capacitor C1 can store the data voltage Vdata, thereby completing the data write.

[0111] It should be noted that, in the data writing phase p2, since the first transistor T1 is turned on, the leakage current Ids flows from the third node N3 to the second node N2, and the voltage of the second node N2 gradually increases.

[0112] During the light-emitting phase p3, the gate scan signal GN is stopped from being input, the data write circuit 200 is turned off, and the drive circuit 100 generates a drive current under the control of the data signal Vdata stored in the storage circuit 300, causing the light-emitting element 700 to emit light. For example, during the light-emitting phase p3, the first reset control signal RST1 becomes a low voltage, thereby turning off the third transistor T3. Simultaneously, the second transistor T2 is turned off by the low voltage of the gate scan signal GN, thereby preventing the input of the data voltage Vdata. At this time, the first transistor T1 remains in the on state under the control of the data signal Vdata stored in the storage capacitor C1, and the voltage of the second node N2 increases to exceed the turn-on voltage of the light-emitting device EL, and the light-emitting device EL begins to emit light. Because it is a constant current drive, the voltage of the second node N2 will eventually reach the turn-on voltage of the light-emitting device. At the same time, since the first node N1 and the second node N2 are connected through the first capacitor C1, the voltage of the first node N1 also follows the voltage of the second node N2 and rises to a stable state. Even if the voltages of the N1 and N2 nodes change, the voltage difference between the N1 and N2 nodes, that is, the voltage difference Vgs between the gate and source of the first transistor T1, can remain unchanged. Therefore, the light-emitting current I is constant, as described in the following formula:

[0113] I=kμ(Vdata-ΔV) 2

[0114] Wherein, I is the light emitting current, k is a constant coefficient, μ is the mobility of the first transistor T1 , Vdata is the data signal voltage, and ΔV is the gradually increasing value of the voltage of the second node N2 .

[0115] At least some embodiments of the present disclosure also provide a method for driving a pixel circuit. Figure 3C The signal timing diagram of a driving method of a pixel circuit provided by at least some embodiments of the present disclosure is as follows. Figure 3C The signal timing diagram shown in Figure 3A The pixel circuit shown is specifically implemented as Figure 3B As an example, the pixel circuit structure shown in FIG. Figure 3A The working principle of the pixel circuit shown is explained.

[0116] For example, Figure 3C As shown, the driving method provided in this embodiment may include four stages, namely, an initialization stage t11, a threshold voltage compensation stage t22, a data writing and mobility compensation stage t33, and a light emitting stage t44. Figure 3C The timing waveforms of each signal in each stage are shown in FIG.

[0117] During the initialization phase t11, the first reset control signal RST1 and the second reset control signal RST2 are input, turning on (i.e., conducting) the first reset circuit 410 and the second reset circuit 420. The control terminal 130 of the driver circuit 100 is reset by the first reset circuit 410, and the second terminal 120 of the driver circuit 100 is reset by the second reset circuit 420. For example, during the initialization phase t11, the third transistor T3 is turned on by the high voltage of the first reset control signal RST1, initializing the first node N1 to the initialization voltage Vinit1. Since Vinit1 is a high voltage (e.g., it can be the first power supply voltage, such as VDD or other high voltage), the voltage of the gate of the first transistor T1 (i.e., the first node N1) becomes Vinit1. For example, during the initialization phase t11, the fourth transistor T4 is turned on by the high voltage of the second reset control signal RST2, initializing the second node N2 to the initialization voltage Vinit2. For example, Vinit2 can be a low voltage (e.g., grounded or another low voltage). For example, the voltage of Vinit2 can be less than the second power supply voltage (e.g., VSS), so that the voltage difference Vgs between the gate and source of the first transistor T1 is sufficiently large (e.g., greater than 7V), thereby quickly eliminating the hysteresis state. At the same time, because Vinit2 can be a low voltage, the second node N2 connected to the second electrode of the fourth transistor T4 is also a low voltage after the fourth transistor T4 is turned on, thereby placing the light-emitting device EL in a non-luminous state. For example, the third transistor T3 can be an oxide thin film transistor to reduce low-frequency leakage, so that the first node N1 maintains a low voltage, thereby keeping the first transistor T1 in the off state for a long time, and thus the light-emitting device EL in the non-luminous state for a long time, eliminating flicker. At the same time, the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.

[0118] During the threshold voltage compensation phase t22, the first reset control signal RST1 is input, turning on the first reset circuit 410. The first initialization voltage Vinit1 is applied to the control terminal 130 of the driver circuit 100 via the first reset circuit 410, thereby turning on the driver circuit 100. Simultaneously, the second reset control signal is stopped, turning off the second reset circuit 420. Thus, threshold compensation can be performed using the turned-on driver circuit 100 and storage circuit 300. For example, the first reset control signal RST1 can be maintained at a high voltage, thereby keeping the third transistor T3 turned on; the second reset control signal RST2 can be at a low voltage, thereby turning off the fourth transistor T4. The second transistor T2 is continuously turned off by the low voltage of the gate scan signal GN, thereby continuously preventing the input of the data signal Vdata. Simultaneously, the voltage at the first node N1 (i.e., the first initialization voltage Vinit1) is high, turning on the first transistor T1. Since the voltage VDD of the third node N3 is a high voltage, the voltage of the second node N2 gradually increases from the initial VSS until the voltage difference Vgs between the gate and the source (e.g., the second electrode) of the first transistor T1 is equal to its own threshold voltage Vth. At this time, the voltage V N2 is the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1. At the same time, the threshold voltage Vth of the first transistor T1 is written to both ends of the storage capacitor C1, thereby completing the threshold voltage compensation, as described in the following formula:

[0119] V N2 =Vinit1-Vth

[0120] Among them, V N2 is the voltage of the second node N2, Vinit1 is the voltage V of the second node N2 N2 is the first initialization voltage, and Vth is the threshold voltage of the first transistor T1.

[0121] During the data writing and mobility compensation phase t33, a gate scan signal GN is input, turning on the data writing circuit 200. The data signal Vdata is written to the control terminal 130 of the driving circuit 100 via the data writing circuit 200, and the written data signal Vdata is stored via the storage circuit 300. For example, the first reset control signal RST1 becomes a low voltage, thereby turning off the third transistor T3; the second reset control signal RST2 can be a low voltage, thereby turning off the fourth transistor T4, and the gate scan signal GN becomes a high voltage, thereby turning on the second transistor T2. At this time, the voltage at the first node N1 changes from the first initialization voltage Vinit1 to the data voltage Vdata (the voltage of the data signal Vdata), thereby turning on the first transistor T1. Simultaneously, since the voltage at the first node N1 changes to the data voltage Vdata, the storage capacitor C1 can store the data voltage Vdata, thereby completing the data writing. Since the light emitting device EL connected to the second node N2 can be regarded as a capacitor, and its capacitance is much larger than that of the first capacitor C1, the voltage of the second node N2 remains almost unchanged and remains at the difference between the first initialization voltage Vinit1 in the previous stage t22 and the threshold voltage Vth of the first transistor T1. Since the first transistor T1 is turned on, its driving current Ids flows from the third node N3 to the second node N2, and the voltage of the second node N2 gradually increases by ΔV. At this time, the voltage V N2 is the sum of the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 and the gradually increasing voltage ΔV, as described in the following formula:

[0122] V N2 =Vinit1-Vth+ΔV

[0123] Among them, V N2 is the voltage of the second node N2, Vinit1 is the voltage V of the second node N2 N2 is the first initialization voltage, Vth is the threshold voltage of the first transistor T1, and ΔV is the gradually rising value of the voltage of the second node N2.

[0124] The voltage of the first node N1 is still the data voltage Vdata due to the conduction of the second transistor T2. The driving current of the first transistor T1 is as described in the following formula:

[0125] Ids=kμ(Vgs-Vth) 2

[0126] Where, Ids is the driving current of the first transistor T1, k is a constant coefficient, μ is the mobility of the first transistor T1, Vgs is the voltage difference between the gate and source of the first transistor T1, and Vth is the threshold voltage of the first transistor T1. As can be seen from the above formula, the greater the driving current of the first transistor T1 and the mobility μ of the first transistor T1, the greater its driving current, the greater the voltage ΔV gradually increasing at the second node N2, and therefore the smaller the voltage difference Vgs between the gate and source of the first transistor T1, so (Vgs-Vth) 2 The smaller the value, the greater the mobility μ of the first transistor T1 is, so the driving current Ids of the first transistor T1 is corrected. For example, the driving currents of driving transistors with different mobilities at the same data voltage Vdata are not much different.

[0127] During light-emitting phase t44, the gate scan signal GN is stopped, the data write circuit 200 is turned off, and the driver circuit 100 generates a drive current under the control of the data signal Vdata stored in the storage circuit 300, causing the light-emitting element 700 to emit light. For example, the first reset control signal RST1 becomes a low voltage, thereby turning off the third transistor T3; the second reset control signal RST2 can be a low voltage, thereby turning off the fourth transistor T4. Simultaneously, the low voltage of the gate scan signal GN turns off the second transistor T2, preventing the input of the data voltage Vdata. At this time, the voltage at the second node N2 rises to exceed the turn-on voltage of the light-emitting device EL, and the light-emitting device EL begins to emit light. Because it is a constant current drive, the voltage at the second node N2 will eventually reach the turn-on voltage of the light-emitting device. At the same time, since the first node N1 and the second node N2 are connected via the first capacitor C1, the voltage at the first node N1 also rises to a stable state following the voltage at the second node N2. Even if the voltages at the N1 and N2 nodes change, the voltage difference between the N1 and N2 nodes, i.e., the voltage difference Vgs between the gate and source of the first transistor T1, can remain unchanged. Therefore, the light-emitting current I is constant, as described in the following formula:

[0128] I=kμ(Vdata-ΔV) 2

[0129] Where I is the light-emitting current, k is a constant coefficient, μ is the mobility of the first transistor T1, Vdata is the data signal voltage, and ΔV is the gradually increasing value of the voltage at the second node N2. Thus, this pixel circuit combines the technical effects of threshold voltage compensation, μ mobility compensation, and IR drop compensation.

[0130] For example, in order to simplify the circuit, the second reset control signal RST2 and the gate scan signal GN may share a set of GOA circuits, so as to simplify the wiring of the display screen, improve the resolution, and achieve a narrow frame.

[0131] At least some embodiments of the present disclosure also provide a method for driving a pixel circuit. Figure 6C A signal timing diagram of a pixel circuit driving method provided in at least some embodiments of the present disclosure. Figure 6C The driving method of the disclosed pixel circuit is almost the same as that of the above Figure 3C The disclosed pixel circuit driving method is the same. Figure 6C The signal timing diagram shown in Figure 6A The pixel circuit shown is specifically implemented as Figure 6B As an example, the pixel circuit structure shown in FIG. Figure 6A The working principle of the pixel circuit shown is explained.

[0132] For example, Figure 6C As shown, the driving method provided in this embodiment may include four stages, namely, an initialization stage t11, a threshold voltage compensation stage t22, a data writing and mobility compensation stage t33, and a light emitting stage t44. Figure 6C The timing waveforms of each signal in each stage are shown in FIG.

[0133] For example, with Figure 6C The signal timing diagram of the pixel circuit driving method shown corresponds to Figure 6B The pixel circuit 10 shown is compared with Figure 3C The signal timing diagram of the pixel circuit driving method shown corresponds to Figure 3B The pixel circuit 10 shown is different in that: Figure 6B The illustrated pixel circuit 10 includes a seventh transistor T7 for implementing the second light-emission control circuit 600. For example, the light-emitting device EL is connected to the second node N2 via the seventh transistor T7, thereby ensuring that the drain (e.g., the first electrode) of the first transistor T1 is always at a first power supply voltage, such as VDD. Furthermore, because the voltage difference Vgd between the gate and drain of the first transistor T1 is always less than the threshold voltage Vth of the first transistor T1, the first transistor T1 is only in the off state and the saturation state, thereby stabilizing the characteristics of the first transistor T1.

[0134] For example, the second initialization voltage Vinit2 can be lower than the second power supply voltage (e.g., VSS), so that the voltage difference Vgs between the gate and source of the first transistor T1 is sufficiently large (e.g., greater than 7V), thereby quickly eliminating the hysteresis state. However, because the voltage of the second node N2 is the second initialization voltage Vinit2, the light-emitting device EL is in an inverted state. When the inverted voltage is sufficiently large, a reverse drive current flows through the light-emitting device EL, which is detrimental to the long-term performance of the light-emitting device EL. Therefore, the presence of the seventh transistor T7 prevents the generation of the reverse drive current while also allowing the second initialization voltage Vinit2 to be sufficiently low (e.g., lower than the second power supply voltage) to quickly eliminate the hysteresis.

[0135] In the initialization phase t11, if Figure 6C As shown, the driving method provided by this embodiment is compared with Figure 3C The difference between the driving methods shown is that the second light emitting control signal EM2 is a low voltage and the seventh transistor T7 is turned off.

[0136] In the threshold voltage compensation stage t22, as Figure 6C As shown, the driving method provided by this embodiment is compared with Figure 3C The difference between the driving methods shown is that the second light emitting control signal EM2 is a low voltage and the seventh transistor T7 is turned off.

[0137] For example, in the data writing and mobility compensation phase t33, as shown in FIG. Figure 6C As shown, the driving method provided by this embodiment is compared with Figure 3C The difference between the driving methods shown is that the second light emitting control signal EM2 is a high voltage and the seventh transistor T7 is turned on.

[0138] For example, in the light-emitting stage t44, if Figure 6C As shown, the driving method provided by this embodiment is compared with Figure 3C The difference between the driving methods shown is that the second light emitting control signal EM2 is a high voltage and the seventh transistor T7 is turned on.

[0139] For example, according to Figure 6C In order to simplify the circuit, the second reset control signal RST2 and the gate scan signal GN can share a set of GOA circuits, and the second reset control signal RST2 and the second light-emitting control signal EM2 can also share a set of GOA. For example, an inverter can be added to generate a pair of the second reset control signal RST2 and the second light-emitting control signal EM2. Therefore, Figure 6C The timing diagram shown corresponds to Figure 6B The pixel circuit shown only requires two sets of GOA circuits to work, which is beneficial to simplifying display wiring, improving resolution, and achieving narrow borders.

[0140] At least some embodiments of the present disclosure also provide a method for driving a pixel circuit. Figure 4C The signal timing diagram of a driving method of a pixel circuit provided by at least some embodiments of the present disclosure is as follows. Figure 4C The signal timing diagram shown in Figure 4A The pixel circuit shown is specifically implemented as Figure 4B As an example, the pixel circuit structure shown in FIG. Figure 4A The working principle of the pixel circuit shown is explained.

[0141] For example, Figure 4C As shown, the driving method provided in this embodiment may include five stages, namely, an initialization stage t1, a threshold voltage compensation stage t2, a data writing stage t3, a mobility compensation stage t4, and a light emitting stage t5. Figure 4C The timing waveforms of each signal in each stage are shown in FIG.

[0142] During the initialization phase t1, the first reset control signal RST1 and the second reset control signal RST2 are input, turning on (i.e., conducting) the first reset circuit 410 and the second reset circuit 420, and resetting the second terminal 120 of the driver circuit 100 via the second reset circuit 420. For example, during the initialization phase t11, the third transistor T3 is turned on by the high voltage of the first reset control signal RST1, initializing the first node N1 (the control terminal 130 of the driver circuit 100) to the initialization voltage Vinit1. Since Vinit1 is a high voltage (e.g., it can be the first power supply voltage, such as VDD or other high voltage), the voltage of the gate of the first transistor T1 (i.e., the first node N1) becomes Vinit1. For example, during the initialization phase t11, the fourth transistor T4 is turned on by the high voltage of the second reset control signal RST2, initializing the second node N2 (the second terminal 120 of the driver circuit 100) to the initialization voltage Vinit2. For example, Vinit2 can be a low voltage (e.g., grounded or another low voltage). For example, the voltage of Vinit2 can be less than the second power supply voltage (e.g., VSS), so that the voltage difference Vgs between the gate and source of the first transistor T1 is sufficiently large (e.g., greater than 7V), thereby quickly eliminating the hysteresis state. The voltage difference Vgd between the gate and drain of the first transistor T1 is equal to the difference between Vinit1 and VDD and less than Vth. Therefore, the first transistor T1 is only in the off state and the saturation state, which helps stabilize the characteristics of the first transistor T1. At the same time, the fifth transistor T5 is turned off by the low voltage of the first light-emitting control signal EM1, preventing the input of the first power supply voltage. Because Vinit2 can be a low voltage, after the fourth transistor T4 is turned on, the second node N2 connected to the second electrode of the fourth transistor T4 is also at a low voltage, thereby rendering the light-emitting device EL non-luminous. For example, the third transistor T3 can be an oxide thin film transistor to reduce low-frequency leakage, so that the first node N1 maintains a low voltage, thereby keeping the first transistor T1 in the off state for a long time, and thus keeping the light-emitting device EL in the non-luminous state for a long time, eliminating flicker. At the same time, the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.

[0143] During the threshold voltage compensation phase t2, the first reset control signal RST1 is input, turning on the first reset circuit 410. The first initialization voltage Vinit1 is applied to the control terminal 130 of the driver circuit 100 via the first reset circuit 410, thereby turning on the driver circuit 100. The first light-emission control signal is input, turning on the first light-emission control circuit 500. Simultaneously, the second reset control signal is stopped, turning off the second reset circuit 420. Thus, threshold compensation can be performed on the driver circuit 100 using the turned-on driver circuit 100 and storage circuit 300. For example, the first reset control signal RST1 remains at a high voltage, thereby turning on the third transistor T3 and maintaining the voltage at the first node N1 at the first initialization voltage Vinit1, which can be a high voltage, for example. The second reset control signal RST2 is at a low voltage, turning off the fourth transistor T4. At this point, the voltage at the first node N1, the first initialization voltage Vinit1, is a high voltage, for example, greater than VDD, and the voltage at the third node N3 is a high voltage, for example, VDD. The first light-emitting control signal EM1 can be a high voltage, thereby turning on the fifth transistor T5. The voltage at the second node N2 gradually increases from the initial second initialization voltage Vinit2 until the voltage difference Vgs between the gate and source of the first transistor T1 equals the threshold voltage Vth of the first transistor T1. At this point, the voltage at the second node N2 is the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1. Consequently, the threshold voltage Vth of the first transistor T1 is written across the first capacitor C1. Because the light-emitting device EL connected to the second node N2 can be considered a capacitor with a capacitance much greater than that of the first capacitor C1, the voltage at the second node N2 remains virtually unchanged and remains at the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 in the previous stage t2. This compensates for the threshold voltage Vth of the first transistor T1, completing the threshold voltage compensation. Simultaneously, the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.

[0144] During data write phase t3, a gate scan signal GN is input, turning on the data write circuit 200. The data signal Vdata is written to the control terminal 130 of the driver circuit 100 via the data write circuit 200, and the written data signal Vdata is stored via the storage circuit 300. For example, during data write phase t3, the first light-emitting control signal EM1 may be at a low voltage, thereby turning off the fifth transistor T5. The first reset control signal RST1 may be at a low voltage, thereby turning off the third transistor T3. The second reset control signal RST2 may be at a low voltage, thereby turning off the fourth transistor T4. Simultaneously, the second transistor T2 is turned on by the high voltage of the gate scan signal GN. At this point, the voltage at the first node N1 changes from the first initialization voltage Vinit1 to a higher voltage, such as Vdata, i.e., the data voltage Vdata (the voltage of the data signal Vdata), thereby turning on the first transistor T1. Simultaneously, since the voltage at the first node N1 changes to the data voltage Vdata, the storage capacitor C1 can store the data voltage Vdata, thereby completing the data write.

[0145] In the mobility compensation phase t4, the first reset control signal RST1 is stopped from being input, the first reset circuit 410 is turned off, the second reset control signal is stopped from being input, the second reset circuit 420 is turned off, the gate scan signal GN is input, the data write circuit 200 is turned on, the first light-emitting control signal is input, and the first light-emitting control circuit 500 is turned on. Thus, mobility compensation can be performed by the first light-emitting control circuit 500 and the data write circuit 200 being turned on. For example, in the mobility compensation phase t4, the first light-emitting control signal EM1 can be a high voltage, thereby turning on the fifth transistor T5. The second reset control signal RST2 is a low voltage, thereby turning off the fourth transistor T4. The first reset control signal RST1 is a low voltage, thereby turning off the third transistor T3. The gate scan signal GN remains at a high voltage, thereby keeping the second transistor T2 turned on. At this time, the first transistor T1 is turned on, and the leakage current Ids flows from the first power supply voltage terminal, such as the VDD terminal, to the second node N2. The voltage of the second node N2 gradually increases by ΔV. At this time, the voltage V N2 is the sum of the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 and the gradually increasing voltage ΔV, as described in the following formula:

[0146] V N2 =Vinit1-Vth+ΔV

[0147] Among them, V N2 is the voltage of the second node N2, Vinit1 is the voltage V of the second node N2 N2is the first initialization voltage, Vth is the threshold voltage of the first transistor T1, and ΔV is the gradually increasing value of the voltage at the second node N2. The voltage at the first node N1 remains at the data voltage Vdata due to the conduction of the second transistor T2. The driving current of the first transistor T1 is as described in the following formula:

[0148] Ids=kμ(Vgs-Vth) 2

[0149] Where, Ids is the drain current of the first transistor T1, k is a constant coefficient, μ is the mobility of the first transistor T1, Vgs is the voltage difference between the gate and source of the first transistor T1, and Vth is the threshold voltage of the first transistor T1. As can be seen from the above formula, the greater the driving current of the first transistor T1 and the mobility μ of the first transistor T1, the greater its driving current, the greater the voltage ΔV gradually increasing at the second node N2, and therefore the smaller the voltage difference Vgs between the gate and source of the first transistor T1, so (Vgs-Vth) 2 The smaller the value, the greater the mobility μ of the first transistor T1, so the leakage current Ids of the first transistor T1 is corrected. For example, the driving currents of driving transistors with different mobilities at the same data voltage Vdata are not much different.

[0150] During light-emitting phase t5, the first reset control signal RST1 is stopped, the first reset circuit 410 is turned off, the second reset control signal is stopped, the second reset circuit 420 is turned off, the gate scan signal GN is stopped, the data write circuit 200 is turned off, the first light-emission control signal is input, and the first light-emission control circuit 500 is turned on. Thus, the first power supply voltage can drive the light-emitting element to emit light through the conductive first light-emission control circuit 500 and the conductive drive circuit 100. For example, during light-emitting phase t5, the first light-emission control signal EM1 can be a high voltage, thereby turning on the fifth transistor T5. The first reset control signal RST1 is a low voltage, thereby turning off the third transistor T3. The second reset control signal RST2 is a low voltage, thereby turning off the fourth transistor T4. The gate scan signal GN is a low voltage, thereby turning off the second transistor T2. At this time, the voltage of the second node N2 rises to exceed the turn-on voltage of the light-emitting device EL, and the light-emitting device EL begins to emit light. Because it is a constant current drive, the voltage of the second node N2 will eventually reach the turn-on voltage of the light-emitting device. At the same time, since the first node N1 and the second node N2 are connected via the first capacitor C1, the voltage of the first node N1 also rises to a stable state following the voltage of the second node N2. Even if the voltages of the N1 and N2 nodes change, the voltage difference between the N1 and N2 nodes, that is, the voltage difference Vgs between the gate and source of the first transistor T1, can remain unchanged. Therefore, the light-emitting current I is constant, as described in the following formula:

[0151] I=kμ(Vdata-ΔV) 2

[0152] Where I is the light-emitting current, k is a constant coefficient, μ is the mobility of the first transistor T1, Vdata is the data signal voltage, and ΔV is the gradually increasing value of the voltage at the second node N2. Thus, this pixel circuit combines the technical effects of threshold voltage compensation, μ mobility compensation, and IR drop compensation.

[0153] For example, the above pixel circuit can replace the third transistor T3 connected to the first node N1 with a thin film transistor with lower leakage, such as an oxide thin film transistor, which can reduce low-frequency leakage, thereby maintaining the voltage of the first node N1 and preventing the light-emitting device EL from flickering when emitting light.

[0154] At least some embodiments of the present disclosure also provide a method for driving a pixel circuit. Figure 5C A signal timing diagram of a pixel circuit driving method provided in at least some embodiments of the present disclosure. Figure 5C The driving method of the disclosed pixel circuit is almost the same as that of the above Figure 4C The disclosed pixel circuit driving method is the same. Figure 5C The signal timing diagram shown in Figure 5A The pixel circuit shown is specifically implemented as Figure 5B As an example, the pixel circuit structure shown in FIG. Figure 5A The working principle of the pixel circuit shown is explained.

[0155] For example, Figure 5C As shown, the driving method provided in this embodiment may include five stages, namely, an initialization stage t1, a threshold voltage compensation stage t2, a data writing stage t3, a mobility compensation stage t4, and a light emitting stage t5. Figure 5C The timing waveforms of each signal in each stage are shown in FIG.

[0156] For example, with Figure 5C The signal timing diagram of the pixel circuit driving method shown corresponds to Figure 5B The pixel circuit 10 shown is compared with Figure 4C The signal timing diagram of the pixel circuit driving method shown corresponds to Figure 4B The pixel circuit 10 shown is different in that: Figure 5BThe illustrated pixel circuit 10 further includes a sixth transistor T6 for implementing the third reset control circuit 430. For example, a gate of the sixth transistor T6 is connected to the third reset control signal terminal to receive the third reset control signal RST3, a first electrode of the sixth transistor T6 is connected to the hold voltage terminal to receive the hold voltage Vhold, and a second electrode of the sixth transistor T6 is connected to the third node N3 (the first terminal 110 of the driving circuit 100).

[0157] For example, in the threshold voltage compensation stage t2, as Figure 5C As shown, the driving method provided by this embodiment is compared with Figure 4C The difference between the driving methods shown is that the third reset control signal RST3 can be a high voltage, turning on the sixth transistor T6, and the first light-emitting control signal EM1 can be a low voltage, turning off the fifth transistor T5. Thus, during the Vth compensation phase, the second node N2 can be charged by a holding voltage, such as Vhold, until the voltage of the second node N2 rises to the difference between the first initialization voltage Vinit2 and the threshold voltage Vth of the first transistor T1. At the same time, the third node N3 is a holding voltage, such as Vhold, which can be higher than VDD. At this time, the voltage difference Vgd between the gate and drain of the first transistor T1 is equal to the difference between Vinit1 and Vhold and is less than Vth (e.g., less than 0V). Therefore, the first transistor T1 is only in the off state and the saturation state, which helps stabilize the characteristics of the first transistor T1.

[0158] For example, Figure 5D As shown, the third reset control signal RST3 can share the same timing with the first reset control signal RST1 to avoid the voltage of the third node N3 from drifting during the initialization phase. Figure 5D The driving method shown is similar to Figure 5C The driving methods shown are exactly the same and will not be repeated here.

[0159] For example, according to Figure 5C In the driving method shown, the second reset control signal RST2 and the third reset control signal RST3 can be in a superior-subordinate relationship with each other, that is, the second reset control signal RST2 and the third reset control signal RST3 are emitted by the same signal source, and the second reset control signal RST2 and the third reset control signal RST3 are signals corresponding to two moments in time. In this way, the second reset control signal RST2 and the third reset control signal RST3 can share the same GOA, which is beneficial to simplifying the wiring of the display screen, improving the resolution, and achieving a narrow bezel.

[0160] At the same time, due to Figure 5D The driving method shown is similar to Figure 5C The driving method shown in FIG1, t3, t4 and t5 phases are the same as those described above. Figure 4C The driving methods shown are exactly the same and will not be repeated here.

[0161] At least some embodiments of the present disclosure also provide a method for driving a pixel circuit. Figure 7C The signal timing diagram of a driving method of a pixel circuit provided by at least some embodiments of the present disclosure is as follows. Figure 7C The signal timing diagram shown in Figure 7A The pixel circuit shown is specifically implemented as Figure 7B As an example, the pixel circuit structure shown in FIG. Figure 7A The working principle of the pixel circuit shown is explained.

[0162] For example, Figure 7C As shown, the driving method provided in this embodiment may include five stages, namely, an initialization stage t1, a threshold voltage compensation stage t2, a data writing stage t3, a mobility compensation stage t4, and a light emitting stage t5. Figure 7C The timing waveforms of each signal in each stage are shown in FIG.

[0163] During initialization phase t1, a first reset control signal RST1 is input, turning on (i.e., conducting) the first reset circuit 410. A voltage transmission control signal is input, turning on the voltage transmission control circuit 800, and inputting the second power supply voltage through the first power supply voltage terminal, thereby resetting the second terminal 120 of the driver circuit 100. For example, during initialization phase t1, the voltage transmission control signal Vtc is at a high voltage, turning on the eighth transistor T8 and simultaneously transmitting the second power supply voltage, such as VSS, to the third node N3 (the first electrode of the first transistor T1). The first reset control signal RST1 is at a high voltage, turning on the third transistor T3 and initializing the voltage at the first node N1 to a first initialization voltage Vinit1, which can be a high voltage, such as higher than VDD. The second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata. At this point, the voltage at the first node N1 is the first initialization voltage Vinit1, which can be a high voltage, such as higher than VDD. The voltage at the third node N3 is at a low voltage, such as the second power supply voltage VSS. For example, the voltage difference Vgs between the gate and source of the first transistor T1 is equal to the difference between the first initialization voltage Vinit1 and the second power supply voltage VSS and is greater than the threshold voltage Vth of the first transistor T1, so that the first transistor T1 is in the on state, and the voltage of the second node N2 is reduced to a low voltage, such as the second power supply voltage VSS, thereby resetting the voltage of the second node N2 (the second end 120 of the driving circuit 100).

[0164] During the threshold voltage compensation phase t2, the first reset control signal RST1 is input, turning on (i.e., conducting) the first reset circuit 410. The voltage transmission control signal is input, turning on the voltage transmission control circuit 800, and inputting the first power supply voltage through the first power supply voltage terminal, thereby performing threshold compensation on the driver circuit 100. For example, during the threshold voltage compensation phase t2, the voltage transmission control signal Vtc is at a high voltage, turning on the eighth transistor T8 and simultaneously transmitting the first power supply voltage, such as VDD, to the third node N3 (the first electrode of the first transistor T1). The first reset control signal RST1 is at a high voltage, turning on the third transistor T3 and initializing the voltage at the first node N1 to the first initialization voltage Vinit1, which can be a high voltage, such as higher than VDD. The second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata. At this point, the voltage at the first node N1 is the first initialization voltage Vinit1, which can be a high voltage, such as higher than VDD. The voltage at the third node N3 is also at a high voltage, such as the first power supply voltage VDD. The voltage at the second node N2 gradually increases from its initial value of VSS until the voltage difference Vgs between the gate and source of the first transistor T1 equals the threshold voltage Vth of the first transistor T1. At this point, the voltage at the second node N2 is the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1. Consequently, the threshold voltage Vth of the first transistor T1 is written across the first capacitor C1. Since the light-emitting device EL connected to the second node N2 can be considered a capacitor, and its capacitance is much greater than that of the first capacitor C1, the voltage at the second node N2 remains virtually unchanged and remains the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 in the previous stage t2. This compensates for the threshold voltage Vth of the first transistor T1, completing threshold voltage compensation.

[0165] During the data writing phase t3, the gate scan signal GN is input, the data writing circuit 200 is turned on, the data signal Vdata is written into the control terminal 130 of the driving circuit 100 through the data writing circuit 200, and the written data signal Vdata is stored through the storage circuit 300. For example, during the data writing phase t3, the voltage transmission control signal Vtc is a low voltage, so that the eighth transistor T8 is turned off. The first reset control signal RST1 is a low voltage, so that the third transistor T3 is turned off. The gate scan signal GN is a high voltage, thereby turning on the second transistor T2. At this time, the voltage of the first node N1 changes from the first initialization voltage Vinit1 to a higher voltage, for example, Vdata, that is, the data voltage Vdata (the voltage of the data signal Vdata), thereby turning on the first transistor T1. At the same time, since the voltage of the first node N1 changes to the data voltage Vdata, the storage capacitor C1 can store the data voltage Vdata, thereby completing the data writing.

[0166] In the mobility compensation phase t4, the first reset control signal RST1 is stopped from being input, the first reset circuit 410 is turned off, the gate scan signal GN is input, the data write circuit 200 is turned on, the voltage transmission control signal is input, the voltage transmission control circuit 800 is turned on, and the first power supply voltage is input through the first power supply voltage terminal. Thus, mobility compensation can be performed through the turned-on voltage transmission control circuit 800 and the data write circuit 200. For example, in the mobility compensation phase t4, the voltage transmission control signal Vtc is a high voltage, so that the eighth transistor T8 is turned on, and at the same time, the first power supply voltage, such as VDD, is transmitted to the third node N3 (the first electrode of the first transistor T1). The first reset control signal RST1 is a low voltage, so that the third transistor T3 is turned off. The gate scan signal GN remains at a high voltage, so that the second transistor T2 remains turned on. At this time, the first transistor T1 is turned on, and the driving current Ids flows from the first power supply voltage terminal, such as the VDD terminal, to the second node N2. The voltage of the second node N2 gradually increases by ΔV. At this time, the N2 voltage V N2 is the sum of the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 and the gradually increasing voltage ΔV, as described in the following formula:

[0167] V N2 =Vinit1-Vth+ΔV

[0168] Among them, V N2 is the voltage of the second node N2, Vinit1 is the voltage V of the second node N2 N2is the first initialization voltage, Vth is the threshold voltage of the first transistor T1, and ΔV is the gradually increasing value of the voltage at the second node N2. The voltage at the first node N1 remains at the data voltage Vdata due to the conduction of the second transistor T2. The driving current of the first transistor T1 is as described in the following formula:

[0169] Ids=kμ(Vgs-Vth) 2

[0170] Where, Ids is the driving current of the first transistor T1, k is a constant coefficient, μ is the mobility of the first transistor T1, Vgs is the voltage difference between the gate and source of the first transistor T1, and Vth is the threshold voltage of the first transistor T1. As can be seen from the above formula, the greater the driving current of the first transistor T1 and the mobility μ of the first transistor T1, the greater its driving current, the greater the voltage ΔV gradually increasing at the second node N2, and therefore the smaller the voltage difference Vgs between the gate and source of the first transistor T1, so (Vgs-Vth) 2 The smaller the value, the greater the mobility μ of the first transistor T1 is, so the driving current Ids of the first transistor T1 is corrected. For example, the driving currents of driving transistors with different mobilities at the same data voltage Vdata are not much different.

[0171] During the light-emitting phase t5, the first reset control signal RST1 is stopped, the first reset circuit 410 is turned off, the gate scan signal GN is stopped, the data write circuit 200 is turned off, and the voltage transmission control signal is input, turning on the voltage transmission control circuit 800. Thus, the first power supply voltage can drive the light-emitting element to emit light through the turned-on voltage transmission control circuit 800 and the turned-on driving circuit 100. For example, during the light-emitting phase t5, the voltage transmission control signal Vtc is a high voltage, turning on the eighth transistor T8 and simultaneously transmitting the first power supply voltage, such as VDD, to the third node N3 (the first electrode of the first transistor T1). The first reset control signal RST1 is a low voltage, turning off the third transistor T3. The gate scan signal GN is a low voltage, turning off the second transistor T2. At this time, the voltage of the second node N2 rises to exceed the turn-on voltage of the light-emitting device EL, and the light-emitting device EL begins to emit light. Because it is a constant current drive, the voltage of the second node N2 will eventually reach the turn-on voltage of the light-emitting device. At the same time, since the first node N1 and the second node N2 are connected via the first capacitor C1, the voltage of the first node N1 also rises to a stable state following the voltage of the second node N2. Even if the voltages of the N1 and N2 nodes change, the voltage difference between the N1 and N2 nodes, that is, the voltage difference Vgs between the gate and source of the first transistor T1, can remain unchanged. Therefore, the light-emitting current I is constant, as described in the following formula:

[0172] I=kμ(Vdata-ΔV) 2

[0173] Where I is the light-emitting current, k is a constant coefficient, μ is the mobility of the first transistor T1, Vdata is the data signal voltage, and ΔV is the gradually increasing value of the voltage at the second node N2. Thus, this pixel circuit combines the technical effects of threshold voltage compensation, μ mobility compensation, and IR drop compensation.

[0174] At least some embodiments of the present disclosure also provide a method for driving a pixel circuit. Figure 8C The signal timing diagram of a driving method of a pixel circuit provided by at least some embodiments of the present disclosure is as follows. Figure 8C The signal timing diagram shown in Figure 8A The pixel circuit shown is specifically implemented as Figure 8B As an example, the pixel circuit structure shown in FIG. Figure 8A The working principle of the pixel circuit shown is explained.

[0175] For example, Figure 8C As shown, the driving method provided in this embodiment may include five stages, namely, an initialization stage t1, a threshold voltage compensation stage t2, a data writing stage t3, a mobility compensation stage t4, and a light emitting stage t5. Figure 8C The timing waveforms of each signal in each stage are shown in FIG.

[0176] During initialization phase t1, a second reset control signal RST2 is input, turning on (i.e., conducting) the second reset circuit 420. A gate scan signal GN is input, turning on the data write circuit 200. The reference voltage Vref is input to the control terminal 130 of the driver circuit 100 via the data write circuit 200, thereby resetting the second terminal 120 of the driver circuit 100. For example, during initialization phase t1, the first light-emitting control signal EM1 may be a low voltage, thereby turning off the fifth transistor T5. The second reset control signal RST2 is a high voltage, thereby turning on the fourth transistor T4. Initialization of the second node N2 is completed, and the voltage at the second node N2 reaches the second initialization voltage Vinit2, e.g., a low voltage, thereby turning on the first transistor T1. Simultaneously, the voltage at the first electrode, e.g., the anode, of the light-emitting device EL also reaches the second initialization voltage Vinit2, thereby resetting the light-emitting device EL and preventing it from emitting light. The gate scan signal GN may be a high voltage, thereby turning on the second transistor T2. At the same time, the data signal terminal transmits a reference voltage Vref, such as the first initialization voltage Vinit1, to the first electrode of transistor T2. Since the second transistor T2 is in the on state, the voltage Vinit1 at the first node N1 is a high voltage, such as higher than VDD, the voltage Vinit2 at the second node N2 is a low voltage, such as lower than VSS, and the third node N3 remains at the first power supply voltage, such as VDD. The voltage difference Vgs between the gate and source of the first transistor T1 is equal to the difference between the voltage Vinit2 at the second node N2 and the voltage Vinit1 at the first node N1, and is higher than the threshold voltage Vth of the first transistor T1, thereby turning on the first transistor T1. The voltage difference Vgd between the gate and drain of the first transistor T1 is equal to the difference between Vinit1 and VDD and is lower than Vth. Therefore, the first transistor T1 is only in the off state and the saturation state, which helps stabilize the characteristics of the first transistor T1.

[0177] During the threshold voltage compensation phase t2, the second reset control signal is deactivated, the second reset circuit 420 is deactivated, the gate scan signal GN is input, and the data write circuit 200 is activated. The reference voltage Vref is input to the control terminal 130 of the driver circuit 100 via the data write circuit 200. The first light emission control signal is input, and the first light emission control circuit 500 is activated. Thus, threshold compensation can be performed on the driver circuit 100 using the conductive driver circuit 100 and the storage circuit 300. For example, during the threshold voltage compensation phase t2, the first light emission control signal EM1 can be a high voltage, thereby turning on the fifth transistor T5. The second reset control signal RST2 can be a low voltage, thereby turning off the fourth transistor T4. The gate scan signal GN can be a high voltage, thereby turning on the second transistor T2. Simultaneously, the data signal terminal transmits the reference voltage Vref, for example, the first initialization voltage Vinit1, to the first terminal of the transistor T2. Since the second transistor T2 is in the conductive state, the voltage at the first node N1 connected to the second terminal of the second transistor T2 is also the first initialization voltage Vinit1, for example, a high voltage. At this time, the voltage at the first node N1, the first initialization voltage Vinit1, is a high voltage, for example, higher than VDD. The voltage at the third node N3 is a high voltage, for example, VDD. The voltage at the second node N2 gradually increases from the initial second initialization voltage Vinit2 until the voltage difference Vgs between the gate and source of the first transistor T1 equals the threshold voltage Vth of the first transistor T1. At this time, the voltage at the second node N2 is the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1. Thus, the threshold voltage Vth of the first transistor T1 is written across the first capacitor C1. Since the light-emitting device EL connected to the second node N2 can be regarded as a capacitor with a capacitance much larger than that of the first capacitor C1, the voltage at the second node N2 remains almost unchanged and remains the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 in the previous stage t2. This compensates for the threshold voltage Vth of the first transistor T1, completing the threshold voltage compensation.

[0178] During the data write phase t3, a gate scan signal GN is input, turning on the data write circuit 200. The data signal Vdata is written to the control terminal 130 of the driver circuit 100 via the data write circuit 200, and the written data signal Vdata is stored via the storage circuit 300. For example, during the data write phase t3, the first light-emitting control signal EM1 can be a low voltage, thereby turning off the fifth transistor T5. The second reset control signal RST2 can be a low voltage, thereby turning off the fourth transistor T4. The gate scan signal GN can be a high voltage, thereby turning on the second transistor T2. Simultaneously, the data signal terminal transmits the data voltage Vdata to the first electrode of the transistor T2. Since the second transistor T2 is in the on state, the voltage at the first node N1 changes from the first initialization voltage Vinit1 to a higher voltage, such as Vdata, i.e., the data voltage Vdata (the voltage of the data signal Vdata), thereby turning on the first transistor T1. Simultaneously, since the voltage at the first node N1 changes to the data voltage Vdata, the storage capacitor C1 can store the data voltage Vdata, thereby completing the data write.

[0179] During the mobility compensation phase t4, the second reset control signal is stopped, the second reset circuit 420 is turned off, the gate scan signal GN is input, the data write circuit 200 is turned on and the data voltage Vdata is input, and the first light-emitting control signal is input, turning on the first light-emitting control circuit 500. Thus, mobility compensation can be performed by the first light-emitting control circuit 500 and the data write circuit 200. For example, during the mobility compensation phase t4, the first light-emitting control signal EM1 can be a high voltage, thereby turning on the fifth transistor T5. The second reset control signal RST2 is a low voltage, thereby turning off the fourth transistor T4. The gate scan signal GN can be a high voltage, thereby turning on the second transistor T2. At the same time, the data signal terminal transmits the data voltage Vdata to the first electrode of the transistor T2. Since the second transistor T2 is in the on state, the voltage of the first node N1 remains at a higher voltage, such as Vdata. At this time, the first transistor T1 is turned on, and the driving current Ids flows from the first power supply voltage terminal, such as the VDD terminal, to the second node N2. The voltage of the second node N2 gradually increases by ΔV. At this time, the voltage V N2 is the sum of the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 and the gradually increasing voltage ΔV, as described in the following formula:

[0180] V N2 =Vinit1-Vth+ΔV

[0181] Among them, V N2 is the voltage of the second node N2, Vinit1 is the voltage V of the second node N2N2 is the first initialization voltage, Vth is the threshold voltage of the first transistor T1, and ΔV is the gradually increasing value of the voltage at the second node N2. The voltage at the first node N1 remains at the data voltage Vdata due to the conduction of the second transistor T2. The driving current of the first transistor T1 is as described in the following formula:

[0182] Ids=kμ(Vgs-Vth) 2

[0183] Where, Ids is the driving current of the first transistor T1, k is a constant coefficient, μ is the mobility of the first transistor T1, Vgs is the voltage difference between the gate and source of the first transistor T1, and Vth is the threshold voltage of the first transistor T1. As can be seen from the above formula, the greater the driving current of the first transistor T1 and the mobility μ of the first transistor T1, the greater its driving current, the greater the voltage ΔV gradually increasing at the second node N2, and therefore the smaller the voltage difference Vgs between the gate and source of the first transistor T1, so (Vgs-Vth) 2 The smaller the value, the greater the mobility μ of the first transistor T1 is, so the driving current Ids of the first transistor T1 is corrected. For example, the driving currents of driving transistors with different mobilities at the same data voltage Vdata are not much different.

[0184] During light-emitting phase t5, the second reset control signal is deactivated, the second reset circuit 420 is deactivated, the gate scan signal GN is deactivated, the data write circuit 200 is deactivated, and the first light-emitting control signal is activated, turning on the first light-emitting control circuit 500. Thus, the first power supply voltage can drive the light-emitting element to emit light via the activated first light-emitting control circuit 500 and the activated drive circuit 100. For example, during light-emitting phase t5, the first light-emitting control signal EM1 can be a high voltage, thereby turning on the fifth transistor T5. The second reset control signal RST2 is a low voltage, thereby turning off the fourth transistor T4. The gate scan signal GN is a low voltage, thereby turning off the second transistor T2. At this time, the voltage of the second node N2 rises to exceed the turn-on voltage of the light-emitting device EL, and the light-emitting device EL begins to emit light. Because it is a constant current drive, the voltage of the second node N2 will eventually reach the turn-on voltage of the light-emitting device. At the same time, since the first node N1 and the second node N2 are connected via the first capacitor C1, the voltage of the first node N1 also rises to a stable state following the voltage of the second node N2. Even if the voltages of the N1 and N2 nodes change, the voltage difference between the N1 and N2 nodes, that is, the voltage difference Vgs between the gate and source of the first transistor T1, can remain unchanged. Therefore, the light-emitting current I is constant, as described in the following formula:

[0185] I=kμ(Vdata-ΔV) 2

[0186] Where I is the light-emitting current, k is a constant coefficient, μ is the mobility of the first transistor T1, Vdata is the data signal voltage, and ΔV is the gradually increasing value of the voltage at the second node N2. Thus, this pixel circuit combines the technical effects of threshold voltage compensation, μ mobility compensation, and IR drop compensation.

[0187] The technical effects of the driving method of the pixel circuit provided by the embodiment of the present disclosure refer to the corresponding description of the pixel circuit 10 in the above embodiment, which will not be repeated here.

[0188] At least some embodiments of the present disclosure further provide a display panel comprising a plurality of pixel units arranged in an array. For example, each of the plurality of pixel units comprises a pixel circuit provided by any embodiment of the present disclosure.

[0189] Figure 9A This is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. Figure 9A The display panel 11 is provided in the display device 1 and is electrically connected to a gate driver 12, a timing controller 13, and a data driver 14. The display panel 11 includes pixel units P defined by the intersection of a plurality of scan lines GL and a plurality of data lines DL. The gate driver 12 is configured to drive the plurality of scan lines GL. The data driver 14 is configured to drive the plurality of data lines DL. The timing controller 13 is configured to process image data RGB input from outside the display device 1, provide the processed image data RGB to the data driver 14, and output a scan control signal GCS and a data control signal DCS to the gate driver 12 and the data driver 14 to control the gate driver 12 and the data driver 14.

[0190] For example, the display panel 11 includes a plurality of pixel units P, and the pixel unit P includes any pixel circuit 10 provided in the above embodiments. Figure 2B As shown in the pixel circuit 10. Figure 9A As shown, the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL. For example, the plurality of scan lines are correspondingly connected to the data writing circuit 200 in the pixel circuit 10 of each row of pixel units to provide a gate scan signal, and the plurality of scan lines are also correspondingly connected to the first reset circuit 410 in the pixel circuit 10 of each row of pixel units to provide a first reset control signal.

[0191] For example, the pixel unit P is arranged at the intersection of the scan line GL and the data line DL. Figure 9AAs shown, each pixel unit P is connected to two scan lines GL (providing a gate scan signal and a first reset control signal, respectively), a data line DL, a first power supply voltage line for providing a first power supply voltage, a second power supply voltage line for providing a second power supply voltage, and a first initialization voltage line for providing a first initialization voltage. For example, the first voltage line or the second voltage line can be replaced by a corresponding plate-shaped common electrode (such as a common anode or a common cathode). It should be noted that in Figure 9A Only part of the pixel units P, scan lines GL, and data lines DL are shown.

[0192] For example, the plurality of pixel units P are arranged in a plurality of rows, the first reset circuit 410 of the pixel circuit of each row of pixel units P is connected to a scan line GL to receive a first reset control signal, and the data write circuit 200 of the pixel circuit of each row of pixel units P is connected to another scan line GL to receive a gate scan signal. For example, the data line DL of each column is connected to the data write circuit 200 in the pixel circuit 10 of the column to provide a data signal.

[0193] Figure 9B This is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. Figure 9B The connection relationship between the display panel 11 and the display device is as follows: Figure 9A The panels shown are identical and will not be described again here.

[0194] For example, the display panel 11 includes a plurality of pixel units P, and the pixel unit P includes any pixel circuit 10 provided in the above embodiments. Figure 7B As shown in the pixel circuit 10. Figure 9B As shown, the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL. For example, the plurality of scan lines are also correspondingly connected to the voltage transmission circuit 800 in the pixel circuit 10 of each row of pixel units to provide a voltage transmission control signal.

[0195] For example, the pixel unit P is arranged at the intersection of the scan line GL and the data line DL. Figure 9B As shown, each pixel unit P is compared with Figure 9A Each pixel unit shown is also connected to a scan line GL (providing a first light emitting control signal). Figure 9B Only part of the pixel units P, scan lines GL, and data lines DL are shown.

[0196] For example, the plurality of pixel units P are arranged in a plurality of rows, and the first light emitting control circuit 500 of the pixel circuit of each row of pixel units P is connected to a scan line GL to receive the first light emitting control signal.

[0197] For example, Figure 9BAs shown, the display panel includes a first power supply voltage line that can provide a second power supply voltage. At the same time, according to another pixel circuit 10 provided in some embodiments of the present disclosure, the pixel circuit can be connected to the first power supply voltage line that provides the second power supply voltage through the first power supply voltage terminal, so that the second power supply voltage can be received from the first power supply voltage terminal.

[0198] For example, Figure 9B As shown, the display panel 11 includes a plurality of pixel units P, and the pixel unit P includes any pixel circuit 10 provided in the above embodiments. For example, Figure 8B The pixel circuit 10 shown. The display panel includes a scan line GL that can provide a second reset control signal. At the same time, according to another pixel circuit 10 provided in some embodiments of the present disclosure, the pixel circuit can be connected to the scan line GL that provides the second reset control signal through the first reset control signal terminal, thereby receiving the second reset control signal from the first reset control signal terminal. At the same time, the display panel includes a data line DL that can provide a first initialization voltage. The pixel circuit can be connected to the data line DL that provides the first initialization voltage through the data signal terminal, thereby receiving the first reset control signal from the data signal terminal.

[0199] Figure 9C This is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. Figure 9C The connection relationship between the display panel 11 and the display device is as follows: Figure 9A The panels shown are identical and will not be described again here.

[0200] For example, Figure 9C The display panel 11 shown includes a plurality of pixel units P, and the pixel unit P includes any pixel circuit 10 provided in the above embodiments. For example, Figure 3B As shown in the pixel circuit 10. Figure 9C As shown, the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL. For example, the plurality of scan lines are also correspondingly connected to the second reset circuit 420 in the pixel circuit 10 of each row of pixel units to provide a second reset control signal.

[0201] For example, the pixel unit P is arranged at the intersection of the scan line GL and the data line DL. Figure 9C As shown, each pixel unit P is compared with Figure 9A Each pixel unit shown is also connected to a scan line GL (providing a second reset control signal) and a second initialization voltage line for providing a second initialization voltage. Figure 9C Only part of the pixel units P, scan lines GL, and data lines DL are shown.

[0202] For example, the multiple pixel units P are arranged into multiple rows, the second reset circuit 420 of the pixel circuit of each row of pixel units P is connected to a scan line GL to receive a second reset control signal, and the second initialization voltage end of the pixel circuit of each row of pixel units P is connected to the second initialization voltage line to receive the second initialization voltage.

[0203] Figure 9D This is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. Figure 9D The connection relationship between the display panel 11 and the display device is as follows: Figure 9C The panels shown are identical and will not be described again here.

[0204] For example, Figure 9D The display panel 11 shown includes a plurality of pixel units P, and the pixel unit P includes any pixel circuit 10 provided in the above embodiments. For example, Figure 4B As shown in the pixel circuit 10. Figure 9B As shown, the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL. For example, the plurality of scan lines are also correspondingly connected to the first light emitting control circuit 500 in the pixel circuit 10 of each row of pixel units to provide a first light emitting control signal.

[0205] For example, the pixel unit P is arranged at the intersection of the scan line GL and the data line DL. Figure 9D As shown, each pixel unit P is compared with Figure 9C Each pixel unit shown is also connected to a scan line GL (providing a first light emitting control signal). Figure 9D Only part of the pixel units P, scan lines GL, and data lines DL are shown.

[0206] For example, the plurality of pixel units P are arranged in a plurality of rows, and the first light emitting control circuit 500 of the pixel circuit of each row of pixel units P is connected to a scan line GL to receive the first light emitting control signal.

[0207] For example, Figure 9D As shown, the display panel 11 includes a plurality of pixel units P, and the pixel unit P includes any pixel circuit 10 provided in the above embodiments. For example, Figure 6B The pixel circuit 10 shown in FIG. The display panel includes a scan line GL that can provide a second light-emission control signal. Furthermore, the pixel circuit 10 is connected to the scan line GL providing the second light-emission control signal via a first light-emission control signal terminal, thereby receiving the second light-emission control signal from the first light-emission control signal terminal. Furthermore, the second reset control signal and the gate scan signal can share the same scan line GL, simplifying the layout space around the display panel and enabling the development of high-resolution display panels.

[0208] Figure 9E This is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. Figure 9E The connection relationship between the display panel 11 and the display device is as follows: Figure 9D The panels shown are identical and will not be described again here.

[0209] For example, Figure 9E The display panel 11 shown includes a plurality of pixel units P, and the pixel unit P includes any pixel circuit 10 provided in the above embodiments. For example, Figure 5B As shown in the pixel circuit 10. Figure 9E As shown, the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL. For example, the plurality of scan lines are also correspondingly connected to the third reset circuit 430 in the pixel circuit 10 of each row of pixel units to provide a third reset control signal.

[0210] For example, the pixel unit P is arranged at the intersection of the scan line GL and the data line DL. Figure 9E As shown, each pixel unit P is compared with Figure 9D Each pixel unit shown is also connected to a scan line GL (providing a third reset control signal) and a holding voltage line for providing a holding voltage. Figure 9E Only part of the pixel units P, scan lines GL, and data lines DL are shown.

[0211] For example, the multiple pixel units P are arranged into multiple rows, the third reset circuit 430 of the pixel circuit of each row of pixel units P is connected to a scan line GL to receive a third reset control signal, and the holding voltage end of the pixel circuit of each row of pixel units P is connected to a holding voltage line to receive a holding voltage.

[0212] It should be noted that if Figure 9F In the schematic block diagram of a display panel shown, the third reset circuit 430 of the pixel circuit of the pixel unit P can also achieve the same technical effect as the third reset circuit 430 receiving the third reset control signal by receiving the second reset control signal. That is, the third reset control signal received by the third reset circuit 430 can be replaced by the second reset control signal. At the same time, the second reset control signal and the third reset control signal are signals corresponding to two different moments. This allows the second reset control signal and the third reset control signal to share a scan line GL, which can simplify the layout space around the display panel and enable the development of high-resolution display panels.

[0213] For example, the gate driver 12 provides a plurality of gate signals to the plurality of scan lines GL according to the plurality of scan control signals GCS from the timing controller 13. The plurality of gate signals include a gate scan signal, a first reset control signal, a second reset control signal, a third reset control signal, a first light emission control signal, and a second light emission control signal. These signals are provided to each pixel unit P through the plurality of scan lines GL.

[0214] For example, the data driver 14 converts digital image data RGB input from the timing controller 13 into data signals using reference gamma voltages according to a plurality of data control signals DCS from the timing controller 13. The data driver 14 provides the converted data signals to a plurality of data lines DL.

[0215] For example, the timing controller 13 processes externally input image data RGB to match the size and resolution of the display panel 11, and then provides the processed image data to the data driver 14. The timing controller 13 uses synchronization signals input from outside the display device (such as the dot clock DCLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync) to generate multiple scan control signals GCS and multiple data control signals DCS. The timing controller 13 provides the generated scan control signals GCS and data control signals DCS to the gate driver 12 and the data driver 14, respectively, for control.

[0216] For example, the data driver 14 can be connected to multiple data lines DL to provide data signals Vdata; and can also be connected to multiple first voltage lines, multiple second voltage lines, and multiple initialization voltage lines to provide first voltages, second voltages, and initialization voltages, respectively.

[0217] For example, the gate driver 12 and the data driver 14 can be implemented as semiconductor chips. The display device 1 can also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components can be conventional components, which will not be described in detail here.

[0218] For example, the display device in this embodiment can be any product or component with a display function, such as a monitor, a television, an electronic paper display device, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, or a navigation system. It should be noted that the display device can also include other conventional components or structures. For example, to achieve the necessary functions of the display device, those skilled in the art can configure other conventional components or structures according to specific application scenarios, and the embodiments of this disclosure are not limited thereto.

[0219] The technical effects of the display device provided by at least some embodiments of the present disclosure can be referred to the corresponding description of the pixel circuit 10 in the above embodiments, which will not be repeated here.

[0220] Regarding this disclosure, the following points need to be explained:

[0221] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0222] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0223] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed herein are intended to be encompassed by the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A pixel circuit comprising: A driving circuit, a data writing circuit, a storage circuit, a first reset circuit and a second reset circuit; wherein, The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving the light emitting element to emit light; The data writing circuit is configured to write a data signal into the control terminal of the driving circuit under the control of the first scanning signal; The storage circuit is configured to store the data signal; The first reset circuit is configured to apply a first initialization voltage to the control terminal of the driving circuit under the control of a first reset control signal; The second reset circuit is configured to apply a second initialization voltage to the anode of the light emitting element under the control of a second reset control signal; Wherein, the first reset circuit includes an N-type oxide thin film transistor, The pixel circuit further includes: a third reset circuit, wherein: The third reset circuit is configured to apply a holding voltage to the first terminal of the driving circuit under the control of a third reset control signal during the threshold voltage compensation phase. The driving circuit is turned on under the control of the first reset control signal, and the turn-on time of the driving circuit is longer than the effective time of the third reset control signal, and the third reset control signal and the first reset control signal are both turn-on signals in at least part of the time period. The driving circuit includes a first transistor, the gate of the first transistor serves as the control terminal of the driving circuit, the drain of the first transistor serves as the first terminal of the driving circuit, and the source of the first transistor serves as the second terminal of the driving circuit. In the threshold voltage compensation stage, a voltage difference between the gate of the first transistor and the drain of the first transistor is equal to a difference between the first initialization voltage and the holding voltage, and the difference is less than zero.

2. The pixel circuit according to claim 1, wherein: The data writing circuit includes a second transistor; The gate of the second transistor is connected to the first scan signal terminal to receive the first scan signal, the first electrode of the second transistor is connected to the data signal terminal to receive the data signal, and the second electrode of the second transistor is connected to the control terminal of the driving circuit.

3. The pixel circuit according to claim 1, wherein: The storage circuit includes a storage capacitor, The first electrode of the storage capacitor is connected to the control end of the driving circuit, and the second electrode of the storage capacitor is connected to the second end of the driving circuit.

4. The pixel circuit according to claim 1, wherein: The N-type oxide thin film transistor included in the first reset circuit is a third transistor; The gate of the third transistor is connected to the first reset control signal terminal to receive the first reset control signal, the first electrode of the third transistor is connected to the first initialization voltage terminal to receive the first initialization voltage, and the second electrode of the third transistor is connected to the control terminal of the driving circuit.

5. The pixel circuit according to claim 4, wherein: The second reset circuit includes a fourth transistor, The gate of the fourth transistor is connected to the second reset control signal terminal to receive the second reset control signal, the first electrode of the fourth transistor is connected to the second initialization voltage terminal to receive the second initialization voltage, and the second electrode of the fourth transistor is connected to the anode of the light-emitting element.

6. The pixel circuit according to claim 4 or 5, further comprising: A first light emitting control circuit, wherein The first light emitting control circuit is configured to apply a first power supply voltage to a first terminal of the driving circuit under control of a first light emitting control signal.

7. The pixel circuit according to claim 6, wherein: The first light emitting control circuit includes a fifth transistor, The gate of the fifth transistor is connected to the first light-emitting control terminal to receive the first light-emitting control signal, the first electrode of the fifth transistor is connected to the first power supply terminal to receive the first power supply voltage, and the second electrode of the fifth transistor is connected to the first terminal of the driving circuit.

8. The pixel circuit according to claim 6, wherein: The third reset circuit includes a sixth transistor, The gate of the sixth transistor is connected to the third reset control signal terminal to receive the third reset control signal, the first electrode of the sixth transistor is connected to the holding voltage terminal to receive the holding voltage, and the second electrode of the sixth transistor is connected to the first terminal of the driving circuit.

9. The pixel circuit according to claim 8, wherein: The holding voltage is greater than a first voltage, wherein the first voltage is provided by a first power supply terminal connected to a first terminal of the driving circuit, and the first voltage is higher than a second power supply voltage connected to a cathode of the light-emitting element.

10. The pixel circuit according to claim 1, wherein: The first reset circuit is turned on earlier than the third reset circuit.

11. The pixel circuit according to claim 4 or 5, further comprising: The second light emitting control circuit, wherein The second light emitting control circuit is configured to apply the driving current to the first electrode of the light emitting element under the control of a second light emitting control signal.

12. The pixel circuit according to claim 11, wherein: The second light emitting control circuit includes a seventh transistor, The gate of the seventh transistor is connected to the second light-emitting control terminal to receive the second light-emitting control signal, the first electrode of the seventh transistor is connected to the second terminal of the driving circuit, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting element.

13. The pixel circuit according to claim 1, wherein: The first initialization voltage is greater than a first voltage, wherein the first voltage is provided by a first power supply terminal connected to a first terminal of the driving circuit, and the first voltage is higher than a second power supply voltage connected to a cathode of the light-emitting element.

14. The pixel circuit according to claim 1, wherein: The holding voltage is greater than a first voltage, the first voltage is provided by a first power supply terminal connected to a first terminal of the driving circuit, and the first voltage is higher than a second power supply voltage connected to a cathode of the light-emitting element.

15. A display panel comprising: A plurality of pixel units arranged in an array; wherein, Each of the pixel units comprises a pixel circuit according to any one of claims 1 to 14.

16. A driving method for a pixel circuit according to claim 3, comprising: Initialization stage, threshold voltage compensation stage, data writing and mobility compensation stage, light emitting stage, among which, In the initialization stage, the first reset control signal and the second reset control signal are input to turn on the first reset circuit and the second reset circuit, the first initialization voltage is applied to the control terminal of the drive circuit through the first reset circuit to reset the control terminal of the drive circuit, and the second initialization voltage is applied to the second terminal of the drive circuit through the second reset circuit to reset the second terminal of the drive circuit; In the threshold voltage compensation stage, the first reset control signal is input to turn on the first reset circuit, and the first initialization voltage is applied to the control terminal of the drive circuit through the first reset circuit to turn on the drive circuit. The second reset control signal is stopped to turn off the second reset circuit, and threshold compensation is performed through the turned-on drive circuit and the storage circuit. The third reset control signal is input to turn on the third reset circuit, and the holding voltage is applied to the first terminal of the drive circuit through the third reset circuit. In the data writing and mobility compensation stage, a gate scanning signal is input to turn on the data writing circuit, the data signal is written into the control terminal of the driving circuit through the data writing circuit, and the written data signal is stored through the storage circuit; In the light-emitting phase, the gate scanning signal is stopped from being input, the data writing circuit is turned off, and the driving circuit generates a driving current under the control of the data signal stored in the storage circuit to drive the light-emitting element to emit light. The activation time of the driving circuit is greater than the effective time of the third reset control signal.

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