Display panel driving method, display panel and display device

Abstract

The present disclosure provides a display panel driving method, a display panel, and a display device, including: including display time periods and touch time periods alternately set within a frame time, wherein at least one touch time period is set and at least two display time periods are set; sequentially scanning some gate lines in the display panel within each display time period; pausing the scanning of all gate lines within each touch time period and performing touch recognition; wherein, within the display time period adjacent to the touch time period, level compensation is performed on the gate line to be compensated; the gate line to be compensated is at least one gate line that starts scanning within the display time period adjacent to the touch time period.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel driving method, a display panel, and a display device. Background Art

[0002] As a new touch technology, Full In Cell (FIC) touch has the advantages of good touch effect, low cost, light weight, and suitability for narrow-frame products. It is expected to become a new application scenario for the development of the next product form of monitors (TVs) and electronic whiteboards.

[0003] Embedded touch technologies include active pen (LHB) and passive pen (LVB). Compared to passive pen touch, active pen touch offers better touch quality and high sensitivity, capable of sensing the thickness of the stylus tip and writing pressure. Therefore, active pen touch offers a better user experience and wider application scenarios.

[0004] Active pen touch technology and passive pen touch technology are driven in different ways: Figure 1 As shown, in a display panel using active pen touch technology, touch and display are driven alternately in time-sharing mode within one frame. The touch time period is called a "pit", during which the clock signal (Clk) is at a low level. Figure 2 As shown, the display panel using the passive pen touch technology first displays within one frame time, and then performs touch control after the display is completed. Summary of the Invention

[0005] The embodiments of the present disclosure provide a display panel driving method, a display panel, and a display device. The specific solutions are as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a method for driving a display panel, comprising:

[0007] A frame time includes alternately arranged display time periods and touch time periods, wherein at least one touch time period is arranged and at least two display time periods are arranged;

[0008] sequentially scanning a portion of the gate lines in the display panel in each display time period;

[0009] The scanning of all the gate lines is paused in each touch time period, and touch recognition is performed; wherein, in the display time period adjacent to the touch time period, level compensation is performed on the gate line to be compensated; the gate line to be compensated is at least one of the gate lines that starts scanning in the display time period adjacent to the touch time period.

[0010] Optionally, in the driving method provided in the embodiment of the present disclosure, performing level compensation on the gate line to be compensated specifically includes:

[0011] A gate driving circuit is used to provide a gate driving signal including level compensation to the gate line to be compensated.

[0012] Optionally, in the driving method provided in the embodiment of the present disclosure, providing a gate driving signal including level compensation to the gate line to be compensated by the gate driving circuit specifically includes:

[0013] A first clock signal including level compensation is loaded onto the gate driving circuit, so that the gate driving circuit generates a gate driving signal including level compensation according to the first clock signal including level compensation.

[0014] Optionally, in the driving method provided in the embodiment of the present disclosure, the step of applying the first clock signal including level compensation to the gate driving circuit specifically includes:

[0015] Level compensation is applied within a pulse width time of 1% to 100% of the effective level pulse of the first clock signal, and the first clock signal after level compensation is applied is provided to the gate driving circuit.

[0016] Optionally, in the driving method provided in the embodiment of the present disclosure, the voltage value of the effective level pulse of the first clock signal after level compensation is loaded is greater than the voltage value of the effective level pulse of the last at least one second clock signal in the display time period before the touch time period.

[0017] Optionally, in the above-mentioned driving method provided in the embodiment of the present disclosure, the difference between the voltage value of the effective level pulse of the first clock signal after loading level compensation and the voltage value of the effective level pulse of the second clock signal is 0.25% to 7.5% of the voltage value of the effective level pulse of the first clock signal before compensation.

[0018] Optionally, in the driving method provided by the embodiment of the present disclosure, the voltage value of the effective level pulse of the first clock signal after level compensation is loaded is between 27V and 40V.

[0019] Optionally, in the driving method provided in the embodiment of the present disclosure, the step of applying the first clock signal including level compensation to the gate driving circuit specifically includes:

[0020] Level compensation is applied during 1% to 100% of the pulse interval between the effective level pulses of the first clock signal, and the first clock signal after level compensation is applied is provided to the gate driving circuit.

[0021] Optionally, in the driving method provided in the embodiment of the present disclosure, the voltage value of the first clock signal after level compensation during the pulse interval is less than the voltage value of the last at least one second clock signal during the pulse interval in the display time period before the touch time period.

[0022] Optionally, in the above-mentioned driving method provided in the embodiment of the present disclosure, the difference between the voltage value of the first clock signal after level compensation during the pulse interval and the voltage value of the second clock signal during the pulse interval is 10% to 60% of the voltage value of the first clock signal before compensation during the pulse interval.

[0023] Optionally, in the driving method provided by the embodiment of the present disclosure, the voltage value of the first clock signal after level compensation is applied within the pulse interval is between -4V and -20V.

[0024] Optionally, in the driving method provided in the embodiment of the present disclosure, the gate driving circuit includes a plurality of shift registers arranged in cascade, wherein the input signal terminals of the first to N-th shift registers are connected to the frame trigger signal terminal, and except for the first to N-th shift registers, the input signal terminals of the remaining shift registers are respectively connected to the second output signal terminals of the shift registers N stages above them, the first output signal terminal of each stage of the shift register is electrically connected to a corresponding gate line, and every 2N adjacent stages of the shift registers are electrically connected to 2N clock signal lines, where N is a positive integer;

[0025] Sequentially scanning the corresponding portion of the gate lines in each display time period specifically includes:

[0026] The gate lines corresponding to different clock signal lines are sequentially scanned in each display time period.

[0027] Optionally, in the driving method provided in the embodiment of the present disclosure, the step of applying the first clock signal including level compensation to the gate driving circuit specifically includes:

[0028] The first clock signal containing level compensation is loaded onto the first N shift registers that start working through the first N clock signal lines that start working.

[0029] Optionally, in the driving method provided in the embodiment of the present disclosure, the gate driving circuit includes a plurality of shift registers arranged in cascade, wherein the input signal terminals of the first to N-th shift registers are connected to the frame trigger signal terminal, and except for the first to N-th shift registers, the input signal terminals of the remaining shift registers are respectively connected to the second output signal terminals of the shift registers N stages above them, the first output signal terminal of each stage of the shift register is electrically connected to a corresponding gate line, and every 2N adjacent stages of the shift registers are electrically connected to 2N corresponding clock signal lines, where N is a positive integer;

[0030] Sequentially scanning the corresponding portion of the gate lines in each display time period specifically includes:

[0031] The gate lines corresponding to the same clock signal line are sequentially scanned in each display time period.

[0032] Optionally, in the driving method provided in the embodiment of the present disclosure, the step of applying the first clock signal including level compensation to the gate driving circuit specifically includes:

[0033] The first clock signal containing level compensation is loaded onto the first N shift registers that start working through the N clock signal lines with fixed serial numbers.

[0034] Optionally, in the driving method provided in the embodiment of the present disclosure, the step of applying the first clock signal including level compensation to the gate driving circuit specifically includes:

[0035] The first clock signal containing level compensation is loaded onto the first N shift registers that start working through the N clock signal lines electrically connected to the upper cascaded shift registers.

[0036] Optionally, in the driving method provided in the embodiment of the present disclosure, performing level compensation on the gate line to be compensated specifically includes:

[0037] A gate driving signal including level compensation is provided to the gate line to be compensated through the flip chip film.

[0038] Optionally, in the driving method provided in the embodiment of the present disclosure, providing a gate driving signal including level compensation to the gate line to be compensated through the chip-on-film film specifically includes:

[0039] Level compensation is applied within a pulse width time of 1% to 100% of the first effective level pulse provided by the chip-on-flip film, and the first effective level pulse after level compensation is used as a gate driving signal.

[0040] Optionally, in the driving method provided by the embodiment of the present disclosure, the voltage value of the first effective level pulse after level compensation is smaller than the voltage value of the last at least one second effective level pulse in the display period before the touch period.

[0041] Optionally, in the driving method provided in the embodiment of the present disclosure, the difference between the voltage value of the second effective level pulse and the voltage value of the first effective level pulse after level compensation is 1.25% to 20% of the voltage value of the first effective level pulse before compensation.

[0042] Optionally, in the driving method provided by the embodiment of the present disclosure, the voltage value of the first effective level pulse after level compensation is loaded is between 20V and 40V.

[0043] On the other hand, an embodiment of the present disclosure further provides a display panel, which is driven by any of the driving methods described above.

[0044] Optionally, the above-mentioned display panel provided in the embodiment of the present disclosure includes a gate driving circuit, multiple gate lines and 2N clock signal lines, wherein the gate driving circuit includes multiple shift registers arranged in cascade, wherein the input signal terminals of the first to N-th stage shift registers are connected to the frame trigger signal terminal, and except for the first to N-th stage shift registers, the input signal terminals of the remaining stages of the shift registers are respectively connected to the second output signal terminals of the shift registers separated by N stages above them, the first output signal terminal of each stage of the shift register is electrically connected to a corresponding gate line, and each adjacent 2N stages of the shift registers are electrically connected to the 2N clock signal lines, respectively, and N is a positive integer.

[0045] Optionally, in the above display panel provided by the embodiment of the present disclosure, the shift register includes: an input transistor, a reset transistor, a first output transistor, a second output transistor, a capacitor and a control circuit;

[0046] The gate and the first electrode of the input transistor are both electrically connected to the input signal terminal, and the second electrode of the input transistor is electrically connected to the pull-up node;

[0047] The gate of the reset transistor is electrically connected to the reset signal terminal, the first electrode of the reset transistor is electrically connected to the power signal terminal, and the second electrode of the reset transistor is electrically connected to the pull-up node;

[0048] The gate of the first output transistor is electrically connected to the pull-up node, the first electrode of the first output transistor is electrically connected to the clock signal line, the second electrode of the first output transistor is electrically connected to the first output signal terminal, and the first output signal terminal is electrically connected to the gate line;

[0049] The capacitor is connected between the gate of the first output transistor and the first output signal terminal;

[0050] The gate of the second output transistor is electrically connected to the pull-up node, the first electrode of the second output transistor is electrically connected to the clock signal line, the second electrode of the second output transistor is electrically connected to the second output signal terminal, and the second output signal terminal is electrically connected to the input signal terminal of the shift register N stages below it;

[0051] The control circuit is electrically connected to the pull-up node, the first output signal terminal, the second output signal terminal and the control signal terminal, respectively. The control circuit is configured to control the levels of the pull-up node, the first output signal terminal and the second output signal terminal in response to a signal at the control signal terminal.

[0052] Optionally, the display panel provided in the embodiment of the present disclosure includes a chip-on-film (COF) and a plurality of gate lines, and the COF includes a plurality of terminals electrically connected to the gate lines respectively.

[0053] On the other hand, an embodiment of the present disclosure provides a display device, comprising any one of the display panels described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 This is a working timing diagram of the active pen touch technology in the related art;

[0055] Figure 2 This is a working timing diagram of the passive pen touch technology in the related art;

[0056] Figure 3 A schematic diagram of ideal waveforms of voltages at each node after the shift register provided by the embodiment of the present disclosure pauses scanning;

[0057] Figure 4 A schematic diagram comparing the ideal waveform and the actual waveform of the voltage at each node after the shift register provided by the embodiment of the present disclosure pauses scanning;

[0058] Figure 5 A schematic diagram of performing level compensation on a gate line to be compensated using a gate driving circuit according to an embodiment of the present disclosure;

[0059] Figure 6 for Figure 5 An enlarged schematic diagram of effective level pulse compensation for a clock signal;

[0060] Figure 7 Another schematic diagram of using a gate driving circuit to perform level compensation on a gate line to be compensated according to an embodiment of the present disclosure;

[0061] Figure 8A schematic structural diagram of a gate drive circuit provided in an embodiment of the present disclosure;

[0062] Figure 9 Another schematic diagram of using a gate driving circuit to perform level compensation on a gate line to be compensated according to an embodiment of the present disclosure;

[0063] Figure 10 Another schematic diagram of using a gate driving circuit to perform level compensation on a gate line to be compensated according to an embodiment of the present disclosure;

[0064] Figure 11 Another schematic diagram of using a gate driving circuit to perform level compensation on a gate line to be compensated according to an embodiment of the present disclosure;

[0065] Figure 12 A schematic diagram of using a flip chip film to perform level compensation on a gate line to be compensated according to an embodiment of the present disclosure;

[0066] Figure 13 A schematic structural diagram of a display panel including a gate driving circuit provided in an embodiment of the present disclosure;

[0067] Figure 14 for Figure 8 and Figure 13 Schematic diagram of the structure of the shift register;

[0068] Figure 15 for Figure 14 The working timing diagram of the shift register shown;

[0069] Figure 16 for Figure 8 The working timing diagram of each clock signal line is shown. DETAILED DESCRIPTION

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure. Throughout, the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions.

[0071] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons having ordinary skills in the field to which the present disclosure belongs. The words “include” or “comprise” and the like used in the present disclosure and the claims mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0072] When the display panel uses active pen touch technology, the display time period and the touch time period are set alternately. Therefore, when scanning a certain row of pixels, the scanning will be temporarily stopped (Holding) and touch recognition will be performed. Then, the scanning will continue from the paused row of pixels. In this way, the display and touch are driven alternately multiple times until a frame of the picture is displayed. For example, for a display panel with 4K resolution, when using active pen touch technology, one frame time will be divided into 16 display time periods and 16 touch time periods. Therefore, after scanning every 135 rows of pixels, it will stop for touch. After the first touch is completed, the 136th row of pixels will be scanned again. This cycle will continue until all 2160 rows of pixels are completely scanned.

[0073] However, since the pixel rows charged before the touch period and the pixel rows charged after the touch period pause for different periods of time, their leakage levels are different, resulting in inconsistent display brightness and horizontal stripes or horizontal blocks on the display screen.

[0074] In order to at least solve the above technical problems existing in the related art, an embodiment of the present disclosure provides a method for driving a display panel, which may include the following steps:

[0075] A frame time includes alternately arranged display time periods and touch time periods, wherein at least one touch time period is arranged and at least two display time periods are arranged;

[0076] sequentially scanning a portion of the gate lines in the display panel in each display time period;

[0077] The scanning of all gate lines is paused in each touch time period, and touch recognition is performed; wherein, in the display time period adjacent to the touch time period, the level compensation is performed on the gate line to be compensated to make the brightness of the display image uniform; the gate line to be compensated is at least one gate line that starts scanning in the display time period adjacent to the touch time period.

[0078] In the driving method provided in the embodiment of the present disclosure, during the process of sequentially scanning the gate lines in the display time period after the touch time period, level compensation is performed on at least one gate line to be compensated that is started to be scanned, so that the levels on the gate lines scanned in the two display time periods before and after the touch time period are roughly the same, thereby ensuring the brightness uniformity of the display screen, effectively improving the horizontal stripes or block defects on the display screen, and enhancing the user experience.

[0079] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, the above-mentioned "approximately" may be completely identical, or there may be some deviations. Therefore, as long as the "approximate" relationship between the above-mentioned features satisfies the allowable error (for example, a fluctuation of 5% up and down), it falls within the scope of protection of the present disclosure.

[0080] In some embodiments, in the driving method provided in the embodiments of the present disclosure, level compensation is performed on the gate lines to be compensated. Specifically, a gate drive circuit (Gate On Array, GOA) can be used to provide gate drive signals containing level compensation to the gate lines to be compensated. Using GOA driving technology can eliminate the need for chip-on-film (COF), reducing manufacturing costs while also facilitating a narrow-frame design for display panels and improving product competitiveness.

[0081] In some embodiments, as Figure 3 As shown, each time the touch time period is entered (i.e., the touch signal T_EN is at a high level), the shift register of the gate drive circuit needs to suspend scanning. During this touch time period, the clock signal CLK is at a low level, the pull-up node PU in the shift register is at a high level, and the pull-up node PU needs to maintain a high level during this touch time period.

[0082] However, if Figure 4 As shown, during the touch time period, due to the leakage of the transistor that affects the level of the pull-up node PU, the level of the pull-up node PU decreases as the pause time increases; specifically, Figure 4 The dashed line represents the ideal waveforms of the pull-up node PU and the first output signal terminal Gout, while the solid line represents the actual waveforms of the pull-up node PU and the first output signal terminal Gout. Therefore, when scanning is restarted, the output transistors, which are controlled by the level of the pull-up node PU, are turned on at different levels. This causes a difference in amplitude and delay between the active level pulses of the clock signal CLK provided by the output transistors to the first row of pixels to be scanned again and the active level pulses of the clock signal CLK applied to other rows of pixels. This results in a poor charging effect on the first row of pixels to be scanned again, ultimately causing dark lines (i.e., horizontal stripes) to appear on the displayed image.

[0083] Based on this, in order to improve the horizontal stripe defects, in the above-mentioned driving method provided in the embodiment of the present disclosure, a gate driving signal including level compensation is provided to the gate line to be compensated through a gate driving circuit. Specifically, the gate driving circuit can be loaded with a clock signal CLK including level compensation so that the gate driving circuit generates a gate driving signal including level compensation according to the clock signal CLK including level compensation.

[0084] For example, Figure 5 and Figure 6 As shown, the first clock signal including level compensation is loaded to the gate driving circuit, which can be specifically implemented in the following manner:

[0085] Level compensation is applied during the 1% to 100% pulse width of the effective level pulse of the first clock signal, and the first clock signal after level compensation is applied is provided to the gate drive circuit. Figure 5 FIG shows the loading level compensation within the 100% pulse width time of the effective level pulse of the first clock signal CLK N+1 to N+6; Figure 6 Figure 2 shows that level compensation is applied within approximately 17% of the pulse width of the active level pulse of the clock signal CLK, i.e., the ratio of the time t for applying the compensation level to the pulse width T is approximately 17%. In specific implementations, the length of the compensation time can be selected based on the severity of the horizontal streaks and the compensated voltage value. In some embodiments, when the compensated voltage value is fixed, the more severe the horizontal streaks, the longer the compensation time; for example, the compensation time may account for more than 50% of the pulse width. Conversely, when the compensated voltage value is fixed, the milder the horizontal streaks, the shorter the compensation time; for example, the compensation time may account for less than 50% of the pulse width.

[0086] In some embodiments, as Figure 5 As shown, the voltage value V1 of the active level pulses of the first clock signals CLK N+1 to N+6 after level compensation can be greater than the voltage value V2 of the last active level pulse of at least one of the second clock signals CLK N-5 to N in the display period before the touch period. Optionally, the difference V1-V2 between the voltage value V1 of the active level pulses of the first clock signals CLK N+1 to N+6 after level compensation and the voltage value V2 of the active level pulses of the second clock signals CLK N-5 to N can be 0.25% to 7.5% of the voltage value V3 of the active level pulses of the first clock signals CLK N+1 to N+6 before compensation, that is, the value range of (V1-V2) / V3 is 0.25% to 7.5%. Generally, the voltage value V3 of the active level pulses of the first clock signals CLK N+1 to N+6 before compensation can be equal to the voltage value V2 of the active level pulses of the second clock signals CLK N-5 to N, that is, V3 = V2.

[0087] In a specific implementation, the voltage value V1 after level compensation of the active level pulses of the first clock signals CLK N+1 to N+6 can be selected according to the severity of the horizontal stripes and the length of the compensation time. In some embodiments, when the compensation time is fixed, the more severe the horizontal streak, the larger the voltage value V1 after level compensation is applied to the active level pulses of the first clock signals CLK N+1 to N+6. Accordingly, the larger the difference V1-V2 between the voltage value V1 after level compensation applied to the active level pulses of the first clock signals CLK N+1 to N+6 and the voltage value V2 of the active level pulses of the second clock signals CLK N-5 to N. For example, the value range of (V1-V2) / V3 may be 2.5% to 7.5%. Conversely, when the compensation time is fixed, the milder the horizontal streak, the smaller the voltage value V1 after level compensation is applied to the active level pulses of the first clock signals CLK N+1 to N+6. Accordingly, the smaller the difference V1-V2 between the voltage value V1 after level compensation applied to the active level pulses of the first clock signals CLK N+1 to N+6 and the voltage value V2 of the active level pulses of the second clock signals CLK N-5 to N. For example, the value range of (V1-V2) / V3 may be 0.25% to 2.5%.

[0088] In some embodiments, the voltage value V1 of the clock signals CLK N+1 to N+6 after level compensation may be in the range of 27 V to 40 V. For example, the voltage value V3 of the clock signals CLK N+1 to N+6 before level compensation is 32 V. Preferably, the voltage value V1 of the clock signals CLK N+1 to N+6 after level compensation is in the range of 32.1 V to 34 V.

[0089] As can be seen from the above, the amplitude of the effective-level pulse of the first clock signal after level compensation is increased. This, on the one hand, increases the gate drive signal output by the output transistor in the gate drive circuit. On the other hand, the bootstrap effect of the capacitor raises the level of the pull-up node PU, thereby increasing the degree of openness of the output transistor and further increasing the gate drive signal provided by the output transistor. Due to the influence of these two factors, the dark lines in the display image before compensation are brighter after compensation, effectively improving the horizontal stripes on the image.

[0090] In some embodiments, the falling edge of the active-level pulse contained in the clock signal is too large, preventing the pull-up node PU from being pulled down in time, thus affecting the timely shutdown of the output transistor. This may cause the data signal of the pixel row that should have stopped scanning to be overwritten with the data signal of the next pixel row to be scanned, resulting in poor serial display.

[0091] Based on this, in order to improve the serial display defect, in the driving method provided in the embodiment of the present disclosure, the first clock signal including level compensation is applied to the gate driving circuit, which can be specifically implemented in the following manner:

[0092] like Figure 7 As shown, level compensation can be applied within 1% to 100% of the pulse interval T' between the effective level pulses of the first clock signal, and the first clock signal after level compensation is applied is provided to the gate drive circuit. In specific implementations, the length of the compensation time can be selected based on the severity of the serial display and the compensated voltage value. In some embodiments, when the compensated voltage value is fixed, the more severe the serial display, the longer the compensation time, for example, the compensation time may account for more than 50% of the pulse interval T'; conversely, when the compensated voltage value is fixed, the milder the serial display, the shorter the compensation time, for example, the compensation time may account for less than 50% of the pulse interval T'.

[0093] In some embodiments, as Figure 7 As shown, the voltage value V4 of the first clock signals CLK N+1 to N+6 after level compensation during the pulse interval T' is less than the voltage value V5 of at least one of the last second clock signals CLK N-5 to N during the pulse interval T' during the display period before the touch period. Optionally, the difference V4-V5 between the voltage value V4 of the first clock signals CLK N+1 to N+6 after level compensation during the pulse interval T' and the voltage value V5 of the second clock signals CLK N-5 to N during the pulse interval T' is 10% to 60% of the voltage value V6 of the first clock signals CLK N+1 to N+6 before compensation during the pulse interval T', that is, the value range of (V5-V4) / V6 is 10% to 60%. Generally, the voltage value V6 of the first clock signals CLK N+1 to N+6 before compensation during the pulse interval T' can be equal to the voltage value V5 of the second clock signals CLK N-5 to N during the pulse interval T', that is, V5 = V6.

[0094] In a specific implementation, the voltage value V4 of the first clock signals CLK N+1-N+6 after compensation within the pulse interval T' can be selected according to the severity of the serial display and the length of the compensation time. In some embodiments, when the compensation time is fixed, the more severe the serial display is, the smaller the voltage value V4 of the first clock signals CLK N+1 to N+6 after compensation within the pulse interval T' is, and accordingly, the greater the absolute value |V4-V5| of the difference between the voltage value V4 of the first clock signals CLK N+1 to N+6 after compensation within the pulse interval T' and the voltage value V5 of the second clock signals CLK N-5 to N within the pulse interval T' is, for example, the value range of (V4-V5) / V6 is 30% to 60%; conversely, when the compensation time is fixed, the milder the serial display is, the larger the voltage value V4 of the first clock signals CLK N+1 to N+6 after compensation within the pulse interval T' is, and accordingly, the absolute value |V4-V5| of the difference between the voltage value V4 of the first clock signals CLK N+1 to N+6 after compensation within the pulse interval T' and the voltage value V5 of the second clock signals CLK N-5 to N within the pulse interval T' is. The smaller the absolute value |V4-V5| of the difference between the voltage values ​​V5 of N-5 to N within the pulse interval T', for example, the value range of (V5-V4) / V6 is 10% to 30%.

[0095] In some embodiments, the voltage value V4 of the first clock signals CLK N+1 to N+6 after level compensation during the pulse interval T' can range from -4 V to -20 V. For example, the voltage value V6 (equal to the voltage value V5) of the first clock signals CLK N+1 to N+6 before level compensation during the pulse interval T' is -10 V. Preferably, the voltage value V4 of the first clock signals CLK N+1 to N+6 after level compensation during the pulse interval T' is -15 V.

[0096] The above-mentioned method of applying level compensation within the pulse interval time T' between the effective level pulses of the first clock signals CLK N+1 to N+6 can quickly lower the falling edge of the effective level pulses contained in the first clock signals CLK N+1 to N+6, thereby timely lowering the level of the pull-up node PU through the bootstrap effect of the capacitor, and controlling the output transistor to be turned off in time through the PU node, thereby effectively avoiding serial display defects.

[0097] In some embodiments, in the above driving method provided in the embodiments of the present disclosure, as Figure 8As shown, the gate drive circuit may include a plurality of shift registers GOAm (m is a positive integer) arranged in cascade, wherein the input signal terminals In of the first to N-th shift registers, such as In(1) to In(6), are connected to the frame trigger signal terminal STV, and except for the first to N-th shift registers, the input signal terminals In of the remaining shift registers, such as In(7) to In(12), are respectively connected to the second output signal terminals OutC of the shift registers separated by N stages therefrom, such as Out(1) to Out(6), and the first output signal terminal Gout of each shift register is electrically connected to a gate line, and each adjacent 2N-stage shift register GOAm is electrically connected to 2N clock signal lines Clk, respectively, and N is a positive integer;

[0098] Sequentially scanning the corresponding portion of the gate lines in each display time period may specifically include:

[0099] In each display time period, gate lines corresponding to different clock signal lines can be scanned sequentially. In this case, since the output of the m-th shift register controls the input of the m+N-th shift register below it, it is necessary to compensate for the effective level pulses of the first N clock signal lines that start working after the touch time ends. In other words, the gate drive circuit is loaded with the first clock signal containing level compensation, which can be specifically achieved by the first N clock signal lines that start working (for example, Figure 5 CLK N+1~N+6, and Figure 9 The CLK N+1 to N+4 clock signal lines in the touch control section are used to load the first clock signal containing the level compensation to the first N shift registers that start operating. Furthermore, it should be understood that because the sequence number of the first clock signal line that starts scanning after a pause is different, the N clock signal lines that undergo level compensation after each touch control period are not fixed.

[0100] Optionally, the gate lines corresponding to the same clock signal line can be scanned sequentially in each display time period. In this case, the clock signal containing the level compensation can be loaded to the first N shift registers that start working through the N clock signal lines with fixed serial numbers. Figure 10 As shown, it is possible to pause each time the scanning reaches the gate line corresponding to the first clock signal line Clk1 , and then after the touch time period ends, it is necessary to perform level compensation on the second clock signal line Clk2 to the seventh clock signal line Clk7 .

[0101] In some embodiments, in the driving method provided by the embodiments of the present disclosure, considering that the output of a shift register will affect the input of the cascaded shift register below it, the level of the pull-up node in the cascaded shift register below it can be controlled, thereby eliminating the horizontal stripe defect caused by leakage of the pull-up node. Figure 11As shown, the gate drive circuit is loaded with a first clock signal containing level compensation. Specifically, the first N shift registers that start working can be electrically connected to the N clock signal lines of the upper cascaded shift registers respectively, and the first N shift registers that start working are loaded with the first clock signal containing level compensation. In other words, the clock signal lines of the first N shift registers that start working normally pull up the level of the pull-up node PU. At the same time, the first N shift registers that resume working are loaded with the first clock signal containing level compensation to achieve secondary charging of the pull-up node PU, thereby effectively eliminating the horizontal stripe defect caused by leakage of the pull-up node PU. Specifically, Figure 11 The figure shows that the time when the gate line corresponding to the Nth clock signal line ClkN is scanned is the time point when the display time period ends. After the touch time period ends, the N-5th clock signal line ClkN-5 to the Nth clock signal line ClkN repeatedly give a high level, so that the pull-up node PU in the shift register corresponding to the N+1th clock signal line ClkN+1 to the N+6th clock signal line ClkN+6 can be recharged, thereby eliminating the horizontal stripes on the display screen caused by leakage of the pull-up node PU.

[0102] For chip-on-film (COF) products, the touch-sensitive period begins after the display period ends. After pixel charging is complete, a pause is required for touch recognition. This causes a decrease in brightness in the display area (AA) due to leakage in the pixel circuit. After the touch period ends and the display period begins, the brightness displayed immediately after the pixel charging is higher than after the pause, resulting in horizontal streaks or block defects on the screen.

[0103] Based on this, in the driving method provided in the embodiment of the present disclosure, level compensation is performed on the gate line to be compensated. Specifically, a gate driving signal including level compensation can be provided to the gate line to be compensated through a chip-on-chip film.

[0104] In some embodiments, in the above driving method provided in the embodiments of the present disclosure, as Figure 12 As shown, a gate drive signal including level compensation is provided to the gate line to be compensated through the chip-on-chip film. Specifically, the level compensation can be loaded within 1% to 100% of the pulse width time of the first effective level pulse provided by the chip-on-chip film, and the first effective level pulse after level compensation is used as the gate drive signal required by the gate line to be compensated (for example, the n+1th gate line Gn+1 to the m+1th gate line Gm+1).

[0105] In specific implementations, the length of the compensation time can be selected based on the severity of the horizontal streaks and the compensated voltage value. In some embodiments, when the compensated voltage value is fixed, the more severe the horizontal streaks, the longer the compensation time; for example, the compensation time may account for more than 50% of the pulse width time. Conversely, when the compensated voltage value is fixed, the milder the horizontal streaks, the shorter the compensation time; for example, the compensation time may account for less than 50% of the pulse width time.

[0106] In some embodiments, as Figure 12 As shown, the voltage value V7 after level compensation applied to the first active level pulse provided by the chip-on-film to the gate lines to be compensated (e.g., gate lines Gn+1-m+1) is less than the voltage value V8 of the last at least one second active level pulse (e.g., provided to gate lines G1-n) during the display period before the touch period. Optionally, the difference V7-V8 between the voltage value V7 after level compensation applied to the first active level pulse and the voltage value V8 of the second active level pulse (e.g., provided to gate lines G1-n) is 1.25% to 20% of the voltage value of the first active level pulse (e.g., provided to gate lines Gn+1-m+1) before compensation (generally equal to voltage value V8).

[0107] In a specific implementation, the voltage value V7 after the first effective level pulse compensation can be selected according to the severity of the horizontal stripes and the length of the compensation time. In some embodiments, when the compensation time is fixed, the more severe the horizontal streak is, the smaller the compensated voltage value V7 of the first effective level pulse (for example, provided to the gate lines Gn+1 to m+1) is, and accordingly, the larger the difference V8-V7 between the voltage value V8 of the second effective level pulse (for example, provided to the gate lines G1 to n) and the compensated voltage value V7 of the first effective level pulse (for example, provided to the gate lines Gn+1 to m+1) is, for example, the value range of (V8-V7) / V8 can be 10% to 20%; conversely, when the compensation time is fixed, the milder the horizontal streak is, the smaller the compensated voltage value V7 of the first effective level pulse (for example, provided to the gate lines Gn+1 to m+1) is, and accordingly, the smaller the difference V8-V7 between the voltage value V8 of the second effective level pulse (for example, provided to the gate lines G1 to n) and the compensated voltage value V7 of the first effective level pulse (for example, provided to the gate lines Gn+1 to m+1) is, for example, the value range of (V8-V7) / V8 can be 1.25% to 10%.

[0108] In some embodiments, the voltage value V7 of the first effective level pulse provided by the chip-on-film to the gate lines to be compensated (e.g., gate lines Gn+1-m+1) after level compensation can be in the range of 20V to 40V. For example, the voltage value V8 of the second effective level pulse (e.g., provided to gate lines G1-n) is 32V. Preferably, the voltage value of the first effective level pulse provided by the chip-on-film to the gate lines to be compensated (e.g., gate lines Gn+1-m+1) after level compensation is in the range of 28V to 31.5V.

[0109] Based on the same inventive concept, embodiments of the present disclosure provide a display panel that is driven using the aforementioned driving method provided in embodiments of the present disclosure. Optionally, the display panel may be a liquid crystal display panel. Because the principles underlying the problem solved by the display panel are similar to those underlying the aforementioned driving method, the implementation of the display panel provided in embodiments of the present disclosure can be referenced to the implementation of the aforementioned driving method provided in embodiments of the present disclosure, and any repetitions will not be repeated.

[0110] In some embodiments, as Figure 8 and Figure 13 As shown, the above-mentioned display panel provided by the embodiment of the present disclosure may include a gate driving circuit, a plurality of gate lines and 2N clock signal lines, wherein the gate driving circuit includes a plurality of shift registers GOAm (m is a positive integer) arranged in cascade, wherein the input signal terminal In of the first to N-th stage shift registers is connected to the frame trigger signal terminal STV, and except for the first to N-th stage shift registers, the input signal terminals In of the remaining stages of the shift registers are respectively connected to the second output signal terminals OutC of the shift registers spaced N stages above them, the first output signal terminal Gout of each stage of the shift register is electrically connected to a gate line, and each adjacent 2N stages of the shift registers GOAm are electrically connected to 2N clock signal lines Clk, respectively, and N is a positive integer.

[0111] In some embodiments, as Figure 14 As shown, the shift register provided by the embodiment of the present disclosure may include: an input transistor M1, a reset transistor M2, a first output transistor M3, a second output transistor M4, a capacitor C and a control circuit; wherein,

[0112] The gate and the first electrode of the input transistor M1 are both electrically connected to the input signal terminal In, and the second electrode of the input transistor M1 is electrically connected to the pull-up node PU;

[0113] The gate of the reset transistor M2 is electrically connected to the reset signal terminal Rst, the first electrode of the reset transistor M2 is electrically connected to the low-level power supply terminal LVGL, and the second electrode of the reset transistor M2 is electrically connected to the pull-up node PU;

[0114] The gate of the first output transistor M3 is electrically connected to the pull-up node PU, the first electrode of the first output transistor M3 is electrically connected to the clock signal line Clk, the second electrode of the first output transistor M3 is electrically connected to the first output signal terminal Gout, and the first output signal terminal Gout is electrically connected to the gate line;

[0115] The capacitor C is connected between the gate of the first output transistor M3 and the first output signal terminal Gout;

[0116] The gate of the second output transistor M4 is electrically connected to the pull-up node PU, the first electrode of the second output transistor M4 is electrically connected to the clock signal line Clk, the second electrode of the second output transistor M4 is electrically connected to the second output signal terminal OutC, and the second output signal terminal OutC is electrically connected to the input signal terminal In of the shift register N stages below it;

[0117] The control circuit is electrically connected to the pull-up node PU, the first output signal terminal Gout, the second output signal terminal OutC and the control signal terminal respectively, and the control circuit is configured to control the levels of the pull-up node PU, the first output signal terminal Gout and the second output signal terminal OutC in response to the signal of the control signal terminal. Optionally, the control circuit may include a fifth transistor M5, a sixth transistor M6 / M6' through a thirteenth transistor M13 / M13'; and the control signal terminal may include a reset signal terminal STV', an input signal terminal In, and a high-level power supply terminal VDDO / VDDE. During the pull-down phase, the high-level power supply terminal VDDO and the high-level power supply terminal VDDE operate alternately, and the sixth transistor M6 through the thirteenth transistor M13 and the sixth transistor M6' through the thirteenth transistor M13' operate alternately. In other words, the sixth transistor M6 through the thirteenth transistor M13 operate during half of the pull-down phase under the control of the high-level power supply terminal VDDO, and the sixth transistor M6' through the thirteenth transistor M13' operate during the other half of the pull-down phase under the control of the high-level power supply terminal VDDE, thereby extending the service life of the sixth transistor M6 / M6' through the thirteenth transistor M13 / M13'. At the beginning of a frame, the fifth transistor M5 resets the pull-up node PU of all shift registers under the control of the reset signal terminal STV'.

[0118] Below Figure 8 and Figure 14 The structure of the shift register shown in the figure is used as an example. Figure 15 and Figure 16 The working timing diagram shown briefly explains the working process of the shift register.

[0119] First, under the control of the reset signal terminal STV', the fifth transistor M5 resets the pull-up node PU of all shift registers. Then, taking the first stage shift register as an example:

[0120] In the input stage t1, the frame trigger signal terminal STV is loaded with a signal to the input signal terminal In(1) to turn on the first transistor M1, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10, wherein the pull-up node PU of the first-level bit register GOA1 is pulled up by the first transistor M1, the pull-down node PD1 is pulled down by the eighth transistor M8 and the tenth transistor M10, and the gate level of the seventh transistor M7 is pulled down by the ninth transistor M9.

[0121] In the output phase t2, the clock signal loaded on the first clock signal line Clk1 is at a high level. Due to the bootstrap effect of the capacitor C, the level of the pull-up node PU is further pulled up. The high level pull-up node PU turns on the first output transistor M3 and the second output transistor M4, so that the first output signal terminal Gout(1) and the second output signal terminal Out(1) output a high level. The high level of the first output signal terminal Gout(1) is provided to the corresponding gate line as a gate drive signal, and the high level of the second output signal terminal Out(1) is provided to the input signal terminal In(7) of the seventh-stage shift register GOA7.

[0122] In the reset phase t3, the reset transistor M2 of the first-stage shift register GOA1 is turned on, pulling down the pull-up node PU; the sixth transistor T6 and the seventh transistor T7 are turned on, pulling up the pull-down node PD1, so that the eleventh transistor T11, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, pulling down the pull-up node PU, the second output signal terminal Out(1) and the first output signal terminal Gout(1), respectively.

[0123] In some embodiments, the display panel provided in the embodiments of the present disclosure may include a chip-on-chip film and multiple gate lines, wherein the chip-on-chip film includes multiple terminals electrically connected to each gate line respectively, so as to provide gate drive signals to the gate lines through the terminals of the chip-on-chip film.

[0124] Based on the same inventive concept, embodiments of the present disclosure provide a display device including the display panel described above. Because the principles underlying the problems solved by the display device are similar to those of the display panel described above, the implementation of the display device provided by embodiments of the present disclosure can refer to the implementation of the display panel described above, and any repetitions will not be repeated.

[0125] In some embodiments, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, a smart watch, a fitness wristband, a personal digital assistant, etc. The display device includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output and input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. In addition, it will be understood by those skilled in the art that the above structure does not constitute a limitation on the display device provided in the embodiments of the present disclosure. In other words, the display device provided in the embodiments of the present disclosure may include more or fewer of the above components, or a combination of certain components, or a different arrangement of components.

[0126] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A method for driving a display panel, wherein: include: A frame time includes alternately arranged display time periods and touch time periods, wherein at least one touch time period is arranged and at least two display time periods are arranged; sequentially scanning a portion of the gate lines in the display panel in each display time period; The scanning of all the gate lines is paused in each touch time period, and touch recognition is performed; wherein, in the display time period adjacent to the touch time period, level compensation is performed on the gate line to be compensated; the gate line to be compensated is at least one of the gate lines that starts scanning in the display time period adjacent to the touch time period; The level compensation for the gate line to be compensated specifically includes: Providing a gate drive signal including level compensation to the gate line to be compensated through a gate drive circuit; The step of providing a gate drive signal including level compensation to the gate line to be compensated by the gate drive circuit specifically includes: A first clock signal including level compensation is loaded onto the gate driving circuit, so that the gate driving circuit generates a gate driving signal including level compensation according to the first clock signal including level compensation.

2. The driving method according to claim 1, wherein: The step of applying the first clock signal including level compensation to the gate driving circuit specifically includes: Level compensation is applied within a pulse width time of 1% to 100% of the effective level pulse of the first clock signal, and the first clock signal after level compensation is applied is provided to the gate driving circuit.

3. The driving method according to claim 2, wherein: A voltage value of the effective level pulse of the first clock signal after level compensation is applied is greater than a voltage value of the last effective level pulse of at least one second clock signal in a display period before the touch period.

4. The driving method according to claim 3, wherein: The difference between the voltage value of the effective level pulse of the first clock signal after level compensation and the voltage value of the effective level pulse of the second clock signal is 0.25% to 7.5% of the voltage value of the effective level pulse of the first clock signal before compensation.

5. The driving method according to claim 4, wherein: The voltage value of the effective level pulse of the first clock signal after level compensation is added is between 27V and 40V.

6. The driving method according to claim 1, wherein: The step of applying the first clock signal including level compensation to the gate driving circuit specifically includes: Level compensation is applied during 1% to 100% of the pulse interval between the effective level pulses of the first clock signal, and the first clock signal after level compensation is applied is provided to the gate driving circuit.

7. The driving method according to claim 6, wherein: A voltage value of the first clock signal after level compensation during the pulse interval is smaller than a voltage value of the last at least one second clock signal during the pulse interval in the display period before the touch period.

8. The driving method according to claim 7, wherein: The difference between the voltage value of the first clock signal after level compensation during the pulse interval and the voltage value of the second clock signal during the pulse interval is 10% to 60% of the voltage value of the first clock signal before compensation during the pulse interval.

9. The driving method according to claim 8, wherein: The voltage value of the first clock signal after level compensation is applied within the pulse interval is between -4V and -20V.

10. The driving method according to any one of claims 1 to 9, wherein: The gate drive circuit includes a plurality of shift registers arranged in cascade connection, wherein the input signal terminals of the first to Nth stage shift registers are connected to the frame trigger signal terminal, and the input signal terminals of the remaining stages of the shift registers, except for the first to Nth stage shift registers, are respectively connected to the second output signal terminals of the shift registers N stages above them, the first output signal terminal of each stage of the shift register is electrically connected to a corresponding gate line, and every 2N adjacent stages of the shift registers are electrically connected to 2N clock signal lines, where N is a positive integer; Sequentially scanning the corresponding portion of the gate lines in each display time period specifically includes: The gate lines corresponding to different clock signal lines are sequentially scanned in each display time period.

11. The driving method according to claim 10, wherein: The step of applying the first clock signal including level compensation to the gate driving circuit specifically includes: The first clock signal containing level compensation is loaded onto the first N shift registers that start working through the first N clock signal lines that start working.

12. The driving method according to claim 10, wherein: The gate drive circuit includes a plurality of shift registers arranged in cascade, wherein the input signal terminals of the first to Nth stage shift registers are connected to the frame trigger signal terminal, and the input signal terminals of the remaining stages of the shift registers, except for the first to Nth stage shift registers, are respectively connected to the second output signal terminals of the shift registers N stages above them, the first output signal terminal of each stage of the shift register is electrically connected to a corresponding gate line, and every 2N adjacent stages of the shift registers are electrically connected to 2N corresponding clock signal lines, where N is a positive integer; Sequentially scanning the corresponding portion of the gate lines in each display time period specifically includes: The gate lines corresponding to the same clock signal line are sequentially scanned in each display time period.

13. The driving method according to claim 12, wherein: The step of applying the first clock signal including level compensation to the gate driving circuit specifically includes: The first clock signal containing level compensation is loaded onto the first N shift registers that start working through the N clock signal lines with fixed serial numbers.

14. The driving method according to claim 12, wherein: The step of applying the first clock signal including level compensation to the gate driving circuit specifically includes: The first clock signal containing level compensation is loaded onto the first N shift registers that start working through the N clock signal lines electrically connected to the upper cascaded shift registers.

15. The driving method according to claim 1, wherein: The level compensation for the gate line to be compensated specifically includes: A gate driving signal including level compensation is provided to the gate line to be compensated through the flip chip film.

16. The driving method according to claim 15, wherein: The method of providing a gate drive signal including level compensation to the gate line to be compensated by using a chip-on-chip film specifically includes: Level compensation is applied within a pulse width time of 1% to 100% of the first effective level pulse provided by the chip-on-flip film, and the first effective level pulse after level compensation is used as a gate driving signal.

17. The driving method according to claim 16, wherein: A voltage value of the first effective level pulse after level compensation is applied is smaller than a voltage value of the last at least one second effective level pulse in a display period before the touch period.

18. The driving method according to claim 17, wherein: The difference between the voltage value of the second effective level pulse and the voltage value of the first effective level pulse after level compensation is 1.25% to 20% of the voltage value of the first effective level pulse before compensation.

19. The driving method according to claim 18, wherein: The voltage value of the first effective level pulse after loading level compensation is between 20V and 40V.

20. A display panel, wherein: The display panel is driven by the driving method according to any one of claims 1 to 19.

21. The display panel according to claim 20, wherein: It includes a gate drive circuit, multiple gate lines and 2N clock signal lines, wherein the gate drive circuit includes multiple shift registers arranged in cascade, wherein the input signal terminals of the first to N-th shift registers are connected to the frame trigger signal terminal, and except for the first to N-th shift registers, the input signal terminals of the remaining shift registers are respectively connected to the second output signal terminals of the shift registers N levels above them, the first output signal terminal of each level of the shift register is electrically connected to a corresponding gate line, and each adjacent 2N levels of the shift registers are electrically connected to the 2N clock signal lines, and N is a positive integer.

22. The display panel according to claim 21, wherein: The shift register includes: an input transistor, a reset transistor, a first output transistor, a second output transistor, a capacitor and a control circuit; The gate and the first electrode of the input transistor are both electrically connected to the input signal terminal, and the second electrode of the input transistor is electrically connected to the pull-up node; The gate of the reset transistor is electrically connected to the reset signal terminal, the first electrode of the reset transistor is electrically connected to the low-level power supply terminal, and the second electrode of the reset transistor is electrically connected to the pull-up node; The gate of the first output transistor is electrically connected to the pull-up node, the first electrode of the first output transistor is electrically connected to the clock signal line, the second electrode of the first output transistor is electrically connected to the first output signal terminal, and the first output signal terminal is electrically connected to the gate line; The capacitor is connected between the gate of the first output transistor and the first output signal terminal; The gate of the second output transistor is electrically connected to the pull-up node, the first electrode of the second output transistor is electrically connected to the clock signal line, the second electrode of the second output transistor is electrically connected to the second output signal terminal, and the second output signal terminal is electrically connected to the input signal terminal of the shift register N stages below it; The control circuit is electrically connected to the pull-up node, the first output signal terminal, the second output signal terminal and the control signal terminal, respectively. The control circuit is configured to control the levels of the pull-up node, the first output signal terminal and the second output signal terminal in response to a signal at the control signal terminal.

23. The display panel according to claim 20, wherein: The chip-on-film comprises a chip-on-film and a plurality of gate lines, wherein the chip-on-film comprises a plurality of terminals electrically connected to the gate lines respectively.

24. A display device, wherein: Comprising the display panel according to any one of claims 20-23.

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