Memory device and operating method of the memory device

Abstract

A memory device and an operating method of the memory device are provided. A memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation based on a target pump clock, and to perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks based on a number of data bits stored in a selected memory cell of the plurality of memory cells in which the memory operation is to be performed, and to control the peripheral circuit to perform the memory operation on the selected memory cell.

Description

Memory device and its operation method Technical Field

[0001] This disclosure generally relates to an electronic device, and more specifically, to a memory device and a method of operating the memory device. Background Technology

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device can include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are memory devices that store data only when powered on and lose the stored data when power is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0004] Non-volatile memory devices are memory devices whose data is not lost even when power is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0005] According to one aspect of this disclosure, a memory device may be provided, comprising: a plurality of memory cells; peripheral circuitry configured to generate a plurality of operating voltages for use in memory operations based on a target pump clock, and to perform memory operations by using the plurality of operating voltages; and control logic configured to select a target pump clock from the plurality of pump clocks based on the number of data bits stored in a selected memory cell for which a memory operation is to be performed, and to control the peripheral circuitry to perform a memory operation on the selected memory cell.

[0006] According to another aspect of this disclosure, a method for operating a memory device comprising a plurality of memory cells may be provided, the method comprising the steps of: determining a target pump clock among a plurality of pump clocks based on the number of data bits stored in a selected memory cell for which a memory operation is to be performed; generating a plurality of operating voltages for use in the memory operation based on the target pump clock; and performing the memory operation by using the plurality of operating voltages. Attached Figure Description

[0007] Examples of implementation methods will now be described more fully below with reference to the accompanying drawings; however, these implementation methods may be implemented in different forms and should not be construed as being limited to the implementation methods set forth herein.

[0008] In the accompanying drawings, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as being "between" two elements, that element may be the only element between the two elements, or there may be one or more intermediate elements. The same reference numerals always denote the same elements.

[0009] Figure 1 is a diagram illustrating a storage device according to one embodiment of the present disclosure.

[0010] Figure 2 is a diagram showing the structure of the memory device shown in Figure 1.

[0011] Figure 3 is a diagram showing the memory cell array shown in Figure 2.

[0012] Figure 4 is a diagram illustrating another embodiment of the memory cell array shown in Figure 2.

[0013] Figure 5 is a circuit diagram showing any of the memory blocks shown in Figure 4.

[0014] Figure 6 is a circuit diagram illustrating another embodiment of one of the memory blocks shown in Figure 4.

[0015] Figure 7 is a diagram showing the distribution of threshold voltages based on the number of data bits stored in a memory cell.

[0016] Figure 8 is a diagram showing the operation mode table used by the operation mode storage unit shown in Figure 2.

[0017] Figure 9 is a diagram illustrating the generation of operating voltage according to one embodiment of the present disclosure.

[0018] Figure 10 is a diagram showing the configuration and operation of the pump circuit shown in Figure 9.

[0019] Figure 11 is a flowchart illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0020] Figure 12 is a flowchart that shows the flowchart shown in Figure 11 in detail. Detailed Implementation

[0021] The specific structural and functional descriptions disclosed herein are merely illustrative and intended to describe embodiments based on the concepts outlined herein. Embodiments based on the concepts outlined herein can be implemented in various forms and should not be construed as limited to those described herein.

[0022] Some implementations provide a memory device with improved power consumption during memory operation and a method of operating the memory device.

[0023] Figure 1 is a diagram illustrating a storage device according to one embodiment of the present disclosure.

[0024] Referring to FIG1, the storage device 50 may include a memory device 100 and a memory controller 200 configured to control the operation of the memory device 100. The storage device 50 may be a means for storing data under the control of a host device, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet PC, or in-vehicle infotainment device.

[0025] Depending on the host interface used as the communication scheme with the host, the storage device 50 can be manufactured as any of various types of storage devices. For example, the storage device 50 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), micro MMC (micro-MMC), secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash storage (UFS) device, compact flash (CF) card, smart media card (SMC), memory stick, etc.

[0026] The storage device 50 can be manufactured in any of a variety of package types. For example, the storage device 50 can be manufactured in any of the following package types: point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0027] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array comprising a plurality of memory cells for storing data.

[0028] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0029] A memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0030] A memory block can be a unit used to erase data. In one embodiment, the memory device 100 can be a dual data rate synchronous dynamic random access memory (DDR SDRAM), a low power dual data rate 4 (LPDDR4) SDRAM, a graphics dual data rate (GDDR) SRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin-transfer torque random access memory (STT-RAM), etc. In this specification, for ease of description, the case where the memory device 100 is a NAND flash memory is assumed and described.

[0031] Memory device 100 receives commands and addresses from memory controller 200 and accesses regions in the memory cell array selected by address. That is, memory device 100 can perform operations instructed by commands on regions selected by address. For example, memory device 100 can perform write (programming) operations, read operations, and erase operations. In a programming operation, memory device 100 can program data into the region selected by address. In a read operation, memory device 100 can read data from the region selected by address. In an erase operation, memory device 100 can erase data stored in the region selected by address.

[0032] The memory controller 200 can control the overall operation of the storage device 50.

[0033] When power is applied to storage device 50, memory controller 200 may execute firmware (FW). When storage device 100 is a flash memory device, memory controller 200 may execute FW such as a flash translation layer (FTL) for controlling communication between the host and storage device 100.

[0034] In one embodiment, the memory controller 200 may receive data and logical block addresses (LBAs) from a host and translate the LBAs into physical block addresses (PBAs) that represent the addresses of memory cells in the memory device 100 where data will be stored.

[0035] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., in response to requests from the host. During programming operations, the memory controller 200 can provide programming commands, PBAs, and data to the memory device 100. During read operations, the memory controller 200 can provide read commands and PBAs to the memory device 100. During erase operations, the memory controller 200 can provide erase commands and PBAs to the memory device 100.

[0036] In one implementation, the memory controller 200 can autonomously generate commands, addresses, and data regardless of any requests from the host, and send these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0037] In one embodiment, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices according to an interleaving scheme to improve operational performance. The interleaving scheme can be an operation scheme that allows the operation periods of at least two memory devices 100 to overlap with each other.

[0038] The host can communicate with the storage device 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Unloaded DIMM (LRDIMM).

[0039] Figure 2 is a diagram showing the structure of the memory device shown in Figure 1.

[0040] Referring to Figure 2, the memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may be implemented in hardware, software, or a combination of both. For example, the control logic 130 may be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0041] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to address decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to read / write circuitry 123 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells can be defined as a physical page. That is, memory cell array 110 may be configured with multiple physical pages. According to one embodiment of this disclosure, each of the multiple memory blocks BLK1 to BLKz included in memory cell array 110 may include multiple dummy cells. One or more dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0042] Each memory cell of the memory device can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0043] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0044] The peripheral circuitry 120 drives the memory cell array 110. For example, the peripheral circuitry 120 can perform programming, reading, or erasing operations on the memory cell array 110.

[0045] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to one embodiment of this disclosure, word lines may include normal word lines and dummy word lines. According to one embodiment of this disclosure, row lines RL may also include pipe select lines.

[0046] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 receives the row address RADD of address ADDR from control logic 130.

[0047] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address in the received address ADDR. Address decoder 121 selects at least one word line from the word lines of the selected memory blocks based on the decoded row address. Address decoder 121 can apply an operating voltage Vop provided by voltage generator 122 to the selected word line.

[0048] During programming, address decoder 121 can apply a programming voltage to selected word lines and a pass voltage with a level lower than the programming voltage to unselected word lines. During programming verification, address decoder 121 can apply a verification voltage to selected word lines and a verification pass voltage with a level higher than the verification voltage to unselected word lines.

[0049] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and a read pass voltage at a level higher than the read voltage to the unselected word line.

[0050] According to one embodiment of this disclosure, an erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the address ADDR input to the memory device 100 includes a block address. An address decoder 121 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0051] According to one embodiment of this disclosure, address decoder 121 can decode a column address in an address ADDR sent to it. The decoded column address can be sent to read / write circuitry 123. In one example, address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0052] Voltage generator 122 can generate multiple operating voltages Vop by using the external power supply voltage provided to memory device 100. Voltage generator 122 operates under the control of control logic 130.

[0053] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0054] In one embodiment, voltage generator 122 can generate multiple operating voltages Vop by using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0055] To generate multiple operating voltages Vop with various voltage levels, voltage generator 122 may include multiple pump capacitors for receiving internal power supply voltages, and under the control of control logic 130, generate multiple operating voltages Vop by selectively activating the multiple pump capacitors. The multiple generated operating voltages Vop may be provided to memory cell array 110 by address decoder 121.

[0056] In one embodiment, voltage generator 122 can generate multiple operating voltages Vop used in memory operations based on a target pump clock. Voltage generator 122 can generate the target pump clock in response to a clock control signal and generate multiple operating voltages Vop based on the target pump clock. The multiple operating voltages Vop can include at least one of programming voltage, erase voltage, pass voltage, verification voltage, read voltage, and negative voltage.

[0057] The read / write circuit 123 includes first page buffers PB1 to m-th page buffers PBm. First page buffers PB1 to m-th page buffers PBm are connected to the memory cell array 110 via corresponding first bit lines BL1 to m-th bit lines BLm. First page buffers PB1 to m-th page buffers PBm operate under the control of control logic 130.

[0058] The first page buffer PB1 to the m-th page buffer PBm exchange data DATA with the data input / output circuit 124. During programming, the first page buffer PB1 to the m-th page buffer PBm receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0059] During programming, when a programming pulse is applied to a selected word line, page buffers PB1 through PBm (page m to page m) can transmit data DATA received via data input / output circuit 124 to a selected memory cell through bit lines BL1 through BLm. The selected memory cell is programmed based on the transmitted data DATA. Memory cells connected to bit lines through which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. Memory cells connected to bit lines through which a programming disable voltage (e.g., power supply voltage) is applied can maintain a constant threshold voltage. During programming verification, page buffers PB1 through PBm (page m to page m) read data DATA stored in the selected memory cell from the selected memory cell through bit lines BL1 through BLm.

[0060] In a read operation, the read / write circuit 123 can read data DATA from the memory cell of the selected page via the bit line BL, and store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0061] During an erase operation, the read / write circuit 123 can float the bit line BL. In one embodiment, the read / write circuit 123 may include column select circuitry.

[0062] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates under the control of the control logic 130.

[0063] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 outputs data sent from the first page buffer PB1 to the m-th page buffer PBm included in the read / write circuit 123 to the external controller.

[0064] In a read or verification operation, the sensing circuit 125 may generate a reference current in response to the enable bit VRYBIT signal generated by the control logic 130, and output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the read / write circuit 123 with the reference voltage generated by the reference current.

[0065] Control logic 130 can be connected to address decoder 121, voltage generator 122, read / write circuit 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0066] Control logic 130 can control peripheral circuitry 120 by generating several signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, read / write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, read / write circuit control signal PBSIGNALS to read / write circuit 123, and enable bit VRYBIT to sensing circuit 125. Furthermore, control logic 130 can determine whether the verification operation passed or failed in response to pass signal PASS or failure signal FAIL output by sensing circuit 125.

[0067] In one embodiment, peripheral circuitry 120 may generate multiple operating voltages based on a target pump clock. Peripheral circuitry 120 can then perform memory operations on selected memory cells from a plurality of memory cells using these multiple operating voltages. Memory operations may include at least one of programming, erasing, and reading operations.

[0068] Control logic 130 can select a target pump clock from multiple pump clocks based on the number of data bits stored in the selected memory cell from multiple memory cells to which the memory operation is to be performed. Control logic 130 can control peripheral circuitry 120 to perform memory operations on the selected memory cell.

[0069] In one embodiment, the control logic 130 may include an operation mode storage unit 131 and a memory operation controller 132.

[0070] The operation mode storage unit 131 can store an operation mode table including multiple pump clocks corresponding to multiple operation modes. The frequency of at least one of the multiple pump clocks can be different from the frequency of another pump clock.

[0071] The memory operation controller 132 can select a target operation mode from multiple operation modes based on a command CMD received from outside the memory device 100. In one embodiment, the memory operation controller 132 can select the target operation mode from multiple operation modes based on a command CMD received from, for example, the memory controller 200. The memory operation controller 132 can select a target pump clock corresponding to the target operation mode based on an operation mode table.

[0072] In one embodiment, the memory operation controller 132 can select a target operation mode from multiple operation modes based on the number of data bits stored in the selected memory cell. Memory operations are performed on the selected memory cell according to the command CMD. As the number of data bits to be stored in the selected memory cell decreases, the memory operation controller 132 can select a pump clock with a lower frequency as the target pump clock from multiple pump clocks. In another embodiment, as the power consumption required in the memory block decreases, the memory operation controller 132 can select a pump clock with a lower frequency as the target pump clock from multiple pump clocks.

[0073] The memory operation controller 132 can generate a clock control signal that indicates the generation of a target pump clock. The clock control signal can be included in the operation signal OPSIG.

[0074] Figure 3 is a diagram showing the memory cell array shown in Figure 2.

[0075] Referring to Figure 3, the memory cell array 110 may include first memory blocks BLK1 to BLKz, which are commonly connected to first bit lines BL1 to m-th bit lines BLm. In Figure 3, for ease of description, the components included in the first memory block BLK1 of the plurality of memory blocks BLK1 to BLKz are shown, and the components included in each of the other memory blocks BLK2 to BLKz are omitted. It should be understood that each of the other memory blocks BLK2 to BLKz is configured identically to the first memory block BLK1.

[0076] The memory block BLK1 may include multiple cell strings CS1_1 to CS1_m (m is a positive integer). The first cell string CS1_1 to the m-th cell string CS1_m are respectively connected to the first bit line BL1 to the m-th bit line BLm. Each of the first cell string CS1_1 to the m-th cell string CS1_m includes a drain selection transistor DST, multiple memory cells MC1 to MCn (n is a positive integer) connected in series, and a source selection transistor SST.

[0077] The gate terminal of the drain select transistor DST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the drain select line DSL1. The gate terminals of the first memory cell MC1 to the n-th memory cell MCn included in each of the first unit strings CS1_1 to the n-th word line WL1 to the n-th word line WLn are respectively connected to the first word line WL1 to the n-th word line WLn. The gate terminal of the source select transistor SST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the source select line SSL1.

[0078] For ease of description, the structure of the unit string will be described based on the first unit string CS1_1 among multiple unit strings CS1_1 to CS1_m. However, it should be understood that each of the other unit strings CS1_2 to CS1_m is configured identically to the first unit string CS1_1.

[0079] The drain terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the first bit line BL1. The source electrode of the drain select transistor DST included in the first cell string CS1_1 is connected to the drain terminal of the nth memory cell MCn included in the first cell string CS1_1. The first memory cells MC1 to the nth memory cell MCn are connected in series with each other. The drain terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the source terminal of the first memory cell MC1 included in the first cell string CS1_1. The source terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the common source line CSL. In one embodiment, the common source line CSL may be connected to the first memory block BLK1 to the zth memory block BLKz.

[0080] Drain select line DSL1, first word lines WL1 to nth word lines WLn, and source select line SSL1 are included in the row line RL shown in Figure 2. Drain select line DSL1, first word lines WL1 to nth word lines WLn, and source select line SSL1 are controlled by the address decoder 121 shown in Figure 2. The common source line CSL can be controlled by the control logic 130 shown in Figure 2. The first bit line BL1 to the mth bit line BLm are controlled by the read / write circuit 123 shown in Figure 2.

[0081] Figure 4 is a diagram illustrating another embodiment of the memory cell array shown in Figure 2.

[0082] Referring to FIG4, the memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate (not shown). The multiple memory cells may be arranged along the +X, +Y, and +Z directions. The structure of each memory block will be described in more detail with reference to FIGS. 5 and 6.

[0083] Figure 5 is a circuit diagram showing any one of the memory blocks BLKa from BLK1 to BLKz shown in Figure 4.

[0084] Referring to Figure 5, the storage block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the storage block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 5 shows two cell strings arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it should be understood that three cell strings may be arranged in the column direction.

[0085] In one implementation, a storage block may include multiple sub-blocks. A sub-block may include a string of cells arranged in a "U" shape on a column.

[0086] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0087] The selector transistors SST and DST, and the memory cells MC1 to MCn, can have structures similar to each other. In one embodiment, each of the selector transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In one embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0088] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0089] In one embodiment, source select transistors of cell strings arranged in the same row are connected to source select lines extending in the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 5, the source select transistors of cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21 to CS2m in the second row are connected to the second source select line SSL2.

[0090] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0091] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0092] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in opposite directions in the +Z direction and connected in series between the source selection transistor SST and the transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and connected in series between the transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected through the transistor PT. The gate electrodes of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0093] The gate of the transistor PT in each cell string is connected to the pipeline PL.

[0094] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0095] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. In Figure 5, the cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0096] Memory cells connected to the same word line in a cell string arranged in the row direction constitute a page. For example, memory cells connected to the first word line WL1 in cell strings CS11 to CS1m in the first row constitute one page. Memory cells connected to the first word line WL1 in cell strings CS21 to CS2m in the second row constitute another page. When either drain select line DSL1 or DSL2 is selected, a cell string arranged in a row direction can be selected. When any word line WL1 to WLn is selected, a page can be selected from the selected cell string.

[0097] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings in the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, and odd-numbered cell strings in the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines.

[0098] In one implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the operational reliability of the memory block BLKa improves. On the other hand, the size of the memory block BLKa increases. When the number of dummy memory cells decreases, the size of the memory block BLKa decreases. On the other hand, the operational reliability of the memory block BLKa may deteriorate.

[0099] To effectively control at least one dummy memory cell, the dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of the memory block BLKa. When an erase operation is performed after the programming operation, the dummy memory cell can have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0100] Figure 6 is a circuit diagram showing another embodiment of a storage block BLKb, one of the storage blocks BLK1 to BLKz shown in Figure 4.

[0101] Referring to Figure 6, the memory block BLKb may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) beneath the memory block BLKb.

[0102] In one implementation, a storage block may include multiple sub-blocks. A sub-block may include a string of cells arranged in an "I" shape in a column.

[0103] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a common source select line.

[0104] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gate electrodes of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0105] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0106] Therefore, except that the transistor PT is excluded from each cell string in Figure 6, the circuit of memory block BLKb in Figure 6 is similar to the circuit of memory block BLKa in Figure 5.

[0107] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be connected to the even-numbered bit lines, and odd-numbered cell strings in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be connected to the odd-numbered bit lines.

[0108] In one implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. When the number of dummy memory cells increases, the operational reliability of the memory block BLKb improves. On the other hand, the size of the memory block BLKb increases. When the number of dummy memory cells decreases, the size of the memory block BLKb decreases. On the other hand, the operational reliability of the memory block BLKb may deteriorate.

[0109] To effectively control at least one dummy memory cell, the dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of memory block BLKb. When an erase operation is performed after the programming operation, the dummy memory cell can have a desired threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0110] Figure 7 is a schematic diagram showing the distribution of threshold voltages based on the number of data bits stored in a memory cell.

[0111] Referring to Figure 7, a single-level cell (SLC) can be a memory cell that stores one data bit. A three-level cell (TLC) can be a memory cell that stores three data bits.

[0112] A single-level cell (SLC) can be programmed into either erase state E or programmable state P. A three-level cell (TLC) can be programmed into either erase state E or any of the first programming states P1 through the seventh programming states P7.

[0113] Vw1 can be the voltage window of the threshold voltage distribution of a single-stage cell (SLC). Vw2 can be the voltage window of the threshold voltage distribution of a three-stage cell (TLC). As the number of data bits stored in a memory cell increases, the threshold voltage distribution window of the memory cell can become wider.

[0114] As the threshold voltage distribution window widens, the operating voltage level required for memory operations can become higher. Memory operations can include at least one of programming, erasing, and reading operations. Therefore, as the number of data bits stored in a memory cell increases, the power consumption required in the memory device can increase. Conversely, as the number of data bits stored in a memory cell decreases, the power consumption required in the memory device can decrease.

[0115] In one implementation, the pump clock frequency can be increased as the power consumption of memory operations increases, and decreased as the power consumption of memory operations decreases. In another implementation, power efficiency can be improved by varying the pump clock frequency based on the power consumption of the memory device or the number of data bits stored in the memory cell performing the memory operation.

[0116] Figure 8 is a diagram showing the operation mode table used by the operation mode storage unit shown in Figure 2.

[0117] Referring to Figure 8, the operation mode storage unit can store an operation mode table, which includes multiple pump clocks CLK1 to CLKn (n is a natural number greater than 1) corresponding to multiple operation modes OM1 to OMn respectively. The frequency of at least one of the multiple pump clocks CLK1 to CLKn can be different from the frequency of the other clock.

[0118] Each of the first operation mode table 131a and the second operation mode table 131b can be an implementation of the operation mode table.

[0119] In the first operation mode table 131a, multiple operation modes can be distinguished from each other based on the number of data bits stored in the memory cell to be performed on the memory operation. For example, when the number of data bits stored in the memory cell is 1, the target operation mode can be OM1, and the target pump clock can be CLK1. When the number of data bits stored in the memory cell is 2, the target operation mode can be OM2, and the target pump clock can be CLK2. Similarly, when the number of data bits stored in the memory cell is n, the target operation mode can be OMn, and the target pump clock can be CLKn.

[0120] The frequency of the target pump clock can be increased as the number of data bits stored in the memory cell to be used for memory operations increases. Conversely, the frequency of the target pump clock can be decreased as the number of data bits stored in the memory cell to be used for memory operations decreases. In one embodiment, the frequency of the target pump clock can be increased as the number of data bits to be stored corresponding to the memory cell to be used for memory operations increases. In another embodiment, the frequency of the target pump clock can be decreased as the number of data bits to be stored corresponding to the memory cell to be used for memory operations decreases.

[0121] In the second operation mode table 131b, multiple operation modes can be distinguished from each other based on the power consumption level of the memory operation. For example, when the power consumption level is 1, the target operation mode can be OM1, and the target pump clock can be CLK1. When the power consumption level is 2, the target operation mode can be OM2, and the target pump clock can be CLK2. Similarly, when the power consumption level is n, the target operation mode can be OMn, and the target pump clock can be CLKn. As the power consumption level of the memory operation increases, the frequency of the target pump clock can be increased.

[0122] As the power consumption level of memory operations increases, the frequency of the target pump clock can be increased. As the power consumption level of memory operations decreases, the frequency of the target pump clock can be decreased.

[0123] Figure 9 is a diagram illustrating the generation of operating voltage according to one embodiment of the present disclosure.

[0124] Referring to FIG9, the operation mode storage unit 131 can store an operation mode table, which includes multiple pump clocks corresponding to multiple operation modes. The operation mode table can be configured as described above in FIG8.

[0125] The memory operation controller 132 can determine the target operation mode among multiple operation modes based on the received command CMD and the operation mode table stored in the operation mode storage unit 131.

[0126] The memory operation controller 132 can select a target operation mode from multiple operation modes based on the number of data bits stored in the memory cell to be executed according to the command CMD. The memory operation controller 132 can also select a target pump clock CLK corresponding to the target operation mode.

[0127] In one embodiment, as the number of data bits stored in a memory cell decreases, the memory operation controller 132 can select a pump clock with a lower frequency as the target pump clock CLK from a plurality of pump clocks. In another embodiment, as the power consumption required for memory operation decreases, the memory operation controller 132 can select a pump clock with a lower frequency as the target pump clock CLK from a plurality of pump clocks.

[0128] The memory operation controller 132 can generate a clock control signal CLK_CTL, which indicates the generation of the target pump clock CLK.

[0129] The voltage generator 122 may include a clock generator 122a and a pump circuit 122b.

[0130] Clock generator 122a can generate a target pump clock CLK in response to the clock control signal CLK_CTL.

[0131] Pump circuit 122b may include multiple pumps. Pump circuit 122b may generate multiple operating voltages Vop based on a target pump clock CLK. The multiple operating voltages Vop may include at least one of a programming voltage, an erase voltage, a pass voltage, a verification voltage, a read voltage, and a negative voltage.

[0132] Figure 10 is a diagram showing the configuration and operation of the pump circuit shown in Figure 9.

[0133] Referring to Figure 10, the pump circuit may include a first pump 1PMP to a fourth pump 4PMP.

[0134] The first pump (PMP 1) can output either a programming voltage (Vpgm) or an erase voltage (Vera) based on the memory operation to be performed, and the levels of these voltages can be adjusted based on the target pump clock (CLK). The second pump (PMP 2) can output a pass voltage (Vpass) based on the target pump clock (CLK). The third pump (PMP 3) can output either a verification voltage (Vvfy) or a read voltage (Vr) based on the memory operation to be performed, and the levels of these voltages can be adjusted based on the target pump clock (CLK). The fourth pump (PMP 4) can output a negative voltage (Vneg) based on the target pump clock (CLK).

[0135] As the frequency of the target pump clock CLK increases, the output voltage level can increase. As the frequency of the target pump clock CLK decreases, the output voltage level can decrease. For example, as the frequency of the target pump clock CLK increases, the programming voltage Vpgm or erase voltage Vera can increase. For example, as the frequency of the target pump clock CLK decreases, the programming voltage Vpgm or erase voltage Vera can decrease. For example, as the frequency of the target pump clock increases, the pass voltage Vpass can increase. For example, as the frequency of the target pump clock decreases, the pass voltage Vpass can decrease. For example, as the frequency of the target pump clock CLK increases, the verification voltage Vvfy or read voltage Vr can increase. For example, as the frequency of the target pump clock CLK decreases, the verification voltage Vvfy or read voltage Vr can decrease. For example, as the frequency of the target pump clock CLK increases, the negative voltage Vneg can increase. For example, as the frequency of the target pump clock CLK decreases, the negative voltage Vneg can decrease.

[0136] Therefore, when the power consumption level of memory operations is low, CLK1, with its lower frequency, can be selected as the target pump clock CLK between CLK1 and CLK2. When the power consumption level of memory operations is high, CLK2, with its higher frequency, can be selected as the target pump clock CLK between CLK1 and CLK2.

[0137] As shown in FIG7, the power consumption of memory operations can increase as the number of data bits stored in the memory cell to be used for memory operations increases. Conversely, the power consumption of memory operations can decrease as the number of data bits stored in the memory cell to be used for memory operations decreases. Therefore, when the number of data bits stored in the memory cell to be used for memory operations decreases, CLK1, with a lower frequency, can be selected as the target pump clock CLK between CLK1 and CLK2. When the number of data bits stored in the memory cell to be used for memory operations increases, CLK2, with a higher frequency, can be selected as the target pump clock CLK between CLK1 and CLK2.

[0138] The target pump clock CLK is not limited to this implementation and can be selected from multiple pump clocks. As the power consumption level of memory operations decreases, a pump clock with a lower frequency can be selected as the target pump clock CLK from among multiple pump clocks. As the number of data bits stored in the memory cell to perform memory operations decreases, a pump clock with a lower frequency can be selected as the target pump clock CLK from among multiple pump clocks.

[0139] Figure 11 is a flowchart illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0140] Referring to FIG11, in step S1101, the memory device may determine a target pump clock among multiple pump clocks based on the number of data bits stored in the memory cell to be performed memory operation.

[0141] In step S1103, the memory device may generate multiple operating voltages used in memory operations based on a target pump clock.

[0142] In step S1105, the memory device can perform memory operations by using the plurality of operating voltages.

[0143] Figure 12 is a flowchart that shows the flowchart shown in Figure 11 in detail.

[0144] Referring to FIG12, in step S1201, the memory device may select a target operation mode from multiple operation modes based on the number of data bits stored in the memory cell to be performed memory operation.

[0145] In step S1203, the memory device may select a target pump clock corresponding to the target operating mode based on the operating mode table.

[0146] In step S1205, the memory device may generate a clock control signal that indicates the generation of a target pump clock.

[0147] In step S1207, the memory device may generate a target pump clock based on a clock control signal.

[0148] In one implementation, step S1101 may correspond to steps S1201 and S1203. Step S1103 may correspond to steps S1205 and S1207.

[0149] According to this disclosure, in one embodiment, a memory device with improved power consumption during memory operation and a method of operating the memory device can be provided.

[0150] While this disclosure has been shown and described with reference to certain examples of embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described examples of embodiments, but should be defined not only by the appended claims but also by their equivalents.

[0151] In the above embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps do not necessarily have to be performed in the described order and can be reordered. The embodiments disclosed in this specification and accompanying drawings are merely examples to aid in understanding this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0152] Furthermore, examples of embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is for the purpose of explaining embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and various variations can be made within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure, in addition to the embodiments disclosed herein.

[0153] Cross-references to related applications

[0154] This application claims priority to Korean Patent Application No. 10-2021-0097567, filed with the Korean Intellectual Property Office on July 26, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: Multiple memory units; The peripheral circuitry generates multiple operating voltages used in memory operations based on a target pump clock, and performs the memory operations by using the multiple operating voltages. The control logic selects a target pump clock from among multiple pump clocks based on the number of data bits stored in the selected memory cell from among the plurality of memory cells to perform the memory operation, and controls the peripheral circuitry to perform the memory operation on the selected memory cell, wherein different frequencies of the target pump clock are selected according to different numbers of data bits.

2. The memory device according to claim 1, wherein, The control logic includes: an operation mode storage unit that stores an operation mode table, the operation mode table including a plurality of pump clocks corresponding to a plurality of operation modes; and a memory operation controller that selects a target operation mode among the plurality of operation modes based on a command received from outside the memory device, and selects a target pump clock corresponding to the target operation mode based on the operation mode table.

3. The memory device according to claim 2, wherein, At least one of the plurality of pump clocks has a frequency different from that of the other pump clock.

4. The memory device according to claim 2, wherein, As the power consumption required in the memory operation decreases, the memory operation controller selects a pump clock with a lower frequency from the plurality of pump clocks as the target pump clock.

5. The memory device according to claim 2, wherein, The memory operation controller selects the target operation mode from the plurality of operation modes based on the number of data bits stored in the selected memory cell for which the memory operation is to be performed according to the command.

6. The memory device according to claim 5, wherein, As the number of data bits stored in the selected memory cell decreases, the memory operation controller selects a pump clock with a lower frequency from the plurality of pump clocks as the target pump clock.

7. The memory device according to claim 2, wherein, The memory operation controller generates a clock control signal that indicates the generation of the target pump clock, and wherein the peripheral circuitry includes a voltage generator that generates the target pump clock in response to the clock control signal and generates the plurality of operating voltages based on the target pump clock.

8. The memory device according to claim 7, wherein, The voltage generator includes: a clock generator that generates the target pump clock in response to the clock control signal; and a pump circuit that generates the plurality of operating voltages based on the target pump clock.

9. The memory device according to claim 8, wherein, The pump circuit includes: a first pump that outputs one of a programming voltage and an erase voltage based on the target pump clock; a second pump that outputs a pass voltage based on the target pump clock; a third pump that outputs one of a verification voltage and a read voltage based on the target pump clock; and a fourth pump that outputs a negative voltage based on the target pump clock.

10. The memory device according to claim 1, wherein, The memory operation includes at least one of a programming operation, a reading operation, and an erasing operation on the selected memory cell.

11. A method of operating a memory device, the memory device comprising a plurality of memory cells, the method comprising the steps of: The target pump clock is determined from multiple pump clocks based on the number of data bits stored in the selected memory cell from which the memory operation is to be performed. Multiple operating voltages used in the memory operation are generated based on the target pump clock; And the memory operation is performed by using the plurality of operating voltages, wherein the frequency of the target pump clock is selected according to the different numbers of the data bits.

12. The method according to claim 11, wherein, The step of determining the target pump clock includes the following steps: selecting a target operating mode from multiple operating modes based on the number of data bits stored in the selected memory cell that is to perform the memory operation according to a command received from outside the memory device; and selecting the target pump clock corresponding to the target operating mode based on an operating mode table including multiple pump clocks corresponding to the multiple operating modes respectively.

13. The method according to claim 12, wherein, The step of selecting the target pump clock includes the following steps: as the number of data bits stored in the selected memory cell decreases, a pump clock with a lower frequency is selected from the plurality of pump clocks as the target pump clock.

14. The method according to claim 12, wherein, The step of selecting the target pump clock includes the following steps: as the power consumption required in the memory operation decreases, selecting a pump clock with a lower frequency from the plurality of pump clocks as the target pump clock.

15. The method according to claim 11, wherein, At least one of the plurality of pump clocks has a frequency different from that of the other pump clock.

16. The method according to claim 11, wherein, The step of generating the plurality of operating voltages includes the following steps: generating a clock control signal that indicates the generation of the target pump clock; generating the target pump clock in response to the clock control signal; and generating the plurality of operating voltages based on the target pump clock.

17. The method according to claim 11, wherein, The plurality of operating voltages include at least one of programming voltage, erase voltage, pass voltage, verification voltage, read voltage, and negative voltage.

18. The method according to claim 11, wherein, The memory operation includes at least one of a programming operation, a reading operation, and an erasing operation on the selected memory cell.

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