Dynamic memory parameter calibration method, device, equipment, medium and program product

Abstract

The embodiments of the present application provide a dynamic memory parameter calibration method, apparatus, device, medium, and program product. The method includes: training the dynamic memory DRAM based on multiple sets of test parameters to obtain digital eye diagrams corresponding to each set of test parameters; determining a target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram, wherein the first parameter is the difference between the maximum reference voltage and the minimum reference voltage in the digital eye diagram minus the difference in the eye width of the digital eye diagram; determining at least one of the target reference voltage and write delay of the dynamic memory based on the target digital eye diagram. Using the first parameter, a better target digital eye diagram is found from multiple frames of digital eye diagrams to take into account both the width margin and the eye height margin, thereby improving the symmetry of the digital eye diagram; calibrating the DRAM parameters using the target digital eye diagram improves the quality of parameter calibration and reduces the bit error rate of the DRAM.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a dynamic memory parameter calibration method, apparatus, device, medium, and program product. Background Art

[0002] In electronic devices, DRAM (Dynamic Random Access Memory) interacts with the CPU (Central Processing Unit) to read and write high-speed digital signals. Before normal DRAM read and write operations can begin, the DRAM must be trained to generate a digital eye diagram. DRAM debugging is then performed based on parameters such as the eye width and height of the digital eye diagram.

[0003] The DRAM receiver circuit causes the digital eye diagram to be asymmetric, making it impossible to take into account both the eye width margin and the eye height margin. For example, if a reference voltage with a good eye width margin is found in the horizontal direction and the DRAM reference voltage is calibrated based on the midpoint of the line segment corresponding to the eye width margin, the eye height margin, that is, the margin in the vertical direction, will not be optimized. This makes the DRAM susceptible to noise, resulting in a high sampling bit error rate and unable to meet the requirements of high-speed reading and writing.

[0004] Therefore, there is an urgent need to provide an optimized DRAM parameter calibration method to find a better point from the digital eye diagram to calibrate the DRAM parameters, so as to take into account both the eye width margin and the eye height margin. Summary of the Invention

[0005] The embodiments of the present application provide a dynamic memory parameter calibration method, apparatus, device, medium, and program product. By training the first parameter of the corresponding digital eye diagram through multiple rounds, a target digital eye diagram with better eye width margin and eye height margin is determined from multiple frames of digital eye diagrams. DRAM parameters are calibrated based on the target digital eye diagram, thereby improving the quality of parameter calibration and reducing the bit error rate of DRAM.

[0006] In a first aspect, an embodiment of the present application provides a method for calibrating dynamic memory parameters, the method comprising:

[0007] Based on multiple groups of test parameters, the dynamic memory is trained to obtain a digital eye diagram corresponding to each group of test parameters;

[0008] Determining a target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram, wherein the first parameter is a difference between a maximum reference voltage and a minimum reference voltage in the digital eye diagram minus a difference between eye widths of the digital eye diagram;

[0009] At least one of a target reference voltage and a write delay of the dynamic memory is determined based on a target digital eye diagram.

[0010] In some embodiments, the test parameter includes a delay of a receiver circuit of the dynamic memory.

[0011] In some implementations, performing an eye diagram scan on the dynamic memory based on multiple sets of test parameters to obtain a digital eye diagram corresponding to each set of test parameters includes:

[0012] adjusting the delay of a receiver circuit of the dynamic memory according to a preset step size;

[0013] At each delay, the dynamic memory is trained based on the data signal sent by the processor to obtain a digital eye diagram at the delay.

[0014] In some embodiments, the receiver circuit includes a decision feedback equalizer that adjusts the delay of the receiver circuit of the dynamic memory according to a preset step size, including:

[0015] The delay on the feedback path of the decision feedback equalizer is adjusted according to a preset step size.

[0016] In some implementations, training the dynamic memory based on multiple sets of test parameters to obtain a digital eye diagram corresponding to each set of test parameters includes:

[0017] During each round of training, read the value of the test register;

[0018] Determine the test parameters corresponding to the current round of training according to the value of the test register;

[0019] Training the dynamic memory according to the test parameters to obtain a digital eye diagram corresponding to this round of training;

[0020] Adjust the value of the test register.

[0021] In some implementations, determining the test parameters corresponding to the current round of training based on the value of the test register includes:

[0022] Obtaining a pre-established correspondence between the value of the test register and the test parameter;

[0023] Based on the corresponding relationship and the value of the read test register, the test parameters corresponding to the current round of training are determined.

[0024] In some implementations, determining a target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram includes:

[0025] For each round of training, calculate the first parameter of the digital eye diagram corresponding to this round of training;

[0026] If the first parameter is less than or equal to a preset threshold, the training is terminated;

[0027] The digital eye diagram corresponding to this round of training is determined as the target digital eye diagram.

[0028] In some implementations, determining a target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram includes:

[0029] The digital eye diagram with the smallest first parameter among the digital eye diagrams is determined as the target digital eye diagram.

[0030] In some embodiments, determining at least one of a target reference voltage and a write delay of the dynamic memory based on a target digital eye diagram includes:

[0031] Extracting the straight line where the eye width and the straight line where the eye height of the target digital eye diagram are located respectively;

[0032] The horizontal coordinate and the vertical coordinate of the intersection point of the straight line where the eye width is located and the straight line where the eye height is located are respectively determined as the write delay and the target reference voltage of the dynamic memory.

[0033] In some embodiments, the method further comprises:

[0034] configuring the target reference voltage in a mode register of the dynamic memory;

[0035] The write delay is configured in a register of the processor.

[0036] In some embodiments, the method further comprises:

[0037] An evaluation result of the dynamic memory is generated according to the target digital eye diagram.

[0038] In a second aspect, an embodiment of the present application provides a dynamic memory parameter calibration device, comprising:

[0039] An eye diagram acquisition module is used to train the dynamic memory based on multiple groups of test parameters to obtain a digital eye diagram corresponding to each group of test parameters;

[0040] a target eye diagram determining module, configured to determine a target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram, wherein the first parameter is a difference between a maximum reference voltage and a minimum reference voltage in the digital eye diagram minus a difference in eye width of the digital eye diagram;

[0041] The parameter determination module is used to determine at least one of a target reference voltage and a write delay of the dynamic memory based on a target digital eye diagram.

[0042] In some embodiments, the test parameter includes a delay of a receiver circuit of the dynamic memory.

[0043] In some implementations, the eye diagram acquisition module includes:

[0044] a delay adjustment unit, configured to adjust the delay of a receiver circuit of the dynamic memory according to a preset step size;

[0045] The first eye diagram acquisition unit is used to train the dynamic memory based on the data signal sent by the processor at each delay to obtain a digital eye diagram at the delay.

[0046] In some embodiments, the receiver circuit includes a decision feedback equalizer and a delay adjustment unit, specifically configured to:

[0047] The delay on the feedback path of the decision feedback equalizer is adjusted according to a preset step size.

[0048] In some implementations, the eye diagram acquisition module includes:

[0049] The value reading unit is used to read the value of the test register in each round of training;

[0050] A test parameter determination unit, configured to determine the test parameters corresponding to the current round of training according to the value of the test register;

[0051] A second eye diagram acquisition unit is used to train the dynamic memory according to the test parameters to obtain a digital eye diagram corresponding to this round of training;

[0052] A value adjustment unit is used to adjust the value of the test register.

[0053] In some embodiments, the test parameter determination unit is specifically configured to:

[0054] Obtaining a pre-established correspondence between the value of the test register and the test parameter;

[0055] Based on the corresponding relationship and the value of the read test register, the test parameters corresponding to the current round of training are determined.

[0056] In some implementations, the target eye diagram determination module is specifically configured to:

[0057] For each round of training, calculate the first parameter of the digital eye diagram corresponding to this round of training;

[0058] If the first parameter is less than or equal to a preset threshold, the training is terminated;

[0059] The digital eye diagram corresponding to this round of training is determined as the target digital eye diagram.

[0060] In some implementations, the target eye diagram determination module is specifically configured to:

[0061] The digital eye diagram with the smallest first parameter among the digital eye diagrams is determined as the target digital eye diagram.

[0062] In some embodiments, the parameter determination module is specifically configured to:

[0063] Extracting the straight line where the eye width and the straight line where the eye height of the target digital eye diagram are located respectively;

[0064] The horizontal coordinate and the vertical coordinate of the intersection point of the straight line where the eye width is located and the straight line where the eye height is located are respectively determined as the write delay and the target reference voltage of the dynamic memory.

[0065] In some embodiments, the apparatus further includes a parameter configuration module configured to:

[0066] configuring the target reference voltage in a mode register of the dynamic memory;

[0067] The write delay is configured in a register of the processor.

[0068] In some embodiments, the apparatus further comprises:

[0069] An evaluation module is used to generate an evaluation result of the dynamic memory according to the target digital eye diagram.

[0070] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: at least one processor and a memory;

[0071] The memory stores computer-executable instructions;

[0072] The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the method described in the first aspect.

[0073] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the method described in the first aspect is implemented.

[0074] In a fifth aspect, an embodiment of the present application further provides a computer program product, comprising a computer program, which implements the method described in the first aspect when executed by a processor.

[0075] The dynamic memory parameter calibration method, apparatus, device, medium, and program product provided by the embodiments of the present application require DRAM training before normal read and write operations are performed on the DRAM to improve the reliability of the read and write operations. In order to improve the quality of DRAM training and quickly find a digital eye diagram with a relatively good eye width margin and eye height margin, the following training method is provided: based on different test parameters, multiple rounds of DRAM training are performed to obtain a digital eye diagram corresponding to each round of training; based on a first parameter of the digital eye diagram, a target digital eye diagram with a relatively good eye width margin and eye height margin is determined from the obtained multiple frames of digital eye diagrams, wherein the first parameter is the difference between the maximum reference voltage and the minimum reference voltage in the word eye diagram minus the difference in eye width of the digital eye diagram; then, based on the target digital eye diagram, DRAM parameters (including at least one of the reference voltage and write delay) are calibrated, thereby quickly determining a reliable reference voltage and write delay, and performing DRAM read and write operations based on the determined parameters, thereby reducing the bit error rate of the DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the embodiments of the present application, and together with the description, are used to explain the principles of the embodiments of the present application.

[0077] Figure 1 Schematic diagram of a DRAM training process provided by an embodiment of the present application;

[0078] Figure 2 1 is a flow chart of a dynamic memory parameter calibration method provided in an embodiment of the present application;

[0079] Figure 3 A schematic diagram of a digital eye diagram provided in accordance with an embodiment of the present application;

[0080] Figure 4 A schematic flow chart of another dynamic memory parameter calibration method provided in an embodiment of the present application;

[0081] Figure 5 A schematic diagram of the structure of a chip provided in one embodiment of the present application;

[0082] Figure 6 For this application Figure 5 A schematic diagram of the structure of the DRAM in the embodiment shown;

[0083] Figure 7 A schematic flow chart of another dynamic memory parameter calibration method provided in an embodiment of the present application;

[0084] Figure 8 1 is a structural diagram of a dynamic memory parameter calibration device provided in an embodiment of the present application;

[0085] Figure 9 This is a structural block diagram of an electronic device provided in an embodiment of the present application.

[0086] The above drawings illustrate specific embodiments of the present invention, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present invention in any way, but rather to illustrate the concepts of the present invention for those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0087] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numbers in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0088] An eye diagram is a graph displayed by accumulating a series of digital signals on an oscilloscope. Due to the oscilloscope's persistence, the waveforms of each symbol scanned overlap, forming a pattern resembling an eye, hence the name "eye diagram." Because it represents the image of a digital signal, it is also called a digital eye diagram. Eye diagrams reveal the overall characteristics of digital signals and can be used to evaluate digital signal transmission performance.

[0089] Figure 1 This is a schematic diagram of a DRAM training process provided by an embodiment of the present application, referring to Figure 1 As shown in the figure, before normal DRAM operation, the DRAM controller first trains the DRAM. The DRAM controller transmits the eye diagram signal sent by the CPU (Central Processing Unit) to the DRAM, and then collects the signal output by the receiver circuit in the DRAM to form a digital eye diagram. The horizontal axis of the digital eye diagram represents the write delay, and the vertical axis represents the reference voltage. The DRAM controller then selects a point in the digital eye diagram with the best eye width margin and eye height margin to calibrate the DRAM write delay and reference voltage.

[0090] Due to the receiver circuit, the digital eye diagram is usually asymmetric, which makes it impossible to take into account both the eye width margin and the eye height margin. For example, in the horizontal direction, the reference voltage value with a better eye width margin is found, such as Figure 1 The reference voltage value corresponding to the straight line AB is selected to calibrate the DRAM parameters at the midpoint P of the line segment AB, that is, the write delay is calibrated based on the horizontal coordinate of point P, and the reference voltage is calibrated based on the vertical coordinate of point P. Figure 1It can be seen that due to the asymmetry of the digital eye diagram, the eye height margin corresponding to point P is not the maximum eye height. The optimal eye height margin is as follows: Figure 1 As shown by the straight line CD in , the difference between the eye width margin and the eye height margin is large, resulting in low accuracy of the determined parameters, which in turn affects the execution of DRAM read and write operations and causes a high DRAM bit error rate.

[0091] In order to improve the quality of DRAM parameter calibration, find better parameters, and thus reduce the bit error rate of DRAM, the present application provides a dynamic memory parameter calibration method, which performs multiple rounds of DRAM training through different test parameters to obtain a digital eye diagram under each test parameter, and based on the first parameter (the difference between the maximum reference voltage and the minimum reference voltage in the digital eye diagram minus the difference in the eye width of the digital eye diagram), selects a target digital eye diagram with better eye width margin and eye height margin, and performs DRAM parameter calibration based on the target digital eye diagram with better quality, thereby improving the accuracy of parameter calibration and thereby improving the yield of DRAM read and write operations.

[0092] Figure 2 FIG. 1 is a flow chart of a dynamic memory parameter calibration method provided by an embodiment of the present application. Figure 2 As shown, the dynamic memory parameter calibration method includes the following steps S201 to S203.

[0093] S201 , training the dynamic memory based on multiple groups of test parameters to obtain a digital eye diagram corresponding to each group of test parameters.

[0094] The test parameters are used to adjust the symmetry of the digital eye diagram, and the test parameters may include parameters of a receiver circuit in a dynamic memory DRAM.

[0095] Training dynamic memory, specifically DQ training of DRAM. After the test parameters are configured, the DRAM controller is controlled to transmit the training signals (DQ and DQS) output by the processor to the DRAM to perform DQ training on the DRAM. Based on the training signals received by the DRAM, a digital eye diagram is generated.

[0096] The training signal is an input signal corresponding to data of a specific pattern, so as to write or read the data of the specific pattern in the DRAM.

[0097] The training signal can be divided into a write training signal. The write training signal is used to perform write training on the DRAM, so as to perform DRAM training by writing corresponding data in the DRAM.

[0098] The DQ signal is a data signal, and the DQS signal is a signal for synchronizing the DQ signal between the DRAM and the DRAM controller.

[0099] Each set of test parameters can correspond to one or more digital eye diagrams.

[0100] A test parameter sequence may be generated in advance, the test parameter sequence including a plurality of different test parameters, and then the first test parameter in the test parameter sequence is sequentially taken out to train the DRAM to obtain a digital eye diagram corresponding to the test parameter.

[0101] In some embodiments, the test parameter includes a delay of a receiver circuit of a dynamic memory DRAM.

[0102] The delay of the receiver circuit may include a plurality of adjustable gears, and the delay of the receiver circuit corresponds to different gears in different test parameters.

[0103] S202 : Determine a target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram.

[0104] The first parameter is the difference between the maximum and minimum reference voltages in the digital eye diagram minus the difference in the eye width. The maximum reference voltage Vmax is the ordinate of the point with the largest ordinate in the digital eye diagram, while the minimum reference voltage Vmin is the ordinate of the point with the smallest ordinate in the digital eye diagram. The eye width Vw is the time difference between two crossing points in the digital eye diagram.

[0105] Based on the first parameter of each digital eye diagram, a target digital eye diagram with better eye width margin and eye height margin can be determined from each digital eye diagram.

[0106] The maximum reference voltage Vmax, minimum reference voltage Vmin and eye width Vw of the digital eye diagram can be obtained by manually selecting points.

[0107] After each digital eye diagram is obtained, the maximum reference voltage Vmax, the minimum reference voltage Vmin and the eye width Vw of the digital eye diagram are automatically extracted, and based on the extracted three parameters, the first parameter corresponding to the digital eye diagram is calculated.

[0108] The maximum reference voltage Vmax and minimum reference voltage Vmin in the digital eye diagram can be determined by determining the upper and lower boundaries of the digital eye diagram. The eye width Vw can be the time difference corresponding to the longest line segment of the line parallel to the horizontal axis intercepted by the digital eye diagram. In other words, the maximum difference between the horizontal coordinates of the two points where the line parallel to the horizontal coordinate intersects the digital eye diagram is the eye width.

[0109] For example, Figure 3 A schematic diagram of a digital eye diagram provided in one embodiment of the present application is shown in FIG. Figure 3 In the embodiment, the eye diagram is approximately rhombus-shaped. In some embodiments, the eye diagram can also be approximately hexagonal, such as Figure 3 As shown, the horizontal axis of the digital eye diagram is time t, that is, delay, and the vertical axis is voltage V, that is, reference voltage. Figure 3 The point corresponding to the maximum reference voltage Vmax of the digital eye diagram is point a, the point corresponding to the minimum reference voltage Vmin is point b, and the eye width Vw is the time difference corresponding to the line segment cd.

[0110] In some embodiments, determining a target digital eye diagram from the digital eye diagrams based on the first parameter of the digital eye diagram includes:

[0111] The digital eye diagram with the smallest first parameter among the digital eye diagrams is determined as the target digital eye diagram.

[0112] The first parameter is the difference between the maximum reference voltage Vmax and the minimum reference voltage Vmin, and the eye width Vw. The smaller the first parameter, the smaller the difference between the eye height margin and the eye width margin of the corresponding digital eye diagram, and the better the symmetry of the digital eye diagram. Therefore, the digital eye diagram with the smallest first parameter is determined as the target digital eye diagram, which improves the symmetry of the target digital eye diagram and achieves optimization of the digital eye diagram.

[0113] In some embodiments, in order to increase the speed of determining the target digital eye diagram, the first digital eye diagram whose corresponding first parameter is less than a preset threshold can be determined as the target digital eye diagram, thereby eliminating the need to calculate the first parameters of all digital eye diagrams.

[0114] S203 : Determine at least one of a target reference voltage and a write delay of the dynamic memory based on a target digital eye diagram.

[0115] The target reference voltage is used to calibrate the reference voltage of the DRAM, and the write delay is used to calibrate the write delay time of the DRAM.

[0116] During a normal write operation, the receiver circuit determines whether the input signal is “0” or “1” by comparing the DQ signal with a configured reference voltage (ie, a target reference voltage).

[0117] In some embodiments, the receiver circuit includes a DFE (Decision Feedback Equalization) module. DFE is a nonlinear equalizer consisting of a feedforward part and a feedback part. The feedforward part can offset the inter-symbol interference that is ahead in time and the inter-symbol interference that is delayed in time, and the feedback part can offset the inter-symbol interference that is delayed in time.

[0118] Specifically, a set point can be determined from the target digital eye diagram; the horizontal coordinate of the set point is determined to be the write delay of the dynamic memory DRAM, and the vertical coordinate of the set point is determined to be the target reference voltage of the DRAM. Normal read, write, and addressing operations can then be performed based on the determined write delay and target reference voltage.

[0119] The set point may be the center of a circumscribed rectangle corresponding to the digital eye diagram, or the center of a diamond or hexagon corresponding to the digital eye diagram.

[0120] A target area for determining a set point can be determined based on the upper and lower boundaries of the digital eye diagram, and a corresponding set point can be determined from the target area. The set point is the point in the target area where a second parameter is the largest, where the second parameter is the sum of the distance between the two points where a straight line passing through the set point and parallel to the abscissa intersects the digital eye diagram, and the distance between the two points where a straight line passing through the set point and parallel to the ordinate intersects the digital eye diagram.

[0121] The dynamic memory parameter calibration method provided in this embodiment requires training the DRAM before normal read and write operations to improve the reliability of the read and write operations. To improve the quality of DRAM training and quickly find a digital eye diagram with relatively good eye width margin and eye height margin, the following training method is provided: based on different test parameters, multiple rounds of DRAM training are performed to obtain digital eye diagrams corresponding to each round of training; based on a first parameter of the digital eye diagram, a target digital eye diagram with relatively good eye width margin and eye height margin is determined from the obtained multiple frames of digital eye diagrams, where the first parameter is the difference between the maximum reference voltage and the minimum reference voltage in the digital eye diagram minus the difference in eye width of the digital eye diagram; then, based on the target digital eye diagram, DRAM parameters (including at least one of the reference voltage and write delay) are calibrated, thereby quickly determining a reliable reference voltage and write delay, and performing DRAM read and write operations based on the determined parameters, thereby reducing the DRAM bit error rate.

[0122] Figure 4 A flow chart of another dynamic memory parameter calibration method provided in an embodiment of the present application. Figure 2 Based on the embodiment shown, step S201 and step S203 are further refined, and steps related to target reference voltage and write delay storage are added after step S203. In this embodiment, the test parameter is the delay of the receiver circuit as an example. Figure 4 As shown, the dynamic memory parameter calibration method includes the following steps S401 to S406.

[0123] S401 : Adjust the delay of the receiver circuit of the dynamic memory according to a preset step size.

[0124] The time interval corresponding to the preset step length can be determined according to the UI (Unit Interval, bit data duration) corresponding to the DRAM and the total number of steps.

[0125] A digital eye diagram typically shows a time window of 1.25UI.

[0126] Taking a UI of 200 ps as an example (data rate is 5 Gbps), if the total number of steps is 8, the time interval corresponding to the preset step size is 25 ps.

[0127] The initial value of the receiver circuit delay can be 0, the maximum value, the minimum value, or another value. In subsequent training, the receiver circuit delay is increased or decreased based on a preset step size, resulting in a different receiver circuit delay for each round of training. Specifically, the feedback voltage output by the DFE module in the receiver circuit can be used to train the DRAM digital eye diagram delay.

[0128] The DFE module is used to eliminate the influence of the previous bit (data written in the previous round of training) on ​​the next bit (data written in the next round of training) by pulling down or raising the residual voltage of the previous bit. For example, when the previous bit is 1, the residual voltage is positive. In this way, the DFE module pulls down the positive voltage to avoid affecting the subsequent written data.

[0129] Exemplarily, the delay of the receiver circuit corresponding to each round of training can be: 0, -1step, 1step, -2step, 2step, and so on. One step is the time interval corresponding to the above preset step size, and -1step means that the delay is reduced by 1 time interval. Taking the time interval of 25ps as an example, the delay of the receiver circuit corresponding to -1step is -25ps, 2step is 50ps, and so on.

[0130] In some embodiments, the receiver circuit includes a decision feedback equalizer, which adjusts the delay of the receiver circuit of the dynamic memory according to a preset step size, including:

[0131] The delay on the feedback path of the decision feedback equalizer is adjusted according to a preset step size.

[0132] S402 : At each delay, the dynamic memory is trained based on the data signal sent by the processor to obtain a digital eye diagram at the delay.

[0133] The delay of each receiver circuit corresponds to one round of training. During each round of training, the test parameter is the delay of the receiver circuit corresponding to that round of training. Based on the data signal sent by the processor, the DRAM is trained to obtain the digital eye diagram corresponding to that round of training.

[0134] For example, Figure 5 A schematic diagram of the structure of a chip provided in one embodiment of the present application is shown in FIG. Figure 5 As shown, the chip includes a central processing unit (CPU), a graphics processing unit (GPU), other logic modules, a cache, a DRAM controller, a physical interface (PHY), and DRAM. During each training round, the DRAM controller transmits the data signal (DQ signal) sent by the CPU to the DRAM via the PHY to train the DRAM. Based on the signal output by the DRAM's DQ pin, it forms the digital eye diagram corresponding to that training round.

[0135] Figure 6 For this application Figure 5 The structural diagram of the DRAM in the embodiment shown is as follows: Figure 6 As shown, the DRAM includes an internal circuit and a receiver circuit. The receiver circuit includes an input buffer module and a delay control module. The input buffer module determines whether the signal input to the DRAM internal circuit is "0" or "1" by comparing the DQ signal input by the CPU with the reference voltage Vref. The delay control module is used to control the delay of the DQ signal. Its input signal includes the feedback voltage output by the DFE module and the delay of the current round of training stored in the register, such as the delay stored in MRxx OP[3:0]. The feedback voltage output by the DFE module is used to increase or decrease the residual voltage in the input buffer module, thereby eliminating the influence of the previous bit written on the next bit. The delay stored in MRxx OP[3:0] is used to adjust the delay of the DQ signal corresponding to each round of training, so as to perform DRAM write training with different delays and obtain a digital eye diagram with better eye width margin and eye height margin.

[0136] By adjusting the test parameter delay with a fixed preset step size, multiple rounds of training can be performed, resulting in high training efficiency.

[0137] S403: Calculate the first parameter of each digital eye diagram.

[0138] S404 , determining a digital eye pattern with the smallest first parameter among the digital eye patterns as the target digital eye pattern.

[0139] S405 , respectively extracting a straight line where the eye width and the eye height of the target digital eye diagram are located.

[0140] In some embodiments, the straight line of eye width is parallel to the horizontal axis of the digital eye diagram and is the straight line with the largest distance between the intersection with the digital eye diagram; the straight line of eye height is parallel to the vertical axis and is the straight line with the largest distance between the intersection with the digital eye diagram.

[0141] In some embodiments, the straight line where the eye height is located can be determined based on the position of the maximum reference voltage point and the position of the minimum reference voltage point in the digital eye diagram, and the straight line where the eye width is located can be determined based on the position of the two intersection points of the digital eye diagram.

[0142] S406 , respectively determining the abscissa and ordinate of the intersection of the straight line where the eye width is located and the straight line where the eye height is located, which are used as the write delay and target reference voltage of the dynamic memory.

[0143] The intersection of the line where the eye width lies and the line where the eye height lies is set as the set point. The horizontal coordinate of the set point is determined to be the write delay, and the vertical coordinate is determined to be the target reference voltage.

[0144] S407 , configuring the target reference voltage in the mode register of the dynamic memory, and configuring the write delay in the register of the processor.

[0145] After obtaining the write delay and target reference voltage, in order to facilitate the calibration of corresponding parameters during DRAM operation based on the write delay and target reference voltage, the target reference voltage can be stored in the DRAM mode register (Mode R, MR), and the write delay can be stored in the processor register.

[0146] In this embodiment, the delay of the receiver circuit is used as a test parameter, and the delay of the receiver circuit is adjusted through a fixed preset step size to achieve multiple rounds of DRAM training based on different delays, thereby improving training efficiency. The symmetry of the generated digital eye diagram is also adjusted by adjusting the delay of the receiver circuit. Based on the first parameter, the digital eye diagram with the best symmetry is selected from the multiple digital eye diagrams obtained as the target digital eye diagram. A set point that takes into account both the eye width margin and the eye height margin is determined from the target digital eye diagram to calibrate the DRAM parameters, thereby improving the yield of the DRAM during normal operation and reducing crosstalk and bit error rate during signal transmission.

[0147] In some embodiments, after determining the target digital eye diagram, the method further includes:

[0148] An evaluation result of the dynamic memory is generated according to the target digital eye diagram.

[0149] Specifically, DRAM evaluation results can be generated based on parameters such as eye width, eye height, eye amplitude, eye crossing ratio, and extinction ratio corresponding to the target digital eye diagram.

[0150] Figure 7 A flow chart of another dynamic memory parameter calibration method provided in an embodiment of the present application. Figure 2 Based on the embodiment shown, step S201 and step S202 are further refined, as shown in FIG. Figure 7As shown, the dynamic memory parameter calibration method includes the following steps S701 to S708.

[0151] S701, during each round of training, read the value of the test register.

[0152] The test register is used to store the binary value corresponding to the test parameter.

[0153] S702: Determine test parameters corresponding to this round of training according to the value of the test register.

[0154] Specifically, the delay of the receiver circuit corresponding to the current round of training may be determined according to the binary number stored in the test register.

[0155] In some embodiments, determining the test parameters corresponding to the current round of training according to the value of the test register includes:

[0156] Obtain a pre-established correspondence between the value of the test register and the test parameter; and determine the test parameter corresponding to the current round of training based on the correspondence and the value of the read test register.

[0157] In some embodiments, the delay corresponding to each binary number can be found through a lookup table. For example, the delay corresponding to 0000 is 0, the delay corresponding to 0001 is -25 ps, the delay corresponding to 0010 is 25 ps, and so on.

[0158] After reading the value of the test register, the register value can be adjusted according to the preset rules to obtain the test parameters corresponding to the next round of training.

[0159] S703: Training the dynamic memory according to the test parameters to obtain a digital eye diagram corresponding to this round of training.

[0160] S704: Adjust the value of the test register.

[0161] Step S704 can be executed at any time point after step S701 and before the next round of training, such as being executed in parallel or serially with any step after step S701 to update the value of the test register before the next round of training. This application does not limit the execution timing of step S704.

[0162] In some embodiments, the initial value of the binary number stored in the test register is 0000. Adjusting the value of the test register can specifically be to increase the binary number stored in the test register by 1, thereby updating the binary number stored in the test register, and adjusting the delay of the receiver circuit forward or backward, thereby adjusting the symmetry of the digital eye diagram.

[0163] S705 , for each round of training, calculating a first parameter of the digital eye diagram corresponding to the current round of training.

[0164] S706: If the first parameter is less than or equal to a preset threshold, end the training.

[0165] Specifically, it can be determined whether the first parameter of the digital eye diagram corresponding to this round of training is greater than a preset threshold; if not, execute step S707; if so, execute step S704, and after executing step S704, return to step S701 to perform the next round of training.

[0166] S707: Determine the digital eye diagram corresponding to this round of training as the target digital eye diagram.

[0167] The preset threshold value may be a fixed value, or a value that is adaptively set according to DRAM performance parameters, usage requirements, and the like.

[0168] If the first parameter of the digital eye diagram obtained by the current training is less than or equal to the preset threshold, the training is terminated in advance, that is, no subsequent training is required, and the digital eye diagram corresponding to the current round of training is directly determined to be the required target digital eye diagram.

[0169] If the first parameter of the digital eye diagram obtained by the current training is greater than the preset threshold, the digital eye diagram obtained by the current training and its first parameter are stored, and the next round of training is performed, and so on, until the first parameter of the digital eye diagram obtained is less than or equal to the preset threshold, or the number of training rounds reaches the preset number of rounds.

[0170] S708 : Determine at least one of a target reference voltage and a write delay of the dynamic memory based on the target digital eye diagram.

[0171] If the first parameter is greater than the preset threshold, the next round of training is performed, and steps S701 to S707 are repeated, that is, the value of the test register is read again, so that the DRAM is trained with the new test parameters to obtain a new digital eye diagram, and the first parameter of the digital eye diagram is calculated. If the first parameter is less than or equal to the preset threshold, the training is terminated.

[0172] If there is still no digital eye diagram whose first parameter is less than or equal to the preset threshold after the training is completed, the digital eye diagram with the minimum first parameter is determined as the target digital eye diagram.

[0173] Exemplarily, when the first parameter is greater than a preset threshold, the value of the test register may be adjusted, thereby returning to step S701 to perform the next round of training.

[0174] In this way, the first digital eye diagram that satisfies the first parameter less than or equal to the preset threshold can be determined as the target digital eye diagram, thereby terminating the training early, improving the training rate, and improving the rate of determining the target digital eye diagram.

[0175] Corresponding to the above method embodiment, Figure 8 Schematic diagram of a dynamic memory parameter calibration device provided by an embodiment of the present application. Figure 8 As shown, the dynamic memory parameter calibration device includes: an eye diagram acquisition module 810 , a target eye diagram determination module 820 and a parameter determination module 830 .

[0176] Among them, the eye diagram acquisition module 810 is used to train the dynamic memory based on multiple groups of test parameters to obtain digital eye diagrams corresponding to each group of test parameters; the target eye diagram determination module 820 is used to determine the target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram, wherein the first parameter is the difference between the maximum reference voltage and the minimum reference voltage in the digital eye diagram minus the difference in the eye width of the digital eye diagram; the parameter determination module 830 is used to determine at least one of the target reference voltage and write delay of the dynamic memory based on the target digital eye diagram.

[0177] In some embodiments, the test parameter includes a delay of a receiver circuit of the dynamic memory.

[0178] In some implementations, the eye diagram acquisition module 810 includes:

[0179] a delay adjustment unit, configured to adjust the delay of a receiver circuit of the dynamic memory according to a preset step size;

[0180] The first eye diagram acquisition unit is used to train the dynamic memory based on the data signal sent by the processor at each delay to obtain a digital eye diagram at the delay.

[0181] In some embodiments, the receiver circuit includes a decision feedback equalizer and a delay adjustment unit, specifically configured to:

[0182] The delay on the feedback path of the decision feedback equalizer is adjusted according to a preset step size.

[0183] In some implementations, the eye diagram acquisition module 810 includes:

[0184] The value reading unit is used to read the value of the test register in each round of training;

[0185] A test parameter determination unit, configured to determine the test parameters corresponding to the current round of training according to the value of the test register;

[0186] A second eye diagram acquisition unit is used to train the dynamic memory according to the test parameters to obtain a digital eye diagram corresponding to this round of training;

[0187] A value adjustment unit is used to adjust the value of the test register.

[0188] In some embodiments, the test parameter determination unit is specifically configured to:

[0189] Obtaining a pre-established correspondence between the value of the test register and the test parameter;

[0190] Based on the corresponding relationship and the value of the read test register, the test parameters corresponding to the current round of training are determined.

[0191] In some implementations, the target eye diagram determination module 820 is specifically configured to:

[0192] For each round of training, calculate the first parameter of the digital eye diagram corresponding to this round of training;

[0193] If the first parameter is less than or equal to a preset threshold, the training is terminated;

[0194] The digital eye diagram corresponding to this round of training is determined as the target digital eye diagram.

[0195] In some implementations, the target eye diagram determination module 820 is specifically configured to:

[0196] The digital eye diagram with the smallest first parameter among the digital eye diagrams is determined as the target digital eye diagram.

[0197] In some implementations, the parameter determination module 830 is specifically configured to:

[0198] Extracting the straight line where the eye width and the straight line where the eye height of the target digital eye diagram are located respectively;

[0199] The horizontal coordinate and the vertical coordinate of the intersection point of the straight line where the eye width is located and the straight line where the eye height is located are respectively determined as the write delay and the target reference voltage of the dynamic memory.

[0200] In some embodiments, the apparatus further includes a parameter configuration module configured to:

[0201] configuring the target reference voltage in a mode register of the dynamic memory;

[0202] The write delay is configured in a register of the processor.

[0203] In some embodiments, the apparatus further comprises:

[0204] An evaluation module is used to generate an evaluation result of the dynamic memory according to the target digital eye diagram.

[0205] The above device embodiment is an embodiment corresponding to the above method embodiment and has the same technical effects as the method embodiment. The detailed description of the device embodiment can refer to the detailed description of the above method embodiment and will not be repeated here.

[0206] An embodiment of the present application also provides an electronic device, including: at least one processor and a memory.

[0207] The memory stores computer-executable instructions. The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the above-mentioned dynamic memory parameter calibration method.

[0208] Figure 9 9 is a block diagram of a structure of an electronic device provided in an embodiment of the present application. The electronic device includes a memory 910 and at least one processor 920.

[0209] The memory 910 stores computer-executable instructions.

[0210] At least one processor 920 executes the computer-executable instructions stored in the memory 910 , so that the electronic device implements the aforementioned dynamic memory parameter calibration method.

[0211] The memory 910 and the processor 920 are connected via a bus 930 .

[0212] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the processor implements the dynamic memory parameter calibration method provided in any embodiment of the present application.

[0213] An embodiment of the present application further provides a computer program product, including a computer program, which, when executed by a processor, implements the dynamic memory parameter calibration method provided in any embodiment of the present application.

[0214] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0215] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0216] The above are only preferred embodiments of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of the embodiments of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the embodiments of the present application.

Claims

1. A method for calibrating dynamic memory parameters, characterized in that: include: Based on multiple groups of test parameters, the dynamic memory is trained to obtain a digital eye diagram corresponding to each group of test parameters; Determining a target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram, wherein the first parameter is a difference between a maximum reference voltage and a minimum reference voltage in the digital eye diagram minus a difference between eye widths of the digital eye diagram; Determining at least one of a target reference voltage and a write delay of the dynamic memory based on a target digital eye diagram; The method of determining a target digital eye diagram from each digital eye diagram based on the first parameter of the digital eye diagram includes: The digital eye diagram with the smallest first parameter among the digital eye diagrams is determined as the target digital eye diagram.

2. The method according to claim 1, characterized in that The test parameter includes a delay of a receiver circuit of the dynamic memory.

3. The method according to claim 2, characterized in that Based on multiple groups of test parameters, an eye diagram scan is performed on the dynamic memory to obtain a digital eye diagram corresponding to each group of test parameters, including: adjusting the delay of a receiver circuit of the dynamic memory according to a preset step size; At each delay, the dynamic memory is trained based on the data signal sent by the processor to obtain a digital eye diagram at the delay.

4. The method according to claim 3, characterized in that The receiver circuit includes a decision feedback equalizer, which adjusts the delay of the receiver circuit of the dynamic memory according to a preset step size, including: The delay on the feedback path of the decision feedback equalizer is adjusted according to a preset step size.

5. The method according to claim 1, wherein The dynamic memory is trained based on multiple groups of test parameters to obtain digital eye diagrams corresponding to each group of test parameters, including: During each round of training, read the value of the test register; Determine the test parameters corresponding to the current round of training according to the value of the test register; Training the dynamic memory according to the test parameters to obtain a digital eye diagram corresponding to this round of training; Adjust the value of the test register.

6. The method according to claim 5, characterized in that Determine the test parameters corresponding to this round of training according to the value of the test register, including: Obtaining a pre-established correspondence between the value of the test register and the test parameter; Based on the corresponding relationship and the value of the read test register, the test parameters corresponding to the current round of training are determined.

7. The method according to claim 5, characterized in that Determining a target digital eye diagram from the digital eye diagrams based on a first parameter of the digital eye diagrams includes: For each round of training, calculate the first parameter of the digital eye diagram corresponding to this round of training; If the first parameter is less than or equal to a preset threshold, the training is terminated; The digital eye diagram corresponding to this round of training is determined as the target digital eye diagram.

8. The method according to any one of claims 1 to 7, characterized in that Determining at least one of a target reference voltage and a write delay of the dynamic memory based on a target digital eye diagram includes: Extracting the straight line where the eye width and the straight line where the eye height of the target digital eye diagram are located respectively; The horizontal coordinate and the vertical coordinate of the intersection point of the straight line where the eye width is located and the straight line where the eye height is located are respectively determined as the write delay and the target reference voltage of the dynamic memory.

9. The method according to claim 8, characterized in that The method further comprises: configuring the target reference voltage in a mode register of the dynamic memory; The write delay is configured in a register of the processor.

10. The method according to any one of claims 1 to 7, characterized in that The method further comprises: An evaluation result of the dynamic memory is generated according to the target digital eye diagram.

11. A dynamic memory parameter calibration device, characterized in that: include: An eye diagram acquisition module is used to train the dynamic memory based on multiple groups of test parameters to obtain a digital eye diagram corresponding to each group of test parameters; a target eye diagram determining module, configured to determine a target digital eye diagram from each digital eye diagram based on a first parameter of the digital eye diagram, wherein the first parameter is a difference between a maximum reference voltage and a minimum reference voltage in the digital eye diagram minus a difference in eye width of the digital eye diagram; a parameter determination module, configured to determine at least one of a target reference voltage and a write delay of the dynamic memory based on a target digital eye diagram; The method of determining a target digital eye diagram from each digital eye diagram based on the first parameter of the digital eye diagram includes: The digital eye diagram with the smallest first parameter among the digital eye diagrams is determined as the target digital eye diagram.

12. An electronic device, characterized in that: include: at least one processor and memory; The memory stores computer-executable instructions; The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the method according to any one of claims 1 to 10 is implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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