Semiconductor structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor structure and a method for manufacturing the same, including: providing a substrate including a core NMOS region, a core PMOS region, and a peripheral NMOS region; oxidizing the substrate in the core PMOS region to convert a portion of the substrate thickness in the core PMOS region into an oxide layer; removing the oxide layer; forming a first semiconductor layer on the remaining substrate in the core PMOS region, wherein the hole mobility in the first semiconductor layer is greater than the hole mobility in the substrate in the core PMOS region; forming a gate dielectric layer, the gate dielectric layer being located on the first semiconductor layer and on the substrate in the core NMOS region and the peripheral NMOS region; and forming a gate on the gate dielectric layer. The present invention relates to the field of semiconductors and is advantageous in reducing the height difference between the core PMOS region and the core NMOS region, thereby facilitating subsequent production processes.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Generally, a semiconductor structure is divided into different regions according to different functions. For example, the semiconductor structure is divided into a core region, a peripheral region, an array region, etc.

[0003] The core area is the area used to form the core circuit, which generally includes the core PMOS transistor, the core NMOS transistor and the corresponding circuits that control the corresponding transistors; the peripheral area is the area used to form the peripheral circuit, which generally includes the peripheral PMOS transistor, the peripheral NMOS transistor and the corresponding circuits that control the corresponding transistors.

[0004] The core region and the peripheral region form transistors with different structures according to the functional requirements of different semiconductor structures. Summary of the Invention

[0005] The technical problem solved by the embodiments of the present application is to provide a method for manufacturing a semiconductor structure and a structure thereof, which are conducive to solving the impact caused by the height difference between the core PMOS region and the core NMOS region.

[0006] An embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate including a core NMOS region, a core PMOS region, and a peripheral NMOS region; performing an oxidation treatment on the substrate in the core PMOS region to convert a portion of the thickness of the substrate in the core PMOS region into an oxide layer; removing the oxide layer; forming a first semiconductor layer on the remaining substrate in the core PMOS region, wherein the hole mobility in the first semiconductor layer is greater than the hole mobility in the substrate in the core PMOS region; forming a gate dielectric layer, wherein the gate dielectric layer is located on the first semiconductor layer, the core NMOS region, and the substrate in the peripheral NMOS region; and forming a gate on the gate dielectric layer.

[0007] Correspondingly, an embodiment of the present application also provides a semiconductor structure, including: a substrate, the substrate including a core NMOS region, a core PMOS region and a peripheral NMOS region, and in a direction perpendicular to the surface of the substrate, the thickness of the substrate of the core PMOS region is less than the thickness of the substrate of the core NMOS region; a first semiconductor layer, the first semiconductor layer is located on the surface of the substrate of the PMOS region, and the hole mobility in the first semiconductor layer is greater than the carrier mobility in the substrate of the core PMOS region; a gate dielectric layer, the gate dielectric layer is located on the substrate of the core NMOS region and the peripheral NMOS region and the first semiconductor layer of the PMOS region; a gate, the gate is located on the gate dielectric layer.

[0008] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0009] In the above technical solution, a portion of the core PMOS region's substrate is oxidized to form an oxide layer, which is then removed to reduce the core PMOS region's substrate height. This reduces the height difference between the core NMOS region and the core PMOS region in a direction perpendicular to the substrate surface. A first semiconductor layer, a gate dielectric layer, and a gate are then formed on the core PMOS region's substrate surface, thereby achieving the functional requirements of the core PMOS region. By reducing the core PMOS region's substrate height, the adverse effects of the height difference between the core PMOS region and the core NMOS region on subsequent production are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments are exemplarily described by the figures in the corresponding drawings. Unless otherwise stated, the figures in the drawings are not limited to scale.

[0011] Figure 1 A schematic cross-sectional structure diagram corresponding to a semiconductor structure;

[0012] Figures 2 to 21 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] To meet the functional requirements of the core PMOS region, in some embodiments, a first conductive layer is formed on the substrate surface of the core PMOS region. In some embodiments, the first conductive layer serves as part of the work function layer, regulating carriers. However, the formation of the first conductive layer creates a height difference between the core PMOS region and other regions, thereby increasing the complexity of subsequent processes. For example, during the polishing process, even if the core PMOS region has been polished, some film layers in other regions may still need to be removed. In this case, additional steps are still required to remove these layers.

[0014] The embodiments of the present application provide a method for manufacturing a semiconductor structure and a structure thereof, which reduce the height difference between the core PMOS region and the core NMOS region by reducing the substrate height of the core PMOS region.

[0015] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in each embodiment of the present application to help readers better understand the present application. However, even without these technical details and various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0016] Figure 1 A schematic diagram of a cross-sectional structure corresponding to a semiconductor structure.

[0017] refer to Figure 1 In some embodiments, the semiconductor structure may include an array region 11, a switch control module 1 (SWC switch control) is provided between four array regions 11, a word line driver 2 (SWD sub word-line driver) is provided between two adjacent array regions 11 along the word line extension direction, a sense amplifier region 12 (SA sense amplify) is provided between two array regions 11 along the bit line extension direction, a core region 13 includes the switch control module 1, the word line driver 2 and the sense amplifier region 12, and a peripheral region 14, which is located in the core region 13 and the peripheral area of ​​the array region 11.

[0018] Specifically, the array area 11 is an area for forming a memory array, which may include word lines, bit lines, and storage capacitors; the sense amplifier area 12 is a sense amplifier module, which may include a sense amplifier and a circuit structure for controlling the sense amplifier; the core area 13 is a core circuit area, which may include core NMOS transistors and core PMOS transistors; and the peripheral area 14 is a peripheral circuit area, which may include peripheral NMOS transistors and peripheral PMOS transistors.

[0019] Figures 2 to 21 Schematic diagram of the structures corresponding to the steps of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0020] refer to Figure 2 , providing a substrate 101 including a core NMOS region 111 , a core PMOS region 112 and a peripheral NMOS region 113 .

[0021] In some embodiments, the substrate 101 may be a silicon substrate or a silicon-on-insulator substrate. In addition, the surfaces of the core NMOS region 111 , the core PMOS region 112 , and the peripheral NMOS region 113 are flush.

[0022] In some embodiments, the substrate 101 may further include a peripheral PMOS region 114 .

[0023] The core NMOS region 111 is a region where a core NMOS transistor is to be formed, the core PMOS region 112 is a region where a core PMOS transistor is to be formed, the peripheral NMOS region 113 is a region where a peripheral NMOS transistor is to be formed, and the peripheral PMOS region 114 is a region where a peripheral PMOS transistor is to be formed.

[0024] It should be noted that for ease of viewing, the accompanying drawings draw the core NMOS region 111 , the core PMOS region 112 , the peripheral NMOS region 113 and the peripheral PMOS region 114 in adjacent positions, and the actual positions of each region shall be subject to the actual production process.

[0025] Core Area 13 (reference Figure 1 ) includes a core NMOS region 111 and a core PMOS region 112, a peripheral region 14 (reference Figure 1 ) includes a peripheral NMOS region 113 and a peripheral PMOS region 114.

[0026] refer to Figures 2 to 7 , the substrate 101 in the core PMOS region 112 is oxidized to convert a portion of the substrate 101 in the core PMOS region 112 into an oxide layer 141 .

[0027] By forming an oxide layer 141 and controlling the thickness of the oxide layer 141 in a direction perpendicular to the surface of the substrate 101, the thickness of the substrate 101 that needs to be removed in the core PMOS region 112 is controlled. Directly removing the substrate 101 in the core PMOS region 112 by dry etching may cause loss of the lattice. By forming the oxide layer 141 and then removing the oxide layer 141 by wet etching, the lattice damage can be reduced.

[0028] The following describes in detail the method for forming the oxide layer 141 in some embodiments with reference to the accompanying drawings:

[0029] In some embodiments, reference Figure 2 Before forming the oxide layer, a first barrier layer 121 may be formed on the surface of the substrate 101 in the core PMOS region 112 .

[0030] The first barrier layer 121 is used to slow down the oxidation rate when a portion of the substrate 101 in the core PMOS region 112 is subsequently oxidized, thereby controlling the thickness of the oxide layer.

[0031] In some embodiments, the material of the first barrier layer 121 may be silicon oxide.

[0032] In some embodiments, during the process of forming the first barrier layer 121 , the first barrier layer 121 may be further formed on the surface of the substrate 101 in the core NMOS region 111 and the peripheral NMOS region 113 .

[0033] In some embodiments, the first barrier layer 121 is also used to stop etching during the subsequent etching of the second barrier layer 131 .

[0034] Continue to refer Figure 2 In some embodiments, a second barrier layer 131 may be formed on the surface of the first barrier layer 121 in the core NMOS region 111 and the peripheral NMOS region 113 , and the material of the second barrier layer 131 is different from that of the first barrier layer 121 .

[0035] The second barrier layer 131 is used to stop etching during the subsequent etching of the third barrier layer 122. The second barrier layer 131 is also used to protect the core NMOS region 111 and the substrate 101 of the peripheral NMOS region 113 from being oxidized during the subsequent oxidation of the substrate 101 of the core NMOS region 111. In some embodiments, the second barrier layer 131 is also used to protect the first barrier layer 121 of the core NMOS region 111, the peripheral NMOS region 113 and the peripheral PMOS region 114 from being etched during the subsequent etching of the oxide layer.

[0036] In some embodiments, the material of the second barrier layer 131 may be silicon nitride.

[0037] Continue to refer Figure 2 In some embodiments, a third barrier layer 122 may be further formed on the surface of the second barrier layer 131 in the core NMOS region 111 , the core PMOS region 112 , the peripheral NMOS region 113 , and the peripheral PMOS region 114 .

[0038] The third barrier layer 122 is used to protect the second barrier layer 131 from etching the core NMOS region 111 , the peripheral NMOS region 113 and the peripheral PMOS region 114 when the core PMOS region 112 is subsequently etched.

[0039] In some embodiments, the material of the third barrier layer 122 may be the same as that of the first barrier layer 121 , and both may be silicon oxide.

[0040] After forming the oxide layer and before removing the oxide layer, the process further includes removing the first barrier layer 121 located in the core PMOS region 112 .

[0041] refer to Figure 3, the third barrier layer 122 of the core PMOS region 112 is removed until the surface of the second barrier layer 131 of the core region is exposed.

[0042] In some embodiments, the third barrier layer 122 in the core PMOS region 112 may be removed by selective wet etching. In another embodiment, the third barrier layer 122 in the core PMOS region 112 may be removed by mask etching.

[0043] refer to Figure 4 , the second barrier layer 131 of the core PMOS region 112 is removed until the surface of the first barrier layer 121 of the core region is exposed.

[0044] A wet etching process is used to remove the second barrier layer 131 in the core PMOS region 112. During the wet etching process, since the third barrier layer 122 still remains in the core NMOS region 111, the peripheral NMOS region 113, and the peripheral PMOS region 114, the third barrier layer 122 protects the second barrier layer 131 in the core NMOS region 111, the peripheral NMOS region 113, and the peripheral PMOS region 114 during the wet etching process.

[0045] refer to Figure 5 , remove the third barrier layer 122 of the core NMOS region 111, the peripheral NMOS region 113 and the peripheral PMOS region 114 (refer to Figure 4 ), until the surface of the second barrier layer 131 is exposed.

[0046] In some embodiments, a wet etching process is used to remove the third barrier layer 122 of the core NMOS region 111, the peripheral NMOS region 113, and the peripheral PMOS region 114 (refer to FIG. Figure 4 ), in other embodiments, the third barrier layer 122 of the core NMOS region 111, the peripheral NMOS region 113, and the peripheral PMOS region 114 may be removed by grinding (refer to Figure 4 ).

[0047] refer to Figure 6 , the substrate 101 in the core PMOS region 112 is oxidized to convert a portion of the substrate 101 in the core PMOS region 112 into an oxide layer 141 .

[0048] In some embodiments, the thickness of the oxide layer 141 in the direction perpendicular to the surface of the substrate 101 is It is understandable that the thickness of the oxide layer 141 can be adjusted according to actual needs.

[0049] In some embodiments, the oxidation treatment method includes thermal oxidation, in-situ water vapor generation oxidation, or radical oxidation.

[0050] Taking thermal oxidation as an example, in some embodiments, an oxidizing gas is introduced into a heating furnace. At a high temperature of 900°C to 1200°C, the oxidizing gas diffuses toward the substrate 101 of the core PMOS region 112 and chemically reacts with the substrate 101 to form an oxide layer 141.

[0051] refer to Figure 7 , the first barrier layer 121 of the core PMOS region 112 is removed until the surface of the oxide layer 141 is exposed.

[0052] In some embodiments, the first barrier layer 121 of the core PMOS region 112 is removed by wet etching.

[0053] refer to Figure 8 , remove the oxide layer 141 of the core PMOS region 112 (refer to Figure 7 ), until the surface of the substrate 101 of the core PMOS region 112 is exposed.

[0054] In some embodiments, the oxide layer 141 of the core PMOS region 112 is removed by wet etching (refer to Figure 7 ).

[0055] By removing the oxide layer 141 (ref. Figure 7 ) lowers the height of the core PMOS region 112 from the surface of the substrate 101 .

[0056] In some embodiments, the first barrier layer and the oxide layer are made of the same material, and the first barrier layer and the oxide layer can be removed simultaneously.

[0057] refer to Figure 9 A first semiconductor layer 151 is formed on the remaining substrate 101 of the core PMOS region 112 , and hole mobility in the first semiconductor layer 151 is greater than hole mobility in the substrate 101 of the core PMOS region 112 .

[0058] In some embodiments, the first semiconductor layer 151 serves as a work function layer of the core PMOS region 112 and plays a role in regulating carriers.

[0059] In a direction perpendicular to the surface of the substrate 101 , the top surface height of the first semiconductor layer 151 in the core PMOS region 112 is greater than or equal to the top surface height of the substrate 101 in the core NMOS region 111 , the peripheral NMOS region 113 , and the peripheral PMOS region 114 .

[0060] In some embodiments, the first semiconductor layer 151 is formed by a selective epitaxial process; the material of the first semiconductor layer 151 includes silicon germanium or germanium.

[0061] In some other embodiments, a first semiconductor layer may be deposited in the core NMOS region, the core PMOS region, the peripheral NMOS region, and the peripheral PMOS region, and then removed.

[0062] When the material of the first semiconductor layer 151 is silicon germanium, the molar concentration of germanium is 5% to 50%.

[0063] It can be understood that the higher the concentration of the germanium element, the higher the hole mobility of the corresponding first semiconductor layer 151, and the worse the stress resistance of the corresponding first semiconductor layer 151. Therefore, the stress resistance of the first semiconductor layer 151 is generally improved by increasing the thickness of the first semiconductor layer 151 in a direction perpendicular to the surface of the substrate 101.

[0064] In some embodiments, the thickness of the first semiconductor layer 151 in a direction perpendicular to the surface of the substrate 101 may be

[0065] In some embodiments, the first semiconductor layer 151 is configured to become a part of the work function layer of the core PMOS region 112 , thereby realizing the function of the core PMOS region 112 .

[0066] refer to Figure 10 After forming the first semiconductor layer 151, the second barrier layer 131 is removed (refer to Figure 9 ), and retain the first barrier layer 121 located in the core NMOS region 111 and the peripheral NMOS region 113.

[0067] In some embodiments, the second barrier layer 131 may be removed by grinding (see Figure 9 ), in other embodiments, the second barrier layer 131 may be removed by wet etching (refer to Figure 9 ).

[0068] In some embodiments, the first barrier layer 121 of the peripheral PMOS region 114 is also retained.

[0069] The first barrier layer 121 is used to protect the substrate 101 from being oxidized during the subsequent process of forming the protection layer, such as the core NMOS region 111 , the peripheral NMOS region 113 , and the peripheral PMOS region 114 .

[0070] refer to Figures 11 to 13 After forming the first semiconductor layer 151 , the process may further include: forming a second semiconductor layer 161 on the surface of the substrate 101 in the core NMOS region 111 , the peripheral NMOS region 113 , and the peripheral PMOS region 114 using a selective epitaxial process, wherein the material of the second semiconductor layer 161 is the same as that of the substrate 101 .

[0071] The second semiconductor layer 161 is used to further reduce the height difference between the core NMOS region 111 and the core PMOS region 112 .

[0072] In some embodiments, in a direction perpendicular to the surface of the substrate 101 , a top surface height of the second semiconductor layer 161 is less than or equal to a top surface height of the first semiconductor layer 151 .

[0073] The following will be combined Figures 11 to 13 The steps for forming the second semiconductor layer 161 in some embodiments are described in detail:

[0074] refer to Figure 11 A protective layer 171 is formed on the surface of the first semiconductor layer 151 by chemical oxidation.

[0075] The protection layer 171 is used to prevent a second semiconductor layer from being formed on the surface of the first semiconductor layer 151 in the core PMOS region 112 .

[0076] The protection layer 171 also covers the surface of the first barrier layer 121 in the core NMOS region 111 , the peripheral NMOS region 113 , and the peripheral PMOS region 114 .

[0077] In some embodiments, oxidation is performed using hydrogen peroxide or ozone, and the thickness of the protective layer 171 in a direction perpendicular to the surface of the substrate 101 is less than or equal to 2 nm.

[0078] The thickness of the protection layer 171 is less than or equal to 2 nm to avoid excessive consumption of the first semiconductor layer 151 , which would result in reduced efficiency of the first semiconductor layer 151 in regulating carriers in the core PMOS region 112 .

[0079] In some embodiments, the material of the protection layer 171 may be silicon oxide.

[0080] refer to Figure 12 , remove the protection layer 171 and the first barrier layer 121 of the core NMOS region 111, the peripheral NMOS region 113 and the peripheral PMOS region 114 (refer to Figure 11 ) until the top surface of the substrate 101 is exposed.

[0081] In some embodiments, the protective layer 171 and the first barrier layer 121 of the core NMOS region 111, the peripheral NMOS region 113 and the peripheral PMOS region 114 can be removed by wet etching (refer to Figure 11 ).

[0082] In some embodiments, since the first barrier layer 121 (refer to Figure 11 ) In the process of the previous production process, the first barrier layer 121 (reference Figure 11 ) is damaged, so the first barrier layer 121 is removed (refer to Figure 11 ).

[0083] refer to Figure 13 A second semiconductor layer 161 is formed on the top surface of the substrate 101 in the core NMOS region 111 , the peripheral NMOS region 113 , and the peripheral PMOS region 114 .

[0084] In some embodiments, the second semiconductor layer 161 is formed by selective epitaxial growth.

[0085] In other embodiments, the second semiconductor layer may not be formed on the top surface of the substrate in the core NMOS region, the peripheral NMOS region, and the peripheral PMOS region. It is understandable that the second semiconductor layer can be selectively generated according to the height difference between the core NMOS region and the core PMOS region.

[0086] In some embodiments, the thickness of the second semiconductor layer 161 in the direction perpendicular to the surface of the substrate 101 is .

[0087] It is understandable that the thickness of the second semiconductor layer 161 in a direction perpendicular to the surface of the substrate 101 can be adjusted according to actual production requirements.

[0088] refer to Figures 14 to 17 , forming a gate dielectric layer 15 , the gate dielectric layer 15 is located on the first semiconductor layer 151 , the core NMOS region 111 and the substrate 101 of the peripheral NMOS region 113 .

[0089] In some embodiments, in a direction perpendicular to the surface of the substrate 101 , the thickness of the gate dielectric layer 15 of the core NMOS region 111 and the core PMOS region 112 is the same, the thickness of the gate dielectric layer 15 of the peripheral NMOS region 113 and the peripheral PMOS region 114 is the same, and the thickness of the gate dielectric layer 15 of the core NMOS region 111 is less than the thickness of the gate dielectric layer 15 of the peripheral NMOS region 113.

[0090] In some embodiments, a second semiconductor layer 161 is further included, and the gate dielectric layer 15 is located on the surface of the second semiconductor layer 161 of the core NMOS region 111, the peripheral NMOS region 113 and the peripheral PMOS region 114, and the first semiconductor layer 151 of the core PMOS region 112. In other embodiments, the second semiconductor layer is not formed, and the gate dielectric layer is located on the surface of the substrate.

[0091] Specifically, refer to Figure 14, forming a first initial gate dielectric layer 191, the first initial gate dielectric layer 191 covers the top surface of the second semiconductor layer 161 of the core NMOS region 111, the peripheral NMOS region 113 and the peripheral PMOS region 114, and also covers the top surface of the protection layer 171 of the core PMOS region 112.

[0092] In some embodiments, the material of the first initial gate dielectric layer 191 may be silicon oxide.

[0093] In some embodiments, in a direction perpendicular to the substrate 101, the thickness of the first initial gate dielectric layer 191 is .

[0094] refer to Figure 15 , remove the first initial gate dielectric layer 191 and the protective layer 171 of the core NMOS region 111 and the core PMOS region 112 (refer to Figure 14 ) until the surfaces of the second semiconductor layer 161 of the core NMOS region 111 and the first semiconductor layer 151 of the core PMOS region 112 are exposed.

[0095] In some embodiments, the first initial gate dielectric layer 191 and the protective layer 171 of the core NMOS region 111 and the core PMOS region 112 may be removed by mask etching (refer to FIG. Figure 14 ).

[0096] refer to Figure 16 , forming a second initial gate dielectric layer 192, the second initial gate dielectric layer 192 is located on the top surfaces of the second semiconductor layer 161 of the core NOMS region 111, the first semiconductor layer 151 of the core PMOS region 112, the first initial gate dielectric layer 191 of the peripheral NMOS region 113 and the first initial gate dielectric layer 191 of the peripheral PMOS region 114.

[0097] The thickness of the second initial gate dielectric layer 192 in a direction perpendicular to the surface of the substrate 101 is smaller than the thickness of the first initial gate dielectric layer 191 .

[0098] In some embodiments, in a direction perpendicular to the surface of the substrate 101, the thickness of the second initial gate dielectric layer 192 is

[0099] In some embodiments, the first initial gate dielectric layer 191 and the second initial gate dielectric layer 192 may be made of the same material, which may be silicon oxide.

[0100] In some embodiments, the first initial gate dielectric layer 191 is also connected to the first barrier layer 121 (refer to Figure 11 ) are made of the same material, thereby reducing the types of materials and etchants in the production process, thereby reducing the manufacturing cost and complexity of the semiconductor process.

[0101] In some embodiments, the first initial gate dielectric layer 191 is denser than the first barrier layer 121 (refer to Figure 11 ) has high density, which can reduce leakage current, improve charge transfer efficiency, and thus improve the performance of the semiconductor structure.

[0102] refer to Figure 17 , forming a third initial gate dielectric layer 193 , which covers the top surface of the second initial gate dielectric layer 192 .

[0103] It can be understood that the relative dielectric constant of the third initial gate dielectric layer 193 is greater than the relative dielectric constants of the second initial gate dielectric layer 192 and the first initial gate dielectric layer 191 , and the third initial gate dielectric layer 193 is a high dielectric constant gate dielectric layer.

[0104] In some embodiments, the material of the third initial gate dielectric layer 193 may be hafnium oxide.

[0105] In some embodiments, the second initial gate dielectric layer 192 and the third initial gate dielectric layer 193 in the core NMOS region 111 and the core PMOS region 112 together constitute the gate dielectric layer 15 of the core NMOS region 111 and the core PMOS region 112, and the first initial gate dielectric layer 191, the second initial gate dielectric layer 192 and the third initial gate dielectric layer 193 in the peripheral NMOS region 113 and the peripheral PMOS region 114 together constitute the gate dielectric layer 15 of the peripheral NMOS region 113 and the peripheral PMOS region 114.

[0106] refer to Figures 18 to 21 , a gate 19 is formed on the gate dielectric layer 15 .

[0107] In some embodiments, the gate 19 of the core NMOS region 111 and the peripheral NMOS region 113 includes: a second work function layer 17 and a gate electrode layer 18 ; the gate 19 of the core PMOS region 112 and the peripheral PMOS region 114 includes: a first work function layer 16 , a second work function layer 17 and a gate electrode layer 18 .

[0108] The process steps for forming the gate 19 include: Figure 18 , a first work function layer 16 is formed on the gate dielectric layer 15 of the core NMOS region 111 , the core PMOS region 112 and the peripheral NMOS region 113 .

[0109] In some embodiments, the first intermediate layer 201 , the first functional regulation layer 211 , and the second intermediate layer 202 are formed in sequence, and the first intermediate layer 201 , the first functional regulation layer 211 , and the second intermediate layer 202 together constitute the first work function layer 16 .

[0110] refer to Figure 19, the first work function layer 16 of the core NMOS region 111 and the peripheral NMOS region 113 is removed.

[0111] refer to Figure 20 A second work function layer 17 is formed on the gate dielectric layer 15 of the core NMOS region 111 and the peripheral NMOS region 113 , and the second work function layer 17 is also located on the surface of the first work function layer 16 .

[0112] In some embodiments, a second functional adjustment layer 212 and a third intermediate layer 203 are sequentially formed, and the second functional adjustment layer 212 and the third intermediate layer 203 cover the third initial gate dielectric layer 193 . The second functional adjustment layer 212 and the third intermediate layer 203 together constitute the second work function layer 17 .

[0113] In some embodiments, the second function regulating layer and the third intermediate layer in the core PMOS region and the peripheral PMOS region may also be removed.

[0114] In some other embodiments, the first work function layer may further cover the surface of the second work function layer.

[0115] It is understandable that since the core NMOS region 111 and the core PMOS region 112 have different functions, corresponding first work function layers 16 and second work function layers 17 are formed on the surfaces of the core NMOS region 111 and the core PMOS region 112 .

[0116] refer to Figure 21 A gate electrode layer 18 is formed on the second work function layer 17 .

[0117] In some embodiments, the gate electrode layer 18 may be composed of a polysilicon gate electrode layer 221 , a fourth intermediate layer 204 , and a metal gate electrode layer 231 .

[0118] In some embodiments, the material of the fourth intermediate layer 204 can be the same as that of the third intermediate layer 203 , using titanium nitride, thereby reducing the types of materials in the production process. The material of the metal gate electrode layer 231 can be tungsten.

[0119] The fourth intermediate layer 204 plays a transition role in the process of carriers from the polysilicon gate electrode layer 221 migrating to the metal gate electrode layer 231, thereby reducing the possibility of abnormalities caused by direct connection between the polysilicon gate electrode layer 221 and the metal gate electrode layer 231 during the carrier migration process.

[0120] In some embodiments, the second work function layer 17 and the gate electrode layer 18 of the core NMOS region 111 and the peripheral NMOS region 113 together constitute the gate 19 , and the first work function layer 16 , the second work function layer 17 and the gate electrode layer 18 of the core PMOS region 112 and the peripheral PMOS region 114 together constitute the gate 19 .

[0121] In some embodiments, an isolation layer 20 is further formed on the surface of the gate 19 .

[0122] In some embodiments, the isolation layer 20 is composed of a first isolation layer 241, a second isolation layer 251 and a third isolation layer 261, and the materials of the first isolation layer 241, the second isolation layer 251 and the third isolation layer 261 are different from each other. The material of the first isolation layer 241 can be silicon nitride, the material of the second isolation layer 251 can be sulfur hydroxide, and the material of the third isolation layer 261 can be silicon oxynitride.

[0123] In some embodiments, the isolation layer 20 is used to protect the gate 19 . In other embodiments, the isolation layer 20 is also used to separate adjacent gates 19 so that the gates 19 are not connected to each other.

[0124] The manufacturing method of the semiconductor structure provided in the embodiment of the present application reduces the height difference between the core NMOS region and the core PMOS region by oxidizing part of the substrate of part of the core PMOS region, thereby facilitating subsequent production processes. The embodiment of the present application also forms a second conductive layer on the substrate surface of the core NMOS region, thereby further reducing the height difference between the core NMOS region and the core PMOS region.

[0125] An embodiment of the present application also provides a semiconductor structure. The semiconductor structure provided by the embodiment of the present application is described below in conjunction with the accompanying drawings. It should be noted that, for the parts that are the same as or corresponding to the manufacturing method of the aforementioned semiconductor structure, reference can be made to the aforementioned corresponding description and will not be repeated below.

[0126] refer to Figure 21 In some embodiments, the semiconductor structure includes: a substrate 101, the substrate 101 including a core NMOS region 111, a core PMOS region 112, and a peripheral NMOS region 113, and in a direction perpendicular to the surface of the substrate 101, the thickness of the substrate 101 in the core PMOS region 112 is less than the thickness of the substrate 101 in the core NMOS region 111; a first semiconductor layer 151, the first semiconductor layer 151 is located on the surface of the substrate 101 in the core PMOS region 112, and the hole mobility in the first semiconductor layer 151 is greater than the hole mobility in the substrate 101 in the core PMOS region 112; a gate dielectric layer 15, the gate dielectric layer 15 is located on the substrate 101 in the core NMOS region 111 and the peripheral NMOS region 113, and on the first semiconductor layer 151 in the core PMOS region 112; and a gate 19, the gate 19 is located on the gate dielectric layer 15.

[0127] In some embodiments, the top surface of the first semiconductor layer 151 is higher than the surface of the substrate 101 of the core NMOS region 111 , so that during the production process, the grinding process stops when the surface of the first semiconductor layer 151 is exposed, thereby avoiding damage to the substrate 101 .

[0128] In some embodiments, the semiconductor structure further includes a second semiconductor layer 181 . The second semiconductor layer 161 is located on the surface of the substrate 101 in the core NMOS region 111 and the peripheral NMOS region 113 . The material of the second semiconductor layer 161 is the same as that of the substrate 101 .

[0129] By providing the second semiconductor layer 161 , the height difference between the core NMOS region 111 and the core PMOS region 112 is further reduced, thereby facilitating subsequent production processes.

[0130] In some embodiments, in a direction perpendicular to the surface of the substrate 101, the height difference between the top surface of the first semiconductor layer 151 and the surface of the substrate 101 of the core NMOS region 111 is less than or equal to .

[0131] By providing a substrate 101 with a top surface height lower than that of the core PMOS region 112 of the core NMOS region 111, the top surface height of the first semiconductor layer 151 is reduced, so that the height difference between the top surface of the first semiconductor layer 151 and the surface of the substrate 101 of the core NMOS region 111 is less than or equal to To facilitate subsequent production processes.

[0132] In some embodiments, the top surface of the first semiconductor layer 151 is higher than the top surface of the second semiconductor layer 161 , so that during the production process, the grinding process stops when the surface of the first semiconductor layer 151 is exposed, thereby avoiding damaging the second semiconductor layer 161 .

[0133] In some embodiments, in a direction perpendicular to the surface of the substrate 101, the height difference between the top surface of the second semiconductor layer 161 and the top surface of the first semiconductor layer 151 is less than or equal to .

[0134] By adjusting the height of the top surface of the second semiconductor layer 161, the height difference between the core NMOS region 111 and the core PMOS region 112 is reduced so that the height difference between the top surface of the second semiconductor layer 161 and the top surface of the first semiconductor layer 151 is less than or equal to , thus facilitating the subsequent production process.

[0135] In some embodiments, the semiconductor structure further includes: a peripheral PMOS region 114, and the gate dielectric layer 15 is also located on the substrate 101 of the peripheral PMOS region 114; the gate 19 includes: a first work function layer 16, and the first work function layer 16 is located on the core PMOS region 112 and the gate dielectric layer 15 of the peripheral PMOS region 114; a second work function layer 17, and the second work function layer 17 is located on the surface of the first work function layer 16, and is also located on the substrate 101 of the core NMOS region 111 and the peripheral NMOS region 113; a polycrystalline silicon gate electrode layer 221, and the polycrystalline silicon gate electrode layer 221 is located on the surface of the second work function layer 17; and a metal gate electrode layer 231, and the metal gate electrode layer 231 is located on the polycrystalline silicon gate electrode layer 221.

[0136] Specifically, the second initial gate dielectric layer 192 and the third initial gate dielectric layer 193 in the core NMOS region 111 and the core PMOS region 112 together constitute the gate dielectric layer 15 of the core NMOS region 111 and the core PMOS region 112, and the first initial gate dielectric layer 191, the second initial gate dielectric layer 192 and the third initial gate dielectric layer 193 in the peripheral NMOS region 113 and the peripheral PMOS region 114 together constitute the gate dielectric layer 15 of the peripheral NMOS region 113 and the peripheral PMOS region 114.

[0137] The second work function layer 17 and the gate electrode layer 18 of the core NMOS region 111 and the peripheral NMOS region 113 together constitute the gate 19 . The first work function layer 16 , the second work function layer 17 and the gate electrode layer 18 of the core PMOS region 112 and the peripheral PMOS region 114 together constitute the gate 19 .

[0138] The first work function layer 16 includes: a first intermediate layer 201, a first functional adjustment layer 211 and a second intermediate layer 202; the second work function layer 17 includes: a second functional adjustment layer 212 and a third intermediate layer 203; the gate electrode layer 18 includes: a polysilicon gate electrode layer 221, a fourth intermediate layer 204 and a metal gate electrode layer 231.

[0139] In some embodiments, the semiconductor structure further includes an isolation layer 20 .

[0140] In some embodiments, the isolation layer 20 is composed of a first isolation layer 241 , a second isolation layer 251 , and a third isolation layer 261 .

[0141] An embodiment of the present application provides a semiconductor structure, which reduces the height difference between the core NMOS region and the core PMOS region by providing core NMOS regions and core PMOS regions with different substrate heights, and can further control the height difference between the core NMOS region and the core PMOS region by providing different thicknesses of the second semiconductor layer as required, thereby facilitating subsequent production processes.

[0142] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate including a core NMOS region, a core PMOS region and a peripheral NMOS region; forming a first barrier layer on the surface of the substrate in the core PMOS region; performing an oxidation process on the substrate of the core PMOS region to convert a portion of the substrate thickness of the core PMOS region into an oxide layer; removing the first barrier layer located in the core PMOS region; removing the oxide layer; forming a first semiconductor layer on the remaining substrate of the core PMOS region, wherein hole mobility in the first semiconductor layer is greater than hole mobility in the substrate of the core PMOS region; forming a gate dielectric layer, wherein the gate dielectric layer is located on the first semiconductor layer, the core NMOS region, and the substrate of the peripheral NMOS region; A gate is formed on the gate dielectric layer.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: In a direction perpendicular to the surface of the substrate, the thickness of the oxide layer is 10 Å-200 Å.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The oxidation treatment method includes thermal oxidation, in-situ water vapor generation oxidation or radical oxidation.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: In the process step of forming the first barrier layer, the first barrier layer is further formed on the substrate surface of the core NMOS region and the peripheral NMOS region; Before forming the oxide layer, the method further comprises: A second barrier layer is formed on the surface of the first barrier layer in the core NMOS region and the peripheral NMOS region, and the material of the second barrier layer is different from that of the first barrier layer.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: After forming the first semiconductor layer, the method further includes: The second barrier layer is removed, and the first barrier layer located in the core NMOS region and the peripheral NMOS region is retained.

6. The method for manufacturing a semiconductor structure according to claim 1 or 5, wherein: The substrate further includes a peripheral PMOS region; and after forming the first semiconductor layer, further includes: A second semiconductor layer is formed on the surface of the substrate in the core NMOS region, the peripheral PMOS region and the peripheral NMOS region by adopting a selective epitaxial process. The material of the second semiconductor layer is the same as that of the substrate.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: Before forming the second semiconductor layer, the method further includes: A protective layer is formed on the surface of the first semiconductor layer by adopting a chemical oxidation method.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: The protective layer is oxidized using hydrogen peroxide or ozone, and has a thickness of less than or equal to 2 nm in a direction perpendicular to the surface of the substrate.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first semiconductor layer is formed by a selective epitaxial process; the material of the first semiconductor layer includes silicon germanium or germanium.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The material of the first semiconductor layer is silicon germanium, and the molar concentration of germanium in the silicon germanium is 5% to 50%.

11. The method for manufacturing a semiconductor structure according to claim 1, wherein: The process steps for forming the gate include: forming a first work function layer on the gate dielectric layer of the core NMOS region, the core PMOS region and the peripheral NMOS region; removing the first work function layer in the core NMOS region and the peripheral NMOS region; forming a second work function layer on the gate dielectric layer of the core NMOS region and the peripheral NMOS region, wherein the second work function layer is also located on a surface of the first work function layer; A gate electrode layer is formed on the second work function layer.

12. A semiconductor structure formed by the method according to any one of claims 1 to 11, characterized in that: include: a substrate, the substrate comprising a core NMOS region, a core PMOS region, and a peripheral NMOS region, wherein in a direction perpendicular to a surface of the substrate, a thickness of the substrate in the core PMOS region is smaller than a thickness of the substrate in the core NMOS region; a first semiconductor layer, wherein the first semiconductor layer is located on a surface of the substrate of the core PMOS region, and hole mobility in the first semiconductor layer is greater than hole mobility in the substrate of the core PMOS region; a gate dielectric layer, the gate dielectric layer being located on the substrates of the core NMOS region and the peripheral NMOS region and the first semiconductor layer of the core PMOS region; A gate is located on the gate dielectric layer.

13. The semiconductor structure according to claim 12, wherein: In a direction perpendicular to the surface of the substrate, a height difference between a top surface of the first semiconductor layer and the surface of the substrate of the core NMOS region is less than or equal to 10Å.

14. The semiconductor structure according to claim 12 or 13, wherein: The top surface of the first semiconductor layer is higher than the substrate surface of the core NMOS region.

15. The semiconductor structure according to claim 12, wherein: Also includes: A second semiconductor layer is located on the surface of the substrate in the core NMOS region and the peripheral NMOS region, and the material of the second semiconductor layer is the same as that of the substrate.

16. The semiconductor structure according to claim 15, wherein: In a direction perpendicular to the surface of the substrate, a height difference between a top surface of the second semiconductor layer and a top surface of the first semiconductor layer is less than or equal to 10Å.

17. The semiconductor structure according to claim 16, wherein: A top surface of the first semiconductor layer is higher than a top surface of the second semiconductor layer.

18. The semiconductor structure according to claim 12, wherein: The substrate further includes a peripheral PMOS region, and the gate dielectric layer is further located on the substrate in the peripheral PMOS region; the gate includes: a first work function layer, the first work function layer being located on the gate dielectric layer in the core PMOS region and the peripheral PMOS region; a second work function layer, the second work function layer being located on a surface of the first work function layer and also being located on the substrate of the core NMOS region and the peripheral NMOS region; a polysilicon gate electrode layer, wherein the polysilicon gate electrode layer is located on a surface of the second work function layer; A metal gate electrode layer is located on the polysilicon gate electrode layer.

Images