Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the structure comprises: a substrate; a first dielectric layer, a plurality of gate structures and a plurality of source-drain doped layers; a second dielectric layer located on the first dielectric layer and the gate structures; a gate conductive layer located in the second dielectric layer and a protective layer located on the gate conductive layer; a first source-drain conductive opening located in the first dielectric layer and the second dielectric layer; and a first source-drain conductive layer located in the first source-drain conductive opening and electrically connected with the source-drain doped layers. By forming the gate conductive layer first and then forming the first source-drain conductive layer, the gate conductive opening corresponding to the gate conductive layer has a larger space in the etching process without being limited by the etching of the self-aligned film, thereby increasing the volume of the formed gate conductive layer and effectively reducing the contact resistance between the gate conductive layer and the gate structure, so as to improve the performance of the finally formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, such as using flash memory as a storage device in electronic devices like digital cameras, laptops, or tablets. Therefore, reducing the size of flash memory cells and thus lowering the cost of flash memory is one direction of technological development. For NOR gate electrically erasable tunneling oxide flash memory, the conductive structures on the source and drain surfaces can be fabricated using self-aligned contact technology, thereby meeting the need to manufacture smaller flash memory sizes.

[0003] However, there are still many problems with semiconductor structures formed using self-aligned electrical contact processes in the existing technology. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the final semiconductor structure.

[0005] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a base and fins located on the base; an isolation layer located on the substrate, the isolation layer covering a portion of the sidewalls of the fins, and the top surface of the isolation layer being lower than the top surface of the fins; a plurality of gate structures located on the isolation layer, the gate structures spanning the fins and covering a portion of the sidewalls and the top surface of the fins; source / drain doped layers located within the fins on both sides of the gate structures; and a first dielectric layer located on the isolation layer, the first dielectric layer covering the sidewalls of the gate structures and exposing the top surface of the gate structures. A second dielectric layer located on the first dielectric layer and the gate structure; a gate conductive opening located within the second dielectric layer, the gate conductive opening exposing the top surface of the gate structure, and the projection of the gate structure on the substrate surface falling within the projection of the gate conductive opening on the substrate surface; a gate conductive layer located within the gate conductive opening; a first source / drain conductive opening located within the first dielectric layer and the second dielectric layer; a first source / drain conductive layer located within the first source / drain conductive opening, the first source / drain conductive layer being electrically connected to the source / drain doped layer, and the first source / drain conductive layer being electrically isolated from the gate conductive layer.

[0006] Optionally, it further includes: a second source / drain conductive opening located within the first dielectric layer, the second source / drain conductive opening being located on both sides of the gate structure, and the second source / drain conductive opening exposing the source / drain doped layer; a second source / drain conductive layer located within the second source / drain conductive opening, the second source / drain conductive layer being adjacent to the surface of the source / drain doped layer, and the top surface of the second source / drain conductive layer being lower than the top surface of the first dielectric layer.

[0007] Optionally, the first source / drain conductive layer is located on the surface of the second source / drain conductive layer.

[0008] Optionally, the second dielectric layer is also located within the second source / drain conductive opening.

[0009] Optionally, a first dielectric layer and a second dielectric layer located between the sidewall of the first source / drain conductive opening and the gate conductive layer and the gate structure are used as an electrical isolation layer to achieve electrical isolation between the first source / drain conductive layer and the gate conductive layer.

[0010] Optionally, the material of the protective layer is different from the material of the second dielectric layer; the material of the protective layer includes silicon nitride or silicon carbide; the material of the second dielectric layer includes silicon oxide.

[0011] Optionally, the gate structure includes a gate layer, and the material of the gate layer includes a metal.

[0012] Optionally, it further includes: a protective layer opening located on the gate conductive opening; a protective layer located within the protective layer opening, the protective layer being located on the gate conductive layer, and the projection of the gate conductive layer on the substrate surface being located within the projection of the protective layer on the substrate surface.

[0013] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base and fins located on the base; forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the fins, and the top surface of the isolation layer being lower than the top surface of the fins; forming a first dielectric layer, a plurality of gate structures and a plurality of source / drain doped layers, the gate structures being located on the isolation layer, the source / drain doped layers being located within the fins on both sides of the gate structures, and the source / drain doped layers also being located between adjacent gate structures, the first dielectric layer covering the sidewalls of the gate structures and exposing the gate structures. The top surface of the gate structure; a second dielectric layer is formed on the first dielectric layer and the gate structure; a gate conductive opening is formed in the second dielectric layer, the gate conductive opening exposing the top surface of the gate structure, and the projection of the gate structure on the substrate surface is located within the projection of the gate conductive opening on the substrate surface; a gate conductive layer is formed in the gate conductive opening; a first source / drain conductive opening is formed in the first dielectric layer and the second dielectric layer; a first source / drain conductive layer is formed in the first source / drain conductive opening, the first source / drain conductive layer is electrically connected to the source / drain doped layer, and the first source / drain conductive layer is electrically isolated from the gate conductive layer.

[0014] Optionally, before forming the second dielectric layer, the method further includes: forming a second source / drain conductive opening within the first dielectric layer, the second source / drain conductive opening being located on both sides of the gate structure and exposing the source / drain doped layer; forming a second source / drain conductive layer within the second source / drain conductive opening, the second source / drain conductive layer being located on the surface of the source / drain doped layer, and the top surface of the second source / drain conductive layer being lower than the top surface of the first dielectric layer.

[0015] Optionally, the first source / drain conductive layer is located on the surface of the second source / drain conductive layer.

[0016] Optionally, the method for forming the second source / drain conductive layer includes: forming a conductive material layer inside the second source / drain conductive opening and on the first dielectric layer; planarizing the conductive material layer until the top surface of the first dielectric layer is exposed to form the initial second source / drain conductive layer; and performing a back etching process on the initial second source / drain conductive layer to form the second source / drain conductive layer.

[0017] Optionally, the process of forming the second dielectric layer on the first dielectric layer further includes: forming the second dielectric layer within the second source / drain conductive opening.

[0018] Optionally, the method for electrically isolating the first source / drain conductive layer from the gate conductive layer includes: after etching the second dielectric layer and the first dielectric layer using the protective layer as a mask, using the first dielectric layer and the second dielectric layer located between the sidewall of the first source / drain conductive opening and the gate conductive layer and the gate structure as an electrical isolation layer, and achieving electrical isolation between the first source / drain conductive layer and the gate conductive layer through the electrical isolation layer.

[0019] Optionally, the method for forming a gate conductive layer and a protective layer on the gate conductive layer within the second dielectric layer includes: forming a gate conductive opening within the second dielectric layer, the gate conductive opening exposing the top surface of the gate structure; forming the gate conductive layer within the gate conductive opening, the top surface of the gate conductive layer being lower than the top surface of the second dielectric layer; after forming the gate conductive layer, performing an enlarged etching process on the gate conductive opening located above the gate conductive layer to form a protective layer opening; and forming the protective layer within the protective layer opening.

[0020] Optionally, the method of forming the gate conductive layer within the gate conductive opening includes: forming an initial gate conductive layer within the gate conductive opening, the top surface of the initial gate conductive layer being flush with the top surface of the second dielectric layer; and etching back the initial gate conductive layer to form the gate conductive layer.

[0021] Optionally, the process for expanding the etching process includes: a wet etching process.

[0022] Optionally, the method of forming the protective layer within the opening of the protective layer includes: forming a protective material layer within the opening of the protective layer and on the top surface of the second dielectric layer; and planarizing the protective material layer until the top surface of the second dielectric layer is exposed, thereby forming the protective layer.

[0023] Optionally, the material of the protective layer is different from the material of the second dielectric layer; the material of the protective layer includes silicon nitride or silicon carbide; the material of the second dielectric layer includes silicon oxide.

[0024] Optionally, the gate structure includes a gate layer, and the material of the gate layer includes a metal.

[0025] Optionally, after forming the gate conductive layer within the gate conductive opening, the method further includes: enlarging the gate conductive opening located above the gate conductive layer by etching to form a protective layer opening; forming the protective layer within the protective layer opening, wherein the protective layer is located on the gate conductive layer, and the projection of the gate conductive layer on the substrate surface is located within the projection of the protective layer on the substrate surface.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the method of forming the technical solution of the present invention, by first forming the gate conductive layer and then forming the first source-drain conductive layer, the gate conductive opening corresponding to the gate conductive layer is not restricted by the etching of the self-aligned film layer during the etching process and has a large space, thereby increasing the volume of the formed gate conductive layer, effectively reducing the contact resistance between the gate conductive layer and the gate structure, thereby improving the performance of the finally formed semiconductor structure.

[0028] Furthermore, before forming the second dielectric layer, the method further includes: forming a second source / drain conductive opening within the first dielectric layer, the second source / drain conductive opening being located on both sides of the gate structure and exposing the source / drain doped layer; forming a second source / drain conductive layer within the second source / drain conductive opening, the second source / drain conductive layer being located on the surface of the source / drain doped layer, and the top surface of the second source / drain conductive layer being lower than the top surface of the first dielectric layer. By forming the second source / drain conductive layer, the electrical contact area between the first source / drain conductive layer and the source / drain doped layer can be increased, thereby reducing the contact resistance between the first source / drain conductive layer and the source / drain doped layer, and improving the performance of the finally formed semiconductor structure. Attached Figure Description

[0029] Figures 1 to 4 This is a schematic diagram of a semiconductor structure.

[0030] Figures 5 to 16 This is a schematic diagram of the steps in another embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0031] As described in the background section, semiconductor structures formed using self-aligned electrical contact processes in the prior art still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0032] Please refer to Figure 1 A substrate 100 is provided; a gate structure 101, a first dielectric layer 103, and a plurality of source / drain doped layers 102 are formed thereon. The gate structure 101 is located on the substrate 100 and has a first protective layer 104. The source / drain doped layers 102 are located in the substrate 100 on both sides of the gate structure 101. The first dielectric layer 103 covers the sidewalls of the gate structure 101. A source / drain contact layer 105 is formed on the source / drain doped layers 102 and a second protective layer 106 is formed on the source / drain contact layer 105 within the first dielectric layer 103. The materials of the first protective layer 104 and the second protective layer 106 are different.

[0033] Please refer to Figures 2 to 4 , Figure 2 This is a top view of a semiconductor structure omitting the second dielectric layer. Figure 3 yes Figure 2 Schematic diagram of the cross section along line AA. Figure 4 yes Figure 2 A cross-sectional view along the BB line shows that a second dielectric layer 107 is formed within the first dielectric layer 103; a gate conductive opening (not shown) is formed within the second dielectric layer 107, exposing the sidewall of the second protective layer 106; a gate conductive layer 108 is formed within the gate conductive opening, and the gate conductive layer 108 is electrically connected to the gate structure 101; a source / drain conductive opening (not shown) is formed within the second dielectric layer 107, exposing the source / drain contact layer 105; and a source / drain conductive layer 109 is formed within the source / drain conductive opening, and the source / drain conductive layer 109 is electrically connected to the source / drain contact layer 105.

[0034] In this embodiment, since the materials of the first protective layer 104 and the second protective layer 106 are different, the gate conductive layer 108 and the source / drain conductive layer 109 are formed by a self-aligned electrical contact process, which effectively reduces the process difficulty. Moreover, the gate conductive layer 108 is located between the source / drain conductive layers 109, which effectively reduces the area occupied by the gate structure 101, thereby improving the integration of the final semiconductor structure.

[0035] However, since the gate conductive opening is formed by the second protective layer 106 as a self-aligned film layer, the second protective layer 106 restricts the formation space of a portion of the gate conductive opening (e.g., Figure 3 As shown in Part A, this reduces the volume of the final gate conductive layer 108, thereby increasing the contact resistance between the gate conductive layer 108 and the gate structure 101, and affecting the performance of the final semiconductor structure.

[0036] Based on this, the present invention provides a semiconductor structure and a method for forming the same. By first forming the gate conductive layer and then forming the first source-drain conductive layer, the gate conductive opening corresponding to the gate conductive layer is not restricted by the etching of the self-aligned film layer during the etching process, thus having a larger space. This increases the volume of the formed gate conductive layer, effectively reducing the contact resistance between the gate conductive layer and the gate structure, thereby improving the performance of the final semiconductor structure.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 5 to 16 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 5 and Figure 6 , Figure 5 It is a 3D diagram of a semiconductor structure. Figure 6 yes Figure 5 A schematic diagram of the cross-section along line AA in the middle, showing the substrate.

[0040] In this embodiment, the substrate includes a base 200 and a fin 201 located on the base 200.

[0041] In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown) having a mask layer (not shown) on the initial substrate, the mask layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the mask layer as a mask to form the substrate 200 and the fin 201.

[0042] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0043] In this embodiment, the fin 201 is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0044] Please refer to Figure 7 An isolation layer 202 is formed on the substrate.

[0045] In this embodiment, the isolation layer 202 covers part of the sidewall of the fin 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0046] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate; etching away a portion of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0047] The insulating layer 202 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the insulating layer 202 is made of silicon oxide.

[0048] After forming the isolation layer 202, the process further includes forming a first dielectric layer, a plurality of gate structures, and a plurality of source / drain doped layers. The gate structures are located on the substrate, and the source / drain doped layers are located within the substrate on both sides of the gate structures, and are also located between adjacent gate structures. The first dielectric layer covers the sidewalls of the gate structures. For a detailed formation process, please refer to [reference needed]. Figures 8 to 11 .

[0049] Please refer to Figure 8 Several pseudo-gate structures 203 are formed on the substrate.

[0050] In this embodiment, the pseudo-gate structure 203 spans the fin 201 and covers part of the sidewall and top surface of the fin 201.

[0051] In this embodiment, the pseudo-gate structure 203 includes: a pseudo-gate dielectric layer, a pseudo-gate layer located on the pseudo-gate dielectric layer, and a sidewall (not shown) located on the sidewalls of the pseudo-gate dielectric layer and the pseudo-gate layer.

[0052] In this embodiment, the gate dielectric layer is made of silicon oxide; in other embodiments, the pseudo-gate dielectric layer may also be made of silicon oxynitride.

[0053] In this embodiment, the pseudo-gate layer is made of polycrystalline silicon.

[0054] In this embodiment, the sidewall is made of silicon nitride.

[0055] Please refer to Figure 9 A plurality of source / drain doped layers 204 are formed in the substrate.

[0056] In this embodiment, the source / drain doped layer 204 is located within the fin 201.

[0057] In this embodiment, the method for forming the source / drain doped layer 204 includes: etching the fin using the pseudo-gate structure 203 as a mask to form a plurality of source / drain openings (not shown) in the fin; forming the source / drain doped layer 204 in the source / drain openings, wherein the source / drain doped layer 204 is located between adjacent pseudo-gate structures 203.

[0058] Please refer to Figure 10 A first dielectric layer 205 is formed on the substrate.

[0059] In this embodiment, the first dielectric layer 205 covers the sidewalls of the pseudo-gate structure 203 and exposes the top surface of the pseudo-gate structure 203.

[0060] In this embodiment, the first dielectric layer 205 is made of silicon oxide; in other embodiments, the first dielectric layer may also be made of a low-K dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-K dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0061] Please refer to Figure 11 After the first dielectric layer 205 is formed, the gate structure 206 is formed.

[0062] In this embodiment, the method for forming the gate structure 206 includes: removing the dummy gate structure 203, forming a gate opening (not shown) in the first dielectric layer 205, and forming the gate structure 206 in the gate opening.

[0063] It should be noted that, in this embodiment, the pseudo-gate dielectric layer and the pseudo-gate layer of the pseudo-gate structure 203 are specifically removed, while the sidewalls are retained.

[0064] In this embodiment, the gate structure 206 includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a mask layer (not shown) located on the gate layer.

[0065] The gate layer is made of a metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate layer is made of tungsten.

[0066] Please refer to Figure 12 After the gate structure 206 is formed, a second source / drain conductive layer 207 is formed in the first dielectric layer 205. The second source / drain conductive layer 207 is located on the surface of the source / drain doped layer 204, and the top surface of the second source / drain conductive layer 207 is lower than the top surface of the first dielectric layer 205.

[0067] In this embodiment, the method for forming the second source / drain conductive layer 207 includes: forming a second source / drain conductive opening (not shown) in the first dielectric layer 205, the second source / drain conductive opening being located on both sides of the gate structure 206, and the second source / drain conductive opening exposing the source / drain doped layer 204; and forming a second source / drain conductive layer 207 in the second source / drain conductive opening.

[0068] In this embodiment, the method for forming a second source-drain conductive layer 207 within the second source-drain conductive opening includes: forming a conductive material layer (not shown) within the second source-drain conductive opening and on the first dielectric layer 205; planarizing the conductive material layer until the top surface of the first dielectric layer 205 is exposed to form the initial second source-drain conductive layer (not shown); and performing a back etching process on the initial second source-drain conductive layer to form the second source-drain conductive layer 207.

[0069] In this embodiment, by forming the second source / drain conductive layer 207, the electrical contact area between it and the source / drain doped layer 204 can be increased, thereby reducing the contact resistance between the subsequently formed first source / drain conductive layer and the source / drain doped layer 204 and improving the performance of the finally formed semiconductor structure.

[0070] Please refer to Figure 13 After the second source / drain conductive layer 207 is formed, a second dielectric layer 208 is formed on the first dielectric layer 205 and the gate structure 206.

[0071] In this embodiment, during the process of forming the second dielectric layer 208 on the first dielectric layer 205 and the gate structure 206, the method further includes: forming the second dielectric layer 208 within the second source-drain conductive opening.

[0072] In this embodiment, the material of the second dielectric layer 208 is silicon oxide; in other embodiments, the material of the second dielectric layer may also be a low-K dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-K dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0073] Please refer to Figure 14 A gate conductive opening (not shown) is formed in the second dielectric layer 208, the gate conductive opening exposes the top surface of the gate structure 206, and the projection S1 of the gate structure 206 on the substrate surface is located within the projection S3 of the gate conductive opening on the substrate surface.

[0074] In this embodiment, please continue to refer to Figure 14 After forming the gate conductive opening, a gate conductive layer 209 is formed in the gate conductive opening; a protective layer 210 is formed in the gate conductive opening, the protective layer 210 is located on the gate conductive layer 209, and the projection S3 of the gate conductive layer 209 on the substrate surface is located within the projection S2 of the protective layer 210 on the substrate surface.

[0075] In this embodiment, the method for forming a gate conductive layer 209 and a protective layer 210 on the gate conductive layer 209 within the second dielectric layer 208 includes: forming a gate conductive opening (not shown) within the second dielectric layer 208, the gate conductive opening exposing the top surface of the gate layer; forming the gate conductive layer 209 within the gate conductive opening, the top surface of the gate conductive layer 209 being lower than the top surface of the second dielectric layer 208; after forming the gate conductive layer 209, performing an enlarged etching process on the gate conductive opening located above the gate conductive layer 209 to form a protective layer opening (not shown); and forming the protective layer 210 within the protective layer opening.

[0076] In this embodiment, the method of forming the gate conductive layer 209 within the gate conductive opening includes: forming an initial gate conductive layer (not shown) within the gate conductive opening, the top surface of the initial gate conductive layer being flush with the top surface of the second dielectric layer 208; and etching back the initial gate conductive layer to form the gate conductive layer 209.

[0077] In this embodiment, the method of forming the protective layer 210 within the opening of the protective layer includes: forming a protective material layer (not shown) within the opening of the protective layer and on the top surface of the second dielectric layer 208; and planarizing the protective material layer until the top surface of the second dielectric layer 208 is exposed, thereby forming the protective layer 210.

[0078] In this embodiment, the enlarged etching process includes a wet etching process.

[0079] In this embodiment, the material of the protective layer 210 is different from the material of the second dielectric layer 208. Because the material of the protective layer 210 is different from that of the second dielectric layer 208, during the subsequent etching of the second dielectric layer 208 to form the first source / drain conductive layer, a self-aligned electrical contact process can be used to form the first source / drain conductive opening, effectively reducing the difficulty of the etching process.

[0080] In this embodiment, the protective layer 210 is made of silicon nitride; the second dielectric layer 208 is made of silicon oxide. In other embodiments, the protective layer may also be made of silicon carbide.

[0081] Please refer to Figure 15 Using the protective layer 210 as a mask, the second dielectric layer 208 and the first dielectric layer 205 are etched to form a first source / drain conductive opening 211 in the first dielectric layer 205 and the second dielectric layer 208.

[0082] In this embodiment, since the projection S3 of the gate conductive layer 209 on the substrate surface is located within the projection S2 of the protective layer 210 on the substrate surface, a portion of the first dielectric layer 205 and the second dielectric layer 208 are also present between the formed first source / drain conductive opening 211 and the gate conductive layer 209. The retained first dielectric layer 205 and the second dielectric layer 208 provide electrical isolation between the subsequently formed first source / drain conductive layer and the gate conductive layer 209.

[0083] Please refer to Figure 16 A first source-drain conductive layer 212 is formed within the first source-drain conductive opening 211. The first source-drain conductive layer 212 is electrically connected to the source-drain doped layer 204, and the first source-drain conductive layer 212 is electrically isolated from the gate conductive layer 209.

[0084] In this embodiment, the first source / drain conductive layer 211 is located on the surface of the second source / drain conductive layer 207.

[0085] In this embodiment, the method for electrically isolating the first source / drain conductive layer 211 from the gate conductive layer 209 includes: after etching the second dielectric layer 208 and the first dielectric layer 205 using the protective layer 210 as a mask, using the first dielectric layer 205 and the second dielectric layer 206 located between the sidewall of the first source / drain conductive opening 211 and the gate conductive layer 209 and the gate structure 206 as an electrical isolation layer, and achieving electrical isolation between the first source / drain conductive layer 211 and the gate conductive layer 209 through the electrical isolation layer.

[0086] In this embodiment, by first forming the gate conductive layer 209 and then forming the first source / drain conductive layer 211, the gate conductive opening corresponding to the gate conductive layer 209 is not restricted by the etching of the self-aligned film layer during the etching process, thus having a larger space. This increases the volume of the formed gate conductive layer 209, effectively reducing the contact resistance between the gate conductive layer 209 and the gate structure 206, thereby improving the performance of the final semiconductor structure.

[0087] Furthermore, since the third projection pattern S3 of the gate conductive layer 209 on the substrate surface is within the range of the second projection pattern S2 of the protective layer 210 on the substrate surface, a certain gap can be formed between the first source / drain conductive layer 211 formed with the protective layer 210 as a mask and the gate conductive layer 209, thereby achieving electrical isolation between the first source / drain conductive layer 211 and the gate conductive layer 209.

[0088] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate, the substrate including a base 200 and fins 201 located on the base 200; an isolation layer 202 located on the substrate, the isolation layer 202 covering a portion of the sidewalls of the fins 201, and the top surface of the isolation layer 202 being lower than the top surface of the fins 201; a plurality of gate structures 206 located on the isolation layer 202, the gate structures 206 spanning the fins 201 and covering a portion of the sidewalls and top surface of the fins 201; source / drain doped layers 204 located within the fins 201 on both sides of the gate structures 206; and a first dielectric layer 205 located on the isolation layer 202, the first dielectric layer 205 covering the sidewalls of the gate structures 206 and exposing the gate structures 201. The top surface of 6; a second dielectric layer 208 located on the first dielectric layer 205 and the gate structure 206; a gate conductive opening located within the second dielectric layer 208, the gate conductive opening exposing the top surface of the gate structure 206, and the projection S1 of the gate structure 206 on the substrate surface being located within the projection S3 of the gate conductive opening on the substrate surface; a gate conductive layer 209 located within the gate conductive opening; a first source / drain conductive opening 211 located within the first dielectric layer 205 and the second dielectric layer 208; a first source / drain conductive layer 212 located within the first source / drain conductive opening 211, the first source / drain conductive layer 212 being electrically connected to the source / drain doped layer 204, and the first source / drain conductive layer 212 being electrically isolated from the gate conductive layer 209.

[0089] In this embodiment, it further includes: a second source / drain conductive opening located within the first dielectric layer 205, the second source / drain conductive opening being located on both sides of the gate structure 206, and the second source / drain conductive opening exposing the source / drain doped layer 204; a second source / drain conductive layer 207 located within the second source / drain conductive opening, the second source / drain conductive layer 207 being adjacent to the surface of the source / drain doped layer 204, and the top surface of the second source / drain conductive layer 207 being lower than the top surface of the first dielectric layer 205.

[0090] In this embodiment, the first source / drain conductive layer 212 is located on the surface of the second source / drain conductive layer 207.

[0091] In this embodiment, the second dielectric layer 208 is also located within the second source / drain conductive opening.

[0092] In this embodiment, the first dielectric layer 205 and the second dielectric layer 208 located between the sidewall of the first source-drain conductive opening 211 and the gate conductive layer 209 and the gate structure 206 are used as electrical isolation layers to achieve electrical isolation between the first source-drain conductive layer 212 and the gate conductive layer 209.

[0093] In this embodiment, the material of the protective layer 210 is different from the material of the second dielectric layer 208; the material of the protective layer 210 includes silicon nitride or silicon carbide; the material of the second dielectric layer 208 includes silicon oxide.

[0094] In this embodiment, the gate structure 206 includes a gate layer, and the material of the gate layer includes metal.

[0095] In this embodiment, it further includes: a protective layer opening located on the gate conductive opening; a protective layer 210 located within the protective layer opening, the protective layer 210 being located on the gate conductive layer 209, and the projection S3 of the gate conductive layer 209 on the substrate surface being located within the projection S1 of the protective layer 210 on the substrate surface.

[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a base and fins located on the base; An isolation layer is located on the substrate, the isolation layer covers a portion of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin; A plurality of gate structures are located on the isolation layer, the gate structures spanning the fin and covering part of the sidewalls and top surface of the fin; Source and drain doped layers located within the fins on both sides of the gate structure; A first dielectric layer is located on the isolation layer, the first dielectric layer covers the sidewalls of the gate structure and exposes the top surface of the gate structure; A second dielectric layer located on the first dielectric layer and the gate structure; A gate conductive opening is located within the second dielectric layer, the gate conductive opening exposes the top surface of the gate structure, and the projection of the gate structure on the substrate surface is located within the projection of the gate conductive opening on the substrate surface; A gate conductive layer is located within the gate conductive opening, and the projection of the gate structure on the substrate surface is located within the projection of the gate conductive layer on the substrate surface; A protective layer located on the gate conductive layer, wherein the projection of the gate conductive layer on the substrate surface lies within the projection of the protective layer on the substrate surface; A first source / drain conductive opening located within the first dielectric layer and the second dielectric layer; A first source / drain conductive layer is located within the first source / drain conductive opening. This first source / drain conductive layer is electrically connected to the source / drain doped layer, and is electrically isolated from the gate conductive layer. The first dielectric layer and the second dielectric layer located between the sidewall of the first source / drain conductive opening and the gate conductive layer and the gate structure are used as electrical isolation layers to achieve electrical isolation between the first source / drain conductive layer and the gate conductive layer.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second source / drain conductive opening is located within the first dielectric layer, the second source / drain conductive opening is located on both sides of the gate structure, and the second source / drain conductive opening exposes the source / drain doped layer; The second source-drain conductive layer is located within the second source-drain conductive opening, the second source-drain conductive layer is adjacent to the surface of the source-drain doped layer, and the top surface of the second source-drain conductive layer is lower than the top surface of the first dielectric layer.

3. The semiconductor structure as described in claim 2, characterized in that, The first source / drain conductive layer is located on the surface of the second source / drain conductive layer.

4. The semiconductor structure as described in claim 2, characterized in that, The second dielectric layer is also located within the second source / drain conductive opening.

5. The semiconductor structure as described in claim 4, characterized in that, The first dielectric layer and the second dielectric layer located between the sidewall of the first source / drain conductive opening and the gate conductive layer and the gate structure are used as electrical isolation layers to achieve electrical isolation between the first source / drain conductive layer and the gate conductive layer.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the protective layer is different from that of the second dielectric layer; the material of the protective layer includes silicon nitride or silicon carbide; the material of the second dielectric layer includes silicon oxide.

7. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate layer, and the material of the gate layer includes a metal.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: A protective layer opening is located on the gate conductive opening, and the protective layer is located within the protective layer opening.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base and fins located on the base; An isolation layer is formed on the substrate, the isolation layer covering a portion of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin; A first dielectric layer, a plurality of gate structures, and a plurality of source / drain doped layers are formed. The gate structures are located on the isolation layer, the source / drain doped layers are located in the fins on both sides of the gate structures, and the source / drain doped layers are also located between adjacent gate structures. The first dielectric layer covers the sidewalls of the gate structures and exposes the top surface of the gate structures. A second dielectric layer is formed on the first dielectric layer and the gate structure; A gate conductive opening is formed within the second dielectric layer, the gate conductive opening exposing the top surface of the gate structure, and the projection of the gate structure onto the substrate surface lies within the projection of the gate conductive opening onto the substrate surface. In the gate conductive layer formed at the gate conductive opening, the projection of the gate structure on the substrate surface is located within the projection of the gate conductive layer on the substrate surface; A protective layer is formed on the gate conductive layer, wherein the projection of the gate conductive layer on the substrate surface is located within the projection of the protective layer on the substrate surface; A first source / drain conductive opening is formed within the first dielectric layer and the second dielectric layer; A first source / drain conductive layer is formed within the first source / drain conductive opening. The first source / drain conductive layer is electrically connected to the source / drain doped layer, and is electrically isolated from the gate conductive layer. The method for electrically isolating the first source / drain conductive layer from the gate conductive layer includes: after etching the second dielectric layer and the first dielectric layer using the protective layer as a mask, using the first dielectric layer and the second dielectric layer located between the sidewall of the first source / drain conductive opening and the gate conductive layer and the gate structure as an electrical isolation layer, and achieving electrical isolation between the first source / drain conductive layer and the gate conductive layer through the electrical isolation layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming the second dielectric layer, the method further includes: forming a second source / drain conductive opening within the first dielectric layer, the second source / drain conductive opening being located on both sides of the gate structure and exposing the source / drain doped layer; forming a second source / drain conductive layer within the second source / drain conductive opening, the second source / drain conductive layer being located on the surface of the source / drain doped layer and the top surface of the second source / drain conductive layer being lower than the top surface of the first dielectric layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first source / drain conductive layer is located on the surface of the second source / drain conductive layer.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the second source / drain conductive layer includes: forming a conductive material layer inside the second source / drain conductive opening and on the first dielectric layer; planarizing the conductive material layer until the top surface of the first dielectric layer is exposed to form an initial second source / drain conductive layer; and performing a back etching process on the initial second source / drain conductive layer to form the second source / drain conductive layer.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process of forming the second dielectric layer on the first dielectric layer also includes: forming the second dielectric layer within the second source / drain conductive opening.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, A method for forming a gate conductive layer within a second dielectric layer and a protective layer on the gate conductive layer includes: forming a gate conductive opening within the second dielectric layer, the gate conductive opening exposing a top surface of the gate structure; forming the gate conductive layer within the gate conductive opening, the top surface of the gate conductive layer being lower than the top surface of the second dielectric layer; after forming the gate conductive layer, performing an enlarged etching process on the gate conductive opening located above the gate conductive layer to form a protective layer opening; and forming the protective layer within the protective layer opening.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method of forming the gate conductive layer within the gate conductive opening includes: forming an initial gate conductive layer within the gate conductive opening, wherein the top surface of the initial gate conductive layer is flush with the top surface of the second dielectric layer; and etching back the initial gate conductive layer to form the gate conductive layer.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, The enlarged etching process includes: wet etching process.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method of forming the protective layer within the opening of the protective layer includes: forming a protective material layer within the opening of the protective layer and on the top surface of the second dielectric layer; planarizing the protective material layer until the top surface of the second dielectric layer is exposed, thereby forming the protective layer.

18. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the protective layer is different from that of the second dielectric layer; the material of the protective layer includes silicon nitride or silicon carbide; the material of the second dielectric layer includes silicon oxide.

19. The method for forming a semiconductor structure as described in claim 9, characterized in that, The gate structure includes a gate layer, and the material of the gate layer includes a metal.

20. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the gate conductive layer within the gate conductive opening, the method further includes: enlarging the gate conductive opening located above the gate conductive layer by etching to form a protective layer opening; and forming the protective layer within the protective layer opening.

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