Chip splicing method and chip splicing structure

Abstract

The present application relates to a kind of chip splicing method and chip splicing structure, comprising the following steps: S1. two chips are placed under range measuring instrument splicing, make its two adjacent pixel pitch on the chip equal to N times the pixel size of range measuring instrument;S2. after splicing, the joint of two chips is bonded by bonding member, so that two chips are firmly bonded;S3. repeat step S1, S2, until M * T chip is firmly bonded to form chip assembly;S4. removable traceless glue is bonded on the surface of the chip assembly, and the chip assembly is bonded on the fixed plate by the traceless glue;S5. there is adhesive medium on the backing plate, the chip assembly and the fixed plate are transferred to the backing plate, so that the surface of the chip assembly and the side opposite to the fixed plate are bonded with the adhesive medium. The chip assembly can be disassembled without damage after splicing, which greatly solves the overall scrap of module caused by chip failure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a chip splicing method and chip splicing mechanism. Background Technology

[0002] With the development of digital technology, semiconductor manufacturing technology, and the arrival of the information age, image sensors, as optoelectronic components in the optoelectronic industry, are increasingly being used.

[0003] Compared to amorphous silicon, CMOS flat panel detectors have the advantages of high frame rate, low noise, and low dose. However, due to wafer size limitations, the largest wafer size that can be manufactured at present is 12 inches (300 mm) in diameter.

[0004] CMOS flat panel detectors are difficult to fabricate with large target areas, and due to the square shape of the internal chips, the actual chip size after wafer dicing is less than 300mm. In practical applications, CMOS flat panel detectors are limited by wafer size, making it difficult to achieve large imaging areas. Currently, the industry generally involves directly bonding several chips onto a large chip substrate using a medium with strong adhesive properties. This approach results in chips that cannot be removed, and if one chip in the module fails, the entire module becomes unusable. Large-sized chips are extremely expensive, leading to significant cost waste.

[0005] Therefore, those skilled in the art are dedicated to developing a chip splicing method and chip splicing mechanism that allows for the non-destructive disassembly of chip components after splicing, greatly solving the problem of overall module scrapping due to chip defects. Moreover, the splicing method is simple and easy to operate. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a chip splicing method and chip splicing mechanism, which allows for the non-destructive disassembly of chip components after splicing, greatly solving the problem of overall scrapping of modules due to chip defects. Moreover, the splicing method is simple and easy to operate.

[0007] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A chip splicing method, comprising the following steps:

[0008] S1. Place two chips under the rangefinder and splice them together, so that the distance between adjacent pixels on the two chips is equal to N times the pixel size of the rangefinder;

[0009] S2. After splicing, use adhesive to bond the seam between the two chips to make the two chips bond firmly;

[0010] S3. Repeat steps S1 and S2 until the M*T chips are firmly bonded together to form a chip assembly;

[0011] S4. Adhering a removable traceless glue on the surface of the chip assembly, and adhering the chip assembly on a fixed plate through the traceless glue;

[0012] S5. Coating an adhesive medium on a backing plate, and transferring the chip assembly and the fixed plate to the backing plate, so that the surface of the chip assembly and the side opposite to the fixed plate abuts and adheres to the adhesive medium;

[0013] S6. Removing the adhesive and the traceless glue on the fixed plate and the chip assembly, so that the surface of the chip assembly adheres to the backing plate through the adhesive medium.

[0014] The beneficial effects of the present application are that after the chips are placed at the required distance, the chips are pre-fixed through the adhesive, and then the chips are transferred to the backing plate through the traceless glue and the fixed plate, and the adhesive and the traceless glue are removed, so that the chips are fixed on the backing plate, and the CMOS flat panel detector module of the target size is obtained by splicing. The present application has the excellent characteristics of rework, that is, the chip assembly can be disassembled without damage after splicing, which greatly solves the overall scrapping of the module due to the chip failure, greatly saves the cost. When one of the chips is abnormal, it only needs to be replaced, so that the overall scrapping of the module due to the chip failure is solved, and the operator can perform manual operation, which is free from the dependence on the equipment, and the splicing method is simple and has strong operability.

[0015] On the basis of the above technical solution, the present application can be further improved as follows.

[0016] Further, in step S1, the distance measuring instrument includes a distance measuring microscope, and the precision error is less than or equal to 10 microns.

[0017] The beneficial effects of the above further scheme are that the distance measuring microscope is used, the distance error between the two chips is further reduced, and the splicing precision and splicing efficiency are improved.

[0018] Further, in step S2, the adhesive includes an anti-static adhesive tape, and the tensile strength of the anti-static adhesive tape is >40N / 10mm, and the peeling force is >5N.

[0019] The beneficial effects of the above further scheme are that the anti-static adhesive tape is used, which not only prevents the static electricity from damaging the chip, but also facilitates the fixation of the chip, prevents the displacement, and is beneficial to the subsequent removal.

[0020] Further, after step S2, it further includes measuring the splicing gap between the two chips again to ensure that the splicing gap does not change in the adhesive fixation.

[0021] The beneficial effect of the further solution is that the gap between the two chips is measured again, avoiding the movement of the chips when using the adhesive, which causes the gap to change.

[0022] Further, in step S5, the backing plate is made of one or more of alumina, silicon carbide, aluminum nitride or glass, and has a coefficient of thermal expansion of 10 ppm or less.

[0023] The beneficial effect of the further solution is that the backing plate is made of a material with a small coefficient of thermal expansion, which has a small thermal effect and reduces the gap variation between the chip assemblies.

[0024] A chip splicing structure made by the chip splicing method described above. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A chip splicing schematic diagram for an embodiment of the present application;

[0026] Figure 2 A chip splicing adhesive schematic diagram for an embodiment of the present application;

[0027] Figure 3 A chip splicing adhesive side view schematic diagram for an embodiment of the present application;

[0028] Figure 4 A chip assembly adhesive schematic diagram for an embodiment of the present application;

[0029] Figure 5 A chip assembly adhesive traceless adhesive schematic diagram for an embodiment of the present application;

[0030] Figure 6 A chip assembly adhesive traceless adhesive side view schematic diagram for an embodiment of the present application;

[0031] Figure 7 A chip assembly adhesive on a backing plate schematic diagram for an embodiment of the present application;

[0032] Figure 8 A chip assembly splicing completed schematic diagram for an embodiment of the present application.

[0033] In the drawings, the components represented by the respective reference numerals are listed as follows:

[0034] 1, chip; 2, pixel; 3, adhesive; 4, traceless adhesive; 5, fixed plate; 6, adhesive medium; 7, backing plate. DETAILED DESCRIPTION

[0035] The principles and features of the present application are described below in conjunction with the drawings, and the examples are used to explain the present application and are not intended to limit the scope of the present application.

[0036] In the description of the present application, it is to be understood by those skilled in the art that the terms "center", "length", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "inner", "outer", "peripheral side", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the systems or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0037] In the description of the present application, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified and limited.

[0038] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0039] As shown in Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 A chip splicing method, comprising the following steps:

[0040] S1. Place two chips 1 under the distance measuring instrument for splicing, so that the distance between the adjacent pixels 2 on the two chips 1 is equal to N times the pixel size of the distance measuring instrument, as shown in Figure 1 The distance between the adjacent pixels on the two chips 1 is equal to N times the pixel size t of the distance measuring instrument, that is, L=N*t. It is beneficial to accurately determine the distance between the two chips 1. In a specific embodiment, the distance measuring instrument includes a distance measuring microscope, and the precision error is less than or equal to 10 microns (precision error ± 10 μm). When operating, the distance measuring microscope display screen, the splicing gap size and the pixel misplacement size are observed, so that the splicing gap meets the requirements and the pixels are not misaligned.

[0041] S2. After the splicing is completed and the splicing gap is adjusted, the splicing gap of the two chips 1 is bonded by the bonding member 3, the two chips 1 are pre-fixed, the two chips 1 are bonded firmly, and it is ensured that the subsequent movement will not cause the change of the splicing gap. In the specific embodiment, the bonding member 3 includes an anti-static adhesive tape, the tensile strength of the anti-static adhesive tape is > 40N / 10mm, and the peeling force is > 5N.

[0042] After pre-fixing, the splicing gap between the two chips 1 is measured again to ensure that the splicing gap of the two chips 1 does not change in distance during bonding and fixing.

[0043] S3. Repeat steps S1 and S2 until M*T chips 1 are bonded firmly to form a chip assembly. In the specific embodiment, according to the actual requirements of the CMOS flat panel detector, M*T chips 1 are bonded firmly to form the required chip assembly.

[0044] S4. The removable traceless adhesive 4 is bonded on the surface of the chip assembly, and the chip assembly is bonded to the fixing plate 5 through the traceless adhesive 4. In the specific embodiment, the fixing plate 5 can be made of alumina (i.e. ceramic), silicon carbide, aluminum nitride, glass, etc. The coefficient of thermal expansion of the plate material is below 10 ppm, which reduces the influence of temperature on the thermal expansion of the fixing plate 5.

[0045] S5. The bonding medium 6 is coated on the backing plate 7, which is used to bond and fix the spliced chip assembly, and the bonding is easy to disassemble without damaging the chip assembly. The chip assembly and the fixing plate 5 are transferred to the backing plate 7, so that the chip assembly surface and the side opposite to the fixing plate 5 are in contact with the bonding medium 6. In the specific embodiment, the backing plate 7 is made of alumina, silicon carbide, aluminum nitride or glass, and the coefficient of thermal expansion is below 10 ppm, which further ensures that the gap change between the chip assemblies is within 1 / 4 pixel size.

[0046] S6. The bonding member 3 and the traceless adhesive 4 on the fixing plate 5 and the chip assembly are removed, so that the chip assembly surface is bonded to the backing plate 7 through the bonding medium 6, thereby completing the splicing of the plurality of chips 1.

[0047] In the present application, the chip 1 is placed at the required distance, then pre-fixed by the adhesive 3, then transferred to the backing plate 7 by the traceless glue 4 and the fixing plate 5, and the adhesive 4 and the traceless glue 5 are taken out, so that the chip 1 is fixed on the backing plate 7, and the CMOS flat panel detector module of the target size is obtained by splicing. The present application has the excellent characteristics of rework, that is, the chip assembly can be disassembled without damage after splicing, which greatly solves the overall scrapping of the module caused by the chip failure, greatly saves the cost. When one of the chips is abnormal, it only needs to be replaced, so as to solve the overall scrapping of the module caused by the chip failure, and the operator can perform manual operation, and is free from the dependence on the equipment, and the splicing method is simple and has strong operability.

[0048] The present application also provides a chip splicing structure made by the chip splicing method.

[0049] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the different embodiments or examples described in the present application and the features of the different embodiments or examples can be combined and combined by those skilled in the art without contradiction.

[0050] The above is only the preferred embodiment of the present application, and does not limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip tiling method, characterized by, It comprises the following steps: S1. Place two chips (1) under the range-finding instrument for splicing, so that the distance between the adjacent pixels (2) on the two chips (1) is equal to N times the pixel size of the range-finding instrument; S2. After splicing, use an adhesive (3) to bond the splicing seam of the two chips (1), so that the two chips (1) are firmly bonded; S3. Repeat steps S1 and S2 until M*T chips (1) are firmly bonded to form a chip assembly; S4. Bond a removable traceless adhesive (4) on the surface of the chip assembly, and bond the chip assembly to a fixed plate (5) through the traceless adhesive (4); S5. Apply an adhesive medium (6) on the backing plate (7), and transfer the chip assembly and the fixed plate (5) to the backing plate (7), so that the surface of the chip assembly and the side opposite to the fixed plate (5) are bonded to the adhesive medium (6); S6. Remove the adhesive (3) and the traceless adhesive (4) on the fixed plate (5) and the chip assembly, so that the surface of the chip assembly is bonded to the backing plate (7) through the adhesive medium (6).

2. The chip tiling method of claim 1, wherein: In step S1, the range-finding instrument comprises a range-finding microscope, and the precision error is less than or equal to 10 microns.

3. The chip tiling method of claim 1, wherein: In step S2, the adhesive (3) comprises an anti-static adhesive tape, and the tensile strength of the anti-static adhesive tape is >40N / 10mm, and the peel strength is >5N.

4. The chip tiling method of claim 1, wherein: After step S2, it further comprises measuring the splicing gap between the two chips (1) again to ensure that the splicing gap does not change in distance during bonding and fixing.

5. The chip tiling method of claim 1, wherein: In step S5, the backing plate (7) is made of one or more of alumina, silicon carbide, aluminum nitride or glass, and the thermal expansion coefficient is less than 10 ppm.

6. A chip tiling structure, characterized by: A chip splicing structure made by the chip splicing method of any one of claims 1 to 5. A chip splicing structure made by the chip splicing method of any one of claims 1 to 5.

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