Antiferroelectric thin film structures and electronic devices, memory cells, electronic devices

Abstract

A structure of a ferroelectric thin film, an electronic device, a memory cell, and an electronic apparatus are disclosed, wherein the structure of the ferroelectric thin film includes: a dielectric layer including a ferroelectric phase of hafnium oxide; and an insertion layer in the dielectric layer, the insertion layer including an oxide. An electronic device to which the structure of the ferroelectric thin film has been applied can ensure an operating voltage range with little hysteresis.

Description

Technical Field

[0001] The embodiments relate to antiferroelectric thin film structures and electronic devices, memory cells, and electronic apparatuses including the antiferroelectric thin film structures. Background Technology

[0002] As electronic devices shrink proportionally, the available space occupied by electronic circuits within these devices also decreases. Therefore, there is a demand for miniaturization and high performance of electronic components such as capacitors and transistors included in electronic circuits. To this end, research continues on dielectric thin films with high dielectric constants, even with small thicknesses, to exhibit the desired operating characteristics. Summary of the Invention

[0003] An antiferroelectric thin film structure with a high dielectric constant is provided.

[0004] An electronic device employing an antiferroelectric thin film structure is provided.

[0005] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0006] According to one aspect of an example embodiment, an antiferroelectric thin film structure includes: a dielectric layer comprising an antiferroelectric phase of hafnium oxide; and an insertion layer in the dielectric layer comprising an oxide.

[0007] The dielectric layer may include at least one of Y, Al, Ti, Sr, Zr, La and N as a dopant.

[0008] The amount of dopant can be 50% or less of the total elements in the dielectric layer.

[0009] When the oxide included in the intercalation layer is represented as M x O y When M is selected, it can be at least one of Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu.

[0010] The thickness of the intercalation layer can be greater than 0% of the total thickness of the antiferroelectric thin film structure and less than or equal to 50% of that total thickness.

[0011] The dielectric layer may include a first dielectric layer above the insertion layer and a second dielectric layer below the insertion layer. The first dielectric layer and the second dielectric layer may have a thickness greater than 0.

[0012] According to another embodiment, an electronic device includes: a lower electrode; an upper electrode; and the aforementioned antiferroelectric thin film structure between the lower electrode and the upper electrode.

[0013] At least one of the lower electrode and the upper electrode may include at least one of nitride, oxide and metal oxide.

[0014] The at least one of the lower and upper electrodes may include at least one of Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

[0015] The dielectric layer may include at least one of Y, Al, Ti, Sr, Zr, La and N as a dopant.

[0016] The amount of dopant can be 50% or less of the total elements in the dielectric layer.

[0017] When the oxide is represented as M x O y When M is selected, it can be at least one of Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu.

[0018] The thickness of the intercalation layer can be greater than 0% of the total thickness of the antiferroelectric thin film structure and less than or equal to 50% of that total thickness.

[0019] The electronic device may further include a transistor electrically connected to at least one of the lower electrode and the upper electrode.

[0020] According to another embodiment, an electronic device includes: a semiconductor substrate; an upper electrode; and an antiferroelectric thin film structure between the semiconductor substrate and the upper electrode.

[0021] The dielectric layer may include at least one of Y, Al, Ti, Sr, Zr, La and N as a dopant.

[0022] The amount of dopant can be 50% or less of the total elements in the dielectric layer.

[0023] When the oxide is represented as M x O yWhen M is selected, it can be at least one of Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu.

[0024] The thickness of the intercalation layer can be greater than 0% of the total thickness of the antiferroelectric thin film structure and less than or equal to 50% of that total thickness.

[0025] The electronic device may further include an insulating layer between the semiconductor substrate and the antiferroelectric thin film structure.

[0026] The electronic device may further include a conductive layer between the antiferroelectric thin film structure and the insulating layer.

[0027] The conductive layer may include at least one of Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

[0028] The semiconductor substrate may include a source region, a drain region, and a channel region between the source and drain regions, with an antiferroelectric thin film structure on the channel region.

[0029] The dielectric layer and the insertion layer may differ in at least one of the following: charge, partial charge, and asymmetric charge distribution, such that an additional electric dipole is formed at the interface between the dielectric layer and the insertion layer.

[0030] According to another embodiment, a storage cell may include a charge storage device comprising the aforementioned antiferroelectric thin film structure. The charge storage device may be at least one of a capacitor and a floating gate.

[0031] According to another embodiment, an electronic device may include the aforementioned storage unit. Attached Figure Description

[0032] From the following description taken in conjunction with the accompanying drawings, some exemplary embodiments of the present invention will become more apparent:

[0033] Figure 1 This is a cross-sectional view of a schematic structure of an electronic device including an antiferroelectric thin film structure according to some exemplary embodiments;

[0034] Figure 2A and Figure 2B It is displayed in Figure 1 The curves showing the polarization hysteresis characteristics with different insertion layer thicknesses in the antiferroelectric thin film structure of electronic devices;

[0035] Figure 3A and Figure 3B It is displayed in Figure 1 A graph showing the capacitive hysteresis characteristics of electronic devices with different insertion layer thicknesses;

[0036] Figure 4 It is a cross-sectional view of a schematic structure of an electronic device based on a comparative example;

[0037] Figure 5 It is displayed in Figure 4 A graph showing the capacitive hysteresis characteristics of electronic devices based on the composition of the dielectric layer of the electronic device.

[0038] Figure 6A It is a cross-sectional view of a schematic structure of an electronic device according to some example embodiments;

[0039] Figure 6B It is a layout diagram of a semiconductor device according to some example implementations;

[0040] Figure 6C and Figure 6D yes Figure 6B The semiconductor device shown along Figure 6B A sectional view taken by line A-A';

[0041] Figure 7 It is a cross-sectional view of a schematic structure of an electronic device according to some example embodiments;

[0042] Figure 8 These are cross-sectional views of a schematic structure of an electronic device according to some example embodiments; and

[0043] Figure 9 and Figure 10 This is a conceptual diagram illustrating an electronic device architecture that can be applied to electronic devices according to some example implementations. Detailed Implementation

[0044] Referring now to some exemplary embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. The same reference numerals in the drawings denote the same elements, and in the drawings, the dimensions of elements may be enlarged for clarity and ease of explanation. In this respect, present embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments described below with reference to the accompanying drawings are only to illustrate aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “one or more of…” following a column of elements modify the entire column of elements, rather than individual elements within that column.

[0045] It will be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on that other layer or substrate, or there may be an intervening layer. For ease of description, spatial relational terms such as “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature as shown in the figures and another element(s). It will be understood that if the device in the figures is flipped, the element described as being “below” or “below” other elements or features will be oriented “above” other elements or features. Thus, the device can be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relational descriptions used herein are interpreted accordingly.

[0046] Terms such as "first" and "second" may be used to describe various components, but only for the purpose of distinguishing one component from others. Unless otherwise indicated, these terms do not limit the differences in the materials or structures of the components.

[0047] A singular expression includes a plural expression unless it has a distinct meaning in the context. When used in this specification, the terms “comprising” and / or “including” or “including” and / or “comprising” indicate the presence of the stated element, but do not exclude the presence or addition of one or more other elements.

[0048] When used in this specification, the terms “unit,” “device,” and “module” refer to a unit that performs at least one function or operation and can be implemented as hardware, software, or a combination of hardware and software. For example, “unit,” “device,” and “module” can include and / or be included in, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0049] The use of the terms “one,” “an,” and “the,” as well as similar indicators, will be interpreted to cover both the singular and plural.

[0050] The operations of the constructive method may be performed in any suitable order unless otherwise indicated herein. The use of any and all exemplary language (e.g., "such as") provided herein is intended only to illustrate the technical ideas of this disclosure and does not constitute a limitation on the scope of this disclosure unless otherwise stated.

[0051] Figure 1 This is a cross-sectional view of a schematic structure of an electronic device including an antiferroelectric thin film structure according to some example embodiments.

[0052] According to some example embodiments, the antiferroelectric thin film structure 150 includes hafnium oxide (HfO). x (e.g., HfO2), and includes a dielectric layer 120 presenting an antiferroelectric phase and an insertion layer 130 inserted into the dielectric layer 120.

[0053] According to some example embodiments, electronic device 100 includes a lower electrode 110 and an upper electrode 190 spaced apart from each other, and an antiferroelectric thin film structure 150 disposed between the lower electrode 110 and the upper electrode 190. Electronic device 100 may be, for example, a charge storage device, such as a capacitor.

[0054] Antiferroelectric thin film structure 150 is proposed as a structure that can exhibit a high dielectric constant and a small hysteresis operating voltage range.

[0055] The hafnium oxide included in the dielectric layer 120 can be used as a high-k dielectric material. Depending on the type and amount of dopant, the crystal phase of the hafnium oxide, and / or the stress state with adjacent layers, the hafnium oxide can exhibit paraelectric, ferroelectric, and / or antiferroelectric properties. For example, hafnium oxide is ferroelectric in an orthorhombic phase and antiferroelectric in a tetragonal phase. The dielectric constant and / or hysteresis characteristics vary according to these states. In some example embodiments, the phase of the hafnium oxide may be affected, for example, by stress on the lattice of the hafnium oxide. For example, in some example embodiments, the hafnium oxide can be induced to a tetragonal phase by stress, for example, due to lattice mismatch with adjacent layers, by internal stress due to the included dopant, by external pressure and / or stress sources and / or similar factors. The composition and / or thickness of the hafnium oxide may also affect the phase transition of the hafnium oxide.

[0056] An antiferroelectric thin film structure 150 according to some exemplary embodiments includes a dielectric layer 120 comprising a hafnium oxide (HfO2) having an antiferroelectric phase to exhibit a high dielectric constant. The dielectric layer 120 may be doped with at least one of Y, Al, Ti, Sr, Zr, La, and N. The amount of doped Y, Al, Ti, Sr, Zr, La, and / or N may be 50% or less atomically relative to all elements of the dielectric layer 120. For example, when the hafnium oxide is doped with, for example, dopant D, the doped hafnium oxide may be represented as HfO2. (1-x) D x O2, where x can be, for example, 0.8 or less. The amount of dopant D can be appropriately set according to the type of dopant.

[0057] Insertion layer 130 is a layer included within dielectric layer 120. For example, insertion layer 130 may be a layer embedded within dielectric layer 120. When the region of dielectric layer 120 is divided into a first dielectric layer 121 located on insertion layer 130 and a second dielectric layer 122 located below insertion layer 130, the respective thicknesses of the first dielectric layer 121 and the second dielectric layer 122 are both set to be greater than 0. Insertion layer 130 may be referred to as a built-in field control layer.

[0058] For example, a built-in field (which is an electric field generated within the dielectric layer 120 between the upper electrode 190 and the lower electrode 110) is generated due to, for example, the work function difference at the electrode interface and defects in the dielectric layer 120. This built-in field can be a cause and / or contributing factor to a shift in capacitance-voltage behavior and / or formation hysteresis within the operating voltage range. The insertion layer 130 can control the built-in field by forming additional electric dipoles or charges within the dielectric layer 120. For example, not limited to a particular theory, the insertion layer 130 can form an electric field that cancels out the built-in field.

[0059] Insertion layer 130 may include an oxide. This oxide layer may be, for example, an insulating oxide layer. When the oxide included in insertion layer 130 is denoted as M... x O yIn this case, M may include at least one of Al, Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu. O is oxygen, and x and y are real numbers greater than 0. In some example embodiments, the oxide may have a band gap of 4 eV or greater; and / or the oxygen ratio of the oxide may be less than or equal to the oxygen ratio of a hafnium oxide (e.g., HfO2). In some example embodiments, the charge (and / or partial charge) distribution in the oxide may differ from that in the hafnium oxide, and / or the oxide may have a different degree of asymmetric charge distribution than that in the hafnium oxide, thereby forming additional electric dipoles and / or charges at the interface between the insertion layer 130 and the dielectric layer 120.

[0060] For example, in some exemplary embodiments, at least one of the oxide number, electronegativity, and / or electronic structure may be different from the dielectric layer 120, such that the band arrangement and / or charge distribution of the antiferroelectric thin film structure 150 may be altered compared to an antiferroelectric thin film structure without the insert layer 130.

[0061] The thickness of the insertion layer 130 can be greater than 0% and / or less than or equal to 50% of the total thickness of the antiferroelectric thin film structure 150. The thickness of the insertion layer 130 can be, for example, 1% or greater, 3% or greater, 5% or greater, 30% or less, and / or 10% or less of the total thickness of the antiferroelectric thin film structure 150. The location of the insertion layer 130 is not particularly limited, except that it is disposed within the dielectric layer 120. For example, the insertion layer 130 can be disposed at any location within the dielectric layer 120, such as on the upper, center, or lower side of the dielectric layer 120. The material included in the insertion layer 130 and its thickness can be appropriately set to reduce hysteresis by controlling the built-in field within the dielectric layer 120.

[0062] Each of the upper electrode 190 and the lower electrode 110 may include a conductive material. For example, each of the upper electrode 190 and the lower electrode 110 may include at least one of a metal, a metal nitride, a metal oxide, and combinations thereof.

[0063] The lower electrode 110 can be configured to have a material that enables the dielectric layer 120 to have an antiferroelectric phase by providing appropriate tensile stress to the interface with the dielectric layer 120. Depending on the tensile stress, the crystal phase of hafnium oxide (HfO2) can be transformed into an orthorhombic crystal phase exhibiting ferroelectricity or a tetragonal crystal phase exhibiting antiferroelectricity. The lower electrode 110 may include at least one of, for example, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. For example, in some exemplary embodiments, after fabricating the lower electrode 110, an antiferroelectric thin film structure 150 may be formed on the lower electrode 110.

[0064] An antiferroelectric thin film structure 150 can be formed on the lower electrode 110, and an upper electrode 190 can be formed on the first dielectric layer 121. The antiferroelectric thin film structure 150 can be formed by various stacking methods. For example, an atomic layer deposition (ALD) method can be used to sequentially form a second dielectric layer 122, an insertion layer 130, and a first dielectric layer 121. Taking the second dielectric layer 122 and the insertion layer 130 as examples, after forming a hafnium layer on the lower electrode 110 (e.g., by supplying an Hf precursor to the chamber), a purging operation is performed to remove any remaining residual material, and the hafnium layer is oxidized by injecting an oxidant. The hafnium precursor may include, for example, hafnium coordinated to a ligand, and the oxidant may include, for example, at least one of O2, O3, H2O, H2O2, and the like. Then, a layer is formed by supplying an M-containing precursor to the chamber. Afterward, a purging operation can be performed to remove any remaining material, and the layer can be oxidized by injecting an oxidant. M is formed on the hafnium oxide layer. x O y After the layer is deposited, a purging operation can be performed (e.g., to remove residual gas remaining in the chamber). Following the deposition of the antiferroelectric thin film 150 and / or the upper electrode 190 (e.g., using atomic layer deposition), a thermal processing step can be performed. For example, in some example embodiments, the dielectric layer 120 can be an antiferroelectric layer by controlling the thermal processing and / or the concentration of the dopant.

[0065] The thickness of the intercalation layer 130 may be a factor affecting the polarization and capacitance of the antiferroelectric thin film structure 150. (Refer to...) Figures 2A to 3B Experimental results describing the effect of the thickness of the insertion layer 130.

[0066] Figure 2A and Figure 2B It is shown in Figure 1 The graph shows the polarization hysteresis characteristics with respect to different insertion layer thicknesses in the antiferroelectric thin film structure 150 of the electronic device 100.

[0067] Polarization characteristics (e.g., polarization due to applied voltage) exhibit hysteresis. For example... Figure 2A and Figure 2B As shown in the graph, the operating intervals with very little hysteresis (or almost no hysteresis, also referred to below as no hysteresis) have different widths (e.g., OP1 and OP2).

[0068] Figure 2A and Figure 2B The thickness of each insertion layer is greater than 0% of the total thickness of the antiferroelectric thin film structure 150 and is equal to or less than 10% of the total thickness. Figure 2A The thickness of the insertion layer is less than Figure 2B The thickness of the insertion layer.

[0069] from Figure 2A and Figure 2B As can be seen, as the thickness of the insertion layer increases within the aforementioned range, the width of the hysteresis-free operating range increases from OP1 to OP2, and the center of the hysteresis-free operating range shifts towards 0V. Therefore, it can be observed that the thickness of the insertion layer affects the degree of control over the built-in field and reduces hysteresis.

[0070] Figure 3A and Figure 3B It is shown in Figure 1 The graphs showing the capacitive hysteresis characteristics of different insertion layer thicknesses in the electronic device 100.

[0071] Figure 3A and Figure 3B Corresponding to Figure 2A and Figure 2B It was shown that the hysteresis exhibited by the capacitor changes similarly depending on the thickness of the insertion layer.

[0072] Figure 4 This is a cross-sectional view of a schematic structure of the electronic device 10 according to the comparative example. Figure 5 It is displayed in Figure 4 A graph showing the capacitive hysteresis characteristics of the electronic device 10 based on the composition of the dielectric layer 12 of the electronic device 10.

[0073] The electronic device 10 includes a lower electrode 11, a dielectric layer 12, and an upper electrode 19, and does not include an insertion layer compared to the example embodiment.

[0074] Reference Figure 5 The curve is based on the composition of dielectric layer 12 (e.g., in Hf). 0.3 Zr 0.7 O2, Hf 0.5 Zr 0.5 When the composition of O2 and HfO2 changes, the capacitance value also changes, as does the hysteresis characteristic. For example, as the Zr content increases, the capacitance increases, but the hysteresis also increases. Therefore, in the electronic device 10 according to the comparative example, the case of HfO2 composition exhibiting only low capacitance can be applied to capacitors.

[0075] However, in the antiferroelectric thin film structure 150 according to one embodiment, hysteresis can be reduced due to the inclusion of the intercalation layer 130. Therefore, if an intercalation layer is included, such as in Figure 5 The other components shown in the figure have large capacitance and hysteresis (Hf) 0.3 Zr 0.7 O2, Hf 0.5 Zr 0.5 O2 can be used as a capacitor.

[0076] Figure 6A This is a cross-sectional view of a schematic structure of an electronic device 300 according to some example embodiments.

[0077] The electronic device 300 has a structure in which a capacitor 101 is electrically connected to a transistor 200, and can be a component of an electronic circuit that is implemented as an integrated device.

[0078] Capacitor 101 includes Figure 1 The antiferroelectric thin film structure 150 included in the electronic device 100, for example, may have a similar shape to... Figure 1 The electronic devices 100 have essentially the same structure.

[0079] Capacitor 101 may be electrically connected to transistor 200. For example, capacitor 101 may be connected to transistor 200 via contact 20. Transistor 200 may be a field-effect transistor. One of the lower electrode 110 and the upper electrode 190 of capacitor 101 may be electrically connected to one of the source SR and drain DR of transistor 200. For example, lower electrode 110 may directly contact one of the source SR and drain DR and / or be connected to one of the source SR and drain DR via contact 20.

[0080] The transistor 200 may include a semiconductor substrate 210 (which includes a source SR, a drain DR, and a channel CH), a gate electrode 290 disposed opposite to the channel CH, and a gate insulating layer 220 interposed between the channel CH and the gate electrode 290.

[0081] Semiconductor substrate 210 may include a semiconductor material. For example, the semiconductor material may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), transition metal dichalcogenides, and the like. The semiconductor material may be modified in various forms, such as silicon-on-insulator (SOI).

[0082] The channel CH can be electrically connected to the source SR and the drain DR. For example, the source SR can be electrically connected to one end of the channel CH and / or contact one end of the channel CH, and the drain DR can be electrically connected to the other end of the channel CH and / or contact the other end of the channel CH. In some example embodiments, the channel CH can be defined as a substrate region within the semiconductor substrate 210 between the source SR and the drain DR and / or a substrate region below the gate electrode 290.

[0083] The source SR, drain DR, and channel CH can be formed independently by implanting impurities into different regions of the semiconductor substrate 210. For example, the source SR, channel CH, and drain DR may include a substrate material as a base material. In some example embodiments, the impurities included in the source SR and drain DR may have different polarities and / or may have different concentrations relative to the impurities included in the channel CH.

[0084] The source electrode SR and / or drain electrode DR may include at least one conductive material, such as a metal, a metal compound, and a conductive polymer. The conductive material may form electrodes on and / or in the source electrode SR and / or drain electrode DR. The electrodes may be referred to as the source electrode and the drain electrode, respectively.

[0085] In some example implementations, the channel CH can be implemented as a separate material layer. For example, the channel CH may include oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) materials, quantum dots, and / or organic semiconductors. For example, oxide semiconductors may include InGaZnO, 2D materials may include transition metal dichalcogenides (TMDs) or graphene, and quantum dots may include colloidal quantum dots (QDs) or nanocrystalline structures.

[0086] Gate electrode 290 may be disposed on semiconductor substrate 210 spaced apart from semiconductor substrate 210 and facing channel CH. Gate electrode 290 may have a conductivity of, for example, 1 Mohm / square or less. Gate electrode 290 may include a conductive material, such as at least one of metal, metal nitride, metal carbide, and the like. For example, metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti) and / or tantalum (Ta), and metal nitride may include titanium nitride (TiN) and / or tantalum nitride (TaN). Metal carbide may be a metal carbide doped with (and / or containing) aluminum and / or silicon, and examples of metal carbides may include TiAlC, TaAlC, TiSiC, and TaSiC. Gate electrode 290 may have a structure in which multiple materials are stacked, for example, a stacked structure of metal nitride layers / metal layers such as TiN / Al and / or a stacked structure of metal nitride layers / metal carbide layers / metal layers such as TiN / TiAlC / W. The gate electrode 290 may include a titanium nitride (TiN) layer or a molybdenum (Mo) layer, and the foregoing examples may be used in various modified forms.

[0087] The gate insulating layer 220 between the semiconductor substrate 210 and the gate electrode 290 may comprise a paraelectric material and / or a high-k material, and may have a dielectric constant of, for example, 20 to 70. The gate insulating layer 220 may comprise an insulating material, such as at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, and 2D insulators (such as hexagonal boron nitride (h-BN)). For example, the gate insulating layer 220 may comprise silicon oxide (SiO2), silicon nitride (SiN), etc. x Hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbSc) 0.5 Ta 0.5 O3), lead zinc niobate (PbZnNbO3) and / or similar substances.

[0088] The gate insulating layer 220 may include metal oxides (such as aluminum oxide nitride (AlON), zirconium oxide nitride (ZrON), hafnium oxide nitride (HfON), lanthanum oxide nitride (LaON), or yttrium oxide nitride (YON)), silicates (such as ZrSiON, HfSiON, YSiON, or LaSiON), and / or aluminates (such as ZrAlON or HfAlON). The gate insulating layer 220 may include multiple layers. In some example embodiments, the gate insulating layer 220 may include an antiferroelectric thin film structure 150. The gate insulating layer 220 may form a gate stack together with the gate electrode 290.

[0089] Contact 20 may include a conductive material, such as tungsten, copper, aluminum, polysilicon, or the like.

[0090] The layout of capacitor 101 and transistor 200 can be varied. For example, capacitor 101 can be arranged as follows: Figure 6A It is disposed on the semiconductor substrate 210 as shown, and / or may have a structure in which a capacitor 101 is embedded in the semiconductor substrate 210.

[0091] although Figure 6A An electronic device 300 is shown, comprising a single capacitor 101 and a single transistor 200; however, an electronic device according to another embodiment may have… Figure 6A The structure is a repeating arrangement in a 2D manner, such as a grid. Electronic device 300 may be included, for example, as a storage unit and / or device, and / or included in a storage unit and / or device.

[0092] For example, refer to Figure 6B The semiconductor device D10 may include: a field-effect transistor, including a gate stack 230 and a semiconductor substrate 210, the gate stack 230 including a gate electrode (e.g., Figure 6A The semiconductor substrate 210 includes a gate electrode 290 and a gate insulating layer 220, and has a source, a drain, and a channel; a contact structure 20' disposed on the semiconductor substrate 210 without overlapping with the gate stack 230; and a capacitor 101 disposed on the contact structure 20'. The semiconductor device D10 may further include a bit line structure 13 that electrically connects the field-effect transistors to each other. Figure 6B The semiconductor device D10 is shown, in which contact structures 20' and capacitors 101 are repeatedly arranged in the X and Y directions, but this is a non-limiting example. For example, contact structures 20' may be arranged in the X and Y directions, and capacitors 101 may be arranged in a hexagonal shape such as a honeycomb structure.

[0093] Figure 6C It is along Figure 6B A cross-sectional view taken along line AA to show an example structure of semiconductor device D10. (Refer to...) Figure 6C The semiconductor substrate 210 may have a shallow trench isolation (STI) structure including a device isolation layer 14. The device isolation layer 14 may be a single layer including a single type of insulating layer, and / or may have a multilayer structure including a combination of two or more types of insulating layers. The device isolation layer 14 may include device isolation trenches 14T in the semiconductor substrate 210, and the device isolation trenches 14T may be filled with an insulating material. The insulating material may include, but is not limited to, fluorosilicate glass (FSG), undoped silicate glass (USG), borosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), and / or polysilazane (e.g., Tonen silazane (TOSZ)).

[0094] Furthermore, the semiconductor substrate 210 may further include: an active region AC defined by a device isolation layer 14; and a gate trench 230T, which may be arranged parallel to the upper surface of the semiconductor substrate 210 and / or extend in the X direction. The active region AC may have a relatively long island shape, the island shape having a short axis and a long axis. Figure 6C As shown, the long axis of the active region AC can be arranged in a direction D3 parallel to the upper surface of the semiconductor substrate 210. The gate trench 230T can have a given (and / or otherwise determined) depth from the upper surface of the semiconductor substrate 210 and can be arranged within or across the active region AC. The gate trench 230T can also be provided inside the device isolation trench 14T, and the gate trench 230T provided inside the device isolation trench 14T can have a lower bottom than the bottom of the gate trench 230T provided in the active region AC.

[0095] The first source / drain 210ab and the second source / drain 210ab' can be arranged in the upper part of the active region AC on both sides of the gate trench 230T.

[0096] The gate stack 230 can be disposed within the gate trench 230T. For example, the gate insulating layer 230a, the gate electrode 230b, and the gate capping layer 230c can be sequentially disposed within the gate trench 230T. The gate insulating layer 230a and the gate electrode 230b can be the same as those described above, and the gate capping layer 230c can include silicon oxide, silicon oxide nitride, and / or silicon nitride. The gate capping layer 230c can be disposed on the gate electrode 230b to fill the remaining portion of the gate trench 230T.

[0097] Furthermore, the bit line structure 13 can be disposed on the first source / drain 210ab. The bit line structure 13 can be parallel to the upper surface of the semiconductor substrate 210 and can extend in the Y direction. The bit line structure 13 can be electrically connected to the first source / drain 210ab and can include bit line contacts 13a, bit lines 13b, and / or bit line capping layers 13c sequentially formed on the semiconductor substrate 210. For example, the bit line contact 13a can include polysilicon, the bit line 13b can include a metallic material, and the bit line capping layer 13c can include an insulating material, such as silicon nitride (SiN) and / or silicon oxide nitride (SiON).

[0098] Figure 6C The bit line contact 13a is shown to have a bottom surface at the same level as the upper surface of the semiconductor substrate 210. However, the bit line contact 13a may extend into a recess (not shown) formed from the upper surface of the semiconductor substrate 210 to a predetermined (and / or otherwise desired) depth, such that the bottom surface of the bit line contact 13a may be lower than the upper surface of the semiconductor substrate 210.

[0099] Optionally, the bit line structure 13 may include a bit line interlayer (not shown) between the bit line contact 13a and the bit line 13b. The bit line interlayer may include a metal silicide such as tungsten silicide and / or a metal nitride such as tungsten nitride. Furthermore, bit line spacers (not shown) may be further formed on the sidewalls of the bit line structure 13. The bit line spacers may have a single-layer structure and / or a multi-layer structure, and may include an insulating material such as silicon oxide, silicon oxide nitride, and / or silicon nitride. Additionally, the bit line spacers may further include an air space (not shown).

[0100] Contact structure 20' may be disposed on the second source / drain 210ab'. Contact structure 20' and bit line structure 13 may be disposed on different source / drain electrodes in semiconductor substrate 210. Contact structure 20' may have a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and / or an upper contact pattern (not shown) are sequentially stacked on the second source / drain 210ab'. In addition, contact structure 20' may further include a barrier layer (not shown) surrounding at least one of the side surface and / or bottom surface of the upper contact pattern. In some embodiments, the lower contact pattern may include a conductive and / or semiconductive material (e.g., polysilicon), the upper contact pattern may include a conductive material (e.g., a metallic material), and / or the barrier layer may include a conductive material (e.g., a conductive metal nitride) resistant to degradation and / or defect (and / or inclusion) diffusion.

[0101] The capacitor 101 can be electrically connected to the contact structure 20' and can be disposed on the semiconductor substrate 210. For example, the capacitor 101 may have a lower electrode 110 electrically connected to the contact structure 20', an antiferroelectric thin film structure 150 disposed on the lower electrode 110, and an upper electrode 190 disposed on the antiferroelectric thin film structure 150. The antiferroelectric thin film structure 150 can be disposed on the lower electrode 110 parallel to the surface of the lower electrode 110.

[0102] An interlayer insulating layer 15 may be further disposed between the capacitor 101 and the semiconductor substrate 210. The interlayer insulating layer 15 may be disposed in the space between the capacitor 101 and the semiconductor substrate 210, in which no other structures are disposed. For example, the interlayer insulating layer 15 may cover wiring and / or electrode structures formed on or in the semiconductor substrate 210, such as bit line structures 13, contact structures 20', and gate stacks 230. For example, the interlayer insulating layer 15 may surround the wall of the contact structure 20'. The interlayer insulating layer 15 may include: a first interlayer insulating layer 15a surrounding the bit line contact 13a; and a second interlayer insulating layer 15b covering the side surfaces and / or top surfaces of the bit line 13b and the bit line cover layer 13c.

[0103] The lower electrode 110 of capacitor 101 can be disposed on interlayer insulating layer 15 (e.g., on the second interlayer insulating layer 15b of interlayer insulating layer 15). Furthermore, when multiple capacitors 101 can be disposed, the bottom surfaces of the multiple lower electrodes 110 can be separated from each other by an etch stop layer 16. For example, the etch stop layer 16 may include an opening 16T in which the bottom surfaces of the lower electrodes 110 of capacitor 10 can be disposed.

[0104] like Figure 6C As shown, the lower electrode 110 can have a cylindrical or cup shape with a closed bottom. In another example, such as Figure 6D As shown, the lower electrode 110 may have a cylindrical shape extending in the vertical direction (Z direction), such as a cylinder, a rectangular cylinder or a polygonal cylinder.

[0105] Furthermore, capacitor 101 may further include a support (not shown) to prevent the lower electrode 110 from tilting or collapsing. For example, the support may be arranged on the sidewall of the lower electrode 110.

[0106] The above embodiments illustrate an electronic device, wherein electronic device 100 serves as capacitor 101. However, the antiferroelectric thin film structure 150 according to some embodiments can be applied to logic devices.

[0107] Figure 7 This is a cross-sectional view of a schematic structure of an electronic device 400 according to some example embodiments.

[0108] The electronic device 400 includes a semiconductor substrate 410 and an antiferroelectric thin film structure 150 disposed on the semiconductor substrate 410. An insulating layer 420 can be interposed between the semiconductor substrate 410 and the antiferroelectric thin film structure 150. An upper electrode 490 can be disposed on the antiferroelectric thin film structure 150.

[0109] The semiconductor substrate 410 may include a source electrode SR, a drain electrode DR, and a channel CH electrically connected to the source electrode SR and the drain electrode DR. The semiconductor substrate 410 can be coupled with... Figure 6A The semiconductor substrate 210 is the same as and / or substantially similar to it.

[0110] The upper electrode 490 may be referred to as the gate electrode. The upper electrode 490 may include, for example: Figure 6A The materials and structures of the gate electrode 290 are shown below. For example, the upper electrode 490 may include metals, metal nitrides, metal carbides, and / or combinations thereof, and may have a multi-layered structure. The upper electrode 490 may also be... Figure 1 The upper electrode 190 is the same as and / or substantially similar.

[0111] Insulating layer 420 may be a layer for suppressing and / or preventing electrical leakage, and may include a dielectric material. Insulating layer 420 may include multiple material layers with different dielectric constants. Insulating layer 420 may include insulating materials such as at least one selected from SiO, AlO, HfO, ZrO, LaO, YO, MgO, and 2D insulators. Materials such as h-BN may be used as 2D insulators. The materials of insulating layer 420 are not limited thereto.

[0112] Electronic device 400 may be a logic transistor, wherein the antiferroelectric thin film structure 150 is used for domain switching operation.

[0113] The antiferroelectric material included in the antiferroelectric thin film structure 150 may include ferroelectric domains in which electric dipoles are aligned, and the residual polarization represents 0 (and / or a value close to 0) when no external electric field is applied. In the antiferroelectric material, the direction of polarization can be switched when an external electric field is applied.

[0114] As described above, according to some exemplary embodiments, the antiferroelectric thin film structure 150 includes: a dielectric layer 120 comprising an antiferroelectric phase of HfO2; and an insertion layer 130 inserted into the dielectric layer 120 (e.g., inserted between a first dielectric layer 121 and a second dielectric layer 122). Therefore, the antiferroelectric thin film structure 150 has a wide range of characteristics capable of exhibiting substantially hysteresis-free behavior according to polarization changes in an external electric field. For example, the antiferroelectric thin film structure 150 can exhibit very little hysteresis during domain switching operations.

[0115] Figure 8This is a cross-sectional view of a schematic structure of an electronic device 500 according to some example embodiments.

[0116] Similar to Figure 7 Electronic device 400 and electronic device 500 can be logic transistors, wherein the antiferroelectric thin film structure 150 is used for domain switching operation.

[0117] Electronic device 500 includes a semiconductor substrate 510 and an antiferroelectric thin film structure 150 disposed on the semiconductor substrate 510. An insulating layer 520 may be included between the semiconductor substrate 510 and the antiferroelectric thin film structure 150, and a conductive layer 530 may be included between the insulating layer 520 and the antiferroelectric thin film structure 150. An upper electrode 590 may be disposed on the antiferroelectric thin film structure 150. The upper electrode 590 may be referred to as a gate electrode.

[0118] The semiconductor substrate 510 may include a source SR, a drain DR, and a channel CH electrically connected to the source SR and the drain DR. The semiconductor substrate 510 may be similar to... Figure 7 Semiconductor substrate 410 and / or Figure 6A Semiconductor substrate 210.

[0119] The conductive layer 530 between the antiferroelectric thin film structure 150 and the insulating layer 520 can be configured to have a material that enables the dielectric layer 120 to have an antiferroelectric phase by providing appropriate tensile stress to the interface with the dielectric layer 120. The conductive layer 530 can be coupled with... Figure 1 The lower electrode 110 is the same as and / or substantially similar to the lower electrode. The conductive layer 530 may include at least one of, for example, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

[0120] In some example embodiments, the conductive layer 530 may be configured as a floating gate, and the electronic device 500 may be a floating gate transistor (FGT). For example, the electronic device 500 may be configured to store (e.g., capture) charge into and / or release charge from the conductive layer 530. In some embodiments, for example, if negative charge is stored in the conductive layer 530 (e.g., through tunneling and / or electron injection), current flow may be prevented and / or mitigated even when charge is applied to the upper electrode 590. In some example embodiments, the electronic device 500 may serve as a charge (and / or data) storage cell, for example, in an erasable programmable read-only memory (EPROM) and / or an electrical EPROM (EEPROM).

[0121] Figure 9 and Figure 10 This is a conceptual diagram illustrating an electronic device architecture that can be applied to electronic devices according to some example implementations.

[0122] Reference Figure 9 The electronic device architecture 1000 may include a storage unit 1010 (e.g., cache and main memory), an arithmetic logic unit (ALU) 1020, and a control unit 1030. The storage unit 1010, ALU 1020, and control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1000 may be implemented as a single chip including the storage unit 1010, ALU 1020, and control unit 1030. The storage unit 1010, ALU 1020, and control unit 1030 may communicate directly with each other, for example, through interconnections with metal wires on the chip. In some example embodiments, the storage unit 1010, ALU 1020, and control unit 1030 may be monolithically integrated on a single substrate to form a single chip. Input / output devices 2500 may be connected to the electronic device architecture (chip) 1000 and may be configured to input and / or output information. For example, the input / output devices 2500 may include, but are not limited to, a screen, touchpad, keyboard, bus, microphone, camera, etc. Furthermore, the storage unit 1010 may include both main memory and cache. The electronic device architecture (chip) 1000 may be an on-chip memory processing unit.

[0123] The storage unit 1010, ALU 1020, and / or control unit 1030 may each independently include electronic devices employing the aforementioned antiferroelectric thin-film structure. These electronic devices may be logic transistors and / or capacitors.

[0124] Reference Figure 10The cache 1510, ALU 1520, and control unit 1530 can constitute a central processing unit (CPU) 1500, and the cache 1510 may include static random access memory (SRAM). In addition to the CPU 1500, main memory 1600 and auxiliary memory 1700 may be provided, and input / output devices 2500 may also be provided. The main memory 1600 may be dynamic random access memory (DRAM) and may include electronic devices employing the aforementioned antiferroelectric thin-film structure, such as capacitors.

[0125] In some cases, electronic device architectures can be implemented such that computing unit devices and storage unit devices are adjacent to each other on a single chip without distinguishing between sub-units.

[0126] The aforementioned antiferroelectric thin film structure has a wide operating range without hysteresis and also exhibits a high dielectric constant.

[0127] Antiferroelectric thin film structures can be used in a variety of electronic devices, such as transistors, capacitors, and / or integrated circuit devices.

[0128] Electronic devices that have applied the above-mentioned antiferroelectric thin film structure can ensure a very small operating voltage range with hysteresis.

[0129] It should be understood that the exemplary embodiments described herein should be considered descriptive only and not for limiting purposes. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0130] This application is based on and claims priority to Korean Patent Application No. 10-2021-0096717, filed on July 22, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An antiferroelectric thin film structure, comprising: The dielectric layer includes the antiferroelectric phase of hafnium oxide; as well as An insertion layer in the dielectric layer, the insertion layer comprising an oxide, in The dielectric layer includes Hf (1-x) Zr x O2, 0.5≤x≤0.8, The thickness of the inserted layer is greater than or equal to 5% and less than or equal to 10% of the total thickness of the antiferroelectric thin film structure.

2. The antiferroelectric thin film structure according to claim 1, This includes the oxide in the inserted layer, which is denoted as M. x O y x and y are real numbers greater than 0, and M is at least one of Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu.

3. The antiferroelectric thin film structure according to claim 1, The dielectric layer includes A first dielectric layer comprising the antiferroelectric phase of hafnium oxide above the insertion layer, and A second dielectric layer comprising the antiferroelectric phase of the hafnium oxide beneath the insertion layer, and The first dielectric layer and the second dielectric layer have a thickness greater than 0.

4. The antiferroelectric thin film structure according to claim 1, wherein the dielectric layer and the insertion layer have different charge distributions, such that an electric dipole is formed at the interface between the dielectric layer and the insertion layer.

5. The antiferroelectric thin film structure according to claim 4, wherein the dielectric layer and the insertion layer have different degrees of asymmetric charge distribution, such that an electric dipole is formed at the interface between the dielectric layer and the insertion layer.

6. An electronic device, comprising: Lower electrode; Upper electrode; and The antiferroelectric thin film structure of claim 1 is located between the lower electrode and the upper electrode.

7. The electronic device according to claim 6, The lower electrode and the upper electrode at least one of them include at least one of metal, metal nitride and metal oxide.

8. The electronic device according to claim 7, The at least one of the lower electrode and the upper electrode includes at least one of Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

9. The electronic device according to claim 6, The oxide is referred to as M. x O y x and y are real numbers greater than 0, and M is at least one of Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu.

10. The electronic device according to claim 6, further comprising: A transistor electrically connected to at least one of the lower electrode and the upper electrode.

11. An electronic device, comprising: Semiconductor substrate; Upper electrode; and The antiferroelectric thin film structure of claim 1 is located between the semiconductor substrate and the upper electrode.

12. The electronic device according to claim 11, The oxide is referred to as M. x O y x and y are real numbers greater than 0, and M is at least one of Al, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu.

13. The electronic device according to claim 11, further comprising: An insulating layer between the semiconductor substrate and the antiferroelectric thin film structure.

14. The electronic device according to claim 13, further comprising: A conductive layer between the antiferroelectric thin film structure and the insulating layer.

15. The electronic device according to claim 14, The conductive layer comprises at least one of Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

16. The electronic device according to claim 11, The semiconductor substrate includes a source region, a drain region, and a channel region between the source region and the drain region. The antiferroelectric thin film structure is located in the channel region.

17. The electronic device of claim 11, wherein the dielectric layer and the insertion layer have different charge distributions, such that an electric dipole is formed at the interface between the dielectric layer and the insertion layer.

18. The electronic device of claim 17, wherein the dielectric layer and the insertion layer differ in the degree of asymmetric charge distribution, such that an electric dipole is formed at the interface between the dielectric layer and the insertion layer.

19. A storage unit, comprising: A charge storage device, the charge storage device comprising the antiferroelectric thin film structure of claim 1.

20. The storage unit according to claim 19, wherein The charge storage device is at least one of a capacitor and a floating gate.

21. An electronic device comprising: The storage unit according to claim 19.

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