Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a manufacturing method thereof. A semiconductor device having a built-in gate resistance region in which adjustment of a resistance value of a gate electrode in a switching element is easily performed is obtained. Four built-in gate resistance trenches (8) all function as actual built-in gate resistance trenches for use. One end portion of each of the four built-in gate resistance trenches (8) is electrically connected to a wiring-side contact region (30) of a gate wiring (3) via a wiring contact portion (9L). The other end portion is electrically connected to a pad-side contact region (40) of a gate pad (4) via a pad contact portion (9P). At each of the four built-in gate resistance trenches (8), a distance between the wiring contact portion (9L) and the pad contact portion (9P) is defined as an inter-contact distance (Lr).

Description

Technical Field

[0001] This invention relates to a semiconductor device with a switching element having an insulated gate structure, and more particularly to a semiconductor device and a method thereof for manufacturing which allows for easy adjustment of the built-in gate resistance value for the gate electrode of the switching element. Background Technology

[0002] In recent years, IGBTs, MOSFETs, and other insulated-gate switching devices have been used as semiconductor components for power applications. To control the switching speed of these switching devices, resistors integrated on the chip are sometimes used as built-in gate resistors for the gate electrode of the switching device.

[0003] For example, Patent Document 1 proposes a structure in which a trench-type built-in gate resistor is formed as a built-in gate resistor for use as a gate electrode, thereby suppressing the gate current density and reducing the area of ​​the built-in gate resistor when viewed from above.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2013-062523

[0005] However, in the existing structures disclosed in Patent Document 1, etc., the trench-type built-in gate resistor and the gate electrode of the switching element formed in the unit section are usually connected by polysilicon wiring. In addition, the gate electrode has a trench gate structure.

[0006] Therefore, in order to control the resistance value of the gate electrode, multiple patterns such as trenches, polysilicon wiring, and contacts need to be modified, which presents a problem of difficulty in adjusting the resistance value. This is because multiple masks need to be prepared to correspond to the multiple patterns. Furthermore, the trench gate of a trench-type integrated gate resistor and switching element is equivalent to the trench itself.

[0007] Furthermore, in existing structures, the presence of a relatively thick thermal oxide film around the built-in gate resistor region presents a problem of easily applying stress to the region. Additionally, the thermal oxide film is used as a field oxide film, or LOCOS. Summary of the Invention

[0008] The present invention was proposed to solve the problems mentioned above, and its object is to obtain a semiconductor device having a built-in gate resistor region that is electrically connected to the gate electrode of a switching element and whose resistance value can be easily adjusted.

[0009] The semiconductor device of the present invention includes a switching element with an insulated gate structure, wherein the switching element is disposed on a semiconductor substrate of a first conductivity type. The semiconductor device has: a gate wiring disposed on the semiconductor substrate through an interlayer insulating film and electrically connected to the gate electrode of the switching element; a gate pad disposed on the semiconductor substrate through the interlayer insulating film, the gate pad having an exposed electrical connection area; and a built-in gate resistor region electrically connecting the gate wiring and the gate pad. The built-in gate resistor region includes N (N≥2) local built-in gate resistor regions connected in parallel between the gate wiring and the gate pad, each of the N local built-in gate resistor regions including M (M≥2) built-in gate resistor trenches connected in parallel between the gate wiring and the gate pad. The gate wiring has a wiring-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. The electrode pad has a pad-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. Each of the M built-in gate resistor trenches is embedded in the semiconductor substrate. K (M≥K≥2) of the M built-in gate resistor trenches function as actual built-in gate resistor trenches. Each of the K actual built-in gate resistor trenches is electrically connected to the wiring-side contact area of ​​the gate wiring via a wiring contact portion provided in a manner that penetrates the interlayer insulating film. Each of the K actual built-in gate resistor trenches is electrically connected to the pad-side contact area of ​​the gate pad via a pad contact portion provided in a manner that penetrates the interlayer insulating film. At each of the K actual built-in gate resistor trenches, a gate current path is provided between the wiring contact portion and the pad contact portion. The distance between the wiring contact portion and the pad contact portion in the gate current path is defined as the contact portion distance.

[0010] The effects of the invention

[0011] In the semiconductor device of the present invention, at each of the K practically used built-in gate resistor trenches, a gate current path is provided between a wiring contact and a pad contact, and the distance between the wiring contact and the pad contact in the gate current path is defined as the contact distance.

[0012] Therefore, the resistance value of the gate current path of each of the K actually used built-in gate resistor trenches can be adjusted by the distance between the contacts. Furthermore, by adjusting the number K of the actually used built-in gate resistor trenches, the resistance value of each of the N local built-in gate resistor regions can be adjusted.

[0013] As a result, the semiconductor device of the present invention can, based on the above-mentioned contact distance and the number K of the actual built-in gate resistor trenches used, adjust the resistance value of the built-in gate resistor region, which includes N local built-in gate resistor regions, relatively simply during manufacturing. Attached Figure Description

[0014] Figure 1 This is an explanatory diagram schematically showing the planar structure of the semiconductor device of Embodiment 1 according to a first embodiment.

[0015] Figure 2 This is an explanatory diagram schematically showing the planar structure of the second embodiment 1.

[0016] Figure 3 This is an explanatory diagram schematically showing the planar structure of the third embodiment of implementation 1.

[0017] Figure 4 It means in Figures 1-3 The cross-sectional view shows the cross-sectional structure of the IGBTs arranged in the unit area shown.

[0018] Figure 5 It is a schematic representation Figure 1 A diagram illustrating the detailed structure of the area surrounding the gate pad.

[0019] Figure 6 It is an enlarged representation Figure 5 A top view of the area surrounding the built-in gate resistor.

[0020] Figure 7 It means Figure 6 A sectional view of the cross-sectional structure at section AA.

[0021] Figure 8 This is a graph showing the resistance value dependence of the built-in gate resistor trench for the semiconductor device of Embodiment 2.

[0022] Figure 9 This is a top view showing the enlarged area surrounding the built-in gate resistor in the semiconductor device of Embodiment 3.

[0023] Figure 10 This is a top view showing the enlarged area surrounding the built-in gate resistor in relation to the semiconductor device of Embodiment 4.

[0024] Figure 11 This is a top view of the semiconductor device according to Embodiment 5, showing an enlarged view of the area surrounding the built-in gate resistor.

[0025] Figure 12 This is a top view showing the enlarged area surrounding the built-in gate resistor in the semiconductor device of Embodiment 6.

[0026] Figure 13 This is an explanatory diagram schematically showing the detailed structure of the region surrounding the gate pad in relation to the semiconductor device of Embodiment 7.

[0027] Figure 14 This is an explanatory diagram schematically showing the detailed structure of the area surrounding the gate pad in relation to the semiconductor device of Embodiment 8.

[0028] Figure 15 This is the representation involved in Implementation Method 9. Figure 6 A sectional view of the cross-sectional structure at section AA.

[0029] Figure 16 This is the representation involved in implementation method 10. Figure 6 A sectional view of the cross-sectional structure at section AA.

[0030] Figure 17 This is the representation involved in implementation method 11. Figure 6 A sectional view of the cross-sectional structure at section BB. Detailed Implementation

[0031] <Implementation Method 1>

[0032] Figures 1-3 These are explanatory diagrams schematically illustrating the planar structure of the semiconductor device according to Embodiment 1 of the present invention. Figure 1 The semiconductor device 101A shown is the first embodiment of 1. Figure 2 The semiconductor device 101B shown is the second embodiment of Embodiment 1. Figure 3 The semiconductor device 101C shown is the third embodiment of Embodiment 1. Hereinafter, when referring to semiconductor devices 101A to 101C collectively, they will sometimes be referred to simply as "semiconductor device 101".

[0033] As shown in these figures, the semiconductor device 101 includes, as a main structural element, a cell region 1, a gate wiring 3, a gate pad 4, a built-in gate resistor region 5, and an end region 6.

[0034] Except for a portion of the cell missing area, cell region 1 is rectangular with rounded corners when viewed from above. Semiconductor device 101 has an IGBT as a switching element with an insulated gate structure within cell region 1.

[0035] At once Figure 1 In the semiconductor device 101A of the first embodiment shown, in the cell-deficient region where no cell region 1 is formed, a gate wiring 3 and a gate pad peripheral region A1 are provided, extending longitudinally from the upper part of the cell region 1 to the center. The gate pad peripheral region A1 is located at the center of the lower part of the cell region 1.

[0036] At once Figure 2 In the semiconductor device 101B of the second embodiment shown, a gate pad periphery region A2 is provided in the cell missing region. The gate pad periphery region A2 is located in the lower left of the figure. Figure 3 In the semiconductor device 101C of the third embodiment shown, a gate wiring 3 and a gate pad periphery region A3 are provided in the cell missing area, which run longitudinally through the upper center and lower center respectively. The gate pad periphery region A3 is located in the center of the figure.

[0037] When viewed from above, each of the gate pad peripheral areas A1 to A3 has a gate pad 4 in the center, and an internal gate resistor area 5 is arranged to surround the outer periphery of the gate pad 4 when viewed from above. The gate wiring 3 is arranged to surround the outer periphery of the internal gate resistor area 5 when viewed from above.

[0038] In the cell region 1 of the semiconductor device 101, a configuration is provided Figures 1-3 In the IGBT 50 (not shown), within cell region 1, the gate electrode of the IGBT 50, i.e. the trench gate 2, is configured to extend laterally along the line shown in the figure.

[0039] Gate wiring 3 is also disposed in the outer peripheral region of cell region 1 and is electrically connected to trench gate 2.

[0040] The gate pad 4 has an exposed electrical connection area. Electrical connection with the outside can be achieved through this electrical connection area. As described above, an internal gate resistor region 5 is provided to surround the periphery of the gate pad 4, and the gate wiring 3 is provided to surround the internal gate resistor region 5.

[0041] The gate wiring 3 and the gate pad 4 are electrically connected via a built-in gate resistor region 5. Furthermore, the end region 6 is provided in such a manner that it surrounds the peripheral region of the gate wiring 3.

[0042] The gate wiring 3 can be disposed around the entire periphery of the cell region 1, as in semiconductor devices 101A and 101C, or it can be disposed on a portion of the outer periphery of the cell region 1, as in semiconductor device 101B. In semiconductor device 101B, it is not disposed in the peripheral area at the top of the diagram of cell region 1.

[0043] Alternatively, the gate wiring 3 can be arranged in a manner that runs longitudinally through the center of the cell region 1, as in semiconductor devices 101A and 101C.

[0044] The gate pad 4 can be arranged in the lower center of the cell region 1 as in semiconductor device 101A, in the center of the cell region 1 as in semiconductor device 101C, or in the lower left corner of the cell region 1 as in semiconductor device 101B.

[0045] Figure 4 This is a cross-sectional view showing the cross-sectional structure of the IGBT 50 located in cell region 1.

[0046] like Figure 4 As shown, the semiconductor substrate 11 extends from top to bottom from the drift layer 21 containing the base layer 22 to the collector layer 26. Furthermore, the base layer 22 includes an emitter layer 23 and a contact layer 24 formed on the upper layer.

[0047] exist Figure 4 In this paper, the upper end of the drift layer 21 containing the base layer 22 is referred to as the first main surface of the semiconductor substrate 11, and the lower end of the collector layer 26 is referred to as the second main surface of the semiconductor substrate 11. The first main surface of the semiconductor substrate 11 is the main surface on the surface side of the semiconductor device 101, and the second main surface of the semiconductor substrate 11 is the main surface on the back side of the semiconductor device 101.

[0048] As described above, the semiconductor substrate 11 includes a drift layer 21, a buffer layer 25, and a collector layer 26.

[0049] A buffer layer 25 is disposed adjacent to the second main surface of the first conductivity type, i.e., n-type, drift layer 21. The buffer layer 25 has an n-type impurity concentration that is higher than that of the drift layer 21. + type.

[0050] A collector layer 26 is disposed adjacent to the second main surface of the buffer layer 25. The collector layer 26 exhibits a second conductivity type, i.e., p-type, with a relatively high impurity concentration. + Type. A collector electrode 28 is provided on the second main surface of the collector layer 26.

[0051] A base layer 22 is disposed on the first main surface side within the drift layer 21. The base layer 22 exhibits a second conductivity type, namely p-type.

[0052] Multiple trench gates 2 are formed, extending from the first main surface of the semiconductor substrate 11 through the emitter layer 23 and the base layer 22 to the drift layer 21. The multiple trench gates 2 are configured such that a buried gate electrode 2b is provided as a buried gate electrode through a gate insulating film 2a that serves as a gate trench insulating film.

[0053] Multiple n are arranged on the first principal surface side within the base layer 22. +Emitter layers 23 of the type. Each of the plurality of emitter layers 23 is configured to be adjacent to the corresponding trench gate 2 in the plurality of trench gates 2.

[0054] Between adjacent buried gate electrodes 2b, 2b, a p is provided on the first main surface side within the base layer 22. + The contact layer 24 is configured to contact each of a pair of emitter layers 23 present on both sides. Furthermore, the emitter layers 23 and the contact layer 24 may be formed alternately along the extension direction of the trench gate 2.

[0055] Furthermore, an interlayer insulating film 10 is disposed on the first main surface of the plurality of trench gates 2.

[0056] The emitter electrode 27 is disposed over the entire area of ​​the first main surface of the semiconductor substrate 11, separated by the interlayer insulating film 10. Therefore, the emitter electrode 27 is electrically connected to the emitter layer 23 and the contact layer 24.

[0057] The IGBT 50 is constructed primarily from the trench gate 2, drift layer 21, base layer 22, emitter layer 23, contact layer 24, buffer layer 25, collector layer 26, emitter electrode 27, and collector electrode 28 described above. Figure 4 In the configuration shown, IGBT 50 is an n-channel IGBT, which becomes a switching element with an insulated gate structure.

[0058] also, Figures 1-3 The trench gate 2 shown refers more precisely to the buried gate electrode 2b.

[0059] Figure 5 This is an explanatory diagram schematically showing the detailed structure of the gate pad periphery region A1. Furthermore, the detailed structures of the gate pad periphery regions A2 and A3 are the same as those of the gate pad periphery region A1. The following explanation uses the gate pad periphery region A1 as an example.

[0060] As shown in the figure, the gate pad 4 has a centrally located main pad area 4M and four pad-side contact areas 40 extending from the main pad area 4M toward the gate wiring 3.

[0061] When viewed from above, the main area 4M of the pads is rectangular, becoming the exposed electrical connection area on the surface. Electrical connections with the outside can be made through the main area 4M of the pads.

[0062] As shown in the figure, the gate wiring 3 has an outer peripheral wiring region 3P disposed along the outer periphery of the gate pad 4, and four wiring-side contact regions 30 disposed extending from the outer peripheral wiring region 3P toward the gate pad 4. The four wiring-side contact regions 30 correspond one-to-one with the four pad-side contact regions 40.

[0063] Built-in gate resistor units 7 are provided between the corresponding wiring-side contact areas 30 and pad-side contact areas 40 in the four wiring-side contact areas 30 and four pad-side contact areas 40. Therefore, the four built-in gate resistor units 7 are provided in a one-to-one correspondence with the four wiring-side contact areas 30 and four pad-side contact areas 40. The built-in gate resistor units 7 electrically connect the corresponding wiring-side contact areas 30 and pad-side contact areas 40.

[0064] Four built-in gate resistor units 7 function as N (N≥2) local built-in gate resistor regions, positioned opposite the four edges of the main pad region 4M when viewed from above, and are classified as the 1st to 4th local built-in gate resistor regions. In Embodiment 1, this is {N=4}.

[0065] In embodiment 1, the four built-in gate resistor units 7 have the same resistance value R0. Alternatively, some of the resistance values ​​of the four built-in gate resistor units 7 can be set to different values.

[0066] Figure 6 It is an enlarged representation Figure 5 Top view of the area B1 surrounding the built-in gate resistor. Figure 7 It means Figure 6 A sectional view of the cross-sectional structure at section AA. Figure 6 and Figure 7 Each has its own XYZ orthogonal coordinate system.

[0067] As shown in these figures, at the gate pad 4, a pad-side contact area 40 is provided extending from the main pad area 4M in the -Y direction, and at the gate wiring 3, a wiring-side contact area 30 is provided extending from the outer peripheral wiring area 3P in the +Y direction. The pad-side contact area 40 and the wiring-side contact area 30 are configured to not overlap when viewed from above.

[0068] In the case of the semiconductor device 101 of Embodiment 1, since a wiring-side contact area 30 is provided outside the peripheral wiring area 3P and a pad-side contact area 40 is provided outside the pad main area 4M, the pad wiring distance Wm between the gate wiring 3 and the gate pad 4 is relatively short.

[0069] When viewed from above, four built-in gate resistor trenches 8 are provided from the pad-side contact area 40 to the wiring-side contact area 30. Each of the four built-in gate resistor trenches 8 is rectangular when viewed from above, with a long side extending in the X direction and a short side extending in the Y direction.

[0070] like Figure 6As shown, the four built-in gate resistor trenches 8 have the same shape, and each built-in gate resistor trench 8 has a constant resistor trench width Wr in the short side direction. A portion of the four built-in gate resistor trenches 8 overlaps with the pad-side contact area 40 when viewed from above, and another portion overlaps with the wiring-side contact area 30 when viewed from above.

[0071] As described above, the gate wiring 3 has a wiring-side contact area 30 that overlaps with M (M≥2) built-in gate resistor trenches 8 when viewed from above, and the gate pad 4 has a pad-side contact area 40 that overlaps with M built-in gate resistor trenches 8 when viewed from above. Figure 6 In the example shown, {M = 4}.

[0072] like Figure 7 As shown, the built-in gate resistor trench 8 is embedded in the first conductivity type, i.e., n-type, semiconductor substrate 11, and includes a trench insulating film 8a and a trench electrode 8b as its main structural elements. For ease of explanation, as... Figure 7 The semiconductor substrate 11 shown only has a similar appearance to... Figure 4 The region corresponding to the drift layer 21 shown.

[0073] Furthermore, parameters such as the resistor trench width Wr and the contact distance Lr related to the built-in gate resistor trench 8 are, more precisely, parameters related to the trench electrode 8b, which constitutes the resistive component. Specifically, the resistor trench width Wr is more precisely the width of the trench electrode 8b, and the contact distance Lr is more precisely the distance between the pad contact 9P and the wiring contact 9L at the trench electrode 8b.

[0074] The trench electrode 8b has a resistive trench depth Dr, and a trench insulating film 8a is disposed to cover the entire circumference of the trench electrode 8b. Therefore, the trench electrode 8b is not electrically connected to the semiconductor substrate 11.

[0075] The electrical connection of the built-in gate resistor trench 8 is made precisely by the trench electrode 8b, which is a resistive component, within the built-in gate resistor trench 8. In this specification, for ease of explanation, it is sometimes described as "the electrical connection of the built-in gate resistor trench 8".

[0076] like Figure 7 As shown, an interlayer insulating film 10 is disposed on the first main surface of a semiconductor substrate 11 containing a trench gate 2, and gate wiring 3 and gate pad 4 are disposed on the interlayer insulating film 10.

[0077] In addition, Figure 6 The interlayer insulating film 10 is omitted from the illustration. Furthermore, to clearly show the shape of the four built-in gate resistor trenches 8 and the position of the built-in gate resistor contacts 9, [the following is omitted]. Figure 6The diagram omits a portion of the wiring-side contact area 30 and a portion of the pad-side contact area 40 that exist above the four built-in gate resistor trenches 8.

[0078] exist Figure 6 In the configuration shown, all four built-in gate resistor trenches 8 function as actual built-in gate resistor trenches. That is, K (M≥K≥2) of the M built-in gate resistor trenches 8 become actual built-in gate resistor trenches. In Embodiment 1, this is {K=M=4}.

[0079] like Figure 6 and Figure 7 As shown, one end of the -X side of each of the four built-in gate resistor trenches 8 is electrically connected to the wiring side contact area 30 of the gate wiring 3 via a wiring contact 9L provided in such a way that the interlayer insulating film 10 passes through.

[0080] The other end of the +X side of each of the four built-in gate resistor trenches 8 is electrically connected to the pad-side contact area 40 of the gate pad 4 via a pad contact 9P provided in such a way that the interlayer insulating film 10 passes through.

[0081] Hereinafter, when referring to the wiring contact 9L and the pad contact 9P collectively, it is sometimes called the "built-in gate resistor contact 9". That is, the built-in gate resistor contact 9 includes the wiring contact 9L and the pad contact 9P.

[0082] Therefore, at each of the four built-in gate resistor trenches 8 that function as built-in gate resistor trenches in actual use, a gate current path is provided between the pad contact portion 9P and the wiring contact portion 9L, and the distance between the wiring contact portion 9L and the pad contact portion 9P in the gate current path is defined as the contact distance Lr.

[0083] Therefore, the resistance value R0 of one unit of built-in gate resistor 7 has the characteristic of satisfying the following equation (1) using the above parameters {Lr, K, Wr, Dr}. Furthermore, in Embodiment 1, the resistor trench width Wr is assumed to be constant in the depth direction.

[0084] R0∝Lr / (K×Sr)…(1)

[0085] Furthermore, in equation (1), {Sr=Wr×Dr}, where Sr is the cross-sectional area on the YZ plane.

[0086] In Implementation 1, the trench electrode 8b is assumed to be a cuboid structure, the cross-section on the YZ plane is rectangular, and the cross-sectional area Sr is the area of ​​the rectangle.

[0087] Here, the actual number K of the built-in gate resistor trenches used can be adjusted during manufacturing within the range of {1 to M}, depending on whether the built-in gate resistor contact 9 is present. For example, in one of the four built-in gate resistor trenches 8, by omitting the electrical connection to the gate wiring 3 and the gate pad 4 made by the built-in gate resistor contact 9, the actual number K of the built-in gate resistor trenches used can be set to "3".

[0088] Specifically, by changing the patterned mask used to form the built-in gate resistor contact 9, it is possible to prevent the built-in gate resistor contact 9 from being formed at one built-in gate resistor trench 8.

[0089] In addition, the distance Lr between the contacts can be changed relatively easily by changing the configuration of at least one of the wiring contact 9L and the pad contact 9P.

[0090] Specifically, by changing the patterned mask used to form the built-in gate resistor contact 9, the formation position of the built-in gate resistor contact 9, which is electrically connected to the four built-in gate resistor trenches 8, can be changed.

[0091] As described above, when manufacturing the semiconductor device 101, by changing the number K of the built-in gate resistor trenches actually used and the distance Lr between the contacts, the resistance value R0 of one unit of built-in gate resistor unit 7 can be adjusted relatively easily.

[0092] Furthermore, the interlayer insulating film 10 is a CVD (Chemical Vapor Deposition) film such as BPSG (Boron Phospho Silicate Glass) film or TEOS (tetraethylorthosilicate) oxide film, which differs from thermally oxidized films such as silicon oxide films formed by thermal oxidation. In addition, CVD films refer to films formed by CVD methods, while thermally oxidized films refer to oxide films formed by thermal oxidation. Other CVD films that come to mind include BPSG (Boron-Phospho Tetraethylorthosilicate) oxide films, PSG (Phospho Silicate Glass) films, alumina (Al2O3), and hafnium oxide (HfO2).

[0093] When the interlayer insulating film 10 is set as a thermal oxide film, there is a risk that the resistance value R0 of the built-in gate resistor unit 7 will change due to the stress caused by the relatively thick thermal oxide film.

[0094] In Embodiment 1, the interlayer insulating film 10 is a CVD film. When both the CVD film and the thermally oxidized film are formed with the same thickness, the CVD film exhibits stress suppression characteristics, such as lower stress affecting the peripheral region containing the semiconductor substrate 11 and the trench gate 2 compared to the thermally oxidized film. Therefore, in Embodiment 1, by forming a relatively thin CVD film of approximately 0.1 μm to 0.8 μm as the interlayer insulating film 10, the stress caused by the interlayer insulating film 10 is reduced, thus suppressing variations in the resistance value R0 of the built-in gate resistor unit 7.

[0095] Furthermore, the built-in gate resistor contact 9 can be formed by embedding a W plug or the like, or by embedding the metal that forms the gate wiring 3 and the gate pad 4. Additionally, AlSi, AlSiC, etc., are considered as the metal that forms the gate wiring 3 and the gate pad 4.

[0096] Furthermore, to improve the embeddability of the built-in gate resistor contact 9, a tapered surface that slopes inwards towards the lower side can be provided in the built-in gate resistor contact 9. Moreover, since the contact resistance between the built-in gate resistor contact 9 and the trench electrode 8b of the built-in gate resistor trench 8 is sufficiently small, the presence or absence of the tapered surface of the built-in gate resistor contact 9 will not affect the resistance value of each built-in gate resistor trench 8.

[0097] As described above, a trench insulating film 8a is provided on the inner wall of the built-in gate resistor trench 8, and a trench electrode 8b is provided across the trench insulating film 8a, which is opposite to the semiconductor substrate 11 of the first conductivity type.

[0098] The trench insulating film 8a can be a thermally oxidized film or a CVD film. The trench electrode 8b is polycrystalline silicon with added impurities, and the added impurities can be greater than or equal to 1×10⁻⁶. 18 cm -2 Impurities such as phosphorus are considered as added materials, and doped polysilicon is considered as an example of polysilicon.

[0099] By forming the trench electrode 8b with doped polysilicon, the contact resistance between the gate wiring 3, the gate pad 4 and the trench electrode 8b can be reduced.

[0100] Thus, the built-in gate resistor region 5 of the semiconductor device 101 in Embodiment 1 has four built-in gate resistor units 7. The four built-in gate resistor units 7 function as N (N≥2) local built-in gate resistor regions connected in parallel between the gate wiring 3 and the gate pad 4. In Embodiment 1, this is {N=4}.

[0101] Furthermore, each of the four built-in gate resistor units 7 includes four built-in gate resistor trenches 8. The four built-in gate resistor trenches are M (M≥2) built-in gate resistor trenches 8 connected in parallel between the gate wiring 3 and the gate pad 4. In Embodiment 1, this is {M=4}.

[0102] Of the four built-in gate resistor trenches 8, K (M≥K≥2) serve as the actual built-in gate resistor trenches. In Implementation 1, this is {K=M=4}.

[0103] In the semiconductor device 101 of Embodiment 1, each of the four built-in gate resistor units 7 included in the built-in gate resistor region 5 has four built-in gate resistor trenches 8. All four built-in gate resistor trenches 8 function as actual built-in gate resistor trenches.

[0104] Each of the four built-in gate resistor trenches 8 is electrically connected to the gate wiring 3 via wiring contact 9L, and is electrically connected to the gate pad 4 via pad contact 9P.

[0105] Furthermore, at each of the four built-in gate resistor trenches 8, a gate current path is provided between the wiring contact 9L and the pad contact 9P, and the distance between the wiring contact 9L and the pad contact 9P in the gate current path is defined as the contact distance Lr.

[0106] Therefore, in the semiconductor device 101 of Embodiment 1, the resistance value R0 of one unit of built-in gate resistor unit 7 is determined by the above formula (1), so the resistance value R0 can be adjusted during manufacturing by the number of parallel built-in gate resistor trenches K and the distance between contacts Lr.

[0107] In addition, the resistance value of the built-in gate resistor region 5 is the combined resistance value of the four built-in gate resistor units 7.

[0108] As a result, the semiconductor device of Embodiment 1 can adjust the resistance value of the built-in gate resistor region 5 relatively easily during manufacturing based on the actual number K of the built-in gate resistor trenches and the contact distance Lr.

[0109] In addition, the interlayer insulating film 10 of the semiconductor device 101 is a CVD film comprising at least one of TEOS oxide film, BPTEOS oxide film, PSG film, BPSG film, aluminum oxide and hafnium oxide. The CVD film has the above-mentioned stress suppression characteristics and can be formed with a relatively thin film thickness of about 0.1 μm to 0.8 μm.

[0110] Therefore, the stress around the four built-in gate resistor trenches 8 caused by the interlayer insulating film 10 can be alleviated, and the variation in the resistance characteristics of the four built-in gate resistor trenches 8 can be suppressed.

[0111] Furthermore, the built-in gate resistor region 5 of the semiconductor device 101 in Embodiment 1 includes four built-in gate resistor units 7 arranged such that they are opposite to the four sides of the rectangular pad main region 4M when viewed from above.

[0112] Since each of the four built-in gate resistor units 7 is positioned opposite the four sides of the main pad area 4M when viewed from above, the formation length of the four built-in gate resistor trenches 8 contained in each built-in gate resistor unit 7 can be set to be relatively long. Therefore, the distance Lr between the contacts of each of the four built-in gate resistor trenches 8 can be set to a length sufficient to obtain the desired resistance value.

[0113] Therefore, the semiconductor device 101 of Embodiment 1 can be relatively easily configured with four built-in gate resistor units 7, each having an intended resistance value.

[0114] <Implementation Method 2>

[0115] Figure 8 This is a graph showing the dependence of the resistance value of the built-in gate resistor trench 8, which functions as a built-in gate resistor trench in actual use. In this graph, the horizontal axis represents the contact distance Lr (μm), and the vertical axis represents the resistance value (au; arbitrary unit) of each built-in gate resistor trench 8.

[0116] As shown in the figure, the resistance value R8 of each built-in gate resistor trench 8 fluctuates depending on the distance Lr between the contacts and the number of parallel connections K.

[0117] On the other hand, if the number K of the actual number of parallel built-in gate resistor trenches in each built-in gate resistor unit 7 is set to be greater than or equal to 3, and the distance Lr between the contacts is set to be greater than or equal to 100 μm, then as shown in the region of interest Z1, the resistance value R8 of each built-in gate resistor trench 8 is stable at a constant value.

[0118] according to Figure 8 It can be seen that at each of the built-in gate resistor units 7, if the condition "the number K is greater than or equal to 3 and the distance between the contacts Lr is greater than or equal to 100μm" is met, then the resistance value R8 of each built-in gate resistor trench 8 has the same Lr dependence, and the resistance value R8 is stable at a constant value.

[0119] The semiconductor device 102 of Embodiment 2 is presented with Figures 1 to 7The same structure as the embodiment 1 shown is characterized by satisfying the following conditions (1) and (2).

[0120] Condition (1)... At each built-in gate resistor unit 7, the number K of the parallel connection of the built-in gate resistor trenches 8 that actually function as built-in gate resistor trenches is greater than or equal to 3.

[0121] Condition (2)... The contact distance Lr of the built-in gate resistor trench 8, which functions as a built-in gate resistor trench in actual use, is greater than or equal to 100 μm.

[0122] The semiconductor device 102 of Embodiment 2 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0123] The semiconductor device 102 of Embodiment 2, which satisfies the above conditions (1) and (2), can reliably adjust the resistance value R8 of the built-in gate resistor trench 8, which functions as a built-in gate resistor trench in actual use.

[0124] <Implementation Method 3>

[0125] The overall structure of the semiconductor device 103 in Embodiment 3 is similar to Figures 1-4 The implementation method shown is the same as that of embodiment 1, and the structure of the area A1 surrounding the gate pad is also the same. Figure 5 The implementation method shown is the same as Implementation 1. However, Figure 5 The structure of the built-in gate resistor in the surrounding region B1 and Figure 6 The construction of the embodiment 1 shown is different.

[0126] Figure 9 This refers to the semiconductor device 103 in Embodiment 3, shown in an enlarged view. Figure 5 A top view of the region B1 surrounding the built-in gate resistor is shown. Furthermore, Figure 7 It means Figure 9 A sectional view of the cross-section at the CC section. Figure 9 The document contains an XYZ orthogonal coordinate system.

[0127] Below, regarding Figure 6 The same structures as those in Embodiment 1 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the features of Embodiment 3.

[0128] Regarding the semiconductor device 103, similar to Embodiment 1, the gate wiring 3 has a wiring-side contact area 30 that overlaps with the M built-in gate resistor trenches 8 when viewed from above, and the gate pad 4 has a pad-side contact area 40 that overlaps with the M built-in gate resistor trenches 8 when viewed from above. Figure 9 In the example shown, {M = 4}.

[0129] like Figure 9 As shown, the four built-in gate resistor trenches 8 have the same shape. That is, each of the four built-in gate resistor trenches 8, when viewed from above, is a rectangle with the X direction (which is the first direction) as its long side and the Y direction (which is the second direction) as its short side, with the Y direction intersecting the X direction perpendicularly.

[0130] The four built-in gate resistor trenches 8 are classified as the first to fourth built-in gate resistor trenches arranged in the order of 1st, 2nd, 3rd, and 4th along the Y direction. That is, from Figure 9 From top to bottom, the four built-in gate resistor trenches are classified as the first to the fourth built-in gate resistor trenches.

[0131] One of the four built-in gate resistor trenches 8 is an unused built-in gate resistor trench 8X. Specifically, the third built-in gate resistor trench is an unused built-in gate resistor trench 8X, while the first, second, and fourth built-in gate resistor trenches are actually used built-in gate resistor trenches.

[0132] Therefore, the first and fourth built-in gate resistor trenches at both ends in the Y direction are not built-in gate resistor trenches 8X.

[0133] As described above, in embodiment 3, at least one of the M built-in gate resistor trenches is a non-built-in gate resistor trench, and the first built-in gate resistor trench and the Mth built-in gate resistor trench are not at least one non-built-in gate resistor trench.

[0134] In implementation 3, the number of at least one trench that does not use a built-in gate resistor is "1", which is {M=4}.

[0135] Since there is no built-in gate resistor contact portion 9 that overlaps with the unused built-in gate resistor trench 8X when viewed from above, the unused built-in gate resistor trench 8X is not electrically connected to the gate wiring 3 and the gate pad.

[0136] Therefore, in Figure 9 In the illustrated configuration, three of the four built-in gate resistor trenches 8, excluding the unused built-in gate resistor trench 8X, function as actually used built-in gate resistor trenches. That is, K (M≥K≥2) of the M built-in gate resistor trenches 8 function as actually used built-in gate resistor trenches. In Embodiment 3, since {K=3}, the relationship becomes {M>K}.

[0137] like Figure 9 and Figure 7As shown, one end of each of the three built-in gate resistor trenches 8 (excluding the one that does not use built-in gate resistor trenches 8X) is electrically connected to the pad-side contact area 40 of the gate pad 4 via a pad contact portion 9P provided in such a way that the interlayer insulating film 10 passes through.

[0138] The other end of each of the three built-in gate resistor trenches 8 is electrically connected to the wiring side contact area 30 of the gate wiring 3 via a wiring contact 9L provided in such a way that the interlayer insulating film 10 passes through.

[0139] Therefore, at each of the three built-in gate resistor trenches 8, a gate current path is provided between the pad contact portion 9P and the wiring contact portion 9L, and the distance between the wiring contact portion 9L and the pad contact portion 9P in the gate current path is defined as the contact distance Lr.

[0140] The semiconductor device 103 of Embodiment 3 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0141] In the case of the semiconductor device 103 of Embodiment 3, by providing at least one non-used built-in gate resistor trench 8X, a difference greater than or equal to "1" can be set between the number K of actually used built-in gate resistor trenches and the total number M of built-in gate resistor trenches 8.

[0142] By omitting the formation of the wiring contact 9L and the pad contact 9P, it is relatively easy to achieve the function of not using the built-in gate resistor trench 8X.

[0143] By reducing the number K of the actual built-in gate resistor trenches used, that is, the number K of the actual built-in gate resistor trenches in parallel, it is relatively easy to increase the resistance value R0 of the built-in gate resistor unit 7, which becomes a local built-in gate resistor region.

[0144] As a result, the semiconductor device 103 of Embodiment 3 can relatively easily increase the resistance value of the built-in gate resistor region 5, which includes four built-in gate resistor units 7.

[0145] <Implementation Method 4>

[0146] The overall structure of the semiconductor device 104 in Embodiment 4 is similar to Figures 1-4 The implementation method shown is the same as that of embodiment 1, and the structure of the area A1 surrounding the gate pad is also the same. Figure 5 The implementation method shown is the same as Implementation 1. However, Figure 5 The structure of the built-in gate resistor in the surrounding region B1 and Figure 6 The construction of the embodiment 1 shown is different.

[0147] Figure 10 This refers to the semiconductor device 104 in Embodiment 4, shown in an enlarged view. Figure 5 A top view of the region B1 surrounding the built-in gate resistor. Figure 10 The document contains an XYZ orthogonal coordinate system.

[0148] Below, regarding Figure 6 The same structures as those in Embodiment 1 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the features of Embodiment 4.

[0149] In embodiment 4, the gate wiring 3B has a different shape than the gate wiring 3 in embodiment 1, and the gate pad 4B has a different shape than the gate pad 4 in embodiment 1.

[0150] like Figure 10 As shown, at the gate pad 4B, two pad-side contact areas 41 and 42 are provided in such a way that they extend from the main pad area 4M in the -Y direction. At the gate wiring 3, two wiring-side contact areas 31 and 32 are provided in such a way that they extend from the outer peripheral wiring area 3P in the +Y direction.

[0151] Thus, in embodiment 4, the wiring-side contact area 30 includes two wiring-side contact areas 31 and 32, and the pad-side contact area 40 includes two pad-side contact areas 41 and 42. The pad-side contact areas 41 and 42 are multiple pad-side contact areas, and the wiring-side contact areas 31 and 32 are multiple wiring-side contact areas.

[0152] Multiple wiring-side contact areas, namely wiring-side contact areas 31 and 32, each overlap with a portion of the M built-in gate resistor trenches 8 when viewed from above. Multiple pad-side contact areas, namely pad-side contact areas 41 and 42, each overlap with a portion of the M built-in gate resistor trenches 8 when viewed from above. Figure 10 In the example shown, {M = 4}.

[0153] like Figure 10 As shown, the four built-in gate resistor trenches 8 have the same shape. That is, each of the four built-in gate resistor trenches 8, when viewed from above, is a rectangle with the X direction (which is the first direction) as its long side and the Y direction (which is the second direction) as its short side, with the Y direction intersecting the X direction perpendicularly.

[0154] The pad-side contact areas 41 and 42 and the wiring-side contact areas 31 and 32 are arranged along the +X direction in the order of pad-side contact area 41, wiring-side contact area 31, pad-side contact area 42, and wiring-side contact area 32, without overlapping when viewed from above. That is, multiple pad-side contact areas and multiple wiring-side contact areas are alternately arranged along the formation direction of the built-in gate resistor trench 8, i.e., the X direction.

[0155] exist Figure 10 In the configuration shown, all four built-in gate resistor trenches 8 function as actual built-in gate resistor trenches. That is, K (M≥K≥2) of the M built-in gate resistor trenches 8 function as actual built-in gate resistor trenches. In embodiment 4, this is {K=M=4}.

[0156] like Figure 10 As shown, each of the four built-in gate resistor trenches 8 is electrically connected to the wiring-side contact area 31 via a wiring contact 9L1, and to the wiring-side contact area 32 via a wiring contact 9L2. Therefore, wiring contacts 9L1 and 9L2 correspond one-to-one with wiring-side contact areas 31 and 32. Wiring contacts 9L1 and 9L2 constitute multiple wiring contacts.

[0157] Similarly, each of the four built-in gate resistor trenches 8 is electrically connected to the pad-side contact area 41 via a pad contact portion 9P1, and to the pad-side contact area 42 via a pad contact portion 9P2. Therefore, the pad contacts 9P1 and 9P2 correspond one-to-one with the pad-side contact areas 41 and 42. The pad contacts 9P1 and 9P2 are multiple pad contacts.

[0158] The pad contact portions 9P1 and 9P2 and the wiring contact portions 9L1 and 9L2 are discretely arranged along the +X direction in the order of pad contact portion 9P1, wiring contact portion 9L1, pad contact portion 9P2 and wiring contact portion 9L2.

[0159] Therefore, at each of the four built-in gate resistor trenches 8, a first local gate current path is provided between the pad contact 9P1 and the wiring contact 9L1. Similarly, a second local gate current path is provided between the wiring contact 9L1 and the pad contact 9P2, and a third local gate current path is provided between the pad contact 9P2 and the wiring contact 9L2.

[0160] As described above, at each built-in gate resistor trench 8, the gate current path includes the first to third local gate current paths connected in parallel between the gate wiring 3B and the gate pad 4B as multiple local gate current paths.

[0161] As described above, multiple local gate current paths are each disposed between one of the built-in gate wiring contacts in pad contacts 9P1 and 9P2 and one of the built-in gate pad contacts in wiring contacts 9L1 and 9L2.

[0162] Furthermore, the distance between the wiring contact 9L1 and the pad contact 9P1 in the first local gate current path is defined as the contact distance Lr1. The distance between the wiring contact 9L1 and the pad contact 9P2 in the second local gate current path is defined as the contact distance Lr2. The distance between the wiring contact 9L2 and the pad contact 9P2 in the third local gate current path is defined as the contact distance Lr3. The contact distances Lr1 to Lr3 can all be set to the same value, or different distances can be set between Lr1 and Lr3.

[0163] The semiconductor device 104 of Embodiment 4 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0164] In the case of the semiconductor device 104 of Embodiment 4, each of the four built-in gate resistor trenches 8 that function as built-in gate resistor trenches in actual use includes a first to a third local gate current path that is connected in parallel between the gate wiring 3B and the gate pad 4B.

[0165] By providing first to third local gate current paths that are connected in parallel in each of the four built-in gate resistor trenches 8, the actual number of built-in gate resistor trenches actually used in a single built-in gate resistor unit 7 can be increased from "K" to "3×K". Therefore, the resistance value R0 of the built-in gate resistor unit 7 containing four built-in gate resistor trenches 8 is smaller than the resistance value when the number of parallel trenches is "K".

[0166] In addition, assuming that the formation length of each of the four built-in gate resistor trenches 8 in the X direction is the same as in Embodiment 1, the contact distances Lr1 to Lr3 are each shorter than the contact distance Lr.

[0167] Therefore, the semiconductor device 104 of embodiment 4 can be manufactured in a relatively simple way to reduce the resistance value of the built-in gate resistor region 5.

[0168] <Implementation Method 5>

[0169] The overall structure of the semiconductor device 105 in Embodiment 5 is similar to Figures 1-4 The implementation method shown is the same as that of embodiment 1. The structure of the area A1 surrounding the gate pad is also roughly the same. Figure 5 The implementation method shown is the same as Implementation 1. However, Figure 5 The structure of the built-in gate resistor in the surrounding region B1 and Figure 6 The construction of the embodiment 1 shown is different.

[0170] Figure 11 This refers to the semiconductor device 105 in Embodiment 5, shown in an enlarged view. Figure 5 A top view of the region B1 surrounding the built-in gate resistor. Figure 11 The document contains an XYZ orthogonal coordinate system.

[0171] Below, regarding Figure 6 The same structures as those in Embodiment 1 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the features of Embodiment 5.

[0172] In embodiment 5, the gate wiring 3C has a different shape than the gate wiring 3 in embodiment 1, and the gate pad 4C has a different shape than the gate pad 4 in embodiment 1.

[0173] like Figure 11 As shown, at the gate pad 4C, a pad-side contact area 40I is provided along the X direction within the main pad area 4M, and at the gate wiring 3C, a wiring-side contact area 30I is provided along the X direction within the outer peripheral wiring area 3P.

[0174] Thus, both the wiring-side contact area 30I and the pad-side contact area 40I are positioned along the contact area formation direction, i.e., the X direction. That is, the contact area formation direction is consistent with the formation length direction of the gate wiring 3C and the gate pad 4C, i.e., the X direction.

[0175] The wiring-side contact area 30I and the pad-side contact area 40I are configured to be separated by a pad-to-wiring distance Wm in the Y direction, which is an opposite direction to each other. The Y direction intersects the X direction perpendicularly.

[0176] When viewed from above, the pad-side contact area 40I overlaps with one end of the +Y direction side of each of the M built-in gate resistor trenches 85, and the wiring-side contact area 30I overlaps with the other end of the -Y direction side of each of the M built-in gate resistor trenches 85. Figure 11 In the example shown, {M = 3}.

[0177] Each of the three built-in gate resistor trenches 85 is the same as the built-in gate resistor trench 8 in Embodiment 1, including a trench insulating film 8a and a trench electrode 8b as the main structural elements.

[0178] exist Figure 11 In the illustrated configuration, all three built-in gate resistor trenches 85 function as actual built-in gate resistor trenches. That is, K (M ≥ K ≥ 2) of the M built-in gate resistor trenches 85 function as actual built-in gate resistor trenches. Figure 11 In the example shown, {K=M=3}.

[0179] Each of the three built-in gate resistor trenches 85, which function as built-in gate resistor trenches in actual use, has a first forming region extending in the X direction and a second forming region extending in the Y direction, which are partially bent when viewed from above.

[0180] like Figure 11 As shown, one end of each of the three built-in gate resistor trenches 85 is electrically connected to the pad-side contact area 40I via the pad contact portion 9P. The other end of each of the three built-in gate resistor trenches 85 is electrically connected to the pad-side contact area 40I via the wiring contact portion 9L.

[0181] Therefore, at each of the three built-in gate resistor trenches 85, a curved gate current path is provided between the pad contact 9P and the wiring contact 9L.

[0182] The resistance trench width Wr of each of the three built-in gate resistor trenches 85 is set to be the same. The resistance trench width Wr of each built-in gate resistor trench 85 is also a constant value between the regions before and after bending. Furthermore, the contact distance Lr between the bent pad contact portion 9P and the wiring contact portion 9L of each of the three built-in gate resistor trenches 85 is also set to be the same. The distance between the wiring contact portion 9L and the pad contact portion 9P in the gate current path is defined as the contact distance Lr.

[0183] The semiconductor device 105 of Embodiment 5 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0184] In the semiconductor device 105 of embodiment 5, the wiring side contact area 30I and the pad side contact area 40I are arranged to be separated by a pad wiring distance Wm in the Y direction, which is an opposing direction, so that the pad wiring distance Wm can be set to be relatively long.

[0185] The reason is that the wiring-side contact area 30I is located within the outer peripheral wiring area 3P, and the pad-side contact area 40I is located within the main pad area 4M. According to... Figure 6 The pad wiring distance Wm shown in Embodiment 1 is... Figure 11 This can be clearly seen from the comparison of the pad wiring distance Wm in Embodiment 5 shown.

[0186] Therefore, the semiconductor device 105 of Embodiment 5 can effectively suppress short circuits caused by fluctuations in the manufacturing process that result in electrical connections between the gate wiring 3C and the gate pad 4C.

[0187] Furthermore, since each of the three built-in gate resistor trenches 85, which function as built-in gate resistor trenches in actual use, has a first forming region along the X direction and a second forming region along the Y direction, it is possible to ensure that the contact distance Lr can be set to the length of the intended resistance value.

[0188] Furthermore, regarding the semiconductor device 105, by setting the distance Wm between the pads and wirings to be sufficiently long, the embedding properties of the encapsulation material can be improved when encapsulating the gate pad 4C and gate wiring 3C of the semiconductor device 105 with encapsulation materials such as resin and gel.

[0189] Alternatively, the three built-in gate resistor trenches 85 can each be configured in a meandering shape, or the intermediate region can be positioned below the non-contact area of ​​the gate wiring 3C or the gate pad 4C. Furthermore, the intermediate region of the built-in gate resistor trench 85 refers to the area where the built-in gate resistor contact portion 9 is not formed, and the non-contact area refers to the area of ​​the gate wiring 3C other than the wiring-side contact area 30I, or the area of ​​the gate pad 4C other than the pad-side contact area 40I.

[0190] <Implementation Method 6>

[0191] The overall structure of the semiconductor device 106 in Embodiment 6 is similar to Figures 1-4 The implementation method shown is the same as that of embodiment 1. The structure of the area A1 surrounding the gate pad is also roughly the same. Figure 5 The implementation method shown is the same as Implementation 1. However, Figure 5 The structure of the built-in gate resistor in the surrounding region B1 and Figure 6 The construction of the embodiment 1 shown is different.

[0192] Figure 12 This refers to the semiconductor device 106 in Embodiment 6, shown in an enlarged view. Figure 5 A top view of the region B1 surrounding the built-in gate resistor. Figure 12 The document contains an XYZ orthogonal coordinate system.

[0193] Below, regarding Figure 6 Implementation method 1 shown Figure 11 The same structures as those in Embodiment 5 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the features of Embodiment 6.

[0194] like Figure 12 As shown, at the gate pad 4C, a pad-side contact area 40I is provided along the X direction within the main pad area 4M, and at the gate wiring 3C, a wiring-side contact area 30I is provided along the X direction within the outer peripheral wiring area 3P.

[0195] Thus, both the wiring-side contact area 30I and the pad-side contact area 40I are set along the contact area formation direction, i.e., the X direction.

[0196] The wiring-side contact area 30I and the pad-side contact area 40I are configured to be separated by a pad-to-wiring distance Wm in the Y direction, which is an opposite direction to each other. The Y direction intersects the X direction perpendicularly.

[0197] When viewed from above, the pad-side contact area 40I overlaps with one end of the +Y direction side of each of the M built-in gate resistor trenches 86, and the wiring-side contact area 30I overlaps with the other end of the -Y direction side of each of the M built-in gate resistor trenches 86. Figure 12 In the example shown, {M = 3}.

[0198] Each of the three built-in gate resistor trenches 86 is the same as the built-in gate resistor trench 8 in Embodiment 1, including a trench insulating film 8a and a trench electrode 8b as the main structural elements.

[0199] exist Figure 12 In the configuration shown, all three built-in gate resistor trenches 86 function as actual built-in gate resistor trenches. That is, K (M≥K≥2) of the M built-in gate resistor trenches 86 function as actual built-in gate resistor trenches. Here, {K=M=3}.

[0200] Each of the three built-in gate resistor trenches 86, which function as actual built-in gate resistor trenches, is a parallelogram when viewed from above, with the shorter side as the X direction and the longer side as the tilt direction D8. At each of the three built-in gate resistor trenches 86, the shorter side is in the X direction, and the longer side is in the tilt direction D8. The tilt direction D8 intersects both the X and Y directions.

[0201] like Figure 12 As shown, one end of each of the three built-in gate resistor trenches 86 is electrically connected to the pad-side contact area 40I via the pad contact portion 9P, and the other end of each of the three built-in gate resistor trenches 86 is electrically connected to the wiring-side contact area 30I via the wiring contact portion 9L.

[0202] Therefore, at each of the three built-in gate resistor trenches 86, a gate current path is provided between the pad contact 9P and the wiring contact 9L.

[0203] Among the three built-in gate resistor trenches 86, the trench width Wr is set to be the same, and the inter-contact distance Lr along the inclined direction D8 between the pad contact 9P and the wiring contact 9L is also set to be the same. As described above, the distance between the wiring contact 9L and the pad contact 9P in the gate current path is defined as the inter-contact distance Lr.

[0204] The semiconductor device 106 of Embodiment 6 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0205] In the semiconductor device 106 of Embodiment 6, the wiring-side contact area 30I and the pad-side contact area 40I are arranged apart by a pad wiring distance Wm in the Y direction, which are opposite directions. Therefore, similar to Embodiment 5, the pad wiring distance Wm can be set to be relatively long.

[0206] Therefore, the semiconductor device 106 of Embodiment 6 can effectively suppress short circuits in the electrical connection between the gate wiring 3C and the gate pad 4C caused by fluctuations in the manufacturing process.

[0207] Furthermore, each of the three built-in gate resistor trenches 86, which function as built-in gate resistor trenches in actual use, is a parallelogram when viewed from above, and does not have a curved portion like the built-in gate resistor trench 85 in Embodiment 5.

[0208] Therefore, the semiconductor device 106 of Embodiment 6 can improve the embeddability of the trench electrode 8b, and correspondingly improve the accuracy of the resistance value of the built-in gate resistor trench 86.

[0209] In addition, since the three built-in gate resistor trenches 86, each of which functions as built-in gate resistor trenches in actual use, have their long side direction set to the inclined direction D8, it is possible to ensure that the contact distance Lr can be set to the length of the intended resistance value.

[0210] In embodiment 6, the three built-in gate resistor trenches 86 are configured to appear as parallelograms in a narrow sense when viewed from above, but they can also be configured to appear as rectangles when viewed from above. In this case, the long side of the rectangle is in the sloping direction D8. Furthermore, a rectangle is a special type of parallelogram, which is included in the broader sense of parallelogram.

[0211] <Implementation Method 7>

[0212] The overall structure of the semiconductor device 107 in Embodiment 7 is similar to Figures 1-4 The implementation method shown is the same as Implementation Method 1.

[0213] Figure 13This is an explanatory diagram schematically showing the detailed structure of the gate pad periphery region A1 in the semiconductor device 107 of Embodiment 7. Furthermore, the structure of the built-in gate resistor periphery region B2 in the semiconductor device 107 is similar to... Figure 6 and Figure 7 The construction of Embodiment 1 shown is the same.

[0214] Below, regarding Figure 5 The same structures as those in Embodiment 1 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the features of Embodiment 7.

[0215] An internal gate resistor unit 71 to 74 is provided between the corresponding wiring-side contact areas 30 and pad-side contact areas 40 in the four wiring-side contact areas 30 and the four pad-side contact areas 40. Therefore, the four internal gate resistor units 71 to 74 are provided in a one-to-one correspondence with the four wiring-side contact areas 30 and the four pad-side contact areas 40.

[0216] Built-in gate resistor unit 71 is located on the left side of the figure and is set to a resistance value of R1; built-in gate resistor unit 72 is located at the top of the figure and is set to a resistance value of R2; built-in gate resistor unit 73 is located on the right side of the figure and is set to a resistance value of R3; and built-in gate resistor unit 74 is located at the bottom of the figure and is set to a resistance value of R4.

[0217] The corresponding wiring-side contact area 30 and pad-side contact area 40 are electrically connected through each built-in gate resistor unit 71 to 74.

[0218] Built-in gate resistor units 71 to 74 function as N local built-in gate resistor regions, positioned opposite the four edges of the main pad region 4M when viewed from above, and are classified as the 1st to 4th local built-in gate resistor regions. That is, built-in gate resistor unit 71 is the 1st local built-in gate resistor region, built-in gate resistor unit 72 is the 2nd local built-in gate resistor region, built-in gate resistor unit 73 is the 3rd local built-in gate resistor region, and built-in gate resistor unit 74 is the 4th local built-in gate resistor region.

[0219] The semiconductor device 107 of embodiment 7 is characterized in that the resistance values ​​R1 to R4 of the built-in gate resistor units 71 to 74 are set to different values ​​from each other.

[0220] The semiconductor device 107 of Embodiment 7 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0221] In Embodiment 7, the semiconductor device 107 sets the resistance values ​​R1 to R4 of the built-in gate resistor units 71 to 74, which will become the first to fourth local built-in gate resistor regions, to be different from each other, thereby enabling a wider range of adjustment of the resistance value of the built-in gate resistor region 5.

[0222] In addition, the resistance values ​​R1 to R4 of the built-in gate resistor units 71 to 74 can be set to different values, but some of the resistance values ​​R1 to R4 can also be set to the same resistance value.

[0223] <Implementation Method 8>

[0224] The overall structure of the semiconductor device 108 in embodiment 8 is similar to Figures 1-4 The implementation method shown is the same as Implementation Method 1.

[0225] Figure 14 This is an explanatory diagram schematically showing the detailed structure of the gate pad periphery region A1 in the semiconductor device 108 of Embodiment 8. Furthermore, the structure of the built-in gate resistor periphery region B3 in the semiconductor device 108 is similar to... Figure 6 and Figure 7 The construction of Embodiment 1 shown is largely the same.

[0226] Below, regarding Figure 5 The same structures as those in Embodiment 1 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the features of Embodiment 8.

[0227] In embodiment 8, the gate wiring 3D has a different shape than the gate wiring 3 in embodiment 1.

[0228] like Figure 14 As shown, the gate wiring 3D has an outer peripheral wiring region 3P disposed along the outer periphery of the gate pad 4, and four built-in gate resistance measurement pads 12 disposed at the four corners of the outer peripheral wiring region 3P. Each of the four built-in gate resistance measurement pads 12 is disposed in contact with the outer peripheral wiring region 3P. Each of the four built-in gate resistance measurement pads 12 functions as a wiring-side contact region 30. The four built-in gate resistance measurement pads 12 and the four pad-side contact regions 40 correspond one-to-one.

[0229] Each of the four built-in gate resistance measurement pads 12 has an exposed measurement area. Electrical connection to the outside can be achieved through this measurement area.

[0230] Built-in gate resistor units 7 are provided between the corresponding built-in gate resistance measurement pads 12 and pad-side contact areas 40 in the four built-in gate resistance measurement pads 12 and the four pad-side contact areas 40. Therefore, the four built-in gate resistor units 7 are provided corresponding to the four built-in gate resistance measurement pads 12 and the four pad-side contact areas 40.

[0231] In embodiment 8, similar to embodiment 1, the four built-in gate resistor units 7 have the same resistance value R0. Alternatively, some of the resistance values ​​of the four built-in gate resistor units 7 can be set to different values.

[0232] The built-in gate resistance measuring pad 12 is electrically connected to the pad-side contact area 40 via the built-in gate resistance unit 7. Regarding the electrical connection of the built-in gate resistance unit 7, the built-in gate resistance measuring pad 12 functions as the wiring-side contact area 30.

[0233] The four built-in gate resistor units 7 are positioned opposite the four edges of the main pad area 4M when viewed from above. The four built-in gate resistor units 7 function as N local built-in gate resistor regions.

[0234] The semiconductor device 108 of Embodiment 8 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0235] In Embodiment 8, the semiconductor device 108 uses a built-in gate resistance measuring pad 12, which functions as a wiring-side contact area 30 and as a measuring area for external connection, to measure the resistance value of the built-in gate resistance region 5.

[0236] Specifically, by measuring the voltage between the gate pad 4 and the built-in gate resistance measuring pad 12 or the current flowing through the gate pad 4 and the built-in gate resistance measuring pad 12, the resistance value of the built-in gate resistance region 5, that is, the combined resistance value of the four built-in gate resistance units 7, each with a resistance value R0, can be measured.

[0237] Furthermore, in embodiment 8, four built-in gate resistance measurement pads 12 are provided, but the above-mentioned effect can be achieved as long as at least one built-in gate resistance measurement pad 12 is provided corresponding to at least one of the four built-in gate resistance units 7.

[0238] <Implementation Method 9>

[0239] The overall structure of the semiconductor device 109 in Embodiment 9 is similar to Figures 1-4 The implementation method shown is the same as that of embodiment 1. The structure of the area A1 surrounding the gate pad is also the same. Figure 5 The implementation method shown is the same as Implementation Method 1. Figure 5The planar structure within the peripheral region B1 of the built-in gate resistor is also similar to Figure 6 The implementation method shown is the same as Implementation 1. However, Figure 5 The cross-sectional structure of the region B1 surrounding the built-in gate resistor is different from that in embodiment 1.

[0240] Figure 15 This refers to the semiconductor device 109 in Embodiment 9. Figure 6 A sectional view of the cross-sectional structure at section AA. Figure 15 The document contains an XYZ orthogonal coordinate system.

[0241] Below, regarding Figure 7 The same structures as those in Embodiment 1 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the features of Embodiment 9.

[0242] like Figure 15 As shown, a second conductivity type, i.e., a p-type, well layer 13 is provided on the upper layer of the first main surface side of the n-type semiconductor substrate 11. An internal gate resistor trench 8 is provided within this well layer 13. Furthermore, in... Figure 15 In this context, the semiconductor substrate 11 is more accurately equivalent to the n-type drift layer 21.

[0243] An embedded gate resistor trench 8 is buried within the well layer 13 of the semiconductor substrate 11, with the bottom of the embedded gate resistor trench 8 existing within the well layer 13. Similar to Embodiment 1, the embedded gate resistor trench 8 includes a trench insulating film 8a and a trench electrode 8b as its main structural elements. The trench insulating film 8a is configured to cover the entire circumference of the trench electrode 8b. Therefore, the trench electrode 8b has no electrical connection to the well layer 13.

[0244] Figure 15 The configuration shown is common among the M built-in gate resistor trenches 8. Therefore, the semiconductor device 109 of Embodiment 9 is characterized in that the bottoms of the M built-in gate resistor trenches 8 exist within a p-type well layer 13. That is, the M built-in gate resistor trenches 8 are covered by the well layer 13. Furthermore, in Embodiment 9, as in Embodiment 1, {M = K = 4}.

[0245] The semiconductor device 109 of Embodiment 9 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0246] The semiconductor device 109 of embodiment 9 also has a second conductivity type, namely a p-type well layer 13, thereby enabling the electric field generated at the bottom of the four built-in gate resistor trenches 8 to be mitigated by the well layer 13, thereby improving the reliability of the resistance value of the four built-in gate resistor trenches 8.

[0247] The reason is that, in the presence of the well layer 13, the electric field strength becomes maximum at the pn junction interface between the second conductivity type (p-type) well layer 13 and the first conductivity type (n-type) semiconductor substrate 11, which can mitigate the electric field at the bottom of the four built-in gate resistor trenches 8.

[0248] <Implementation Method 10>

[0249] The overall structure of the semiconductor device 110 in Embodiment 10 is similar to that of the semiconductor device 110 in Embodiment 10. Figures 1-4 The implementation method shown is the same as that of embodiment 1. The structure of the area A1 surrounding the gate pad is also the same. Figure 5 The implementation method shown is the same as Implementation Method 1. Figure 5 The planar structure within the peripheral region B1 of the built-in gate resistor is also similar to Figure 6 The implementation method shown is the same as Implementation 1. However, Figure 5 The cross-sectional structure of the region B1 surrounding the built-in gate resistor and Figure 7 The implementation method shown is different from Implementation Method 1.

[0250] Figure 16 This is a representation of the semiconductor device 110 in Embodiment 10. Figure 6 A sectional view of the cross-sectional structure at section AA. Figure 16 The document contains an XYZ orthogonal coordinate system.

[0251] Below, regarding Figure 7 The same structures as those in Embodiment 1 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the features of Embodiment 10.

[0252] like Figure 16 As shown, a second conductivity type, i.e., p-type, well layer 13B is formed on the upper layer of the semiconductor substrate 11. An embedded gate resistor trench 8 penetrates the well layer 13B and is buried within the semiconductor substrate 11. That is, the formation depth of the well layer 13B is shallower than the formation depth of the embedded gate resistor trench. Furthermore, in Figure 16 In this context, the semiconductor substrate 11 is more accurately equivalent to the n-type drift layer 21.

[0253] A second conductivity type, i.e., p-type, barrier layer 14 is selectively formed within the semiconductor substrate 11. The barrier layer 14 is configured to cover the bottom of the built-in gate resistor trench 8. Therefore, the bottom of the built-in gate resistor trench 8 exists within the barrier layer 14.

[0254] Similar to Embodiment 1, the built-in gate resistor trench 8 includes a trench insulating film 8a and a trench electrode 8b as its main structural elements. The trench insulating film 8a is configured to cover the entire circumference of the trench electrode 8b. Therefore, the trench electrode 8b and the barrier layer 14 are not electrically connected.

[0255] Figure 16The structure shown is common among the M built-in gate resistor trenches 8. Therefore, the semiconductor device 110 of Embodiment 10 is characterized in that the formation depth of the well layer 13B is shallower than the formation depth of the M built-in gate resistor trenches 8, and the bottom of the M built-in gate resistor trenches 8 exists within the barrier layer 14. Furthermore, in Embodiment 10, as in Embodiment 1, {M = K = 4}.

[0256] The semiconductor device 110 of Embodiment 10 has the same effects as the semiconductor device 101 of Embodiment 1, and has the following effects.

[0257] The semiconductor device 110 of embodiment 10 also has a second conductivity type, i.e., p-type, barrier layer 14, which can mitigate the electric field generated at the bottom of the four built-in gate resistor trenches 8 through the barrier layer 14, thereby improving the reliability of the resistance value of the four built-in gate resistor trenches.

[0258] In addition, the formation depth of the well layer 13B can be made shallower than the formation depth of the four built-in gate resistor trenches 8, thereby reducing the manufacturing cost of the semiconductor device 110.

[0259] <Implementation Method 11>

[0260] The overall structure of the semiconductor device 111 in embodiment 11 is similar to Figures 1-4 The implementation method shown is the same as that of embodiment 1. The structure of the area A1 surrounding the gate pad is also the same. Figure 5 The implementation method shown is the same as Implementation Method 1. Figure 5 The planar structure and AA cross-sectional structure within the peripheral region B1 of the built-in gate resistor are also similar to Figure 6 and Figure 7 The implementation method shown is the same as Implementation Method 1.

[0261] The semiconductor device 111 of embodiment 11 is characterized in that Figure 5 The BB cross-section structure within the peripheral region B1 of the built-in gate resistor.

[0262] Figure 17 This is a representation of the semiconductor device 111 in embodiment 11. Figure 6 A sectional view of the cross-sectional structure at section BB. Figure 17 The document contains an XYZ orthogonal coordinate system.

[0263] like Figure 17 As shown, each of the four built-in gate resistor trenches has a constant resistor trench depth Dr in its buried gate electrode 2b. Furthermore, Figure 17 Three built-in gate resistor trenches are shown, but there are actually four.

[0264] like Figure 17As shown, at each of the four built-in gate resistor trenches 8, the surface of the first main surface side of the trench electrode 8b has a resistor surface width Wt, and the bottom surface of the second main surface side of the trench electrode 8b has a resistor bottom surface width Wb. The resistor surface width Wt is the first forming width, and the resistor bottom surface width Wb is the second forming width.

[0265] In embodiments 1 to 10, the trench electrode 8b is assumed to be a cuboid structure. However, in embodiment 11, it is envisioned that when forming the trench for the built-in gate resistor trench 8, a conical surface is formed that tilts inward as it moves downward.

[0266] In embodiment 11, considering the case of forming a conical surface, the trench electrode 8b is formed in such a way that the difference (Wt-Wb) between the resistor surface width Wt and the resistor bottom width Wb satisfies the following formula (2).

[0267] (Wt-Wb)≤Wt / 10…(2)

[0268] Figure 17 The structure shown is common among the M built-in gate resistor trenches 8. Therefore, in the semiconductor device 111 of Embodiment 11, at each of the M built-in gate resistor trenches 8, the trench electrode 8b has a constant resistor trench depth Dr, the surface of the trench electrode 8b has a resistor surface width Wt, and the bottom surface of the trench electrode 8b has a resistor bottom surface width Wb. Moreover, the resistor surface width Wt and the resistor bottom surface width Wb satisfy the above equation (2). Furthermore, in Embodiment 11, as in Embodiment 1, {M = K = 4}.

[0269] With regard to the semiconductor device 111 of embodiment 11, it is characterized in that, at each of the four built-in gate resistor trenches 8, the resistor surface width Wt and the resistor bottom width Wb satisfy the above formula (2).

[0270] The trench for the built-in gate resistor trench 8 that satisfies equation (2) can be implemented, for example, using anisotropic dry etching.

[0271] Furthermore, since the trench insulating film 8a is sufficiently thin, the formation width of the surface of the built-in gate resistor trench 8 can be set as the resistor surface width Wt, and the formation width of the bottom surface of the built-in gate resistor trench 8 can be set as the resistor bottom surface width Wb to apply equation (2). That is, the parameters {Wt, Wb} related to equation (2) can be regarded as the same between the built-in gate resistor trench 8 and the trench electrode 8b.

[0272] In embodiment 11, the resistance value R0 of one unit of built-in gate resistor unit 7 has the characteristic of satisfying the following formula (3) using the above parameters {Lr, K, Wt, Wb, Dr}.

[0273] R0∝Lr / (K×Sr2)…(3)

[0274] Furthermore, in equation (3), Sr2 = Dr × (Wt + Wb) / 2, where Sr2 is the cross-sectional area of ​​the trapezoid in the YZ plane.

[0275] According to equation (3), the resistance value R0 of one unit of built-in gate resistor 7 is inversely proportional to the cross-sectional area Sr2. When forming the trench for the built-in gate resistor trench 8, a tapered angle is generated on the inside during etching, and correspondingly, the width Wb of the resistor bottom surface tends to be shorter than the width Wt of the resistor surface.

[0276] On the other hand, whether it is the rectangular cross-sectional area Sr in equation (1) or the trapezoidal cross-sectional area Sr2 in equation (3), as long as the cross-sectional areas Sr and Sr2 can be made close to constant values, the fluctuation of the resistance value R0 obtained by equation (1) and equation (3) can be suppressed to the minimum.

[0277] Therefore, by setting a built-in gate resistor trench 8 that satisfies equation (2), the fluctuation of the resistance value R0 obtained by applying equation (3) can be minimized.

[0278] In the semiconductor device 111 of embodiment 11, the resistor surface width Wt and resistor bottom width Wb associated with each of the four built-in gate resistor trenches 8 are set in a manner that satisfies equation (2), so that the fluctuation of the resistance value R0 expressed by equation (3) can be suppressed to a minimum.

[0279] <Manufacturing Method>

[0280] The semiconductor devices 101 to 111 of Embodiments 1 to 11 can be manufactured by the following steps (a) to (c).

[0281] Step (a)...determines the number K of the M built-in gate resistor trenches 8 that will function as the actual built-in gate resistor trenches.

[0282] Step (b)...determines the contact distance Lr between the K actual built-in gate resistor trenches.

[0283] Step (c)... forms one of the semiconductor devices 101 to 111 in such a manner that satisfies the number K determined by step (a) above and the distance Lr between the contacts of the K actual built-in gate resistor trenches determined by step (b) above.

[0284] Step (c) is a step of forming any one of the semiconductor devices 101 to 111 in a manner that satisfies the determination content of steps (a) and (b) above.

[0285] Furthermore, the distance Lr between the contacts can be set to the same length among the K actual-use built-in gate resistor trenches, or at least a portion of the K actual-use built-in gate resistor trenches can be set to different lengths.

[0286] The semiconductor device manufacturing method in Embodiments 1 to 11, by performing the above steps (a) to (c), can relatively easily adjust the resistance value of the built-in gate resistor region 5 of any semiconductor device in semiconductor devices 101 to 111 based on the number K of the built-in gate resistor trenches actually used and the distance Lr between the contacts.

[0287] Furthermore, step (c) includes the following step (c-1).

[0288] (c-1) Using CVD, an interlayer insulating film 10 is formed on the first main surface of the semiconductor substrate 11 with a film thickness of about 0.1 μm to 0.8 μm.

[0289] Furthermore, at least one of TEOS oxide film, BPTEOS oxide film, PSG film, BPSG film, alumina and hafnium oxide is considered as the CVD film that forms the interlayer insulating film 10. CVD films using these as constituent materials have stress-suppressing properties as described above.

[0290] Step (c) of the semiconductor device manufacturing method includes step (c-1), so in Embodiments 1 to 11, the variation in the resistance characteristics of each built-in gate resistor unit 7 caused by the interlayer insulating film 10 can be suppressed.

[0291] Furthermore, in step (c-1), a CVD film other than the aforementioned constituent materials may also be formed. However, this is conditional upon the formation of the interlayer insulating film 10 possessing the aforementioned stress suppression characteristics.

[0292] <Other>

[0293] The above describes embodiments 1 to 11, but the construction is not limited to the above embodiments and various extensions can be made.

[0294] For example, in the above embodiment, n-type is shown as the first conductivity type and p-type is shown as the second conductivity type, but the first conductivity type can also be p-type and the second conductivity type can be n-type.

[0295] An IGBT 50 is shown as a switching element with an insulated gate structure, but power devices such as MOSFETs and RC-IGBTs can also be used in addition to the IGBT 50. Furthermore, while a trench-type IGBT 50 is shown in the above embodiment, planar switching elements such as planar IGBTs can also be used.

[0296] Furthermore, various substrates such as voltage-rated semiconductor substrates, FZ substrates, MCZ substrates, and epitaxial substrates can be used as the semiconductor substrate 11. In addition, the FZ substrate is a semiconductor substrate manufactured by the FZ (Floating Zone) method, the MCZ substrate is a semiconductor substrate manufactured by the MCZ (Magnetic field applied Czochralski) method, and the epitaxial substrate is a semiconductor substrate manufactured using the epitaxial growth method.

[0297] Furthermore, within the scope of the invention, the various embodiments can be freely combined, and appropriate modifications or omissions can be made to each embodiment.

[0298] Explanation of the label

[0299] 1. Unit region; 2. Trench gate; 2a. Gate insulating film; 2b. Buried gate electrode; 3. Gate wiring (3B-3D); 3P. Peripheral wiring region; 4. Gate pads (4B-4C); 4M. Main pad region; 5. Built-in gate resistor region; 6. End region; 7. Built-in gate resistor unit (71-74); 11. Semiconductor substrate; 12. Built-in gate resistor measurement pad; 13. Well layer (13B); 14. Barrier layer; 8. Built-in gate resistor trench; 8a. Trench insulating film; 8b. Trench electrode; 8X. Trench without built-in gate resistor; 9. Built-in gate resistor contact; 9L, 9L1, 9L2. Wiring contact; 9P, 9P1, 9P2. Pad contact; 30-32, 30I. Wiring side contact region; 40-42, 40I. Pad side contact region; 101-111, 101A-101C. Semiconductor device.

Claims

1. A semiconductor device comprising a switching element with an insulating gate structure, in, The switching element is disposed on a semiconductor substrate of the first conductivity type. The semiconductor device has: A gate wiring is disposed on the semiconductor substrate with an interlayer insulating film in between, and is electrically connected to the gate electrode of the switching element; A gate pad, disposed on the semiconductor substrate through the interlayer insulating film, having an exposed electrical connection area on its surface; and An internal gate resistor region electrically connects the gate wiring and the gate pad. The built-in gate resistor region comprises N local built-in gate resistor regions connected in parallel between the gate wiring and the gate pad, wherein N ≥ 2. Each of the N local built-in gate resistor regions includes M built-in gate resistor trenches connected in parallel between the gate wiring and the gate pad. The gate wiring has a wiring-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. The gate pad has a pad-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. Each of the M built-in gate resistor trenches is embedded within the semiconductor substrate. Of the M built-in gate resistor trenches, K are used as the actual built-in gate resistor trenches, where M>K≥2. Each of the K practically used built-in gate resistor trenches is electrically connected to the wiring-side contact area of ​​the gate wiring via a wiring contact portion provided in a manner that penetrates the interlayer insulating film. Each of the K practically used built-in gate resistor trenches is electrically connected to the pad-side contact area of ​​the gate pad via a pad contact portion arranged in such a way that it penetrates the interlayer insulating film. At each of the K practically used built-in gate resistor trenches, a gate current path is provided between the wiring contact and the pad contact, wherein the distance between the wiring contact and the pad contact in the gate current path is defined as the contact distance. Each of the M built-in gate resistor trenches is rectangular when viewed from above, with the first direction as the longer side and the second direction as the shorter side. The M built-in gate resistor trenches have 1 to M built-in gate resistor trenches arranged in the order of 1st, 2nd, ... Mth along the second direction. At least one of the M built-in gate resistor trenches is a non-used built-in gate resistor trench, and the first built-in gate resistor trench and the Mth built-in gate resistor trench are not at least one non-used built-in gate resistor trench. The at least one trench without built-in gate resistor has no electrical connection to the gate wiring and the gate pad, respectively.

2. The semiconductor device according to claim 1, wherein, The interlayer insulating film comprises at least one of TEOS oxide film, BPTEOS oxide film, PSG film, BPSG film, aluminum oxide and hafnium oxide.

3. The semiconductor device according to claim 1 or 2, wherein, K≥3， At each of the K actual-use built-in gate resistor trenches, the distance between the contacts is greater than or equal to 100 μm.

4. The semiconductor device according to claim 1 or 2, wherein, The wiring side contact area includes multiple wiring side contact areas. The pad-side contact area includes multiple pad-side contact areas. The wiring contact portion includes multiple wiring contact portions, and each of the multiple wiring contact portions corresponds one-to-one with a multiple wiring-side contact area. The pad contact portion includes multiple pad contact portions, each of which corresponds one-to-one with a pad-side contact area. The gate current path includes multiple local gate current paths connected in parallel between the gate wiring and the gate pad. Each of the plurality of local gate current paths is disposed between one of the plurality of wiring contacts and one of the plurality of pad contacts.

5. The semiconductor device according to claim 1 or 2, wherein, It also has a well layer of a second conductivity type disposed on the upper part of the semiconductor substrate. The bottoms of the M built-in gate resistor trenches exist within the well layer.

6. The semiconductor device according to claim 1 or 2, wherein, The switching element in the insulating gate structure is a MOSFET.

7. A semiconductor device comprising a switching element with an insulating gate structure, in, The switching element is disposed on a semiconductor substrate of the first conductivity type. The semiconductor device has: A gate wiring is disposed on the semiconductor substrate with an interlayer insulating film in between, and is electrically connected to the gate electrode of the switching element; A gate pad, disposed on the semiconductor substrate through the interlayer insulating film, having an exposed electrical connection area on its surface; and An internal gate resistor region electrically connects the gate wiring and the gate pad. The built-in gate resistor region includes N local built-in gate resistor regions connected in parallel between the gate wiring and the gate pad. Each of the N local built-in gate resistor regions includes M built-in gate resistor trenches connected in parallel between the gate wiring and the gate pad, where M ≥ 2. The gate wiring has a wiring-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. The gate pad has a pad-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. Each of the M built-in gate resistor trenches is embedded within the semiconductor substrate. Of the M built-in gate resistor trenches, K are used as the actual built-in gate resistor trenches, where M ≥ K ≥ 2. Each of the K practically used built-in gate resistor trenches is electrically connected to the wiring-side contact area of ​​the gate wiring via a wiring contact portion provided in a manner that penetrates the interlayer insulating film. Each of the K practically used built-in gate resistor trenches is electrically connected to the pad-side contact area of ​​the gate pad via a pad contact portion arranged in such a way that it penetrates the interlayer insulating film. At each of the K practically used built-in gate resistor trenches, a gate current path is provided between the wiring contact and the pad contact, wherein the distance between the wiring contact and the pad contact in the gate current path is defined as the contact distance. The gate pad also has a main pad area that is rectangular when viewed from above, and the main pad area includes the electrical connection area. N＝4， The N local built-in gate resistor regions are configured to be opposite the four sides of the main area of ​​the pad when viewed from above.

8. The semiconductor device according to claim 7, wherein, Both the wiring-side contact area and the pad-side contact area are arranged along the direction in which the contact area is formed. The wiring-side contact area and the pad-side contact area are configured to be spaced apart from the pad wiring distance in opposite directions, and these opposite directions intersect with the directions of the contact areas. Each of the K actually used built-in gate resistor trenches has a first forming region extending in the contact region forming direction and a second forming region extending in the opposite direction.

9. The semiconductor device according to claim 7, wherein, Both the wiring-side contact area and the pad-side contact area are arranged along the direction in which the contact area is formed. The wiring-side contact area and the pad-side contact area are configured to be spaced apart from the pad wiring distance in opposite directions, and these opposite directions intersect with the directions of the contact areas. The K actual-use built-in gate resistor trenches are each parallelograms when viewed from above, with their long sides intersecting the direction of the contact area formation and the opposite direction, respectively.

10. The semiconductor device according to any one of claims 7 to 9, wherein, The N locally built-in gate resistor regions are classified as the 1st to the 4th locally built-in gate resistor regions. The resistance values ​​of the first to fourth local built-in gate resistor regions are set to be different from each other.

11. The semiconductor device according to any one of claims 7 to 9, wherein, The gate wiring has a built-in gate resistance measurement pad with an exposed measurement area on its surface. The built-in gate resistance measurement pad functions as a wiring-side contact area corresponding to at least one of the N local built-in gate resistance regions.

12. A semiconductor device comprising a switching element with an insulating gate structure, in, The switching element is disposed on a semiconductor substrate of the first conductivity type. The semiconductor device has: A gate wiring is disposed on the semiconductor substrate with an interlayer insulating film in between, and is electrically connected to the gate electrode of the switching element; A gate pad, disposed on the semiconductor substrate through the interlayer insulating film, having an exposed electrical connection area on its surface; and An internal gate resistor region electrically connects the gate wiring and the gate pad. The built-in gate resistor region comprises N local built-in gate resistor regions connected in parallel between the gate wiring and the gate pad, wherein N ≥ 2. Each of the N local built-in gate resistor regions includes M built-in gate resistor trenches connected in parallel between the gate wiring and the gate pad, where M ≥ 2. The gate wiring has a wiring-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. The gate pad has a pad-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. Each of the M built-in gate resistor trenches is embedded within the semiconductor substrate. Of the M built-in gate resistor trenches, K are used as the actual built-in gate resistor trenches, where M ≥ K ≥ 2. Each of the K practically used built-in gate resistor trenches is electrically connected to the wiring-side contact area of ​​the gate wiring via a wiring contact portion provided in a manner that penetrates the interlayer insulating film. Each of the K practically used built-in gate resistor trenches is electrically connected to the pad-side contact area of ​​the gate pad via a pad contact portion arranged in such a way that it penetrates the interlayer insulating film. At each of the K practically used built-in gate resistor trenches, a gate current path is provided between the wiring contact and the pad contact, wherein the distance between the wiring contact and the pad contact in the gate current path is defined as the contact distance. The semiconductor device further comprises: A second conductivity type well layer is disposed on the upper layer of the semiconductor substrate; and A second conductivity barrier layer is selectively disposed within the semiconductor substrate. The depth of the well layer is shallower than the depth of the M built-in gate resistor trenches. The bottoms of the M built-in gate resistor trenches are located within the barrier layer.

13. A semiconductor device comprising a switching element with an insulated gate configuration, in, The switching element is disposed on a semiconductor substrate of the first conductivity type. The semiconductor device has: A gate wiring is disposed on the semiconductor substrate with an interlayer insulating film in between, and is electrically connected to the gate electrode of the switching element; A gate pad, disposed on the semiconductor substrate through the interlayer insulating film, having an exposed electrical connection area on its surface; and An internal gate resistor region electrically connects the gate wiring and the gate pad. The built-in gate resistor region comprises N local built-in gate resistor regions connected in parallel between the gate wiring and the gate pad, wherein N ≥ 2. Each of the N local built-in gate resistor regions includes M built-in gate resistor trenches connected in parallel between the gate wiring and the gate pad, where M ≥ 2. The gate wiring has a wiring-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. The gate pad has a pad-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. Each of the M built-in gate resistor trenches is embedded within the semiconductor substrate. Of the M built-in gate resistor trenches, K are used as the actual built-in gate resistor trenches, where M ≥ K ≥ 2. Each of the K practically used built-in gate resistor trenches is electrically connected to the wiring-side contact area of ​​the gate wiring via a wiring contact portion provided in a manner that penetrates the interlayer insulating film. Each of the K practically used built-in gate resistor trenches is electrically connected to the pad-side contact area of ​​the gate pad via a pad contact portion arranged in such a way that it penetrates the interlayer insulating film. At each of the K practically used built-in gate resistor trenches, a gate current path is provided between the wiring contact and the pad contact, wherein the distance between the wiring contact and the pad contact in the gate current path is defined as the contact distance. Each of the M built-in gate resistor trenches has a trench electrode and a trench insulating film covering the trench electrode. The trench electrodes of each of the M built-in gate resistor trenches have a constant resistor trench depth. The surface of each of the M built-in gate resistor trenches has a first formation width. The bottom surface of the trench electrode of each of the M built-in gate resistor trenches has a second forming width. The difference between the first forming width and the second forming width is set to be less than or equal to 1 / 10 of the first forming width.

14. A method of manufacturing a semiconductor device, said semiconductor device comprising a switching element with an insulating gate structure. in, The switching element is disposed on a semiconductor substrate of the first conductivity type. The semiconductor device has: A gate wiring is disposed on the semiconductor substrate with an interlayer insulating film in between, and is electrically connected to the gate electrode of the switching element; A gate pad, disposed on the semiconductor substrate through the interlayer insulating film, having an exposed electrical connection area on its surface; and An internal gate resistor region electrically connects the gate wiring and the gate pad. The built-in gate resistor region comprises N local built-in gate resistor regions connected in parallel between the gate wiring and the gate pad, wherein N ≥ 2. Each of the N local built-in gate resistor regions includes M built-in gate resistor trenches connected in parallel between the gate wiring and the gate pad, where M ≥ 2. The gate wiring has a wiring-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. The gate pad has a pad-side contact area that overlaps with the M built-in gate resistor trenches when viewed from above. Each of the M built-in gate resistor trenches is embedded within the semiconductor substrate. Of the M built-in gate resistor trenches, K are used as the actual built-in gate resistor trenches, where M ≥ K ≥ 2. Each of the K practically used built-in gate resistor trenches is electrically connected to the wiring-side contact area of ​​the gate wiring via a wiring contact portion provided in a manner that penetrates the interlayer insulating film. Each of the K practically used built-in gate resistor trenches is electrically connected to the pad-side contact area of ​​the gate pad via a pad contact portion arranged in such a way that it penetrates the interlayer insulating film. At each of the K practically used built-in gate resistor trenches, a gate current path is provided between the wiring contact and the pad contact, wherein the distance between the wiring contact and the pad contact in the gate current path is defined as the contact distance. The method for manufacturing this semiconductor device includes: Step (a) determines the number K of the M built-in gate resistor trenches that will function as actual built-in gate resistor trenches; Step (b) determines the contact distance between each of the K actually used built-in gate resistor trenches; and Step (c) is to form the semiconductor device in a manner that satisfies the determinations of steps (a) and (b).

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