Semiconductor device

Abstract

This invention provides a semiconductor device that significantly reduces the on-resistance of the semiconductor device. The semiconductor device of this invention includes a plurality of pillar-shaped portions made of semiconductor. Each of the plurality of pillar-shaped portions has a source region, a drain region, and a channel forming region including a channel formed between the source region and the drain region. The semiconductor device of this invention further includes: a gate electrode disposed on a sidewall of the channel forming region through an insulating layer; and a first semiconductor layer disposed on a sidewall of the drain region. The conductivity type of the first semiconductor layer is different from the conductivity type of the semiconductor forming the drain region.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] A semiconductor nanowire is a semiconductor thin wire having a nanometer (nm) order thickness, and is attracting attention as a structure of a next-generation nanodevice, and is expected to be applied to various semiconductor devices such as transistors and light sources. In addition, by adopting a Gate-All-Around (GAA) structure in which a gate electrode surrounds a semiconductor nanowire in the entire circumference, a channel formation region of the semiconductor nanowire can be surrounded by the gate electrode, and complete depletion can be achieved, and current control properties can be improved. According to the GAA structure, both a switching property in which the on / off is sharply switched with respect to time and high density per unit area can be achieved.

[0003] For example, in Non-Patent Literature 1, a semiconductor device provided with a plurality of semiconductor nanowires formed of gallium nitride (GaN) is disclosed. In the semiconductor device disclosed in Non-Patent Literature 1, the plurality of semiconductor nanowires are arranged at intervals from each other in one direction on the surface of a substrate, and each of the semiconductor nanowires extends in a direction perpendicular to the aforementioned one direction. That is, when viewed in a direction perpendicular to the surface of the substrate, the plurality of semiconductor nanowires are formed in a stripe shape. In addition, the channel of the vertical transistor is constituted of an a-plane of GaN. A gate electrode uses chromium (Cr).

[0004] Non-Patent Literature 1: Appl. Phys. Lett. (2016) Vol. 108 213503, F. Yu et al., "Vertical architecture for enhancement mode power transistors based on GaN nanowires"

[0005] The plurality of semiconductor nanowires of the semiconductor device disclosed in Non-Patent Literature 1 are formed in a top-down manner using a dry etching process. After the dry etching process, a wet process using an alkaline solution or the like is used to restore the crystallinity of GaN of the plurality of semiconductor nanowires. Therefore, the pitch of the semiconductor nanowires becomes large, and it is difficult to achieve high density of the semiconductor nanowires per unit area in the arrangement surface. In addition, in the process using the above-described alkaline solution or the like, the a-plane of GaN is easily formed as a channel surface, and it is difficult to increase the surface density. Furthermore, in the semiconductor device disclosed in Non-Patent Literature 1, after the semiconductor nanowires are formed, the gate electrode is formed by oblique evaporation of Cr to the sidewall of the semiconductor nanowires, and therefore it is difficult to control the gate length. Thus, in the semiconductor device disclosed in Non-Patent Literature 1, it is difficult to sufficiently reduce the on-resistance to the extent required for a power device. Summary of the Invention

[0006] To address the aforementioned issues, one aspect of the semiconductor device of the present invention includes a plurality of pillar-shaped portions made of semiconductor. Each of the plurality of pillar-shaped portions has a source region, a drain region, and a channel forming region including a channel formed between the source region and the drain region. Another aspect of the semiconductor device of the present invention further includes: a gate electrode disposed on a sidewall of the channel forming region via an insulating layer; and a first semiconductor layer disposed on a sidewall of the drain region. The conductivity type of the first semiconductor layer is different from the conductivity type of the semiconductor forming the drain region. Attached Figure Description

[0007] Figure 1 This is a perspective view of a semiconductor device according to one embodiment of the present invention.

[0008] Figure 2 It is along Figure 1 Observe the direction of the C1-C1 line shown. Figure 1 A cross-sectional view of the semiconductor device shown.

[0009] Figure 3 It is used for explanation Figure 1 as well as Figure 2 A cross-sectional view of a method for manufacturing a semiconductor device.

[0010] Figure 4 It is used for explanation Figure 1 as well as Figure 2 A cross-sectional view of a method for manufacturing a semiconductor device.

[0011] Figure 5 It is used for explanation Figure 1 as well as Figure 2 A cross-sectional view of a method for manufacturing a semiconductor device.

[0012] Figure 6 It is used for explanation Figure 1 as well as Figure 2 A cross-sectional view of a method for manufacturing a semiconductor device.

[0013] Figure 7 It is used for explanation Figure 1 as well as Figure 2 A cross-sectional view of a method for manufacturing a semiconductor device.

[0014] Figure 8 It is used for explanation Figure 1 as well as Figure 2 A cross-sectional view of a method for manufacturing a semiconductor device.

[0015] Figure 9 It is used for explanationFigure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0016] Figure 10 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0017] Figure 11 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0018] Figure 12 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0019] Figure 13 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0020] Figure 14 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0021] Figure 15 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0022] Figure 16 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0023] Figure 17 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0024] Figure 18 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0025] Figure 19 is a cross-sectional view for explaining Figure 1 and Figure 2 a cross-sectional view of a semiconductor device manufacturing method.

[0026] Figure 20 is a cross-sectional view for explaining Figure 1as well as Figure 2 A cross-sectional view of a method for manufacturing a semiconductor device.

[0027] Label Explanation

[0028] 11: Semiconductor device; 21: Semiconductor; 22: Pillar; 20: Semiconductor layer (second semiconductor layer); 40: Gate insulating film; 50: Gate electrode; 60: Metal layer; 70: Semiconductor layer (first semiconductor layer); D: Drain region; R: Channel formation region; S: Source region. Detailed Implementation

[0029] The following uses Figures 1-20 One embodiment of the present invention will be described.

[0030] In the following figures, the scale of the dimensions is sometimes changed according to the constituent elements in order to make it easier to observe each constituent element.

[0031] (Basic structure of a semiconductor device)

[0032] Figure 1 This is a perspective view of a semiconductor device 11 according to one embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional view of semiconductor device 11 taken with the C1-C1 line shown in the direction indicated. Figure 1 as well as Figure 2 As shown, the semiconductor device 11 includes multiple vertically oriented field-effect transistors (FETs), and is used, for example, as power devices such as inverters. The semiconductor device 11 mainly includes a metal layer 12 constituting the contact region on the source side, a semiconductor layer (second semiconductor layer) 20 and a semiconductor layer (semiconductor) 21C constituting the source region S of the FET, a semiconductor layer (semiconductor) 21A and a semiconductor layer 30 constituting the drain region D of the FET, a semiconductor layer (semiconductor) 21B constituting the channel formation region R of the FET, a gate insulating film (insulating layer) 40, a gate electrode 50, a metal layer (first metal layer) 60 constituting the contact region on the drain side of the FET, and a semiconductor layer (first semiconductor layer) 70. Furthermore, the gate insulating film 40... Figure 1 The middle part is omitted, but as described later, it is located between semiconductor layer 21B and gate electrode 50.

[0033] Hereinafter, the direction parallel to the thickness direction of, for example, the metal layer 12 of the semiconductor device 11 and extending from the surface 12a of the metal layer 12 toward the back surface 12b is defined as the Z direction. Two directions parallel to and perpendicular to the surface 12a of the metal layer 12 are defined as the X direction and the Y direction. The Z direction is perpendicular to both the X and Y directions.

[0034] In addition to the structures described above, the semiconductor device 11, though not shown, may also include, for example, a gate conductive layer directly connected to the gate electrode 50 in the Z direction, and a gate metal layer disposed on the side of the gate conductive layer opposite to the gate electrode 50 side. Furthermore, the semiconductor device 11 may also include, for example, a source conductive layer directly connected to the semiconductor layer 20 of the source region S in the Z direction, and a source metal layer disposed on the side of the source conductive layer opposite to the semiconductor layer 20 side. Alternatively, the gate electrode 50 may also have bonding wires, and the metal layer 12 may also have bonding wires. The gate conductive layer and the source conductive layer function as contact plugs. The gate metal layer functions as a contact terminal to the gate electrode 50, and the source metal layer functions as a contact terminal to the source region S of the FET. The gate conductive layer and the source conductive layer are, for example, formed of tungsten (W). The gate metal layer and the source metal layer are, for example, formed of copper (Cu) and aluminum (Al), for example, respectively. When the gate electrode 50 is provided with bonding wires and the metal layer 12 is provided with bonding wires, each bonding wire may also be formed of copper (Cu) or aluminum (Al).

[0035] like Figure 1 and Figure 2 As shown, the metal layer 60 serves as a substrate supporting the main components of the semiconductor device 11, extending along the XY plane and having a predetermined thickness. If the thickness is fixed, the metal layer has higher strength than the semiconductor layer; therefore, the predetermined thickness can be thinner than the semiconductor substrate used in conventional semiconductor devices. The surface 60a and back surface 60b of the metal layer 60 are flat surfaces substantially parallel to the XY plane. The metal layer 60 is formed, for example, from a metal such as Cu.

[0036] The semiconductor layer 30 is stacked behind the surface 60a of the metal layer 60 in the Z direction, extends along the XY plane, and has a predetermined thickness. The surface 30a and bottom surface 30b of the semiconductor layer 30 are flat surfaces that are substantially parallel to the XY plane. The semiconductor layer 30 is formed, for example, of an n-type semiconductor. An n-type semiconductor is, for example, gallium nitride (GaN) doped with n-type impurities. Examples of n-type impurities include silicon (Si).

[0037] The semiconductor layer 30 has a two-layer structure comprising a first layer 31 and a second layer 32. The first layer 31 extends along the XY plane and is disposed in the semiconductor layer 30 at the rear side in the Z direction, i.e., the lower part of the semiconductor layer 30. The bottom surface 31b of the first layer 31 abuts against the surface 60a of the metal layer 60. The second layer 32 is disposed in the Z direction between the first layer 31 and each of the plurality of pillar-shaped portions 22, extends along the XY plane, and is disposed in the semiconductor layer 30 at the front side in the Z direction, i.e., the upper part of the semiconductor layer 30. The surface 32a of the second layer 32 abuts against the bottom surface 22b of the plurality of pillar-shaped portions 22. The bottom surface 32b of the second layer 32 abuts against the surface 31a of the first layer.

[0038] The first layer 31 is formed of an n-type semiconductor, for example, n-GaN. Hereinafter, n-GaN doped with an n-type impurity is sometimes referred to as n-GaN. The second layer 32 is formed of an n-type semiconductor having a lower impurity concentration than the n-type semiconductor forming the first layer 31. Hereinafter, n-GaN having a relatively higher impurity concentration is sometimes referred to as n + -GaN, and n-GaN having a relatively lower impurity concentration is sometimes referred to as n - -Gan. That is, the first layer 31 is formed of n + -GaN, and the second layer 32 is formed of n - -GaN.

[0039] The semiconductor layers 21A, 21B, and 21C are stacked in the Z direction in this order, have the same shape and size as each other in the XY plane, and constitute one columnar portion (columnar portion) 22. The columnar portion 22 is a so-called semiconductor nanowire. That is, the semiconductor device 11 is provided with a plurality of columnar portions 22. The plurality of columnar portions 22 are arranged at a prescribed interval from each other in the X direction and the Y direction. The plurality of columnar portions 22 each protrude in parallel with the Z direction from a surface 20a of a prescribed region of the semiconductor layer 20 constituting the source region S. The cross section of each of the plurality of columnar portions 22 intersecting the XY plane is, for example, circular, but can be rectangular or a polygon other than rectangular.

[0040] The maximum dimension in the XY plane of each of the plurality of columnar portions 22 is, for example, about 0.3 μm, and is at least 0.5 μm or less. By the plurality of columnar portions 22 being small in diameter as described above, the region Ch forming a channel easily reaches the substantially central portion of the semiconductor layer 21C in the XY plane, and can be completely depleted.

[0041] In addition, the "semiconductor" in the claims collectively indicates the semiconductor 21 constituting the columnar portion 22, and does not mean that the semiconductor layers 21A, 21B, and 21C are formed of the same kind of semiconductor as each other, but includes the same kind or different kind of semiconductor having different impurity concentrations from each other on the basis of satisfying the conditions described later and the like.

[0042] The semiconductor layer 21A is arranged at the foremost portion in the Z direction of the columnar portion 22, that is, the lowermost layer, and constitutes the drain region D together with the semiconductor layer 30. The bottom surface 22b of each of the plurality of columnar portions 22 is in abutment with the surface 30a of the semiconductor layer 30. By being arranged like this, the semiconductor layer 30 is connected to the semiconductor layer 21A of each of the plurality of columnar portions 22. The semiconductor layer 21A is formed of an n-type semiconductor, for example, the same n -- GaN. Also, although not shown, it is also possible that the semiconductor layer 21A that constitutes the drain region D includes a first region and a second region having a lower impurity concentration than the first region, the second region being located between the first region and the semiconductor layer 21B. In this case, the second region has a lower impurity concentration than the first region and a higher impurity concentration than the semiconductor layer 21B. The second region is a drift region.

[0043] The semiconductor layer 21B is an intermediate layer between the semiconductor layers 21A and 21C of the columnar portion 22 in the Z direction, and constitutes a channel formation region R. The channel formation region R includes a region Ch in which a channel is formed between the source region S and the drain region D, and is a region in which a gradient is generated according to a difference in impurity concentration of the semiconductor 21 that forms the semiconductor layers 21A and 21C, respectively, and in which a drift speed of electric charges is increased by a gate voltage. The Z-directional dimension of the semiconductor layer 21B is smaller than the Z-directional dimension of each of the semiconductor layers 21A and 21C.

[0044] The semiconductor layer 21B is formed of, for example, a semiconductor that is not doped with impurities. As the semiconductor that is not doped with impurities, for example, GaN can be given. Hereinafter, GaN that is not doped with impurities will be sometimes referred to as i-GaN. Furthermore, the semiconductor layer 21B can be formed of a semiconductor having a lower impurity concentration than the n-type semiconductor that forms the semiconductor layers 21A and 21C, and is not necessarily limited to a semiconductor that is not doped with impurities. However, the closer the impurity concentration of the semiconductor layer 21B to the impurity concentration of the semiconductor layer 21A, the lower the on-resistance of the FET, but the lower the withstand voltage. The on-resistance and the withstand voltage are in a trade-off relationship. The impurity concentration of the semiconductor layer 21B is appropriately set in consideration of the impurity concentration of the semiconductor layer 21A, the size in the Z direction, and the trade-off relationship. In the semiconductor device 11 of the present embodiment, as will be described later, a Super Junction (SJ) configuration is constituted by the semiconductor layer 21B and the semiconductor layer 70, and reduction of the on-resistance is achieved by the SJ configuration. Therefore, the impurity concentration of the semiconductor layer 21B is preferably low in order to secure the withstand voltage in the FET, and is preferably close to zero for a semiconductor that is not doped with impurities.

[0045] Furthermore, the semiconductor that forms the semiconductor layers 21A, 21B, and 21C is preferably of the same kind, and is, for example, GaN in the present embodiment. The semiconductor layers 21A, 21B, and 21C are formed of the same kind of semiconductor 21, and thus, when the semiconductor device 11 is manufactured, the formation process of the plurality of columnar portions 22 can be continuously and easily performed.

[0046] Further, GaN can convert electric power more efficiently than other semiconductors, and thus can output a higher electric power per unit volume. The band gap of GaN is, for example, about 3 times larger than that of Si, which is often used in conventional power devices. Also, the insulating breakdown field of GaN is about 1 order of magnitude larger than that of Si, and thus a reduction in on-resistance by about 3 orders of magnitude compared to the performance limit caused by Si can be achieved. Furthermore, the saturation electron velocity of GaN is larger than that of Si or the like, and thus the speed of operation of the semiconductor device 11 can be increased.

[0047] The semiconductor layer 21C is disposed at the last portion in the Z direction of the columnar portion 22, that is, the uppermost layer, and constitutes the source region S. The semiconductor layer 21C has a size in the Z direction that is at least larger than the size in the Z direction of the semiconductor layer 21B and slightly smaller than the size in the Z direction of the semiconductor layer 21A. The semiconductor layer 21C is formed of, for example, an n-type semiconductor. The n-type semiconductor is, for example, n-GaN doped with an n-type impurity such as Si as described above.

[0048] The impurity concentration of the n-type semiconductor forming the semiconductor layer 21C is at least higher than the impurity concentration of the semiconductor forming the semiconductor layer 21B and higher than the impurity concentration of the semiconductor forming the semiconductor layer 21A. That is, in each of the plurality of columnar portions 22, the semiconductor layer 21A is formed of an i-type semiconductor, the semiconductor layer 21B is formed of an i-type semiconductor, and the semiconductor layer 21C is formed of an n-type semiconductor. - GaN, the semiconductor layer 21B is formed of i-GaN, and the semiconductor layer 21C is formed of n + GaN. That is, the impurity concentration of the first region and the impurity concentration of the second region in the semiconductor layer 21A are each lower than the impurity concentration of the semiconductor layer 21C.

[0049] Since the size in the Z direction of the semiconductor layer 21A is larger than that of the semiconductor layer 21C and the impurity concentration of the semiconductor forming the semiconductor layer 21A is lower than that of the semiconductor layer 21C, the width of the depletion layer of the FET is ensured, and the withstand voltage of the semiconductor device 11 is ensured. Also, the FET is configured in a vertical type by the plurality of columnar portions 22, the size in the Z direction of the semiconductor layer 21B is suppressed to be smaller than those of the semiconductor layers 21A and 21C, and by using GaN as the semiconductor 21, the on-resistance per unit area in the surface 30a of the semiconductor layer 30 of the semiconductor device 11 is reduced to some extent.

[0050] The semiconductor layer 20, together with the semiconductor layer 21C, constitutes a source region S. The semiconductor layer 20 extends along the XY plane, linking the semiconductor layers 21C of the plurality of columnar portions 22 to each other along the XY plane. The bottom surface 20b of the semiconductor layer 20 abuts against the surfaces 22a of the plurality of columnar portions 22. By so configuring, the semiconductor layer 20 is connected to the semiconductor layers 21C of the plurality of columnar portions 22. The semiconductor layer 20 is composed of the same kind of semiconductor as the semiconductor layers 30, 21A, 21B, and 21C, and is formed of GaN. The semiconductor layer 20 is formed of, for example, an n-type semiconductor, and in the present embodiment, like the semiconductor layer 21C, is formed of an n-type semiconductor + GaN. That is, in the semiconductor device 11, the semiconductor layer 20, the semiconductor layer 21C, and the first layer 31 of the semiconductor layer 30 are formed of an n + GaN, the semiconductor layer 21A, and the second layer 32 of the semiconductor layer 30 are formed of an n - GaN, and the semiconductor layer 21B is formed of i-GaN.

[0051] The metal layer 12 is stacked on the surface 20a of the semiconductor layer 20 for forming a contact region, and is connected to the semiconductor layer 20. The metal layer 12 opposes the metal layer 60 in the Z direction, and functions as an opposing substrate that supports the main components of the semiconductor device 11, and has a prescribed thickness. The surface 12a and the back surface 12b of the metal layer 12 are flat surfaces that are substantially parallel to the XY plane. The metal layer 12 is formed of, for example, a metal such as aluminum (Al) or Cu.

[0052] The gate electrode 50 is provided at least via the gate insulating film 40 on the side wall 21r of the semiconductor layer 21B of the channel formation region R. The gate electrode 50 has a dimension in the Z direction that is larger than the dimension of the semiconductor layer 21B in the Z direction. When viewed in the Z direction, the gate electrode 50 overlaps with the end portion of the semiconductor layer 21A on the channel formation region R side and the end portion of the semiconductor layer 21C on the channel formation region R side. That is, the dimension of the gate electrode 50 in the Z direction is larger than the dimension of the semiconductor layer 21B in the Z direction. In a plan view from the Z direction, the gate electrode 50 is provided so as to surround the periphery of each columnar portion 22. That is, in a plan view from the Z direction, the gate electrode 50 is provided so as to surround the periphery of the channel formation region R. The gate electrode 50 contains, for example, poly-silicon (Poly-Si), and is formed of Poly-Si doped with boron (B). Poly-Si doped with B also has a high work function among materials that can constitute a gate electrode. By setting the work function to be sufficiently high, it is possible to make the threshold voltage of the semiconductor device 11 positive (i.e., Normally Off).

[0053] The gate insulating film 40 is provided on the side wall 50c and the surface 50a of the gate electrode 50. That is, in the XY plane, the gate insulating film 40 is interposed between the gate electrode 50 and the semiconductor layer 21B. The gate insulating film 40 is formed of, for example, silicon oxide (SiO2).

[0054] On the surface 40a of the gate insulating film 40, the insulating layer 46 and the mask insulating film 44 are stacked in the Z direction in this order. The surface 44a of the mask insulating film 44 overlaps the surface 22a of each of the plurality of columnar portions 22 in the Z direction, and is formed to be substantially coplanar with the surface 21a of the semiconductor layer 21C. The size of the insulating layer 46 in the Z direction is larger than that of the mask insulating film 44. The insulating layer 46 is formed of, for example, glass having SiO2as a main component, or SiO2, or the like.

[0055] The insulating layer 42 is provided on the bottom surface 50b of the gate electrode 50. The insulating layer 42 is formed of, for example, glass having SiO2as a main component, or SiO2, or the like. The gate electrode 50 interposed between the plurality of columnar portions 22 is surrounded by the gate insulating film 40 and the insulating layer 42, and is electrically insulated from the semiconductor layer 21B in the semiconductor device 11. Figure 2 The prescribed regions different in the area of the cross section are connected to each other, and are configured to be able to supply a gate voltage.

[0056] The semiconductor layer 70 is provided in the Z direction between the insulating layer 42 and the second layer 32 of the semiconductor layer 30, and on the side wall 21d of the semiconductor layer 21A of the drain region D. In the XY plane, the semiconductor layer 70 is in contact with the semiconductor layer 21A. The bottom surface 70b of the semiconductor layer 70 overlaps the bottom surface 22b of each of the plurality of columnar portions 22 in the Z direction, and is formed to be substantially coplanar with the bottom surface 21b of the semiconductor layer 21A. The semiconductor layer 70 is electrically connected to the semiconductor layers 20 and 21C of the source region S via a metal plug 78 described later.

[0057] The conductive type of the semiconductor layer 70 is at least different from the conductive type of the semiconductor 21 forming the semiconductor layer 21A. The semiconductor layer 70 is formed of, for example, a p-type semiconductor. As the p-type semiconductor, for example, GaN doped with a p-type impurity can be listed. As the p-type impurity, for example, magnesium (Mg) and zinc (Zn) can be listed. Hereinafter, GaN doped with a p-type impurity will be sometimes referred to as p-GaN. In addition, p-GaN in which the impurity concentration is relatively high will be sometimes referred to as p + -GaN, and p-GaN in which the impurity concentration is relatively low will be sometimes referred to as p - -Gan. The high and low of the impurity concentration are independent of the conductivity of the semiconductor.

[0058] In the semiconductor device 11, the sidewall 21d of the semiconductor layer 21A constituting the drain region D of the plurality of columnar portions 22 is in contact with the semiconductor layer 70, and the semiconductor layers 21A, 70 form a PN junction with each other, thereby constituting an SJ structure. Specifically, an SJ structure is provided by the semiconductor layer 21A formed of n - -GaN and the semiconductor layer 70 formed of p + -GaN. By the SJ structure of the semiconductor layer 70, a depletion layer Em supporting the semiconductor layer 21A from the radially outer side along the XY plane is formed. Thereby, as described above, the withstand voltage of the vertical FET of each of the plurality of columnar portions 22 can be ensured, and the on-resistance can be reduced as much as possible. By reducing the on-resistance per unit area of the surface 30a of the semiconductor layer 30, the switching frequency at the time of switching the semiconductor device 11 can be increased. As a result, the power density of the power source of the semiconductor device 11 is increased, and high performance as a power device is achieved. In addition, the semiconductor layer 70 can be provided to the sidewall of the second region, or can be provided to the sidewall of the first region. It can also be provided to the sidewall of both the first region and the second region. By providing the semiconductor layer 70 to the sidewall of the second region having a low impurity concentration, the extension of the depletion layer Em from the radially outer side along the XY plane can be increased, and the on-resistance can be reduced while ensuring the withstand voltage of the FET.

[0059] In the Z direction, between the gate electrode 50 and the semiconductor layer 20, an insulating layer 46 and a mask insulating film 44 are provided in this order in the direction opposite to the Z direction. The surface 44a of the mask insulating film 44 overlaps with the surface 22a of each of the plurality of columnar portions 22 in the Z direction, and is formed to be substantially coplanar with the surface 21a of the semiconductor layer 21C. The columnar portions 22 adjacent to each other on the XY plane are separated from each other by the semiconductor layer 70, the insulating layer 42, the gate insulating film 40, the insulating layer 46, and the mask insulating film 44. The insulating layer 46 is formed of, for example, glass having SiO2 as a main component, or SiO2 or the like, like the insulating layer 42. The mask insulating film 44 is formed of, for example, SiO2 or silicon nitride (SiN).

[0060] The semiconductor device 11 also includes a metal plug 78 and a conductive layer 80. The metal plug 78 connects the metal layer 12 and the semiconductor layer 70 in the Z direction. The surface 78a of the metal plug 78 abuts against the back surface 12b of the metal layer 12. The bottom surface 78b of the metal plug 78 abuts against the surface 70a of the semiconductor layer 70. The metal plug 78 passes through the semiconductor layer 20, mask insulating film 44, insulating layer 46, gate insulating film 40, and insulating layer 42 between the metal layer 12 and the semiconductor layer 70 in the Z direction, in the region where the plurality of pillars 22 are not formed in the XY plane. The metal plug 78 is electrically connected to the semiconductor layer 21C of each of the plurality of pillars 22 via the semiconductor layer 20 constituting the source region S. Therefore, the source voltage supplied from the metal layer 12 to the semiconductor layers 20 and 21C is also supplied to the semiconductor layer 70 via the metal plug 78. The metal plug 78 is formed of a conductive material. Examples of conductive materials mentioned above include (tungsten) W. The metal plug 78 corresponds to the "metal conductive layer" described in the claims.

[0061] The conductive layer 80 is connected to the gate electrode 50 in a predetermined region where multiple columnar portions 22 are not formed in the XY plane, and directly supplies a gate voltage to the gate electrode 50. The conductive layer 80 extends in the Z direction through the insulating layer 46 and the mask insulating film 44 stacked on the gate electrode 50 in the predetermined region.

[0062] like Figure 1 As shown, in regions other than the area where multiple columnar portions 22 are formed in the XY plane, for example, between metal layers 12 and 60, and between semiconductor layer 70, semiconductor layer 20 of source region S, multiple columnar portions 22, etc., an interlayer insulating layer 200 is appropriately provided.

[0063] In the semiconductor device 11 described above, the impurity concentration of semiconductor layer 21B is set to be lower than that of semiconductor layers 21A and 21C. When a positive voltage exceeding a threshold is not supplied to the gate electrode 50, no current flows between the drain region D and the source region S. When the gate voltage is 0V and a voltage less than the threshold is supplied to the gate electrode 50, region Ch of semiconductor layer 21B is almost completely depleted. When a positive voltage exceeding the threshold is supplied to the gate electrode 50, a channel region Ch is formed in semiconductor layer 21B adjacent to the gate electrode 50 via the gate insulating film 40. The n of semiconductor layer 21C forming the source region S... + - The electrons of GaN and the semiconductor layer 21A that forms the drain region D -- The electrons of the GaN are strongly attracted to the region Ch, and the region Ch becomes a flow path for the electrons, through which a current flows between the drain region D and the source region S. The size of the region Ch of the channel formed in the channel formation region R is controlled by the voltage supplied to the gate electrode 50, and the value of the current flowing between the drain region D and the source region S varies. The current between the drain region D and the source region S is controlled by the gate electrode 50.

[0064] In the semiconductor device 11, the SJ structure is formed by interposing the semiconductor layer 70 between the semiconductor layers 21A in the XY plane as described above. In the semiconductor device 11, the depletion layer Em extends from the interface of the semiconductor layers 21B, 21A to the interface of the semiconductor layers 21A, 30. The depletion layer Em is formed in the semiconductor layer 70. + The two sides of the semiconductor layer 70 formed of GaN are separated and formed along the side wall 21d. Therefore, the interface at which the difference in impurity concentration is large is extended more than in the semiconductor device not having the SJ structure, and thus the maximum value of the electric field strength is lower than in the semiconductor device not having the SJ structure, and is substantially fixed from the interface of the semiconductor layers 21B, 21A to the interface of the semiconductor layers 21A, 30. In general, in order to not cause breakdown in a semiconductor device, the withstand voltage is set to be not more than the maximum value of the electric field strength determined by the material of the semiconductor. In addition, when the horizontal axis is set as the position in the Z direction and the vertical axis is set as the electric field strength, the withstand voltage of the semiconductor device is determined by the distribution area of the electric field strength. In the semiconductor device 11, it is possible to reduce the maximum value of the electric field strength while securing the area of the distribution of the electric field strength. In the semiconductor device 11, it is possible to increase the carrier concentration in accordance with the amount by which the maximum value of the electric field strength is reduced, and as a result, it is possible to suppress the on-resistance to be lower.

[0065] (Method of manufacturing semiconductor device)

[0066] Next, the method of manufacturing the semiconductor device 11 of the present embodiment will be described. Figures 3-20 Each of the drawings is a cross-sectional view showing each process of the method of manufacturing the semiconductor device 11.

[0067] As shown in FIG. 1, first, a surface 110a of a substrate 110 for GaN crystal growth is prepared. Figure 3 For example, by a molecular beam epitaxy (MBE) method, or an MOCVD method (Metal Organic Chemical Vapor Deposition), n + -GaN crystal growth, and a semiconductor layer 20 is formed. As the substrate 110, for example, a sapphire substrate can be used.

[0068] Next, on the surface 20a of the semiconductor layer 20, a SiO2 film is formed by, for example, a Chemical Vapor Deposition (CVD) method or a Physical Vapor Deposition (PVD) method, and a mask insulating film 44 is formed. Next, by, for example, a photolithography method and an etching method, only the mask insulating film 44 stacked on the region of the surface 20a of the semiconductor layer 20 where the plurality of columnar portions 22 are formed is removed, and the surface 20a of the semiconductor layer 20 of the region is exposed.

[0069] Next, on the surface 20a of the semiconductor layer 20 exposed in the above process, n + -GaN is crystallized and grown on the surface 122a to a prescribed height in the Z direction, and the semiconductor layer 21A is formed. Alternatively, the 21C, 21B, and 21A can be formed continuously by making the dopant concentration, for example, the Si concentration variable. That is, in the manufacturing method of the semiconductor device 11, the semiconductor 21 constituting the columnar portion 22 is formed from the semiconductor layer 20 which becomes the source region S later, upward in the Z direction. - -GaN is crystallized and grown on the surface 122a to a prescribed height in the Z direction, and the semiconductor layer 21A is formed. Alternatively, the 21C, 21B, and 21A can be formed continuously by making the dopant concentration, for example, the Si concentration variable. That is, in the manufacturing method of the semiconductor device 11, the semiconductor 21 constituting the columnar portion 22 is formed from the semiconductor layer 20 which becomes the source region S later, upward in the Z direction.

[0070] The surface 123a of the semiconductor layer 21A can have a concavo-convex with respect to the XY plane, or can be planarized. Figure 3 In addition, if the semiconductor layers 21C, 21B, and 21A are each grown by MBE, a concavo-convex is generated on each surface. Therefore, it is preferable that the minimum dimension in the Z direction of each of the semiconductor layers 21C, 21B, and 21A becomes Figure 2 In addition, if the semiconductor layers 21C, 21B, and 21A are each grown by MBE, a concavo-convex is generated on each surface. Therefore, it is preferable that the minimum dimension in the Z direction of each of the semiconductor layers 21C, 21B, and 21A becomes

[0071] Next, for example, by a spin coating method, a SOG (Spin-on-Glass) liquid is applied so as to cover the surface 44a of the mask insulating film 44, that is, the bottom surface later, and the columnar body 25 constituted by the semiconductor layers 21C, 21B, and 21A, and is processed, as shown in FIG. 6B. Figure 4As shown, an insulating layer 46 composed of SiO2 or the like is formed. Through this process, the sidewalls 21r of semiconductor layer 21B, the sidewalls of semiconductor layers 21C and 21A, and the surface of semiconductor layer 21A are in contact with the insulating layer 46. The surface 46a of the insulating layer 46 is located above, i.e., in front of, the Z-direction front of the columnar body 25.

[0072] Next, as Figure 5 As shown, the insulating layer 46 is etched back until the surface 46b reaches a position moderately rearward in the Z direction than the bottom surface 21t of the semiconductor layer 21B of the columnar body 25, i.e., the subsequent surface.

[0073] Next, for example, by atomic layer deposition (ALD), SiO2 is deposited into a film to cover the surface 46b of the insulating layer 46 and the sidewalls and surfaces of the exposed columnar bodies 25, such as... Figure 6 The gate insulating film 40 is formed as shown.

[0074] Next, from the surface of the gate insulating film 40 stacked on the insulating layer 46, i.e., the subsequent bottom surface 40b, to the full coverage position of the gate insulating film 40 covering the pillar 25, B-doped Poly-Si is deposited in the Z direction, as follows: Figure 7 As shown, a precursor layer 52 is formed to form the gate electrode 50. Boron doping can also be achieved by implanting boron ions into Poly-Si to allow for thermal diffusion. Next, the precursor layer 52 is etched back until surface 52a reaches a position moderately forward in the Z direction than surface 21p of the semiconductor layer 21B of the pillar 25, i.e., the subsequent bottom surface, thus achieving the desired effect. Figure 8 The gate electrode 50 is formed as shown.

[0075] Next, wet etching is performed using, for example, a chemical solution, such as... Figure 9 As shown, the gate insulating film 40 exposed in the Z direction from the surface of the gate electrode 50, i.e., the subsequent bottom surface 50b, is removed. Through this process, a gate insulating film 40 surrounding the sidewalls 50c and surface 50a of the gate electrode 50 is formed.

[0076] Next, through-holes 54 are formed in the area of ​​the gate electrode 50 in the XY plane where the plurality of pillars 22 are not formed, for example, by photolithography and etching. The through-holes 54 penetrate only the gate electrode 50 in the Z direction. At the bottom of the through-holes 54, the surface of the gate insulating film 40, i.e., the subsequent bottom surface 40b, is exposed.

[0077] Next, SOG liquid is applied and treated in a manner that fills the through-hole 54 and covers the columnar body 25 that protrudes further in the Z direction and is exposed than the bottom surface 50b of the gate electrode 50, as follows: Figure 11 An insulating layer 42 is formed as shown. Next, as...Figure 12 As shown, the insulating layer 42 is subjected to CMP (Chemical Mechanical Polishing) or etching back until the surface of the insulating layer 42, i.e., the subsequent bottom surface 42b, reaches a position that is moderately forward in the Z direction than the bottom surface 50b of the gate electrode 50, i.e., moderately higher than the gate electrode 50. At this point, the bottom surface 42b of the insulating layer 42 is made flat.

[0078] Next, as Figure 13 As shown, for example, p is deposited by metal-organic chemical vapor deposition (MOCVD) in a manner that covers the columnar bodies 25 protruding and exposed in the Z direction from the bottom surface 42b of the insulating layer 42. + -GaN, forming a semiconductor layer 70.

[0079] Next, the Z-direction front portion of the semiconductor layer 70 is removed using a thermal etching method, such as phosphoric acid. Figure 14 As shown, the surface of semiconductor layer 70, i.e., the bottom surface 70b thereafter, is aligned with the rearmost side of the uneven surface of semiconductor layer 21A in the Z direction, and is slightly forward in the Z direction than the surface 21p of semiconductor layer 21B, i.e., higher than semiconductor layer 21B. In this process, the bottom surface 70b of semiconductor layer 70 is aligned in the Z direction with the bottom surfaces 22b of each of the plurality of columnar portions 22 and the bottom surface of semiconductor layer 21A, and is coplanar with the bottom surfaces 22b. Through this process, a plurality of columnar portions 22 protruding from the bottom surface 20b of semiconductor layer 20 in the Z direction are formed.

[0080] Next, as Figure 15 As shown, on the entire flat surface formed by the bottom surface 22b of each of the plurality of columnar portions 22 and the bottom surface 70b of the semiconductor layer 70, for example by MBE, n - GaN crystals are grown to a predetermined height in the Z direction, forming the second layer 32 of the semiconductor layer 30. Next, on the surface of the second layer 32, i.e., the subsequent bottom surface 32b, n is formed, for example, by MBE. + -GaN crystals grow to a specified height in the Z direction to form the first layer 31 of the semiconductor layer 30.

[0081] Next, an adhesive (not shown) is applied to the surface of the first layer 31 of the semiconductor layer 30, i.e., the subsequent bottom surface 31b, such as... Figure 16 As shown, the metal layer 60 is bonded to the bottom surface 31b via an adhesive. For example, an ultraviolet-curable resin or a thermosetting resin can be used as the adhesive, but there are no particular limitations as long as the metal layer 60 can be well bonded to the bottom surface 30b of the semiconductor layer 30. For example, a bonding metal can be deposited instead of an adhesive.

[0082] Next, the substrate 110 is removed from the laminated structure 140 of the substrate 110, the semiconductor layers 20, 21C, 21B, 21A, the mask insulating film 44, the insulating layer 46, the gate insulating film 40, the gate electrode 50, the insulating layer 42, the semiconductor layer 70, 30, and the metal layer 60 manufactured up to the preceding step. Specifically, as shown in FIG. 8, the laminated structure 140 is reversed in the Z direction, and, for example, a laser lift off (LLO) process is performed. In the LLO process, laser light HL from a high-power laser light source not shown is irradiated from the rear in the Z direction with respect to the substrate 110, and, as shown in FIG. 9, the substrate 110 is peeled from the surface 20a of the semiconductor layer 20. In the case where the substrate 110 is a sapphire substrate, the high-power laser light source is preferably a KrF excimer laser. In the case where the KrF excimer laser is used, the central wavelength of the laser light HL is about 248 nm. Figure 17 Figure 18

[0083] Next, in the region of the semiconductor layer 20 in which the plurality of columnar portions 22 are not formed in the XY plane, a region in which the metal plug 78 shown in FIG. 10 and FIG. 11 is formed is formed, and, as shown in FIG. 12, a through-hole 56 is formed. The through-hole 56 reaches the surface 70a of the semiconductor layer 70 in the Z direction from the surface 20a of the semiconductor layer 20 exposed by peeling the substrate 110. The through-hole 56 can be formed, for example, by photolithography and a dry etching method. Next, for example, by a CVD method, a conductive material such as tungsten (W) is deposited in the through-hole 56 and the rear in the Z direction with respect to the through-hole 56. Then, the conductive layer is etched back until the surface of the conductive layer composed of the deposited conductive material is coplanar with the surface 20a of the semiconductor layer 20. By this step, as shown in FIG. 13, the metal plug 78 is formed. Figure 1 Figure 2 Figure 19 Figure 20

[0084] Next, in the region of the semiconductor layer 20 in which the plurality of columnar portions 22 are not formed in the XY plane, a region in which the metal plug 78 shown in FIG. 10 and FIG. 11 is formed is formed, and, as shown in FIG. 12, a through-hole 56 is formed. The through-hole 56 reaches the surface 70a of the semiconductor layer 70 in the Z direction from the surface 20a of the semiconductor layer 20 exposed by peeling the substrate 110. The through-hole 56 can be formed, for example, by photolithography and a dry etching method. Next, for example, by a CVD method, a conductive material such as tungsten (W) is deposited in the through-hole 56 and the rear in the Z direction with respect to the through-hole 56. Then, the conductive layer is etched back until the surface of the conductive layer composed of the deposited conductive material is coplanar with the surface 20a of the semiconductor layer 20. By this step, as shown in FIG. 13, the metal plug 78 is formed. Figure 1 Figure 2 Figure 20

[0085] Next, the surface of the semiconductor layer 20 and the surface 78a of the metal plug 78 in the region of the semiconductor layer 20 overlapping the plurality of columnar portions 22 in the XY plane are coated with an adhesive not shown, and the metal layer 12 is adhered via the adhesive. Furthermore, this step can be performed after the metal plug 78 described above is formed and before the conductive layer 80 is formed.​​​​​​​​​

[0086] In addition, although not shown, in a region other than the region in which the plurality of columnar portions 22 are formed in the XY plane, a through hole is formed by, for example, removing the interlayer insulating layer in the Z direction from the region of the gate conductive layer that is in contact with the gate electrode 50 by photolithography and dry etching. In addition, a through hole is formed by, for example, removing the interlayer insulating layer in the Z direction from the region of the source conductive layer that is in contact with the semiconductor layer 20 of the source region S by photolithography and CNT etching. Subsequently, tungsten (W) is deposited in each of the through holes and in the rear of the through holes in the Z direction by, for example, CVD, thereby forming the gate conductive layer and the source conductive layer. Then, the gate conductive layer and the source conductive layer are etched back until the surfaces of the gate conductive layer and the source conductive layer are flush with the surface 20a of the semiconductor layer 20. The gate metal layer and the source metal layer are bonded to the surfaces of the gate conductive layer and the source conductive layer using an adhesive. This process can be performed at an appropriate timing in consideration of the above-described processes. Alternatively, in the region other than the region in which the plurality of columnar portions 22 are formed in the XY plane, a bonding wire that is in contact with the gate electrode 50 can be formed, for example. In addition, a bonding wire can be formed on the metal layer 12.

[0087] By performing the above-described processes, the semiconductor device 11 shown in FIGS. 1 to 6 is manufactured. Figure 1 and Figure 2 The main configuration of the semiconductor device 11 shown in FIGS. 1 to 6 is completed by performing the above-described processes.

[0088] (EFFECTS)

[0089] The semiconductor device 11 of the above-described embodiment includes the plurality of columnar portions 22 composed of the semiconductor 21. The plurality of columnar portions 22 each include the source region S, the drain region D, the channel formation region R, the gate electrode 50, and the semiconductor layer 70. The channel formation region R includes a region (channel region) Ch in which the channel is formed in the Z direction between the source region S and the drain region D. The gate electrode 50 is provided to the side wall 21r of the semiconductor layer 21B that forms the channel formation region R with the gate insulating film 40 interposed therebetween. The semiconductor layer 70 is provided to the side wall 21d of the semiconductor layer 21A that forms the drain region D. The conductive type of the semiconductor layer 70 is different from the conductive type of the semiconductor 21 of the semiconductor layer 21A.

[0090] In the semiconductor device 11 of the present embodiment, the vertical FETs having the GAA structure are formed by the plurality of columnar portions 22 and the gate electrodes 50 adjacent to the channel formation regions R with the gate insulating films 40 interposed therebetween. In the semiconductor device 11, the columnar portions 22 having a very small pitch of, for example, 0.5 μm or less in the XY plane are realized. In addition, by providing the semiconductor layer 70 adjacent to the semiconductor layer 21A of each of the drain regions D of the plurality of columnar portions 22 in the direction along the XY plane, that is, in the lateral direction, an SJ structure is formed, and the withstand voltage of the plurality of columnar portions 22 is supported in the lateral direction. Therefore, according to the semiconductor device 11 of the present embodiment, as compared with the plurality of columnar portions 22 not having the semiconductor layer 70, a significant super low on-resistance can be realized.

[0091] The plurality of columnar portions 22 of the semiconductor device 11 of the present embodiment are not formed in a top-down manner by using a dry etching process as in the conventional semiconductor device, but are formed in a bottom-up manner, for example, from the semiconductor layer 20. Specifically, the semiconductor layer 20 is formed in a bottom-up manner from the n + The bottom surface 20b of the semiconductor layer 20 composed of GaN is crystallized and grown in the Z direction in the order of the n + GaN, i - GaN, n - GaN, by growing GaN in a bottom-up manner like this, the base end side end portion does not expand more than the tip end side end portion as in the conventional semiconductor nanowire, and a columnar portion 22 having a small pitch and high crystallinity can be formed.

[0092] In addition, in the semiconductor device 11 of the present embodiment, the gate electrode 50 is composed of Poly-Si, and is doped with Br. Specifically, the gate electrode 50 is formed of Poly-Si doped with Br. Further, the semiconductor 21 of the semiconductor layers 21C, 21A, and 21B constituting the source regions S, the drain regions D, and the channel formation regions R of each of the plurality of columnar portions 22 is GaN. As described above, in the plurality of columnar portions 22 composed of the GAA structure, the gate electrode 50 is formed of a material having a high work function, whereby the driving voltage of the semiconductor device 11 can be increased, and normally-off can be reliably realized. In particular, by using p-type Poly-Si, normally-off is easily realized. The high current driving capability and normally-off are in a trade-off relationship, but according to the semiconductor device 11 of the present embodiment, Poly-Si doped with Br is adopted as the material of the gate electrode 50, and therefore the high current driving capability and normally-off can be balanced.

[0093] In addition, in the semiconductor device 11 of this embodiment, the semiconductor layer 70 is electrically connected to the source region S and the semiconductor layer 20, 21C that configures the source region S. According to the semiconductor device 11 of this embodiment, the source voltage is supplied to the semiconductor layer 70, and the semiconductor layer 21A of the drain region D of the columnar portion 22 supports the depletion layer Em, and thus a voltage resistance can be obtained.

[0094] In addition, in the semiconductor device 11 of this embodiment, the semiconductor layer 20 is connected to the semiconductor layer 21C that configures the source region S of each of the plurality of columnar portions 22. According to the semiconductor device 11 of this embodiment, in the source region S, the semiconductor layer 20 is interposed between the plurality of columnar portions 22 that are small in diameter in the XY plane and the metal layer 12 that extends in the XY plane, and thus an increase in contact resistance in the connection between the semiconductor layer 21C and the metal layer 12 that is a contact terminal on the source side can be suppressed, and a decrease in performance can be prevented, and the semiconductor device 11 can operate favorably.

[0095] In addition, in the semiconductor device 11 of this embodiment, the semiconductor layer 30 is connected to the semiconductor layer 21A that configures the drain region D of each of the plurality of columnar portions 22. Thus, according to the semiconductor device 11 of this embodiment, in the drain region D in addition to the source region S, by interposing the semiconductor layer 30 between the semiconductor layer 21A of the plurality of columnar portions 22 that are small in diameter in the XY plane and the metal layer 60 that extends in the XY plane, an increase in contact resistance in the connection between the semiconductor layer 21A and the metal layer 60 that is a contact terminal on the drain side can be suppressed, and a decrease in performance can be prevented.

[0096] In addition, in the semiconductor device 11 of this embodiment, the semiconductor 21 and the semiconductor layer 20 each have an n-type conductivity type, and the semiconductor layer 70 has a p-type conductivity type. Thus, in each of the plurality of columnar portions 22, the region Ch of the channel can be substantially completely depleted, and the movement speed of the electric charge can be increased. As a result, the switching speed and the operation performance of the semiconductor device 11 can be improved.

[0097] In addition, in the semiconductor device 11 of this embodiment, the metal layer 12 is connected to the semiconductor layer 20 on the source side. According to the semiconductor device 11 of this embodiment, an increase in contact resistance between the semiconductor layer 21C and the metal layer 12 that is a contact terminal on the source side having high conductivity can be favorably suppressed. In addition, in the semiconductor device 11 of this embodiment, the metal layer 60 is connected to the semiconductor layer 30 on the drain side. The semiconductor layer 30 has a stacked structure of the first layer 31 and the second layer 32. The semiconductor layer 21A and the second layer 32 are each formed of n - GaN, and the first layer 31 is formed of n +- GaN formation. That is, the conductivity is improved in the order of the semiconductor layer 21C, the second layer 32, the first layer 31, and the metal layer 60. Thus, according to the semiconductor device 11 of the present embodiment, the increase in the contact resistance between the semiconductor layer 21A and the metal layer 12 as a contact terminal having high conductivity on the drain side can be effectively suppressed. Further, by the metal layers 12, 60 functioning as the element substrate and the counter substrate of the semiconductor device 11, a thin and light semiconductor device 11 can be realized.

[0098] Further, in the semiconductor device 11 of the present embodiment, the n - The impurity concentration of the semiconductor layer 21A composed of GaN is lower than that of the semiconductor layer 30 composed of GaN and the first layer 31 composed of GaN, respectively. Thus, the direct coupling of the charge movement caused by the PN junction of the semiconductor layer 21A and the semiconductor layer 70 to the first layer 31 of the semiconductor layer 30 can be suppressed, and the occurrence of breakdown in the semiconductor device 11 can be prevented. + The impurity concentration of the semiconductor layer 70 composed of GaN and the first layer 31 composed of GaN is lower than that of the semiconductor layer 30 composed of GaN, respectively. Thus, the direct coupling of the charge movement caused by the PN junction of the semiconductor layer 21A and the semiconductor layer 70 to the first layer 31 of the semiconductor layer 30 can be suppressed, and the occurrence of breakdown in the semiconductor device 11 can be prevented. + The impurity concentration of the semiconductor layer 70 composed of GaN and the first layer 31 composed of GaN is lower than that of the semiconductor layer 30 composed of GaN, respectively. Thus, the direct coupling of the charge movement caused by the PN junction of the semiconductor layer 21A and the semiconductor layer 70 to the first layer 31 of the semiconductor layer 30 can be suppressed, and the occurrence of breakdown in the semiconductor device 11 can be prevented.

[0099] Further, in the semiconductor device 11 of the present embodiment, the source region S is connected to the metal layer 12 and the semiconductor layer 70 by the metal plug 78 which penetrates the semiconductor layer 20 in the Z direction. According to the semiconductor device 11 of the present embodiment, the source voltage is smoothly supplied from the metal layer 12 to the semiconductor layers 20, 70 via the metal plug 78, and the semiconductor layer 21A of the drain region D of the columnar portion 22 supports the depletion layer Em, and a withstand voltage can be obtained. The metal plug 78 can be easily and stably manufactured using the processes of etching and deposition, compared to the case where the source region S is connected to the metal layer 12 and the semiconductor layer 70 by a plug formed of a semiconductor or the like. Thus, the reliability of the operation of the semiconductor device 11 can be improved.

[0100] The above describes the preferred embodiments of the present application, but the present application is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present application described in the claims. Further, the constituent elements of the plurality of embodiments can be appropriately combined.

[0101] Further, the semiconductor device of one embodiment of the present application can be applied to a power device such as an inverter, but the use of the semiconductor device of the present application is not limited to a power device. For example, the semiconductor device of the present application can be mounted on a vehicle such as an automobile or a moving object such as an airplane, and can be applied to a semiconductor device or a switching device that requires an ultra-low on-resistance. In the semiconductor device of the present application, the material of each component can be changed depending on the use of the semiconductor device, without hindering the effects of the plurality of columnar portions 22 functioning as FETs and the SJ structure.

[0102] For example, in the semiconductor device of the present application, the semiconductor that forms the source region S, the drain region D, and the channel formation region R of each of the plurality of columnar portions is not limited to n-GaN and is not limited to GaN. If allowed in the use of the semiconductor device of the present application, the semiconductor of the columnar portion can be Si, gallium arsenide (GaAs), silicon carbide (SiC), or the like. Further, the semiconductor of the columnar portion preferably has an electrical characteristic corresponding to each region of the FET by changing the impurity concentration.

[0103] For example, in the case where the semiconductor device of the present application is used for a power device such as an inverter, the gate electrode is preferably formed of Poly-Si doped with Br, in accordance with the case where the semiconductor that forms each of the plurality of columnar portions is n-GaN. However, if the semiconductor that forms the FET of the semiconductor device of the present application is SiC and is allowed in the use of the semiconductor device, the gate electrode can be formed of, for example, Al, W, or a conductive material containing these metals. In that case, it is also preferable that the gate electrode have a high work function with respect to the semiconductor that forms the columnar portion.

[0104] The semiconductor device of one embodiment of the present application can have the following structure.

[0105] A semiconductor device of one embodiment of the present application includes a plurality of columnar portions each including a source region, a drain region, and a channel formation region between the source region and the drain region. The semiconductor device of one embodiment of the present application also includes a gate electrode provided to a side wall of the channel formation region with an insulating layer interposed therebetween, and a first semiconductor layer provided to a side wall of the drain region. The first semiconductor layer has a conductivity type different from that of the semiconductor that forms the drain region.

[0106] In the semiconductor device of one embodiment of the present application, the gate electrode can be formed of polysilicon.

[0107] In the semiconductor device of one embodiment of the present application, the gate electrode can be doped with boron.

[0108] In the semiconductor device of one embodiment of the present application, the semiconductor can be gallium nitride.

[0109] In the semiconductor device of one embodiment of the present application, the first semiconductor layer can be electrically connected to the source region.

[0110] In the semiconductor device of one embodiment of the present application, the second semiconductor layer can be connected to the source region of each of the plurality of columnar portions.

[0111] In the semiconductor device of one embodiment of the present application, each of the semiconductor and the second semiconductor layer can be n-type, and the first semiconductor layer can be p-type.

[0112] In the semiconductor device of one embodiment of the present application, the metal layer can be connected to the second semiconductor layer.

[0113] In the semiconductor device of one embodiment of the present application, the source region can be connected to the metal layer and the first semiconductor layer with a metal plug that penetrates through the second semiconductor layer.

[0114] In the semiconductor device of one embodiment of the present application, the drain region can include a first region and a second region between the first region and the channel formation region, and the second region can have a lower impurity concentration than the first region.

[0115] In the semiconductor device of one embodiment of the present application, the first semiconductor layer can be provided on a side wall of the second region.

Claims

1. A semiconductor device, comprising: a plurality of columnar portions composed of a semiconductor, each of the plurality of columnar portions having: a source region; a drain region; and a channel formation region between the source region and the drain region, the semiconductor device further comprising: a gate electrode disposed on a side wall of the channel formation region through an insulating layer, the gate electrode controlling a current between the source region and the drain region; and a first semiconductor layer disposed on a side wall of the drain region, a conduction type of the first semiconductor layer being different from a conduction type of the semiconductor forming the drain region, a second semiconductor layer connected to the source region of each of the plurality of columnar portions, each of the source region, the drain region, and the second semiconductor layer being of an n-type, the conduction type of the first semiconductor layer being of a p-type.

2. The semiconductor device according to claim 1, wherein: the gate electrode is composed of polysilicon.

3. The semiconductor device according to claim 2, wherein: the gate electrode is doped with boron.

4. The semiconductor device according to any one of claims 1 to 3, wherein: the semiconductor is gallium nitride.

5. The semiconductor device according to any one of claims 1 to 3, wherein: the first semiconductor layer is electrically connected to the source region.

6. The semiconductor device according to claim 1, wherein: a metal layer is connected to the second semiconductor layer.

7. The semiconductor device according to claim 6, wherein: the metal layer and the first semiconductor layer are connected by a metal conductive layer that penetrates the second semiconductor layer.

8. The semiconductor device according to any one of claims 1 to 3, wherein: the drain region includes: a first region; and a second region between the first region and the channel formation region, an impurity concentration of the second region being lower than an impurity concentration of the first region.

9. The semiconductor device according to claim 8, wherein: the first semiconductor layer is disposed on a side wall of the second region. ​ ​

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