Semiconductor Structure and Method for Forming the Same

Abstract

The technical solution of the present application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate, the surface of the semiconductor substrate includes a buried oxide layer; a thermal conduction layer, located on the surface of the buried oxide layer, and having a first extension extending into the buried oxide layer and connected to the semiconductor substrate and a second extension extending away from the buried oxide layer; an insulating layer, located on the surface of the thermal conduction layer, and coplanar with the surface of the second extension; a channel layer, located on the surface of the second extension and part of the insulating layer; a gate structure, located on the surface of the channel layer; a source electrode and a drain electrode, respectively located in the channel layer on both sides of the gate structure. The semiconductor structure and the method for forming the same according to the technical solution of the present application can improve the self-heating effect of the device and improve the high-frequency performance of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuits, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Although SOI (Silicon-On-Insulator) devices have excellent subthreshold swing characteristics, low source / drain capacitance, and suppression of latch-up effects, etc., due to the low thermal conductivity of the buried oxide, the channel will become hotter and suffer from severe self-heating effect (SHE), resulting in large power consumption of the device.

[0003] The hotter channel will lead to a decrease in mobility and output conductivity. For example, due to the self-heating effect, the drain-source current I ds will be significantly reduced. Especially during electrostatic discharge (ESD) or in circuits that require impedance matching, the self-heating effect will affect the device performance and reliability of SOI circuits. Summary of the Invention

[0004] The technical problem to be solved by this application is to improve the self-heating effect of the device and enhance the high-frequency performance of the device.

[0005] To solve the above technical problem, this application provides a semiconductor structure, including: a semiconductor substrate, the surface of the semiconductor substrate includes a buried oxide layer; a thermal conduction layer, located on the surface of the buried oxide layer, and having a first extension extending into the buried oxide layer and connected to the semiconductor substrate and a second extension extending away from the buried oxide layer; an insulating layer, located on the surface of the thermal conduction layer, and coplanar with the surface of the second extension; a channel layer, located on the surface of the second extension and a part of the insulating layer; a gate structure, located on the surface of the channel layer; a source electrode and a drain electrode, respectively located in the channel layer on both sides of the gate structure.

[0006] In an embodiment of this application, the distance between the plane where the adjacent side walls of the first extension and the second extension are located is not less than 10 nm.

[0007] In an embodiment of this application, the width of the first extension is 50 nm - 1000 nm.

[0008] In an embodiment of this application, the thickness of the thermal conduction layer between the channel layer and the buried oxide layer is 100 nm - 5000 nm.

[0009] In an embodiment of this application, the ratio range of the distance between the side wall of the second extension and the side wall of the channel layer to the width of the second extension is 0 - 0.5.

[0010] In an embodiment of the present application, the semiconductor structure further includes an isolation structure located on the sidewalls of the source and drain electrodes.

[0011] In an embodiment of the present application, the thickness of the insulating layer is 50 nm - 1000 nm.

[0012] In an embodiment of the present application, the thickness of the buried oxide layer is 10 nm - 1000 nm.

[0013] In an embodiment of the present application, the resistivity of the semiconductor substrate is not less than 3000 Ω·cm.

[0014] In an embodiment of the present application, the material of the heat-conducting layer includes at least one of polysilicon, amorphous carbon, silicon nitride, and silicon carbonitride.

[0015] In an embodiment of the present application, the materials of the buried oxide layer and the insulating layer include silicon dioxide, and the material of the channel layer includes silicon.

[0016] The present application also provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, the surface of which includes a buried oxide layer; forming a heat-conducting layer located on the surface of the buried oxide layer and having a first extension extending into the buried oxide layer and connected to the semiconductor substrate and a second extension extending away from the buried oxide layer; forming an insulating layer on the surface of the heat-conducting layer, and the insulating layer is coplanar with the surface of the second extension; forming a channel layer on the surfaces of the second extension and a part of the insulating layer; forming a gate structure on the surface of the channel layer, and forming a source and a drain in the channel layer on both sides of the gate structure respectively.

[0017] In an embodiment of the present application, the method for forming the heat-conducting layer includes: etching a part of the buried oxide layer and stopping at the surface of the semiconductor substrate, and filling a heat-conducting material at a corresponding position to form the first extension in the buried oxide layer, and the heat-conducting material extends to the surface of the buried oxide layer; planarizing the heat-conducting material to form a heat-conducting layer, and forming a first barrier layer on the surface of the heat-conducting layer; etching a part of the first barrier layer and the heat-conducting layer to form the second extension.

[0018] In an embodiment of the present application, the method for forming an insulating layer on the surface of the heat-conducting layer includes: forming an insulating material layer on the surface of the heat-conducting layer; planarizing the insulating material layer until the surface of the first barrier layer is exposed; removing the first barrier layer and making the surface of the insulating material layer coplanar with the surface of the second extension to form the insulating layer.

[0019] In the embodiment of the present application, the method of forming a channel layer on the surface of the second extension portion and a part of the insulating layer includes: laminating a silicon layer with a specific thickness on the surface of the second extension portion and the insulating layer; forming a second barrier layer on the surface of the silicon layer; etching the second barrier layer and the silicon layer until a part of the insulating layer is exposed to form the channel layer.

[0020] In the embodiment of the present application, the method of laminating a silicon layer with a specific thickness on the surface of the second extension portion and the insulating layer includes: providing a silicon layer; laminating the silicon layer on the surface of the second extension portion and a part of the insulating layer; back-etching or polishing the silicon layer to a specific thickness.

[0021] In the embodiment of the present application, the method of laminating a silicon layer with a specific thickness on the surface of the second extension portion and the insulating layer includes: providing a silicon layer, the silicon layer including a first surface; injecting hydrogen ions and / or inert gas ions into the silicon layer from the first surface to form a peeling layer at a specific depth in the silicon layer; using the first surface as the lamination surface, laminating the silicon layer on the surface of the second extension portion and a part of the insulating layer; performing a peeling heat treatment to remove the peeling layer and the silicon layer on one side of the peeling layer, and forming a silicon layer with a specific thickness on the surface of the second extension portion and a part of the insulating layer.

[0022] In the embodiment of the present application, after etching the second barrier layer and the silicon layer, it further includes: filling an isolation material at the corresponding position; removing the second barrier layer and making the surface of the isolation material and the channel layer coplanar to form an isolation structure on the sidewall of the channel layer.

[0023] In the embodiment of the present application, the method for forming the semiconductor structure further includes: forming a self-aligned metal silicide on the surface of the gate structure, the source electrode, and the drain electrode.

[0024] In the embodiment of the present application, the distance between the planes where the adjacent sidewalls of the first extension portion and the second extension portion are located is not less than 10 nm, the width of the first extension portion is 50 nm - 1000 nm, the thickness of the heat conduction layer between the channel layer and the buried oxide layer is 100 nm - 5000 nm, and the ratio range of the distance between the sidewall of the second extension portion and the sidewall of the channel layer to the width of the second extension portion is 0 - 0.5.

[0025] In the embodiment of the present application, the material of the heat conduction layer includes at least one of polysilicon, amorphous carbon, silicon nitride, and silicon carbonitride, the materials of the buried oxide layer and the insulating layer include silicon dioxide, and the material of the channel layer includes silicon.

[0026] The technical solution of the present application sets a heat-conducting layer between the channel layer and the semiconductor substrate, and the heat-conducting layer bridges the channel layer and the semiconductor substrate, so that the heat generated when the device works is transferred to the semiconductor substrate through the heat-conducting layer, effectively improving the self-heating phenomenon of the channel.

[0027] By controlling various dimensions of the heat-conducting layer, the insulating layer, and the buried oxide layer, the device performance and the self-heating improvement effect can reach the best. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following drawings detail the exemplary embodiments disclosed in the present application. The same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0029] Figures 1 to 20 is a schematic structural diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present application;

[0030] Figure 21 is a schematic diagram of a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various local modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the disclosed embodiments, but has the broadest scope consistent with the claims.

[0032] At present, when the current SOI device works, especially in the high-frequency case, a self-heating phenomenon will occur. Based on this, the technical solution of the present application provides a semiconductor structure. By forming a heat-conducting layer that bridges the channel layer and the semiconductor substrate under the channel layer, the heat generated when the device works is conducted to the semiconductor substrate through the heat-conducting layer, and the heat is dissipated through the semiconductor substrate, effectively alleviating the self-heating phenomenon and greatly improving the high-frequency performance of the device.

[0033] The following will detail the semiconductor structure and its forming method of the technical solution of the present application with specific embodiments and drawings.

[0034] Refer to Figure 20, embodiments of the present application provide a semiconductor structure, which can be applied to both low-frequency devices and high-frequency devices, for example, it can be applied to RF SOI MOSFETs. The semiconductor structure includes a semiconductor substrate 100, and the material of the semiconductor substrate 100 may include (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide; or (iv) a combination of the above. In some embodiments, the semiconductor substrate 100 uses a silicon wafer with a resistivity of not less than 3000 Ω·cm so that the semiconductor substrate 100 has better linearity performance at high frequencies.

[0035] Combined with Figure 20 and Figure 21 , the surface of the semiconductor substrate 100 includes a buried oxide layer 200, and the buried oxide layer 200 serves to isolate the semiconductor substrate 100 from the device, weaken the coupling effect between the device and the semiconductor substrate 100, reduce energy loss, and is beneficial to the normal operation of the device at high frequencies. The thickness S1 of the buried oxide layer 200 depends on the requirements for the high-frequency performance of the device. The higher the requirements for the high-frequency performance of the device, the thicker the thickness S1 of the buried oxide layer 200. In the embodiments of the present application, the thickness S1 of the buried oxide layer 200 is 10 nm - 1000 nm. The material of the buried oxide layer 200 may include silicon oxide or an insulating material with a dielectric constant lower than that of silicon oxide.

[0036] The semiconductor structure further includes a heat-conducting layer 300 located on the surface of the buried oxide layer 200. The heat-conducting layer 300 has a first extension 310 and a second extension 320. The first extension 310 is located in the buried oxide layer 200 and is connected to the semiconductor substrate 100. The second extension 320 extends away from the buried oxide layer 200. The width S2 of the first extension 310 is related to the heat-conducting effect. The larger the width S2, the better the heat-conducting effect, that is, the better the effect of alleviating the self-heating effect. However, the coupling between the device and the semiconductor substrate 100 will also be strengthened accordingly. The width S2 of the first extension 310 in the embodiment of the present application is 50 nm - 1000 nm. The thickness of the second extension 320 depends on the thickness of the required insulating layer 500. The width S3 of the second extension 320 is related to the performance and size of the device. The larger the width S3, the better the effect of improving self-heating, but it is not conducive to the improvement of device performance. In the embodiment of the present application, in order to adapt to high-frequency devices, the size of the width S3 does not exceed 80% of the channel width. For low-frequency and DC devices, the width S3 of the second extension 320 can be equal to the width of the channel layer. The distance S4 between the planes where the adjacent side walls of the first extension 310 and the second extension 320 are located affects the linearity of the device. The larger the distance S4, the weaker the coupling between the device and the semiconductor substrate 100 and the better the non-linearity. In the embodiment of the present application, the distance S4 is at least 10 nm to ensure that the coupling between the device and the semiconductor substrate 100 is within the allowable range. At the same time, the larger the distance S4, the less conducive to the miniaturization of the device. Therefore, it is necessary to comprehensively consider the device size and device performance to determine the specific size of the distance S4.

[0037] The material of the heat-conducting layer 300 needs to have good heat-conducting characteristics. For example, the material of the heat-conducting layer 300 may include at least one of polysilicon, amorphous carbon, silicon nitride, and silicon carbonitride.

[0038] The insulating layer 500 is located on the surface of the heat-conducting layer 300 and is coplanar with the surface of the second extension 320. The insulating layer 500 serves to isolate the device and the heat-conducting layer 300, preventing the device from being in complete contact with the heat-conducting layer 300, which may cause a strong coupling between the device and the semiconductor substrate 100. The larger the thickness of the insulating layer 500, the better the isolation effect. However, when the thickness of the insulating layer 500 is too large, the thickness of the heat-conducting layer 300 between the insulating layer 500 and the buried oxide layer 200 will be too small, affecting the heat-conducting efficiency. Therefore, in order to obtain good isolation and non-linearity, the thickness S5 of the insulating layer 500 is 50 nm - 1000 nm. The thickness S5 of the insulating layer 500 is equal to the thickness of the second extension 320. The material of the insulating layer 500 may include silicon dioxide or other materials with insulating properties.

[0039] The channel layer 600 is located on the surfaces of the second extension portion 320 and a part of the insulating layer 500. That is, one end of the heat conduction layer 300 (i.e., the second extension portion 320) is connected to the channel layer 600, and the other end (i.e., the first extension portion 310) is connected to the semiconductor substrate 100. When the device is operating, the heat generated in the channel layer 600 can be transferred to the semiconductor substrate 100 through the heat conduction layer 300 to alleviate the self-heating effect of the device. The heat transfer direction can be referred to Figure 21 the arrow direction in. The distance S6 between the sidewall of the second extension portion 320 and the sidewall of the channel layer 600 depends on the width S3 of the second extension portion 320. At the same time, the distance S6 also affects the device performance and the self-heating improvement effect. When the distance S6 = 0, the self-heating improvement effect of the device is the best, and all the energy generated during the operation of the device can be transferred to the semiconductor substrate 100 by the heat conduction layer 300. As the distance S6 increases, the self-heating improvement effect of the device becomes worse, but the insertion loss and non-linearity in high-frequency applications such as 5G / mmwave are much better. Therefore, by adjusting the size of the distance S6, the device performance and the self-heating improvement effect can be balanced, and it can be better applied to high-frequency SOC. In addition, by adjusting the size of the distance S6, the coupling between the channel layer 600 and the semiconductor substrate 100 can also be adjusted. As the distance S6 becomes larger, the coupling becomes weaker, and the off-state capacitance of the MOSFET is lower, so better non-linear performance can be obtained in high-frequency applications. In the embodiments of the present application, the ratio range of the distance S6 between the sidewall of the second extension portion and the sidewall of the channel layer to the width S3 of the second extension portion is 0 - 0.5. The material of the channel layer 600 may include silicon. For example, the trench layer 600 may be a silicon wafer.

[0040] In the embodiments of the present application, to achieve good heat conduction efficiency, the thickness S7 of the heat conduction layer 300 between the channel layer 600 and the buried oxide layer 200 is 100nm - 5000nm.

[0041] The gate structure is located on the surface of the channel layer 600. The gate structure includes a gate oxide layer 910, a gate layer 920 located on the surface of the gate oxide layer 910, and sidewalls 930 located on the sidewalls of the gate oxide layer 910 and the gate layer 920. The source electrode 940 and the drain electrode 950 are respectively located in the channel layer 600 on both sides of the gate structure. The sidewalls of the source electrode 940 and the drain electrode 950 also include an isolation structure 800. The isolation structure 800 is, for example, a shallow trench isolation structure. By adding the heat conduction layer 300 in the embodiments of the present application, the impact ionization positive charges near the drain end can also flow to the heat conduction layer 300 and be injected into the semiconductor substrate 100, so the floating body effect can be improved.

[0042] An embodiment of the present application further provides a method for forming a semiconductor structure, which may be the semiconductor structure of the foregoing embodiment. The forming method includes:

[0043] Step S1: Provide a semiconductor substrate, the surface of which includes a buried oxide layer;

[0044] Step S2: Form a thermal conductive layer on the surface of the buried oxide layer, which has a first extension extending into the buried oxide layer and connecting to the semiconductor substrate, and a second extension extending away from the buried oxide layer;

[0045] Step S3: Form an insulating layer on the surface of the thermal conductive layer, and the insulating layer is coplanar with the surface of the second extension;

[0046] Step S4: Form a channel layer on the surface of the second extension and a part of the insulating layer;

[0047] Step S5: Form a gate structure on the surface of the channel layer, and form a source and a drain in the channel layer on both sides of the gate structure respectively.

[0048] Reference Figure 1 , provide a semiconductor substrate 100, the surface of which includes a buried oxide layer 200. The forming method of the buried oxide layer 200 may be a deposition process such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0049] Reference Figure 2 and Figure 3 , wherein Figure 3 is a top view schematic diagram after being cut along the A-A position of Figure 2 , and this top view is a top view schematic diagram of the whole wafer. Etch a part of the buried oxide layer 200 and stop at the surface of the semiconductor substrate 100 to form a first trench 210, and the width of the first trench may be 50 nm - 1000 nm. The process of etching the buried oxide layer 200 may be a dry etching process or a wet etching process.

[0050] Reference Figures 4 to 5, a thermal conductive material 301 is filled in the first trench 210. For example, deposition processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition can be used to fill the first trench 210, and a first extension 210 is formed in the buried oxide layer 200, and the thermal conductive material 301 extends to the surface of the buried oxide layer 200. The thermal conductive material 301 can be a material with thermal conductivity. For example, the thermal conductive material 301 can include at least one of polysilicon, amorphous carbon, silicon nitride, and silicon carbonitride. The thermal conductive material 301 is planarized to form a thermal conductive layer 300, and a first barrier layer 400 is formed on the surface of the thermal conductive layer 300. When planarizing, polishing processes such as chemical mechanical polishing or physical mechanical polishing can be used. After planarization, the thickness of the thermal conductive layer 300 on the surface of the buried oxide layer 200 is 100 nm - 5000 nm. The formation process of the first barrier layer 400 can be deposition processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the material of the first barrier layer 400 can include silicon nitride. The first barrier layer 400 serves to protect the surface of the thermal conductive layer 300 from being damaged. The thickness of the first barrier layer 400 is 50 nm - 100 nm.

[0051] Reference Figures 6 to 8 , where Figure 7 is a top view schematic diagram of the entire wafer, Figure 8 is a top view schematic diagram of the entire wafer after being cut along the Figure 6 B - B position. Part of the first barrier layer 400 and the thermal conductive layer 300 are etched to form the second extension 320 and the second trench 330. The process of etching the first barrier layer 400 and the thermal conductive layer 300 can be a wet etching process.

[0052] Reference Figure 9 and Figure 10 , an insulating layer 500 is formed on the surface of the thermal conductive layer 300, which can include: forming an insulating material layer 510 on the surface of the thermal conductive layer 300, and the material of the insulating material layer 510 can include silicon dioxide or other materials with insulating properties; using physical mechanical polishing or chemical mechanical polishing and other polishing processes to planarize the insulating material layer 510 until the surface of the first barrier layer 400 is exposed; removing the first barrier layer 400, and making the surface of the insulating material layer 510 and the second extension 320 coplanar to form the insulating layer 500. The process of removing the first barrier layer 400 can be various polishing processes, such as physical mechanical polishing or chemical mechanical polishing, etc.

[0053] A channel layer is formed on the surface of the second extension portion 320 and a part of the insulating layer 500. The process of forming the channel layer may include: attaching a silicon layer 610 with a specific thickness to the surface of the second extension portion 320 and the insulating layer 500.

[0054] Reference Figure 11 and Figure 12 , in some embodiments, attaching a silicon layer 610 with a specific thickness to the surface of the second extension portion 320 and the insulating layer 500 can be performed by the following method: providing a silicon layer 620; attaching the silicon layer 620 to the surface of the second extension portion 320 and a part of the insulating layer 500; back-etching or polishing the silicon layer 620 to form a silicon layer 610 with a specific thickness.

[0055] Reference Figures 13 to 15 , in some other embodiments, attaching a silicon layer 610 with a specific thickness to the surface of the second extension portion 320 and the insulating layer 500 can be performed by the following method: providing a silicon layer 620, the silicon layer 620 including a first surface; injecting hydrogen ions and / or inert gas ions into the silicon layer 620 from the first surface to form a peeling layer 630 at a specific depth in the silicon layer 620, and controlling the depth of the peeling layer 630 in the silicon layer 620 by controlling the injection energy of the hydrogen ions and / or inert gas ions, for example, controlling the injection energy of the hydrogen ions and / or inert gas ions to be 10 - 30 KeV to control the depth of the peeling layer 630 to be 80 nm - 120 nm, thereby controlling the thickness of the silicon layer finally formed on the surface of the second extension portion 320 and a part of the insulating layer 500; taking the first surface as the attachment surface, attaching the silicon layer 620 to the surface of the second extension portion 320 and a part of the insulating layer 500; performing peeling heat treatment to remove the peeling layer 630 and the silicon layer 620 on one side of the peeling layer, and forming a silicon layer 610 with a specific thickness on the surface of the second extension portion 320 and a part of the insulating layer 500.

[0056] Reference Figure 16 , a second barrier layer 700 is formed on the surface of the silicon layer 610. The material of the second barrier layer 700 may include, for example, silicon nitride. The second barrier layer 700 can protect the surface of the silicon layer 610 from being damaged by subsequent processes; etching the second barrier layer 700 and the silicon layer 610 until a part of the insulating layer 500 is exposed to form a channel layer 600.

[0057] Reference Figure 17 and Figure 18, after etching the second barrier layer 700 and the silicon layer 610, an isolation material 810 is filled at the corresponding positions; a polishing process such as chemical mechanical polishing or physical mechanical polishing is used to remove the second barrier layer 700, and the surfaces of the isolation material 810 and the channel layer 600 are coplanar, and an isolation structure 800 is formed on the sidewalls of the channel layer 600.

[0058] Reference Figure 19 , a gate structure is formed on the surface of the channel layer 600, and the gate structure includes a gate oxide layer 910, a gate layer 920 located on the surface of the gate oxide layer 910, and sidewalls 930 located on the sidewalls of the gate oxide layer 910 and the gate layer 920.

[0059] Reference Figure 20 , a source electrode 940 and a drain electrode 950 are respectively formed in the channel layer 600 on both sides of the gate structure. In some embodiments, it further includes: forming a self-aligned metal silicide on the surfaces of the gate structure, the source electrode 940 and the drain electrode 950.

[0060] In summary, after reading the content of this application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0061] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.

[0062] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be an intermediate element. In contrast, the term "directly" means without an intermediate element. It should also be understood that the terms "comprise", "comprising", "include", or "including", when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups.

[0063] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0064] In addition, the present application specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or three-dimensional views. Accordingly, differences from the shapes shown due to, for example, manufacturing techniques and / or tolerances are foreseeable. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in the shapes resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that, Comprising: A semiconductor substrate, the surface of the semiconductor substrate comprising a buried oxide layer; A thermal conductive layer, located on the surface of the buried oxide layer, and having a first extension extending into the buried oxide layer and connected to the semiconductor substrate and a second extension extending away from the buried oxide layer; An insulating layer, located on the surface of the thermal conductive layer, and coplanar with the surface of the second extension; A channel layer, located on the surface of the second extension and a part of the insulating layer; A gate structure, located on the surface of the channel layer; A source and a drain, respectively located in the channel layer on both sides of the gate structure.

2. The semiconductor structure according to claim 1, wherein The distance between the adjacent side walls of the first extension and the second extension is not less than 10 nm.

3. The semiconductor structure according to claim 1, wherein, The width of the first extension is 50 nm - 1000 nm.

4. The semiconductor structure according to claim 1, wherein The thickness of the thermal conductive layer between the channel layer and the buried oxide layer is 100 nm - 5000 nm.

5. The semiconductor structure according to claim 1, wherein The ratio range of the distance between the side wall of the second extension and the side wall of the channel layer to the width of the second extension is 0 - 0.

5.

6. The semiconductor structure according to claim 1, characterized in that Further comprising an isolation structure, located on the side walls of the source and the drain.

7. The semiconductor structure according to claim 1, wherein The thickness of the insulating layer is 50 nm - 1000 nm.

8. The semiconductor structure according to claim 1, characterized in that The thickness of the buried oxide layer is 10 nm - 1000 nm.

9. The semiconductor structure according to claim 1, wherein The resistivity of the semiconductor substrate is not less than 3000 Ω·cm.

10. The semiconductor structure according to claim 1, wherein The material of the thermal conductive layer comprises at least one of polysilicon, amorphous carbon, silicon nitride and silicon carbonitride.

11. The semiconductor structure according to claim 1, characterized in that, The materials of the buried oxide layer and the insulating layer comprise silicon dioxide, and the material of the channel layer comprises silicon.

12. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a semiconductor substrate, the surface of the semiconductor substrate comprising a buried oxide layer; Forming a thermal conductive layer, the thermal conductive layer located on the surface of the buried oxide layer, and having a first extension extending into the buried oxide layer and connected to the semiconductor substrate and a second extension extending away from the buried oxide layer; Forming an insulating layer on the surface of the thermal conductive layer, and the insulating layer is coplanar with the surface of the second extension; Forming a channel layer on the surface of the second extension and a part of the insulating layer; Forming a gate structure on the surface of the channel layer, and forming a source and a drain respectively in the channel layer on both sides of the gate structure.

13. The method for forming a semiconductor structure according to claim 12, wherein The method for forming the thermal conductive layer comprises: Etching a part of the buried oxide layer, and stopping at the surface of the semiconductor substrate, and filling a thermal conductive material at the corresponding position, forming the first extension in the buried oxide layer, and the thermal conductive material extending to the surface of the buried oxide layer; Planarizing the thermal conductive material, forming a thermal conductive layer, and forming a first barrier layer on the surface of the thermal conductive layer; Etching a part of the first barrier layer and the thermal conductive layer, forming the second extension.

14. The method for forming a semiconductor structure according to claim 13, wherein The method for forming an insulating layer on the surface of the thermal conductive layer comprises: Forming an insulating material layer on the surface of the thermal conductive layer; Planarizing the insulating material layer until the surface of the first barrier layer is exposed; Removing the first barrier layer, and making the surface of the insulating material layer and the second extension coplanar, forming the insulating layer.

15. The method for forming a semiconductor structure according to claim 12, wherein The method for forming a channel layer on the surface of the second extension and a part of the insulating layer comprises: Bonding a silicon layer with a specific thickness on the surface of the second extension and the insulating layer; Forming a second barrier layer on the surface of the silicon layer; Etch the second barrier layer and the silicon layer until a part of the insulating layer is exposed to form the channel layer.

16. The method for forming a semiconductor structure according to claim 15, wherein, The method for attaching a silicon layer with a specific thickness to the surfaces of the second extension part and the insulating layer includes: Provide a silicon layer; Attach the silicon layer to the surfaces of the second extension part and a part of the insulating layer; Etch back or polish the silicon layer to a specific thickness.

17. The method for forming a semiconductor structure according to claim 15, wherein The method for attaching a silicon layer with a specific thickness to the surfaces of the second extension part and the insulating layer includes: Provide a silicon layer, where the silicon layer includes a first surface; Inject hydrogen ions and / or inert gas ions into the silicon layer from the first surface to form a peeling layer at a specific depth in the silicon layer; Using the first surface as the attachment surface, attach the silicon layer to the surfaces of the second extension part and a part of the insulating layer; Perform peeling heat treatment to remove the peeling layer and the silicon layer on one side of the peeling layer, and form a silicon layer with a specific thickness on the surfaces of the second extension part and a part of the insulating layer.

18. The method for forming a semiconductor structure according to claim 15, wherein, After etching the second barrier layer and the silicon layer, it further includes: Fill an isolation material at the corresponding position; Remove the second barrier layer and make the surfaces of the isolation material and the channel layer coplanar to form an isolation structure on the sidewalls of the channel layer.

19. The method for forming a semiconductor structure according to claim 12, wherein It further includes: Form self-aligned metal silicide on the surfaces of the gate structure, the source electrode, and the drain electrode.

20. The method for forming a semiconductor structure according to claim 12, wherein, The distance between the planes where the adjacent sidewalls of the first extension part and the second extension part are located is not less than 10 nm, the width of the first extension part is 50 nm - 1000 nm, the thickness of the heat conduction layer between the channel layer and the buried oxide layer is 100 nm - 5000 nm, and the ratio range of the distance between the sidewall of the second extension part and the sidewall of the channel layer to the width of the second extension part is 0 - 0.

5.

21. The method for forming a semiconductor structure according to claim 12, wherein, The material of the heat conduction layer includes at least one of polysilicon, amorphous carbon, silicon nitride, and silicon carbonitride, the materials of the buried oxide layer and the insulating layer include silicon dioxide, and the material of the channel layer includes silicon.

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