A preparation method for a Topcon battery passivation structure

Abstract

The present invention provides a method for preparing a Topcon battery passivation structure, comprising: performing texturing, boron diffusion, and etching and cleaning treatments on an N-type crystalline silicon substrate; growing a silicon oxide tunneling layer on the surface of the N-type crystalline silicon substrate; depositing an amorphous silicon layer on the silicon oxide tunneling layer, and heavily phosphorus-doping the amorphous silicon layer when deposited to a portion of a preset thickness; lightly phosphorus-doping the amorphous silicon layer when deposited to the remaining preset thickness, and then annealing; passivating the surface of the annealed N-type crystalline silicon substrate, and then metallizing it to form a battery. The beneficial effects of the present invention are to adjust the amount of phosphine introduced by different process thicknesses, control the concentration gradient of doped phosphorus in the amorphous silicon layer, perform low-temperature annealing, reduce the diffusion rate of phosphorus in silicon, maintain concentration differences, thereby achieving the effect of enriching a high concentration of phosphorus near the tunneling layer to facilitate tunneling, and the phosphorus concentration in the polycrystalline silicon layer is lower than that near the tunneling layer, thereby reducing Auger recombination and parasitic absorption.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a method for preparing a Topcon cell passivation structure. Background Art

[0002] A solar cell is a device that converts light energy directly into electrical energy through the photovoltaic effect. Currently, the most common solar cell is a large-area PN junction made of silicon. Other possible solar cell types include dye-sensitized solar cells, organic solar cells, and quantum dot solar cells.

[0003] Generally, the back of a solar TOPCON cell requires phosphorus doping of the amorphous silicon layer, which is then annealed to obtain a polycrystalline silicon layer. The phosphorus doping concentration is usually consistent, and the square resistance of the polycrystalline silicon layer after phosphorus doping is 20-200Ω / sqr. The single doping method makes it impossible for the contact performance and passivation ability of the N-type crystalline silicon substrate to be in a high-performance state at the same time, and the Auger recombination is high, and the parasitic absorption of the polycrystalline silicon layer in the long wavelength band is high. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a method for preparing a Topcon cell passivation structure, which effectively solves the problem that a general solar TOPCON cell requires an amorphous silicon layer to be doped with phosphorus and annealed to obtain a polycrystalline silicon layer. The single doping method makes it impossible for the contact performance and passivation ability of the N-type crystalline silicon substrate to be in a high-performance state at the same time, and the Auger recombination is high, and the parasitic absorption of the polycrystalline silicon layer in the long wavelength band is high.

[0005] To solve the above technical problems, the present invention adopts a technical solution: a method for preparing a Topcon battery passivation structure, comprising:

[0006] The N-type crystalline silicon substrate is subjected to texturing, boron diffusion and etching and cleaning treatments respectively;

[0007] growing a silicon monoxide tunneling layer on the surface of the treated N-type crystalline silicon substrate;

[0008] Depositing an amorphous silicon layer on the silicon oxide tunneling layer, and performing heavy phosphorus doping on the amorphous silicon layer when the layer is deposited to a portion of the preset thickness; and lightly doping the amorphous silicon layer when the layer is deposited to the remaining preset thickness;

[0009] Annealing the doped N-type crystalline silicon substrate;

[0010] The surface of the N-type crystalline silicon substrate after annealing is passivated and then metallized to form a battery.

[0011] Preferably, the resistivity of the N-type crystalline silicon substrate is 0.5-5Ω·cm, and the thickness is 80-200 μm.

[0012] Preferably, in the process of growing a silicon oxide tunneling layer on the surface of the treated N-type crystalline silicon substrate, the material for making the silicon oxide tunneling layer is silicon dioxide, and the silicon oxide tunneling layer is grown on the surface of the N-type crystalline silicon substrate by thermal oxidation, HNO3 oxidation or atomic layer deposition, wherein the thickness of the silicon oxide tunneling layer is 0.5-2nm.

[0013] Preferably, in the step of depositing an amorphous silicon layer on the silicon oxide tunneling layer, the deposition temperature of the amorphous silicon layer is 250-650° C., and the preset thickness of the amorphous silicon layer is 50-200 nm.

[0014] Preferably, when the amorphous silicon layer is deposited to a predetermined thickness, in the step of heavily phosphorus doping the amorphous silicon layer, the predetermined thickness of the amorphous silicon layer is 20-30% of the predetermined thickness, and phosphine is used for doping, and the doping concentration is 2-4*E 20 .

[0015] More preferably, the sheet resistance of the heavily phosphorus-doped portion of the amorphous silicon layer is 30-100Ω / sqr.

[0016] Preferably, when the predetermined thickness is left, in the step of lightly phosphorus doping the amorphous silicon layer, the predetermined thickness of the amorphous silicon layer is 70-80% of the predetermined thickness, and phosphine is used for doping, and the doping concentration is 0.5-1*E 20 .

[0017] More preferably, the sheet resistance of the lightly phosphorus-doped portion of the amorphous silicon layer is 100-500Ω / sqr.

[0018] Preferably, in the step of annealing the doped N-type crystalline silicon substrate, the annealing temperature is 800-860° C. and the annealing time is 0.5-2 h.

[0019] Preferably, the front passivation layer of the N-type crystalline silicon substrate is aluminum oxide and silicon nitride, and the back passivation layer is silicon nitride, wherein the thickness of the front aluminum oxide is 1-7nm, the thickness of the silicon nitride is 60-110nm, and the thickness of the back silicon nitride is 70-120nm; the slurry used for metallization is conductive silver aluminum paste on the front and conductive silver paste on the back.

[0020] Using the above technical solution, 0.5-2nm silicon oxide is grown on the back substrate of the Topcon battery as a tunneling layer, and an amorphous silicon layer is deposited by LPCVD or PEALD. While depositing the amorphous silicon layer, phosphine gas is introduced as a phosphorus source for doping. The amount of phosphine introduced is adjusted through different processes to control the concentration gradient of doped phosphorus in the amorphous silicon layer. Low-temperature annealing is performed to reduce the diffusion rate of phosphorus in silicon and maintain the concentration difference, thereby achieving the effect of high-concentration phosphorus enrichment near the tunneling layer, which is conducive to tunneling, and the phosphorus concentration in polycrystalline silicon is lower than that near the tunneling layer, thereby reducing Auger recombination and parasitic absorption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of phosphorus concentration in a method for preparing a Topcon battery passivation structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described below in conjunction with the embodiments and drawings:

[0023] In the description of the embodiments of the present invention, it should be understood that the terms "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0024] A method for preparing a Topcon battery passivation structure, comprising:

[0025] S1: The N-type crystalline silicon substrate is subjected to texturing, boron diffusion and etching and cleaning treatments respectively, wherein the resistivity of the N-type crystalline silicon substrate is 0.5-5Ω·cm and the thickness range is 80-200μm; after the selection is completed, the front surface of the N-type crystalline silicon substrate is texturing; after the back surface of the N-type crystalline silicon substrate is texturing, the front surface of the N-type crystalline silicon substrate is subjected to boron diffusion treatment, and the boron source is boron tribromide or boron trichloride, the diffusion temperature is 900-1100℃, and the time is 120-240min, to form a P+ doping layer, and a borosilicate glass layer is also formed on the surface of the P+ doping layer; finally, the square resistance of the N-type crystalline silicon substrate after boron diffusion is 100-180Ω / sqr; all borosilicate glass layers on the front surface, back surface and edge expansion of the N-type crystalline silicon substrate are removed, and then the P+ doping layer on the back surface and edge expansion of the N-type crystalline silicon substrate is removed, and only the P+ doping layer on the front surface of the N-type crystalline silicon substrate is retained.

[0026] S2: growing a silicon oxide tunneling layer on the surface of the treated N-type crystalline silicon substrate; wherein the silicon oxide tunneling layer is made of silicon dioxide, and the silicon oxide tunneling layer is grown on the surface of the N-type crystalline silicon substrate by thermal oxidation, HNO3 oxidation or atomic layer deposition, wherein the thickness of the silicon oxide tunneling layer is 0.5-2nm.

[0027] S3: depositing an amorphous silicon layer on the silicon oxide tunneling layer, and performing heavy phosphorus doping on the amorphous silicon layer when the layer is deposited to a portion of the preset thickness; and performing light phosphorus doping on the amorphous silicon layer when the layer is deposited to the remaining preset thickness; wherein,

[0028] The deposition temperature of the entire amorphous silicon layer is 250-650° C., and the preset thickness of the amorphous silicon layer is 50-200 nm;

[0029] When the amorphous silicon layer is deposited to a predetermined thickness, the amorphous silicon layer is doped with heavy phosphorus. The predetermined thickness of the amorphous silicon layer is 20-30% of the overall predetermined thickness. The amorphous silicon layer is doped with phosphorus using phosphine at a doping concentration of 2-4*E 20 The sheet resistance of the heavily phosphorus-doped amorphous silicon layer is 30-100Ω / sqr;

[0030] When the amorphous silicon layer with the remaining preset thickness is deposited, the remaining part of the amorphous silicon layer is lightly doped with phosphorus. The remaining preset thickness of the amorphous silicon layer is 70-80% of the preset thickness. Phosphine is also used for doping. The doping concentration is 0.5-1*E 20 ; Among them, the sheet resistance of the lightly phosphorus-doped amorphous silicon layer is 100-500Ω / sqr.

[0031] By adjusting the amount of phosphorus source introduced according to the different thicknesses of the amorphous silicon layer, a doping process with two or three steps of phosphorus concentration is obtained, so that the high doping concentration near the tunneling layer in the polysilicon layer increases the tunneling current and improves the contact capability; the low doping concentration outside the tunneling layer in the polysilicon layer can effectively reduce Auger recombination and reduce the parasitic absorption of the poly silicon long wave band, thereby achieving both good contact performance and good passivation capability, solving the problem that passivation and contact cannot be achieved simultaneously by single phosphorus doping concentration.

[0032] S4: Annealing the doped N-type crystalline silicon substrate to activate phosphorus atoms as substitutional impurities to obtain a phosphorus-doped polysilicon layer. The annealing temperature is 800-860° C. and the annealing time is 0.5-2 hours.

[0033] S5: The front passivation layer of the N-type crystalline silicon substrate is aluminum oxide and silicon nitride, and the back passivation layer is silicon nitride. The thickness of the aluminum oxide is 1-7nm, the thickness of the silicon nitride is 60-110nm, and the thickness of the silicon nitride on the back is 70-120nm. The slurry used for metallization is conductive silver aluminum slurry on the front and conductive silver slurry on the back.

[0034] In the above technical solution, 0.5-2nm silicon oxide is grown on the back substrate of the Topcon cell as a tunneling layer, and amorphous silicon is deposited by LPCVD or PEALD. While depositing amorphous silicon, phosphine gas is introduced as a phosphorus source for doping. The amount of phosphine introduced is adjusted according to different process thicknesses to control the concentration gradient of doped phosphorus in the amorphous silicon. Low-temperature annealing is performed to reduce the diffusion rate of phosphorus in silicon and maintain the concentration difference, thereby achieving the effect of high-concentration phosphorus enrichment near the tunneling layer, which is conducive to tunneling, and the phosphorus concentration in polycrystalline silicon is lower than that near the tunneling layer, reducing Auger recombination and parasitic absorption, and increasing the tunneling current and its contact capability.

[0035] Here are a few specific embodiments:

[0036] Example 1

[0037] S1: The N-type crystalline silicon substrate is textured, wherein the resistivity of the N-type crystalline silicon substrate is 1Ω·cm and the thickness range is 160μm; after the back surface of the N-type crystalline silicon substrate is textured, the front surface of the N-type crystalline silicon substrate is subjected to boron diffusion treatment, with boron trichloride as the boron source, the diffusion temperature being 1000℃, and the time being 240min, to form a P+ doped layer, and a borosilicate glass layer is also formed on the surface of the P+ doped layer; finally, the square resistance of the N-type crystalline silicon substrate after boron diffusion is 120Ω / sqr; all borosilicate glass layers on the front surface, back surface and edge expansion of the N-type crystalline silicon substrate are removed, and then the P+ doped layer on the back surface and edge expansion of the N-type crystalline silicon substrate is removed, and only the P+ doped layer on the front surface of the N-type crystalline silicon substrate is retained.

[0038] S2: growing a silicon oxide tunneling layer on the surface of the treated N-type crystalline silicon substrate; wherein the silicon oxide tunneling layer is made of silicon dioxide, and the silicon oxide tunneling layer is grown on the surface of the N-type crystalline silicon substrate by thermal oxidation, wherein the thickness of the silicon oxide tunneling layer is 1 nm.

[0039] S3: depositing an amorphous silicon layer on the silicon oxide tunneling layer, and performing heavy phosphorus doping on the amorphous silicon layer when the layer is deposited to a portion of the preset thickness; and performing light phosphorus doping on the amorphous silicon layer when the layer is deposited to the remaining preset thickness; wherein,

[0040] The deposition temperature of the entire amorphous silicon layer is 600° C., and the preset thickness of the amorphous silicon layer is 150 nm;

[0041] When the amorphous silicon layer is deposited to a predetermined thickness, the amorphous silicon layer is doped with heavy phosphorus. The predetermined thickness of the amorphous silicon layer is 20% of the overall predetermined thickness, which is 30 nm. The amorphous silicon layer is doped with heavy phosphorus using phosphine at a doping concentration of 3*E 20 The sheet resistance of the heavily phosphorus-doped amorphous silicon layer is 50Ω / sqr;

[0042] When the remaining amorphous silicon layer of the preset thickness is deposited, the remaining part of the amorphous silicon layer is lightly doped with phosphorus. The remaining preset thickness of the amorphous silicon layer is 80% of the preset thickness, which is 120 nm. Phosphine is also used for doping, and the doping concentration is 1*E 20 ; Among them, the sheet resistance of the lightly phosphorus-doped amorphous silicon layer is 200Ω / sqr.

[0043] By adjusting the amount of phosphorus source introduced according to the different thicknesses of the amorphous silicon layer, a doping process with two or three steps of phosphorus concentration is obtained, so that the high doping concentration near the tunneling layer in the polysilicon layer increases the tunneling current and improves the contact capability; the low doping concentration outside the tunneling layer in the polysilicon layer can effectively reduce Auger recombination and reduce the parasitic absorption of the poly silicon long wave band, thereby achieving both good contact performance and good passivation capability, solving the problem that passivation and contact cannot be achieved simultaneously by single phosphorus doping concentration.

[0044] S4: Annealing the doped N-type crystalline silicon substrate to activate phosphorus atoms as substitutional impurities to obtain a phosphorus-doped polysilicon layer. The annealing temperature is 820° C., the annealing time is 1 hour, and the sheet resistance after annealing is 200Ω / sqr.

[0045] S5: The surface of the N-type crystalline silicon substrate after annealing is passivated and then metallized to form a battery, wherein the thickness of the front silicon nitride anti-reflection film is 100nm, the thickness of the back silicon nitride anti-reflection film is 100nm, and the refractive index is 2; ALD deposition of aluminum oxide is performed to passivate the front side, wherein the aluminum oxide thickness is 1nm and the refractive index is 2.1; then metallized grid lines are made and transferred into a belt sintering furnace for sintering, wherein the slurry used for metallization is conductive silver slurry, that is, a Topcon passivated contact structure battery with a concentration gradient polysilicon layer is prepared.

[0046] like Figure 1 As shown, the ECV test concentration in the polysilicon near the tunnel layer is 2~4*E 20 , near-surface ECV concentration 0.5~1*E 20 . The contact resistivity can reach 1mΩ·cm 2 Below, while metal composite at 50 ~ 250fA / cm -2 The variation of doping concentration at different positions of the polysilicon layer has both good contact performance and good passivation capability compared to the single concentration doping method, solving the problem that single concentration doping cannot achieve both passivation and contact.

[0047] Example 2

[0048] S1: The N-type crystalline silicon substrate is textured, wherein the resistivity of the N-type crystalline silicon substrate is 0.5Ω·cm and the thickness range is 80μm; after the back surface of the N-type crystalline silicon substrate is textured, the front surface of the N-type crystalline silicon substrate is subjected to boron diffusion treatment, with boron trichloride as the boron source, the diffusion temperature being 900℃, and the time being 240min, to form a P+ doped layer, and a borosilicate glass layer is also formed on the surface of the P+ doped layer; finally, the square resistance of the N-type crystalline silicon substrate after boron diffusion is 100Ω / sqr; all borosilicate glass layers on the front surface, back surface and edge expansion of the N-type crystalline silicon substrate are removed, and then the P+ doped layer on the back surface and edge expansion of the N-type crystalline silicon substrate is removed, and only the P+ doped layer on the front surface of the N-type crystalline silicon substrate is retained.

[0049] S2: growing a silicon oxide tunneling layer on the surface of the treated N-type crystalline silicon substrate; wherein the silicon oxide tunneling layer is made of silicon dioxide, and the silicon oxide tunneling layer is grown on the surface of the N-type crystalline silicon substrate by thermal oxidation, HNO3 oxidation or atomic layer deposition, wherein the thickness of the silicon oxide tunneling layer is 0.5 nm.

[0050] S3: depositing an amorphous silicon layer on the silicon oxide tunneling layer, and performing heavy phosphorus doping on the amorphous silicon layer when the layer is deposited to a portion of the preset thickness; and performing light phosphorus doping on the amorphous silicon layer when the layer is deposited to the remaining preset thickness; wherein,

[0051] The deposition temperature of the entire amorphous silicon layer is 550° C., and the preset thickness of the amorphous silicon layer is 50 nm;

[0052] When the amorphous silicon layer is deposited to a predetermined thickness, the amorphous silicon layer is heavily phosphorus doped. The predetermined thickness of the amorphous silicon layer is 30% of the overall predetermined thickness, which is 15 nm. The heavily phosphorus doped amorphous silicon layer is doped with phosphine at a doping concentration of 2*E 20 The sheet resistance of the heavily phosphorus-doped amorphous silicon layer is 30Ω / sqr;

[0053] When the remaining amorphous silicon layer of the preset thickness is deposited, the remaining portion of the amorphous silicon layer is lightly doped with phosphorus. The remaining preset thickness of the amorphous silicon layer is 70% of the preset thickness, which is 35 nm. Phosphine is also used for doping, and the doping concentration is 0.5*E 20 ; Among them, the sheet resistance of the lightly phosphorus-doped amorphous silicon layer is 200Ω / sqr.

[0054] By adjusting the amount of phosphorus source introduced according to the different thicknesses of the amorphous silicon layer, a doping process with two or three steps of phosphorus concentration is obtained, so that the high doping concentration near the tunneling layer in the polysilicon layer increases the tunneling current and improves the contact capability; the low doping concentration outside the tunneling layer in the polysilicon layer can effectively reduce Auger recombination and reduce the parasitic absorption of the poly silicon long wave band, thereby achieving both good contact performance and good passivation capability, solving the problem that passivation and contact cannot be achieved simultaneously by single phosphorus doping concentration.

[0055] S4: Annealing the doped N-type crystalline silicon substrate to activate phosphorus atoms as substitutional impurities to obtain a phosphorus-doped polysilicon layer. The annealing temperature is 800° C. and the annealing time is 2 hours.

[0056] S5: The surface of the annealed N-type crystalline silicon substrate is passivated and then metallized to form a battery, wherein the thickness of the front silicon nitride is 60nm, the thickness of the back silicon nitride is 70nm, and the refractive index is 2; ALD is performed to deposit aluminum oxide to passivate the front side, wherein the aluminum oxide thickness is 1nm and the refractive index is 2.1; then metallized grid lines are made and transferred into a belt sintering furnace for sintering, wherein the slurry used for metallization is conductive silver slurry, that is, a Topcon passivated contact structure battery with a concentration gradient polysilicon layer is prepared.

[0057] Example 3

[0058] S1: The N-type crystalline silicon substrate is subjected to texturing treatment, wherein the resistivity of the N-type crystalline silicon substrate is 5Ω·cm and the thickness range is 200μm; after the back surface of the N-type crystalline silicon substrate is texturing treated, the front surface of the N-type crystalline silicon substrate is subjected to boron diffusion treatment, with boron tribromide as the boron source, the diffusion temperature being 1100℃, and the time being 120min, to form a P+ doped layer, and a borosilicate glass layer is also formed on the surface of the P+ doped layer; finally, the square resistance of the N-type crystalline silicon substrate after boron diffusion is 180Ω / sqr; all borosilicate glass layers on the front surface, back surface and edge expansion of the N-type crystalline silicon substrate are removed, and then the P+ doped layer on the back surface and edge expansion of the N-type crystalline silicon substrate is removed, and only the P+ doped layer on the front surface of the N-type crystalline silicon substrate is retained.

[0059] S2: growing a silicon oxide tunneling layer on the surface of the treated N-type crystalline silicon substrate; wherein the silicon oxide tunneling layer is made of silicon dioxide, and the silicon oxide tunneling layer is grown on the surface of the N-type crystalline silicon substrate by an HNO3 oxidation method, wherein the thickness of the silicon oxide tunneling layer is 2 nm.

[0060] S3: depositing an amorphous silicon layer on the silicon oxide tunneling layer, and performing heavy phosphorus doping on the amorphous silicon layer when the layer is deposited to a portion of the preset thickness; and performing light phosphorus doping on the amorphous silicon layer when the layer is deposited to the remaining preset thickness; wherein,

[0061] The deposition temperature of the entire amorphous silicon layer is 650° C., and the preset thickness of the amorphous silicon layer is 200 nm;

[0062] When the amorphous silicon layer is deposited to a predetermined thickness, the amorphous silicon layer is doped with heavy phosphorus. The predetermined thickness of the amorphous silicon layer is 25% of the total predetermined thickness, which is 50 nm. The amorphous silicon layer is doped with heavy phosphorus using phosphine at a doping concentration of 4*E 20 The sheet resistance of the heavily phosphorus-doped amorphous silicon layer is 100Ω / sqr;

[0063] When the remaining amorphous silicon layer of the preset thickness is deposited, the remaining part of the amorphous silicon layer is lightly doped with phosphorus. The remaining preset thickness of the amorphous silicon layer is 75% of the preset thickness, which is 150nm. Phosphine is also used for doping, and the doping concentration is 1*E 20 ; Among them, the sheet resistance of the lightly phosphorus-doped amorphous silicon layer is 500Ω / sqr.

[0064] By adjusting the amount of phosphorus source introduced according to the different thicknesses of the amorphous silicon layer, a doping process with two or three steps of phosphorus concentration is obtained, so that the high doping concentration near the tunneling layer in the polysilicon layer increases the tunneling current and improves the contact capability; the low doping concentration outside the tunneling layer in the polysilicon layer can effectively reduce Auger recombination and reduce the parasitic absorption of the poly silicon long wave band, thereby achieving both good contact performance and good passivation capability, solving the problem that passivation and contact cannot be achieved simultaneously by single phosphorus doping concentration.

[0065] S4: Annealing the doped N-type crystalline silicon substrate to activate phosphorus atoms as substitutional impurities to obtain a phosphorus-doped polysilicon layer. The annealing temperature is 860° C. and the annealing time is 0.5 h.

[0066] S5: The surface of the annealed N-type crystalline silicon substrate is passivated and then metallized to form a battery, wherein the thickness of the front silicon nitride is 110nm, the thickness of the back silicon nitride is 120nm, and the refractive index is 2; ALD is performed to deposit aluminum oxide to passivate the front side, wherein the aluminum oxide thickness is 1nm and the refractive index is 2.1; then a metallized grid line is made and transferred into a belt sintering furnace for sintering, wherein the slurry used for metallization is conductive silver slurry, that is, a Topcon passivated contact structure battery with a concentration gradient polysilicon layer is prepared.

[0067] The embodiments of the present invention are described in detail above, but the contents described are only preferred embodiments of the present invention and should not be considered to limit the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A method for preparing a Topcon battery passivation structure, comprising: The N-type crystalline silicon substrate is subjected to texturing, boron diffusion and etching and cleaning treatments respectively; growing a silicon monoxide tunneling layer on the surface of the treated N-type crystalline silicon substrate; Depositing an amorphous silicon layer on the silicon oxide tunneling layer, wherein the preset thickness of the amorphous silicon layer is 50-200 nm; when the amorphous silicon layer is deposited to 20-30% of the preset thickness, heavily phosphorus-doping the amorphous silicon layer; and when the amorphous silicon layer is deposited to the remaining preset thickness, lightly phosphorus-doping the amorphous silicon layer; Annealing the doped N-type crystalline silicon substrate at a temperature of 800-860° C. The surface of the N-type crystalline silicon substrate after annealing is passivated and then metallized to form a battery.

2. The method for preparing a Topcon battery passivation structure according to claim 1, wherein: The resistivity of the N-type crystalline silicon substrate is 0.5-5Ω·cm, and the thickness is 80-200 μm.

3. The method for preparing a Topcon battery passivation structure according to claim 1, wherein: In the process of growing a silicon oxide tunneling layer on the surface of the treated N-type crystalline silicon substrate, the silicon oxide tunneling layer is made of silicon dioxide, and the silicon oxide tunneling layer is grown on the surface of the N-type crystalline silicon substrate by thermal oxidation, HNO3 oxidation or atomic layer deposition, wherein the thickness of the silicon oxide tunneling layer is 0.5-2nm.

4. The method for preparing a Topcon battery passivation structure according to claim 1, wherein: In the step of depositing an amorphous silicon layer on the silicon oxide tunneling layer, the deposition temperature of the amorphous silicon layer is 250-650°C.

5. The method for preparing a Topcon battery passivation structure according to claim 1 or 4, characterized in that: When the amorphous silicon layer is deposited to a predetermined thickness, phosphine is used for doping in the step of heavily phosphorus doping, and the doping concentration is 2-4*E 20 .

6. The method for preparing a Topcon battery passivation structure according to claim 5, characterized in that: The sheet resistance of the heavily phosphorus-doped portion of the amorphous silicon layer is 30-100Ω / sqr.

7. The method for preparing a Topcon battery passivation structure according to claim 1 or 4, characterized in that: When the remaining preset thickness is deposited, in the step of lightly phosphorus doping the amorphous silicon layer, the remaining preset thickness of the amorphous silicon layer is 70-80% of the preset thickness, and phosphine is used for doping, and the doping concentration is 0.5-1*E 20 .

8. The method for preparing a Topcon battery passivation structure according to claim 7, characterized in that: The sheet resistance of the lightly phosphorus-doped portion of the amorphous silicon layer is 100-500Ω / sqr.

9. The method for preparing a Topcon battery passivation structure according to claim 1, wherein: In the step of annealing the doped N-type crystalline silicon substrate, the annealing time is 0.5-2 hours.

10. The method for preparing a Topcon battery passivation structure according to claim 1, characterized in that: The front passivation layer of the N-type crystalline silicon substrate is aluminum oxide and silicon nitride, and the back passivation layer is silicon nitride, wherein the thickness of the front aluminum oxide is 1-7nm, the thickness of the front silicon nitride is 60-110nm, and the thickness of the back silicon nitride is 70-120nm; the slurry used for metallization is conductive silver aluminum slurry on the front and conductive silver slurry on the back.

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