Broadcast transmission circuit and method based on network on chip

Abstract

The embodiment of the present invention discloses a broadcast transmission circuit and method based on an on-chip network. In the embodiment of the present invention, the broadcast transmission circuit includes a control circuit and a broadcast router, the control circuit includes a direction buffer and a control module; the broadcast router includes a receiving data port, a distribution module, a data first-in-first-out queue, a second arbitrator, and a transmission data port; the receiving data port is connected to the direction buffer, and the control module is connected to the second arbitrator; the direction buffer is used to store the direction information of the broadcast data; the control module is used to generate a channel switching instruction according to the direction information stored in the direction buffer, and the channel switching instruction is used to control the channel of the second arbitrator in the broadcast router, so that the second arbitrator corresponding to the direction information schedules the broadcast data cached in the data first-in-first-out queue, and each data first-in-first-out queue corresponds to a channel. Through the above circuit, the broadcast router can avoid the phenomenon of hanging when multicasting, and realize the orderly transmission of the broadcast.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a broadcast transmission circuit and method based on a network on chip. Background Art

[0002] In the System on Chip (SoC), a network-on-chip (NoC) is used to realize communication between subsystems. Specifically, in the NoC architecture, multiple subsystems (i.e., computing cores) are included, and the subsystems are interconnected through a broadcast router (BR), and the subsystems route data to the target subsystem in the form of data packets.

[0003] Since the system-on-chip (SoC) based on the network-on-chip (NoC) can better meet the data transmission requirements of high bandwidth and low latency, NoC is the best interconnection mechanism for the system-on-chip (SoC). However, in the design of complex NoC network topology, when using broadcast router (BR) multicast, resource competition often occurs, resulting in hangs.

[0004] In summary, when broadcast router BR multicasts, how to solve the hanging phenomenon caused by resource competition is a problem that needs to be solved at present. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a broadcast transmission circuit and method based on an on-chip network, which can avoid the hang phenomenon of a broadcast router during multicasting and realize orderly transmission of broadcasts.

[0006] In a first aspect, an embodiment of the present invention provides a broadcast transmission circuit based on a network on chip, the circuit comprising: a control circuit and a broadcast router, wherein the control circuit comprises a direction buffer and a control module;

[0007] The broadcast router includes a receiving data port, a distribution module, a data first-in-first-out queue, a second arbitrator, and a transmitting data port;

[0008] The receiving data port is connected to the direction buffer, and the control module is connected to the second arbitrator;

[0009] The direction buffer is used to store the direction information of the broadcast data; the control module is used to generate a channel switching instruction according to the direction information stored in the direction buffer, and the channel switching instruction is used to control the channel of the second arbitrator in the broadcast router, so that the second arbitrator corresponding to the direction information schedules the broadcast data cached in the data first-in-first-out queue, and each data first-in-first-out queue corresponds to a channel;

[0010] The receiving data port is used to receive the broadcast data; the distribution module is used to distribute the received broadcast data to the corresponding data first-in-first-out queue; the second arbitrator is used to receive the channel switching instruction sent by the control module, and schedule the broadcast data cached in the data first-in-first-out queue according to the channel switching instruction; each of the transmission data ports is used to output the broadcast data.

[0011] Optionally, the direction buffer area is N broadcast first-in-first-out queues, and the control module includes a first arbitrator and a broadcast controller;

[0012] The broadcast router has N data receiving ports, distribution modules, second arbitrators, and data transmission ports, and the data first-in-first-out queues are N*M;

[0013] The N receiving data ports are respectively connected to the N broadcast FIFO queues, and the broadcast controller is connected to the N second arbitrators;

[0014] Each of the broadcast FIFO queues is used to store the direction information of the broadcast data received by its corresponding receiving data port; the first arbitrator is used to schedule the direction information cached in the N broadcast FIFO queues; the broadcast controller is used to generate the channel switching instruction according to the direction information scheduled by the first arbitrator, so that each second arbitrator corresponding to the direction information scheduled by the first arbitrator schedules the broadcast data cached in its corresponding M data FIFO queues.

[0015] Optionally, N is a positive integer greater than or equal to 3, and M is a positive integer greater than or equal to 2.

[0016] Optionally, the direction information is stored in a data packet header of the broadcast data, and the direction information is used to indicate a port number of a transmission data port for outputting the broadcast information.

[0017] Optionally, the bit width of each of the broadcast first-in-first-out queues is greater than or equal to the number of bits of the direction information.

[0018] Optionally, the second arbitrator is also used to send non-broadcast data.

[0019] Optionally, in response to the second arbitrator receiving the channel switching instruction sent by the control module, the second arbitrator is used to schedule the broadcast data corresponding to the broadcast channel indicated by the channel switching instruction;

[0020] In response to the data stored in the data FIFO queue being broadcast data, the second arbitrator determines that the channel corresponding to the data FIFO queue is a broadcast channel.

[0021] Optionally, in response to a non-broadcast channel in the channels of the second arbitrator, the second arbitrator is further configured to schedule non-broadcast data corresponding to the non-broadcast channel before scheduling the broadcast data corresponding to the broadcast channel indicated by the channel switching instruction;

[0022] In response to the data stored in the data FIFO queue being non-broadcast data, the second arbitrator determines that the channel corresponding to the data FIFO queue is a non-broadcast channel.

[0023] Optionally, the non-broadcast data and the broadcast data respectively carry corresponding flag bits, and the second arbitrator determines the type of data according to the flag bits, where the type includes broadcast data and non-broadcast data.

[0024] Optionally, the second arbitrator is further used to send first transmission completion information of the broadcast data to the broadcast controller, where the first transmission completion information is used to indicate that the channel corresponding to the second arbitrator completes the transmission of the broadcast data.

[0025] Optionally, the broadcast controller is further used to send second transmission completion information to the first arbitrator, where the second transmission completion information is used to indicate that all channels transmitting the broadcast data have completed transmission.

[0026] Optionally, in response to the first arbitrator receiving the second transmission completion information, the first arbitrator is used to schedule next new broadcast data.

[0027] In a second aspect, an embodiment of the present invention provides an integrated circuit, comprising multiple cores, an on-chip network, and a broadcast transmission circuit based on the on-chip network as described in the first aspect or any possible embodiment of the first aspect.

[0028] In a third aspect, an embodiment of the present invention provides a broadcast transmission method based on an on-chip network, the method comprising: scheduling direction information stored in a direction cache to determine target direction information; wherein, in response to received broadcast data, writing the direction information of the broadcast data into the direction cache; sending a channel switching instruction to a second arbitrator corresponding to the target direction information; and according to the channel switching instruction, controlling the channel of the second arbitrator corresponding to the target direction information so that the second arbitrator corresponding to the target direction information schedules the broadcast data corresponding to the target direction information.

[0029] In a fourth aspect, an embodiment of the present invention provides a board card, wherein the board card includes the integrated circuit of the second aspect.

[0030] In a fifth aspect, an embodiment of the present invention provides a server, wherein the server includes the board card according to the fourth aspect.

[0031] The embodiment of the present invention uses a control circuit and a broadcast router, wherein the control circuit includes a direction buffer and a control module; the broadcast router includes a receiving data port, a distribution module, a data first-in-first-out queue, a second arbitrator, and a transmission data port; the receiving data port is connected to the direction buffer, and the control module is connected to the second arbitrator; the direction buffer is used to store the direction information of the broadcast data; the control module is used to generate a channel switching instruction according to the direction information stored in the direction buffer, and the channel switching instruction is used to control the channel of the second arbitrator in the broadcast router, so that the second arbitrator corresponding to the direction information schedules the broadcast data cached in the data first-in-first-out queue, and each data first-in-first-out queue corresponds to a channel; the receiving data port is used to receive the broadcast data; the distribution module is used to distribute the received broadcast data to the corresponding data first-in-first-out queue; the second arbitrator is used to receive the channel switching instruction sent by the control module, and schedule the broadcast data cached in the data first-in-first-out queue according to the channel switching instruction; each transmission data port is used to output the broadcast data. Through the above circuit, the phenomenon of broadcast router hanging during multicast can be avoided, and the orderly transmission of broadcast can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0033] Figure 1 It is a schematic diagram of a broadcast transmission circuit in the prior art;

[0034] Figure 2 It is a schematic diagram of the internal circuit structure of a BR in the prior art;

[0035] Figure 3 It is a signal schematic diagram in the prior art;

[0036] Figure 4 It is a schematic diagram of the internal circuit structure of a BR during data transmission in the prior art;

[0037] Figure 5 is a schematic diagram of a broadcast transmission circuit based on an on-chip network according to an embodiment of the present invention;

[0038] Figure 6 is a flow chart of a broadcast transmission method based on an on-chip network according to an embodiment of the present invention;

[0039] Figure 7 is a flow chart of a broadcast transmission method based on an on-chip network according to an embodiment of the present invention;

[0040] Figure 8 is a flow chart of a broadcast transmission method based on an on-chip network according to an embodiment of the present invention;

[0041] Fig. 9 It is a flow chart of a broadcast transmission method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention is described below based on the embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, procedures, components and circuits are not described in detail.

[0043] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0044] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0045] In the description of the present invention, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

[0046] In the system on chip (SoC), a network on chip (NoC) is used to realize communication between subsystems. Specifically, the system on chip (SoC) includes multiple blocks (BANK), each of which includes multiple computing cores, such as Figure 1As shown, taking each BANK including 8 computing cores as an example, they are computing cores CORE0, CORE1, CORE2, CORE3, CORE4, CORE5, CORE6, and CORE7; each BANK also includes two last level registers (Last Level Buffer, LLB), respectively LLB0 and LLB1; each LLB includes two read and write ports S0 and S1, respectively, and each BANK also includes 6 broadcast routers (BroadcastRouter, BR), respectively BR0, BR1, BR2, BR3, BR4, and BR5; each BANK also includes two multicast stations (Broadcasting Station, BS), respectively BS0 and BS1; the 6 BRs form a routing network, which provides a routing path for data transmission between computing cores and between computing cores and LLBs, and the BS is used to control which cores of the multiple cores the data is multicast to; the BANK also includes two asynchronous bridges (Async Bridge), which are used to connect data with other BANKs across asynchronous clock domains.

[0047] Generally, in the prior art, when multiple computing cores need to share data, the main core first sends a read data request to the LLB, and the read data request includes a coremap[7:0] field segment, and the coremap[7:0] field segment is used to indicate which cores among the 8 cores need to share data, wherein coremap[0] to coremap[7] correspond to CORE0 to CORE7. Specifically, for example, coremap[7:0] is represented by a binary number representation method as 8'b11001100, indicating that CORE2, CORE3, CORE6 and CORE7 need to share data, that is, each CORE corresponds to one bit in the binary number; the coremap[7:0] can also be represented by a hexadecimal number representation method as 8'h. In the above embodiment, the main core can be determined according to preset rules. For example, the main core can be agreed to be the core with the smallest number among multiple computing cores that share data. For example, CORE1, CORE3, CORE4, and CORE5 need to share data, then CORE1 can be determined as the main core according to the preset rules; the main core can be the core with the largest number among multiple computing cores that share data. For example, CORE2, CORE5, CORE6, and CORE8 need to share data, then CORE8 can be determined as the main core according to the preset rules.

[0048] After receiving the read data request, the LLB returns the read data, and the read data is multicasted to the cores that need to share the data through the NoC transmission path. For example: CORE2, CORE3, CORE6, and CORE7 need to share the read data returned by LLB, and the data read from LLB0 is first transmitted to BR0 through BS0, where BS0 is used to control the multicasting of the read data to CORE2, CORE3, CORE6, and CORE7 that need to share the read data; then BR0 propagates the read data to BR2 through routing, and BR2 multicasts the read data to CORE2 and CORE3; at the same time, since CORE6 and CORE7 also need to share the read data, BR0 will also multicast the read data to BR1, and then route to BR5 through BR3, and then BR5 multicasts the read data to CORE6 and CORE7.

[0049] According to the above example, the BR can multicast the read data because of the internal circuit structure of the BR. Figure 2As shown, each direction of the BR can receive and send data. The port for receiving data is represented by RX. Each BR can receive data from four directions, that is, each BR includes four RXs, namely RX0, RX1, RX2 and RX3; the port for sending data is represented by TX. Each BR can send data in four directions, that is, each BR includes four TXs, namely TX0, TX1, TX2 and TX3. Among them, each direction of the RX corresponds to a distribution module (splitter), which is used to send the data received in this direction to the TXs in the other three directions. The BR also includes 4 splitters, namely Splitter0, Splitter1, Splitter2 and Splitter3. Each direction of the TX corresponds to an arbiter (Arbiter), which is used to arbitrate the data sent from the other three directions. The BR also includes 4 Arbiters, namely Arbiter0, Arbiter1, Arbiter2 and Arbiter3. And, the TX in each direction can receive data in three directions, and a buffer is set for the data received in each direction, and the buffer is a first-in-first-out queue (First Input First Output, FIFO). Then the BR also includes 12 FIFOs, among which the TX in each direction is provided with 3 FIFOs, which are respectively used to cache data from the other three directions, and the connection between each FIFO and the arbiter in that direction constitutes a channel. Specifically, the transmission process of the read data after entering the BR is as follows: first, it passes through the splitter distribution module, and the read data can be distributed to the FIFO in the target direction according to the routing principle of the shortest path. The data that needs to be routed to the same TX direction is aggregated on the TX side, that is, the three FIFOs in the target direction respectively aggregate the RX data in the three directions, and the data in each FIFO is consistent in the RX direction and the TX direction; the aggregated data is scheduled by the arbiter in the target direction for the data in its three FIFOs, and then sent to the TX port for output after scheduling.

[0050] Specifically, the burst granularity refers to the transmission unit of data, that is, the data structure of the transmission includes a head indication signal (head) and a tail indication signal (tail). The head is used to indicate the start of the transmission of a complete burst of data, and the tail is used to indicate the end of the transmission of a complete burst of data. There will be multiple beats of data transmission between the head and the tail, and the maximum length of the transmitted data is 1KB. For example, the size of a complete burst of data is 1KB. Assuming that the data first-in-first-out queue can store 8 data, and the size of one data is 16B (128 bits), the size of the data stored is much smaller than 1KB, and thus it is impossible to cache all the complete burst of data in the data first-in-first-out queue and then schedule it. Data can only be transmitted in the order of the data stream, that is, a burst of data is written into the queue in sequence according to the data size that can be stored in the data first-in-first-out queue. The data first-in-first-out queue can also be set to store other amounts of data, but in the application scenario of a broadcast router, the amount cannot be too large, because too large a number will waste resources. Arbiter scheduling uses burst data as the granularity, that is, when the arbiter arbitrates a channel to start transmitting data, it must wait until all burst data on the channel is transmitted before it can arbitrate and switch to other channels to transmit data. When data is transmitted in burst granularity, the clock signal (Clock), valid signal (valid), ready signal (ready), head indication signal (head), tail indication signal (tail) and data signal diagram are shown in the figure below. Figure 3 As shown, when the valid signal, the ready signal (ready) and the head indication signal (head) are all high at the same time, data transmission starts; when the valid signal (valid), the ready signal (ready) and the head indication signal (head) are all low at the same time, data transmission ends, wherein the valid signal (valid) is pulled high to indicate that there is data to be sent, and the ready signal (ready) is pulled high to indicate that the downstream is ready to receive data.

[0051] When BR supports multicast and supports data transmission in burst granularity, there will be a head-of-line blocking problem, which will cause the bus to hang. Specifically, Figure 4As shown, RX0 in BR corresponds to Splitter0, and Splitter0 can send the received data to TX1, TX2 and TX3 directions, that is, Splitter0 caches the received data in the data first-in-first-out queue FIFO corresponding to channel 0 of TX1, Splitter0 caches the received data in the data first-in-first-out queue FIFO corresponding to channel 0 of TX2, and Splitter0 caches the received data in the data first-in-first-out queue FIFO corresponding to channel 0 of TX3; the rest will not be repeated. Figure 4 shall prevail.

[0052] For example, when RX0 receives a broadcast data (Broadcast) that needs multicast transmission, namely Broadcast 1, the multicast direction of Broadcast1 is TX1 and TX3; at the same time, RX2 receives Broadcast2 that needs multicast transmission, and the multicast direction of Broadcast2 is also TX1 and TX3. If Arbiter1 is arbitrating the transmission of Broadcast1 data in the TX1 direction, and Arbiter3 is arbitrating the transmission of Broadcast2 data in the TX3 direction, that is, Broadcast1 is transmitted in the TX1 direction, and Broadcast2 is transmitted in the TX3 direction. Broadcast2 in the TX1 direction cannot be arbitrated before the transmission of Broadcast1 in the TX1 direction is completed, and thus it will be blocked in the FIFO corresponding to channel 2 of Arbiter1; Broadcast1 in the TX3 direction cannot be arbitrated before the transmission of Broadcast2 in the TX3 direction is completed, and thus it will be blocked in the FIFO corresponding to channel 0 of Arbiter3. If the length of the burst data transmitted by the two broadcasts is long and exceeds the depth of the data FIFO, the data FIFO resources will be insufficient and the data will be pushed back to the RX level by level, that is, RX0 and RX2 will not be able to receive new data, which will cause the burst data transmission of the two broadcasts to fail, causing the NoC bus to hang. Therefore, how to avoid the hang phenomenon when the broadcast router multicasts and realize the orderly transmission of broadcasts is a problem that needs to be solved.

[0053] In an embodiment of the present invention, a broadcast transmission circuit based on a network on a chip is proposed, and a hang phenomenon that occurs when a broadcast router performs multicast is solved by a control circuit.

[0054] In the embodiment of the present invention, Figure 5The present invention is a schematic diagram of a broadcast transmission circuit based on a network on chip according to an embodiment of the present invention, wherein the broadcast transmission circuit based on a network on chip comprises a control circuit 501 and a broadcast router 502, wherein the control circuit comprises a direction buffer and a control module; the broadcast router comprises a receiving data port 5021, a distribution module 5022, a data first-in-first-out queue 5023, a second arbiter 5024, and a transmission data port 5025. The receiving data port 5021 is connected to the direction buffer, and when the receiving data port 5021 receives multicast data, the direction information of the multicast data will be synchronously written into the direction buffer, and the distribution module 5022 is used to distribute the received broadcast data to the corresponding data first-in-first-out queue. The control module is connected to the second arbitrator 5024, and the control module generates a channel switching instruction according to the direction information stored in the direction buffer area, and the channel switching instruction is used to control the channel of the second arbitrator in the broadcast router, wherein each of the data first-in-first-out queues of the second arbitrator corresponds to a channel; the second arbitrator receives the channel switching instruction sent by the control module, and schedules the broadcast data cached in the data first-in-first-out queue according to the channel switching instruction; each of the transmission data ports is used to output the broadcast data.

[0055] In the embodiment of the present invention, due to the design of the control circuit, the broadcast router can only transmit one broadcast at a time under the control of the control circuit, and will not transmit two broadcasts at the same time. Therefore, the bus hanging phenomenon in the prior art will not occur, and the orderly propagation of the broadcast is guaranteed.

[0056] In a possible implementation, the direction buffer area is N broadcast first-in-first-out queues 5011 ; the control module includes a first arbitrator 5012 and a broadcast controller 5013 .

[0057] In a possible implementation, the number of the receiving data ports, the distribution module, the second arbitrator, and the transmission data ports is N, and the number of the data FIFO queues is N*M, wherein N and M are positive integers, and M represents the number of data FIFO queues corresponding to each transmission data port. The N receiving data ports 5021 are respectively connected to the N broadcast FIFO queues 5011, and the broadcast controller 5013 is connected to the N second arbitrators 5024. Through this implementation, since the N broadcast FIFO queues 5011 have a one-to-one correspondence with the N receiving data ports, that is, each broadcast FIFO queue stores the direction information of the broadcast data of the corresponding receiving data port, it is convenient for the first arbitrator to schedule the direction information of the broadcast data of each receiving data port.

[0058] In a possible implementation, the direction buffer is used to store direction information of broadcast data; the control module is used to generate a channel switching instruction according to the direction information stored in the direction buffer, and the channel switching instruction is used to control the channel of the second arbitrator in the broadcast router, so that the second arbitrator corresponding to the direction information schedules the broadcast data cached in the data first-in-first-out queue, and each of the data first-in-first-out queues corresponds to a channel.

[0059] Specific as Figure 5 As shown, taking RX0 as an example, RX0 has a corresponding distribution module splitter0, which is used to send the data received in this direction to TX1, TX2 and TX3 in the other three directions; TX in each direction can receive data in three directions. Taking TX0 as an example, TX0 can receive data from RX1, RX2 and RX3. There is a data FIFO corresponding to the data in each direction, that is, TX0 has 3 FIFOs, which are used to cache the data from RX1, RX2 and RX3 in three directions respectively, and the connection between each FIFO and the Arbiter in this direction constitutes a channel.

[0060] In a possible implementation, N is a positive integer greater than or equal to 3, and M is a positive integer greater than or equal to 2. Specifically, since BR is used to implement multicast, there is at least one input RX and two output TXs, and each TX also corresponds to an RX in the same direction, and each RX also corresponds to a TX in the same direction, so at least 3 TXs and 3 RXs are required, and then at least three groups of broadcast FIFOs connected to RX are required; since multicast is transmitted in at least two directions, in the broadcast router, at least 2 groups of data FIFOs are connected to each second arbitrator.

[0061] In a possible implementation, the direction information is stored in the data packet header of the broadcast data, that is, the direction information is stored in the head indication signal of the broadcast data, and the direction information is used to indicate the port number of the transmission data port that outputs the broadcast information. Assuming that the direction information is represented by a binary number, if RX0 receives a Broadcast that needs to be sent to TX1 and TX3, the direction information in the data packet header of the Broadcast can be represented as 4'b0101, and the binary number corresponds to TX0 to TX3, that is, the binary number is 1, indicating that it needs to be transmitted to the corresponding TX, and the binary number is 0, indicating that it does not need to be transmitted to the corresponding TX. Here, the meanings of 1 and 0 are not fixed, and the embodiments of the present invention do not limit them.

[0062] In a possible implementation, the bit width of each of the broadcast FIFO queues is greater than or equal to the number of bits of the direction information, and each memory address of the broadcast FIFO queue can cache the direction information of a broadcast data, and then the first arbitrator reads the data in the broadcast FIFO queue once to determine the direction information of the broadcast data corresponding to the data. For example, if the number of bits of the direction information is 4, the bit width of the broadcast FIFO queue is greater than or equal to 4.

[0063] In a possible implementation, the first arbitrator is used to schedule the direction information cached in the N broadcast FIFO queues. For example, assuming that RX0 and RX2 both receive broadcast data, wherein RX0 receives Broadcast1 and RX2 receives Broadcast2, RX0 stores the direction information in the header of Broadcast1 into the broadcast FIFO queue corresponding to RX0, and RX2 stores the direction information in the header of Broadcast2 into the broadcast FIFO queue corresponding to RX2. The first arbitrator performs polling scheduling on the direction information stored in the broadcast FIFO queue corresponding to RX0 and the direction information stored in the broadcast FIFO queue corresponding to RX2. Only the direction information in one broadcast FIFO queue can be scheduled at a time, wherein the polling scheduling refers to querying and scheduling according to the set rules, and the set rules can be the order of data storage time, the order of data volume, or the order of broadcast FIFO queues. For example, the first arbitrator first schedules the direction information in the broadcast FIFO queue corresponding to RX0, and after the scheduling is completed, it schedules the direction information stored in the broadcast FIFO queue corresponding to RX2. This process can be called polling scheduling.

[0064] In a possible implementation, after the first arbitrator obtains the direction information, it sends it to the broadcast controller, and the broadcast controller is used to generate the channel switching instruction according to the direction information scheduled by the first arbitrator, so that each second arbitrator corresponding to the direction information scheduled by the first arbitrator schedules the broadcast data cached in the corresponding M data first-in-first-out queues.

[0065] In a possible implementation, the second arbitrator is also used to send non-broadcast data, and the non-broadcast data is data that has only one corresponding transmission data port, that is, the data only needs to be output through one transmission data port. Specifically, after the second arbitrator corresponding to the direction information receives the channel switching instruction sent by the broadcast controller, the second arbitrator continues the polling operation, and when polling for non-broadcast data of a non-broadcast channel, the non-broadcast data is first transmitted; when polling to the broadcast channel indicated by the channel switching instruction, the broadcast data is transmitted.

[0066] In response to the data stored in the data FIFO queue being non-broadcast data, the second arbitrator determines that the channel corresponding to the data FIFO queue is a non-broadcast channel; in response to the data stored in the data FIFO queue being broadcast data, the second arbitrator determines that the channel corresponding to the data FIFO queue is a broadcast channel; wherein the non-broadcast data and the broadcast data respectively carry corresponding flag bits, and the second arbitrator determines the type of data according to the flag bits.

[0067] In the embodiment of the present invention, since the data FIFO stores limited data, and the lengths of the broadcast data and the parallel broadcast data are relatively long, it is generally not the case that the data FIFO stores both the broadcast data and the parallel broadcast data.

[0068] Optionally, the non-broadcast data and the broadcast data additionally carry a valid bit, and the first two bits in the data first-in-first-out queue store a flag bit and a valid bit. Figure 5 In the embodiment, a data FIFO space can store 128 bits of data (called FIFO bit width), and the data FIFO can include multiple grids (called FIFO depth).

[0069] In a possible implementation, in response to the second arbitrator polling a broadcast channel, but the broadcast channel is not the broadcast channel included in the channel switching instruction, the second arbitrator skips the broadcast channel and continues to poll the next channel. For example, assuming that the second arbitrator corresponds to 3 channels, wherein the first channel is the broadcast channel indicated in the channel switching instruction, the second channel is a non-broadcast channel, and the third channel is a broadcast channel, but the third channel is not the broadcast channel indicated in the channel switching instruction; assuming that before switching to the first channel, the second channel and the third channel need to be polled first, when polling the second channel, since the second channel is a non-broadcast channel, the non-broadcast data in the second channel needs to be transmitted; when polling the third channel, since the third channel is a broadcast channel but not the broadcast channel indicated in the channel switching instruction, the third channel needs to be skipped and the data in the third channel is not processed.

[0070] In a possible implementation, the second arbitrator is further configured to send first transmission completion information of the broadcast data to the broadcast controller, wherein the first transmission completion information is used to indicate that the channel corresponding to the second arbitrator has completed the transmission of the broadcast data. After receiving the first transmission completion information, the broadcast controller is further configured to send second transmission completion information to the first arbitrator, wherein the second transmission completion information is used to indicate that all channels transmitting the broadcast data have completed the transmission.

[0071] In a possible implementation manner, in response to the first arbitrator receiving the second transmission completion information, the first arbitrator is used to schedule next new broadcast data.

[0072] A broadcast transmission method based on an on-chip network is described in detail below through two specific embodiments.

[0073] Specific embodiment 1: Figure 6 The method comprises the following steps:

[0074] Step S600: scheduling direction information stored in a direction buffer to determine target direction information; wherein, in response to received broadcast data, writing the direction information of the broadcast data into the direction buffer.

[0075] Optionally, the direction buffer may store direction information of multiple broadcast data, and the multiple direction information may be processed in a polling manner. The target direction information is the direction information to be processed currently.

[0076] Step S601: Send a channel switching instruction to a second arbitrator corresponding to the target direction information.

[0077] Step S602: According to the channel switching instruction, control the channel of the second arbitrator corresponding to the target direction information, so that the second arbitrator corresponding to the target direction information schedules the broadcast data corresponding to the target direction information.

[0078] Specific embodiment 2: Figure 7 The method comprises the following steps:

[0079] Step S700: RX receives a broadcast packet and writes the direction information in the Broadcast packet header into the broadcast FIFO.

[0080] Step S701: The first arbitrator schedules the direction information in the broadcast FIFO and sends the direction information to the broadcast controller.

[0081] Step S702: The broadcast controller sends a channel switching instruction to a second arbitrator corresponding to the direction information according to the direction information.

[0082] The channel switching instruction is used to instruct the broadcast channel to transmit the Broadcast.

[0083] Step S703: the second arbitrator switches to the broadcast channel corresponding to the channel switching instruction immediately after transmitting the current Burst data; or, the second arbitrator switches to the broadcast channel corresponding to the channel switching instruction after polling the non-broadcast channel.

[0084] Specifically, a specific example of the first case in step S703 is as follows. According to the direction information, it can be known that RX0 has a Broadcast that needs to be sent to TX1 and TX3, then the Broadcast controller will send a channel switching instruction to Arbiter1 corresponding to TX1 and Arbiter3 corresponding to TX3, requiring both Arbiter1 and Arbiter3 to switch to channel 0 to transmit Broadcast data.

[0085] The specific example of the second situation in step S703 is as follows: after receiving the control signal, the second arbitrator will not immediately switch to the channel indicated by the broadcast controller, but needs to continue to poll and transmit non-broadcast data. When the channel required to switch is polled, broadcast transmission is performed to prevent non-broadcast data from starving. For example, when arbiter2 is required by the broadcast controller to switch to channel 0 to transmit broadcast data, but arbiter2 is arbitrating the non-broadcast data of channel 1 at this time, and channel 3 also has non-broadcast data to be transmitted, arbiter1 will first arbitrate and transmit the data of channels 1 and 3 before transmitting the broadcast data of arbitration channel 0.

[0086] Step S704: The second arbitrator sends broadcast data first transmission completion information to the broadcast controller.

[0087] The first transmission completion information is used to indicate that the channel corresponding to the second arbitrator completes the transmission of the broadcast data.

[0088] Step S705: The broadcast controller sends second transmission completion information to the first arbitrator.

[0089] The second transmission completion information is used to indicate that all channels transmitting the broadcast data have completed the transmission.

[0090] In one possible implementation, Figure 8 As shown, after step S705, the method further includes:

[0091] Step S706: The first arbitrator receives the second transmission completion information and schedules direction information corresponding to the next new broadcast data.

[0092] In the embodiment of the present invention, after step S706, steps S700 to S705 are executed again.

[0093] The following is a detailed description of the method for coordinating broadcasts on the broadcast router side during broadcast transmission through a specific embodiment. Fig. 9 The method comprises the following steps:

[0094] Step S900: The receiving data port of the broadcast router receives the broadcast.

[0095] Step S901: The receiving data port sends the broadcast to a distribution module corresponding to the receiving data port.

[0096] Step S902: The distribution module sends the broadcast data to at least two data first-in-first-out queues, wherein the at least two data first-in-first-out queues correspond to different second arbitrators respectively.

[0097] Step S903: At least two of the second arbitrators receive a channel switching instruction sent by the control circuit.

[0098] Step S904: Each of the second arbitrators polls and transmits non-broadcast data of the non-broadcast channel, and when polling the broadcast channel indicated by the channel switching instruction, transmits the broadcast data in the data first-in-first-out queue.

[0099] That is, each of the second arbitrators preferentially transmits the non-broadcast data in the channel corresponding to it, and preferentially transmits the broadcast data in the channel corresponding to the channel switching instruction after completing the transmission of the non-broadcast data.

[0100] In the embodiment of the present invention, by adding a control circuit, locking phenomenon is avoided during broadcast data transmission, and resource consumption is smaller than that of increasing the depth of the data FIFO. Moreover, during broadcast transmission, the arbiter that does not participate in the broadcast transmission can continue to transmit non-broadcast data, and performance loss is smaller.

[0101] An integrated circuit is provided in an embodiment of the present invention. The integrated circuit includes multiple cores, an on-chip network, and a broadcast transmission circuit based on the on-chip network.

[0102] An embodiment of the present invention provides a board card, and the board card includes the integrated circuit.

[0103] An embodiment of the present invention provides a server, and the server includes the board.

[0104] As will be appreciated by those skilled in the art, various aspects of the embodiments of the present invention may be implemented as a system, method or computer program product. Therefore, various aspects of the embodiments of the present invention may take the form of a complete hardware implementation, a complete software implementation (including firmware, resident software, microcode, etc.), or an implementation that combines software aspects with hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." In addition, various aspects of the embodiments of the present invention may take the form of a computer program product implemented in one or more computer-readable media having a computer-readable program code implemented thereon.

[0105] Any combination of one or more computer-readable media can be utilized. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, (but not limited to) electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or apparatuses, or any suitable combination of the foregoing. More specific examples (non-exhaustive enumeration) of computer-readable storage media will include the following: an electrical connection with one or more wires, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of an embodiment of the present invention, a computer-readable storage medium can be any tangible medium that can contain or store a program used by an instruction execution system, device or apparatus or a program used in conjunction with an instruction execution system, device or apparatus.

[0106] A computer readable signal medium may include a propagated data signal having a computer readable program code implemented therein, such as in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any of the following computer readable media: not a computer readable storage medium, and may communicate, propagate, or transmit a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0107] Program code embodied on a computer readable medium may be transmitted using any appropriate medium including, but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0108] The computer program code for performing operations for various aspects of the embodiments of the present invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, C++, etc., and conventional process programming languages ​​such as "C" programming language or similar programming languages. The program code can be executed completely on the user's computer, partially on the user's computer as a stand-alone software package; partially on the user's computer and partially on a remote computer; or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., by using the Internet of an Internet service provider).

[0109] The flowchart legend and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present invention described above describe various aspects of the embodiment of the present invention.It will be understood that each block of the flowchart legend and / or block diagram and the combination of the blocks in the flowchart legend and / or block diagram can be implemented by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that the instructions (executed by the processor of the computer or other programmable data processing device) create a device for implementing the function / action specified in the flowchart and / or block diagram block or block.

[0110] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing device, or other apparatus to operate in a particular manner, so that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / actions specified in the flowchart and / or block diagram blocks or blocks.

[0111] The computer program instructions may also be loaded onto a computer, other programmable data processing device or other apparatus so that a series of operable steps are performed on the computer, other programmable device or other apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide a process for implementing the functions / actions specified in the flowchart and / or block diagram block or blocks.

[0112] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A broadcast transmission circuit based on a network on chip, characterized in that: The circuit includes: A control circuit and a broadcast router, wherein the control circuit comprises a direction buffer and a control module; The broadcast router includes a receiving data port, a distribution module, a data first-in-first-out queue, a second arbitrator, and a transmitting data port; The receiving data port is connected to the direction buffer, and the control module is connected to the second arbitrator; The direction buffer is used to store the direction information of the broadcast data; the control module is used to generate a channel switching instruction according to the direction information stored in the direction buffer, and the channel switching instruction is used to control the channel of the second arbitrator in the broadcast router, so that the second arbitrator corresponding to the direction information schedules the broadcast data cached in the data first-in-first-out queue, and each data first-in-first-out queue corresponds to a channel; The receiving data port is used to receive the broadcast data, and in response to the receiving data port receiving the broadcast data, the direction information of the broadcast data is synchronously written into the direction buffer area; the distribution module is used to distribute the received broadcast data to the corresponding data first-in-first-out queue; the second arbitrator is used to receive the channel switching instruction sent by the control module, and schedule the broadcast data cached in the data first-in-first-out queue according to the channel switching instruction; each of the transmission data ports is used to output the broadcast data.

2. The circuit according to claim 1, characterized in that The direction buffer area is N broadcast first-in-first-out queues, and the control module includes a first arbitrator and a broadcast controller; The number of the receiving data port, the distribution module, the second arbiter, and the transmitting data port is N, and the number of the data first-in-first-out queue is N*M; The N receiving data ports are respectively connected to the N broadcast FIFO queues, and the broadcast controller is connected to the N second arbitrators; Each of the broadcast FIFO queues is used to store the direction information of the broadcast data received by its corresponding receiving data port; the first arbitrator is used to schedule the direction information cached in the N broadcast FIFO queues; the broadcast controller is used to generate the channel switching instruction according to the direction information scheduled by the first arbitrator, so that each second arbitrator corresponding to the direction information scheduled by the first arbitrator schedules the broadcast data cached in its corresponding M data FIFO queues; Wherein, N and M are positive integers, and M is the number of data first-in-first-out queues set corresponding to each data transmission port.

3. The circuit according to claim 1, characterized in that The direction information is stored in a data packet header of the broadcast data, and the direction information is used to indicate a port number of a transmission data port for outputting the broadcast data.

4. The circuit according to any one of claims 1 to 3, characterized in that: In response to the second arbitrator receiving the channel switching instruction sent by the control module, the second arbitrator is used to schedule the broadcast data corresponding to the broadcast channel indicated by the channel switching instruction; In response to the data stored in the data FIFO queue being broadcast data, the second arbitrator determines that the channel corresponding to the data FIFO queue is a broadcast channel.

5. The circuit according to claim 4, characterized in that In response to a non-broadcast channel in the channels of the second arbitrator, the second arbitrator is further configured to schedule non-broadcast data corresponding to the non-broadcast channel before scheduling the broadcast data corresponding to the broadcast channel indicated by the channel switching instruction; In response to the data stored in the data FIFO queue being non-broadcast data, the second arbitrator determines that the channel corresponding to the data FIFO queue is a non-broadcast channel.

6. The circuit according to claim 5, characterized in that The non-broadcast data and the broadcast data carry corresponding flag bits respectively, and the second arbitrator determines the type of data according to the flag bits, where the type includes broadcast data and non-broadcast data.

7. The circuit according to claim 2, characterized in that The second arbitrator is further used to send first transmission completion information of the broadcast data to the broadcast controller, where the first transmission completion information is used to indicate that the channel corresponding to the second arbitrator completes the transmission of the broadcast data.

8. The circuit according to claim 7, characterized in that The broadcast controller is further used to send second transmission completion information to the first arbitrator, where the second transmission completion information is used to indicate that all channels transmitting the broadcast data have completed transmission.

9. An integrated circuit, characterized in that: The integrated circuit includes a plurality of cores, a network on chip, and a broadcast transmission circuit based on the network on chip according to any one of claims 1 to 8.

10. A broadcast transmission method based on an on-chip network, characterized in that: The method includes: The direction information stored in the scheduling direction buffer area is used to determine the target direction information; wherein, in response to the received broadcast data, the direction information of the broadcast data is written into the direction buffer area, and the received broadcast data is distributed to the corresponding data first-in-first-out queue; generating a channel switching instruction according to the direction information stored in the direction buffer, wherein the channel switching instruction is used to control the channel of the second arbitrator in the broadcast router; Sending a channel switching instruction to a second arbitrator corresponding to the target direction information; According to the channel switching instruction, the channel of the second arbitrator corresponding to the target direction information is controlled, and the second arbitrator schedules the broadcast data cached in the data first-in-first-out queue according to the channel switching instruction; Each of the data first-in-first-out queues corresponds to a channel.

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