Imaging Device and Imaging Control Method

Abstract

Embodiments of the present application disclose an imaging device and an imaging control method, belonging to the field of optoelectronic detection technology. In the embodiments of the present application, a switch array and a multiplexer in the imaging unit can sequentially output first image data corresponding to each of a plurality of macro pixels. The processing unit receives the first image data corresponding to each macro pixel, and generates a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel. Since there are overlapping SPAD sub-pixels between every two adjacent macro pixels in the SPAD array in the imaging unit, the number of image data corresponding to the macro pixels output by the imaging unit is increased through the switch array and the multiplexer, thereby improving the planar resolution of the output image without increasing the number of SPAD sub-pixels and subsequent storage.

Description

Technical Field

[0001] This application relates to the field of optoelectronic detection technology, and particularly to an imaging device and an imaging control method. Background Art

[0002] The 3D imaging technology based on a SPAD (Single Photon Avalanche Diode) array has been a research hotspot in recent years and has great application prospects in fields such as consumer electronics, security, robotics, and autonomous driving.

[0003] In the related art, in order to save circuit area, n SPAD sub-pixels that are adjacent to each other spatially in the SPAD array are divided into a macro-pixel, and the n SPAD sub-pixels within each macro-pixel share the same set of processing circuits. In this way, each macro-pixel corresponds to one pixel data. Correspondingly, the resolution of the finally output image is also reduced to 1 / n of the resolution before the macro-pixels are divided. For example, see Figure 1 , 2*2 SPAD sub-pixels that are adjacent to each other spatially are divided into a macro-pixel, and one pixel data is output. In this case, when the SPAD array includes 320*240 SPAD sub-pixels, the resolution of the output image will be 160*120. It can be seen that the imaging method in the related art causes a large loss in the planar resolution of the output image of the SPAD array. Summary of the Invention

[0004] Embodiments of this application provide an imaging device and an imaging control method, which can improve the planar resolution on the basis of the same number of sub-pixels in the SPAD array and subsequent circuits. The technical solution is as follows:

[0005] On the one hand, an imaging device is provided. The imaging device includes: an imaging unit and a processing unit. The imaging unit includes a single photon avalanche diode SPAD array, a switch array, and a multiplexer. The SPAD array includes a plurality of macro-pixels. Each macro-pixel in the plurality of macro-pixels includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro-pixels;

[0006] The switch array is configured to receive the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel in the plurality of macro-pixels, synthesize the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel, obtain one path of first image data corresponding to the corresponding macro-pixel, and output one path of first image data corresponding to each macro-pixel;

[0007] The multiplexer is configured to receive multiple paths of first image data output by the switch array, and sequentially output the multiple paths of first image data to the processing unit;

[0008] The processing unit is configured to receive the first image data corresponding to each macro pixel sequentially output by the multiplexer, and generate a fused image based on the positions of the respective macro pixels, the corresponding first image data, and the corresponding macro pixels.

[0009] Optionally, the switch array includes a first-stage logical OR gate and a second-stage logical OR gate. One row of SPAD sub-pixels in a first macro pixel is connected to one first-stage logical OR gate, and multiple first-stage logical OR gates connected to multiple rows of SPAD sub-pixels in the first macro pixel are connected to one second-stage logical OR gate. The first macro pixel is any one of the multiple macro pixels;

[0010] Each first-stage logical OR gate connected to the first macro pixel is configured to receive the sub-pixel data output by each SPAD sub-pixel in the row of SPAD sub-pixels it is connected to, and synthesize the received sub-pixel data into one path of row pixel data, and output the row pixel data;

[0011] The second-stage logical OR gate connected to the first macro pixel is configured to receive the row pixel data respectively output by the multiple first-stage logical OR gates it is connected to, synthesize the received row pixel data, obtain the first image data corresponding to the first macro pixel, and output the first image data corresponding to the first macro pixel.

[0012] Optionally, the switch array includes a first-stage logical OR gate and a second-stage logical OR gate. One column of SPAD sub-pixels in a first macro pixel is connected to one first-stage logical OR gate, and multiple first-stage logical OR gates connected to multiple columns of SPAD sub-pixels in the first macro pixel are connected to one second-stage logical OR gate. The first macro pixel is any one of the multiple macro pixels;

[0013] Each first-stage logical OR gate connected to the first macro pixel is configured to receive one path of sub-pixel data output by each SPAD sub-pixel in the column of SPAD sub-pixels it is connected to, and synthesize the received sub-pixel data into one path of column pixel data, and output the column pixel data;

[0014] The second-stage logical OR gate connected to the first macro pixel is configured to receive the column pixel data respectively output by the multiple first-stage logical OR gates it is connected to, synthesize the received column pixel data, obtain the first image data corresponding to the first macro pixel, and output the first image data corresponding to the first macro pixel.

[0015] Optionally, the multiplexer includes a plurality of input terminals, an output terminal, and a control terminal. The plurality of input terminals of the multiplexer are connected to the switch array, the control terminal of the multiplexer is connected to the control terminal of the processing unit, and the output terminal of the multiplexer is connected to the input terminal of the processing unit;

[0016] Each input terminal of the multiplexer is used to receive a first image data of one path output by the switch array;

[0017] The control terminal of the multiplexer is used to receive a gating signal output by the control terminal of the processing unit at each measurement moment;

[0018] The output terminal of the multiplexer is used to output a first image data of one path corresponding to the gating signal received at the corresponding measurement moment at each measurement moment.

[0019] Optionally, the processing unit is configured to determine the position of the macro pixel corresponding to the first image data corresponding to the received corresponding gating signal according to the gating signal output at each measurement moment, and use the first image data corresponding to the corresponding gating signal as the pixel data at the determined position of the macro pixel, so as to generate the fused image.

[0020] Optionally, every two adjacent macro pixels among the plurality of macro pixels have (N - 1) rows of overlapping SPAD sub-pixels, or every two adjacent macro pixels among the plurality of macro pixels have (M - 1) columns of overlapping SPAD sub-pixels.

[0021] On the other hand, an imaging control method is provided. The method is applied to the processing unit of an imaging device. The imaging device further includes an imaging unit. The imaging unit includes a single-photon avalanche diode (SPAD) array, a switch array, and a multiplexer. The SPAD array includes a plurality of macro pixels. Each macro pixel among the plurality of macro pixels includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro pixels. Wherein, the switch array is configured to receive the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro pixel among the plurality of macro pixels, synthesize the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro pixel, obtain a first image data of one path corresponding to the corresponding macro pixel, and output a first image data of one path corresponding to each macro pixel to the multiplexer; The method includes:

[0022] The processing unit sequentially outputs different types of gating signals to the multiplexer according to a preset timing sequence, so that when the multiplexer receives a type of gating signal output by the processing unit each time, the multiplexer outputs the first image data corresponding to the corresponding gating signal;

[0023] The processing unit receives the first image data corresponding to each macro-pixel sequentially output by the multiplexer, and generates a fused image according to the first image data corresponding to each macro-pixel and the position of the corresponding macro-pixel.

[0024] Optionally, the switch array includes a first-stage logical OR gate and a second-stage logical OR gate. One row of SPAD sub-pixels in the first macro-pixel is connected to one first-stage logical OR gate, and multiple first-stage logical OR gates connected by multiple rows of SPAD sub-pixels in the first macro-pixel are connected to one second-stage logical OR gate. The first macro-pixel is any one of the multiple macro-pixels;

[0025] Each first-stage logical OR gate connected to the first macro-pixel is configured to receive the sub-pixel data output by each SPAD sub-pixel in one row of the SPAD sub-pixels connected thereto, and synthesize the received sub-pixel data into one-way row pixel data, and output the row pixel data;

[0026] The second-stage logical OR gate connected to the first macro-pixel is configured to receive the row pixel data respectively output by the multiple first-stage logical OR gates connected thereto, synthesize the received row pixel data, obtain the first image data corresponding to the first macro-pixel, and output the first image data corresponding to the first macro-pixel.

[0027] Optionally, the switch array includes a first-stage logical OR gate and a second-stage logical OR gate. One column of SPAD sub-pixels in the first macro-pixel is connected to one first-stage logical OR gate, and multiple first-stage logical OR gates connected by multiple columns of SPAD sub-pixels in the first macro-pixel are connected to one second-stage logical OR gate. The first macro-pixel is any one of the multiple macro-pixels;

[0028] Each first-stage logical OR gate connected to the first macro-pixel is configured to receive one-way sub-pixel data output by each SPAD sub-pixel in one column of the SPAD sub-pixels connected thereto, and synthesize the received sub-pixel data into one-way column pixel data, and output the column pixel data;

[0029] The second-stage logical OR gate connected to the first macro-pixel is configured to receive the column pixel data respectively output by the multiple first-stage logical OR gates connected thereto, synthesize the received column pixel data, obtain the first image data corresponding to the first macro-pixel, and output the first image data corresponding to the first macro-pixel.

[0030] Optionally, the multiplexer includes a plurality of input terminals, an output terminal, and a control terminal. The plurality of input terminals of the multiplexer are connected to the switch array, the control terminal of the multiplexer is connected to the control terminal of the processing unit, the output terminal of the multiplexer is connected to the input terminal of the processing unit, and each input terminal of the multiplexer is configured to receive a path of first image data output by the switch array;

[0031] The processing unit sequentially outputs different types of gating signals to the multiplexer according to a preset timing sequence, including:

[0032] The control terminal of the processing unit outputs a first gating signal to the control terminal of the multiplexer at a first measurement moment, so that the output terminal of the multiplexer outputs a path of first image data corresponding to the first gating signal at the first measurement moment, and the first measurement moment is any one of a plurality of measurement moments.

[0033] Optionally, the processing unit generates a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel, including:

[0034] Determine the position of the macro pixel corresponding to the first image data corresponding to the received corresponding gating signal according to the gating signal output at each measurement moment;

[0035] Use the first image data corresponding to the corresponding gating signal as the pixel data at the position of the macro pixel determined at the corresponding measurement moment to generate the fused image.

[0036] Optionally, every two adjacent macro pixels among the plurality of macro pixels have (N - 1) rows of overlapping SPAD sub-pixels, or every two adjacent macro pixels among the plurality of macro pixels have (M - 1) columns of overlapping SPAD sub-pixels.

[0037] On the other hand, an imaging device is provided, and the device includes:

[0038] A processor;

[0039] A memory for storing processor-executable instructions;

[0040] Wherein, the processor executes the executable instructions in the memory to execute the above imaging control method.

[0041] On the other hand, a computer program product including instructions is provided, and when it runs on a computer, it causes the computer to execute the steps of the above imaging control method.

[0042] The beneficial effects brought by the technical solution provided by the embodiments of the present application at least include:

[0043] In an embodiment of the present application, a switch array and a multiplexer in an imaging unit can sequentially output first image data corresponding to each macro-pixel among a plurality of macro-pixels. A processing unit receives the first image data corresponding to each macro-pixel, and generates a fused image according to the first image data corresponding to each macro-pixel and the position of the corresponding macro-pixel. Since there are overlapping SPAD sub-pixels between every two adjacent macro-pixels among the plurality of macro-pixels included in the SPAD array in the imaging unit, the number of image data corresponding to the macro-pixels output by the imaging unit is increased by the switch array and the multiplexer. Therefore, the planar resolution of the output image is improved without increasing the number of SPAD sub-pixels and subsequent storage. Description of the Drawings

[0044] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0045] Figure 1 is a structural diagram of a SPAD array;

[0046] Figure 2 is a system architecture diagram related to an imaging device provided by an embodiment of the present application;

[0047] Figure 3 is a schematic structural diagram of an imaging device provided by an embodiment of the present application;

[0048] Figure 4 is a schematic diagram of a macro-pixel in a SPAD array provided by an embodiment of the present application;

[0049] Figure 5 is a schematic diagram of the connection relationship between a macro-pixel and a switch array provided by an embodiment of the present application;

[0050] Figure 6 is a schematic diagram of another connection relationship between a macro-pixel and a switch array provided by an embodiment of the present application;

[0051] Figure 7 is a schematic structural diagram of another imaging device provided by an embodiment of the present application;

[0052] Figure 8 is a schematic diagram of a fused image generated by an imaging device provided by an embodiment of the present application;

[0053] Figure 9 is a flowchart of an imaging control method provided by an embodiment of the present application. Detailed Embodiments

[0054] To make the objectives, technical solutions, and advantages of this application more clear, the following will further describe in detail the embodiments of this application with reference to the accompanying drawings.

[0055] Before explaining the embodiments of this application in detail, first introduce the system architecture involved in the embodiments of this application.

[0056] Figure 2 is a system architecture diagram related to an imaging device provided by an embodiment of this application. As Figure 2 shown, the system includes an imaging device 10, a router 20, and a server 30. The imaging device 10 is connected to the router 20, and the router 20 is connected to the server 30. Among them, the imaging device 10 is used to generate an image and output the generated image to the router 20; the router 20 is used to transmit the image generated by the imaging device 10 to the server 30; the server 30 is used to receive the image transmitted by the router 20 and store the received image.

[0057] Among them, the imaging device 10 includes a processing unit 101 and an imaging unit 102. The imaging unit 102 includes a SPAD array. Among them, the SPAD array includes a plurality of macro pixels, each macro pixel includes a plurality of SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro pixels. The imaging unit 102 is used to output first image data corresponding to each macro pixel, and the processing unit 101 is used to receive the first image data corresponding to each macro pixel output by the imaging unit 102 and generate a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel. It should be noted that the detailed implementation manner of the imaging unit 102 can be referred to the introduction in the following text and will not be elaborated here.

[0058] In addition, the imaging device 10 may further include a laser driver 103, a laser 104, a transmitting lens 105, and a receiving lens 106.

[0059] The laser driver 103 can be respectively connected to the imaging unit 102 and the laser 104. The imaging unit 102 can send a transmission start instruction to the laser driver 103 and start timing while sending the transmission start instruction. After receiving the transmission start instruction, the laser driver 103 drives the laser 104 to emit laser light.

[0060] The transmitting lens 105 is used to emit the laser light emitted by the laser 104 and irradiate it on the target object. The transmitting lens 105 can be fixed on the laser 104 or installed inside the laser 104.

[0061] The receiving lens 106 is configured to receive the light reflected by the target object, and then emit the received reflected light onto each SPAD sub-pixel of the SPAD array in the imaging unit 102, so that each SPAD sub-pixel of the SPAD array in the imaging unit 102 outputs sub-pixel data according to the detected reflected light signal, and further enables the imaging unit 102 to output the first image data corresponding to each macro-pixel according to each sub-pixel data. The receiving lens 106 can be fixed above the SPAD array in the imaging unit 102 or installed within the SPAD array 102.

[0062] Optionally, in some possible implementation manners, after obtaining the fused image, the imaging device 10 may further perform intelligent analysis based on the fused image, and then send the fused image and the intelligent analysis result to the server 30 together through the router 20, so that the server 30 stores the fused image and the intelligent analysis result for subsequent use in other services.

[0063] Next, the imaging device provided in the embodiment of the present application will be introduced.

[0064] Figure 3 is a schematic diagram of an imaging device provided in the embodiment of the present application. As Figure 3 shown, the device includes: an imaging unit 301 and a processing unit 302. The imaging unit 301 includes a SPAD array 3011, a switch array 3012, and a multiplexer 3013. The SPAD array 3011 includes a plurality of macro-pixels, each macro-pixel in the plurality of macro-pixels includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro-pixels. Among them, the switch array 3012 is configured to receive the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel among the plurality of macro-pixels, synthesize the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel, obtain a path of first image data corresponding to the corresponding macro-pixel, and output a path of first image data corresponding to each macro-pixel; the multiplexer 3013 is configured to receive the multiple paths of first image data output by the switch array 3012 and sequentially output the multiple paths of first image data to the processing unit 302; the processing unit 302 is configured to receive the first image data corresponding to each macro-pixel output by the SPAD array and generate a fused image according to the first image data corresponding to each macro-pixel and the position of the corresponding macro-pixel.

[0065] In an embodiment of the present application, the SPAD array 3011 includes a plurality of SPAD sub-pixels arranged in a rectangular array, and (N×M) SPAD sub-pixels in the SPAD array 3011 can form a macro-pixel. Then, the SPAD array 3011 includes a plurality of macro-pixels each composed of (N×M) SPAD sub-pixels. Here, N is the number of rows of the macro-pixel, M is the number of columns of the macro-pixel, and N and M may be equal or unequal, which is not limited in the embodiment of the present application.

[0066] It should be noted that in an embodiment of the present application, there are overlapping SPAD sub-pixels between every two adjacent macro-pixels among the plurality of macro-pixels in the SPAD array 3011.

[0067] Exemplarily, when each macro-pixel includes (N×M) SPAD sub-pixels, two vertically adjacent macro-pixels may have multiple rows of overlapping SPAD sub-pixels, and two horizontally adjacent macro-pixels may have multiple columns of overlapping SPAD sub-pixels. For example, two vertically adjacent macro-pixels may have (N - 1) rows of overlapping SPAD sub-pixels, or may have (N - 2) rows of overlapping SPAD sub-pixels, which is not limited in the embodiment of the present application. Two horizontally adjacent macro-pixels have (M - 1) columns of overlapping SPAD sub-pixels, or may have (M - 2) columns of overlapping SPAD sub-pixels, which is not limited in the embodiment of the present application.

[0068] For example, referring to Figure 4 , in a 4×4 SPAD array with a total of 16 SPAD sub-pixels, taking N = M = 3 as an example, a macro-pixel includes 3×3 SPAD sub-pixels. Among them, there are 2 overlapping rows between the vertically adjacent macro-pixel 1 and macro-pixel 2. The SPAD sub-pixels in the first overlapping row include SPAD5 to SPAD7, and the SPAD sub-pixels in the second overlapping row include SPAD9 to SPAD11; there are 2 overlapping columns between the horizontally adjacent macro-pixel 2 and macro-pixel 3. The SPAD sub-pixels in the first overlapping column include SPAD6, SPAD10, and SPAD14, and the SPAD sub-pixels in the second overlapping column include SPAD7, SPAD11, and SPAD15.

[0069] In an embodiment of the present application, the switch array 3012 includes a first-level logic OR gate and a second-level logic OR gate. In a possible implementation manner, taking any one of the plurality of macro-pixels in the SPAD array 3011 as an example, it is called the first macro-pixel. Each row of SPAD sub-pixels in the first macro-pixel is respectively connected to a first-level logic OR gate, and the multiple first-level logic OR gates corresponding to the multiple rows of SPAD sub-pixels in each macro-pixel are connected to a second-level logic OR gate.

[0070] Among them, each first-level logical OR gate connected to the first macro-pixel is used to receive a sub-pixel data path output by each SPAD sub-pixel in a row of SPAD sub-pixels it is connected to. After that, the first-level logical OR gate synthesizes the received sub-pixel data to obtain a row of pixel data and outputs the row of pixel data. For example, for a macro-pixel composed of (N×M) SPAD sub-pixels, the macro-pixel is connected to N first-level logical OR gates, and each first-level logical OR gate outputs a row of pixel data. In this way, N first-level logical OR gates output N rows of pixel data.

[0071] The second-level logical OR gate connected to the first macro-pixel is used to receive the row pixel data respectively output by multiple first-level logical OR gates it is connected to. After that, the second-level logical OR gate synthesizes the received multiple rows of pixel data to obtain a first image data path and outputs the first image data.

[0072] It should be noted that in a possible case, when the first macro-pixel includes 4 SPAD sub-pixels, a first-level logical OR gate can be a two-input OR gate. Correspondingly, a second-level logical OR gate can also be a two-input OR gate.

[0073] For example, referring to Figure 5 , assuming that the SPAD array includes 3×3 SPAD sub-pixels, and SPAD1, SPAD2, SPAD4, and SPAD5 form macro-pixel 1. The SPAD1 and SPAD2 in the first row of this macro-pixel 1 are connected to a first-level logical OR gate, and this first-level logical OR gate is a two-input OR gate. In this case, this first-level logical OR gate receives the sub-pixel data respectively output by SPAD1 and SPAD2, and synthesizes these two sub-pixel data paths into a row of pixel data 1+2; similarly, SPAD4 and SPAD5 in the second row are connected to a first-level logical OR gate, and this first-level logical OR gate receives the sub-pixel data respectively output by SPAD4 and SPAD5, and synthesizes these two sub-pixel data paths into a row of pixel data 4+5.

[0074] Furthermore, the two first-level logical OR gates corresponding to the two rows of SPAD sub-pixels of macro-pixel 1 are connected to a second-level logical OR gate, and this second logical OR gate is also a two-input OR gate. In this way, this second-level logical OR gate receives the row of pixel data 1+2 and the row of pixel data 4+5 output by these two first-level logical OR gates, synthesizes the row of pixel data 1+2 and the row of pixel data 4+5 into a first image data path 1245, and outputs the first image data 1245.

[0075] In another possible case, when the first macro pixel includes X SPAD sub-pixels and X is greater than 4, each first-level logic OR gate connected to the first macro pixel may include one or more two-input OR gates, and the second logic OR gate connected to the first macro pixel may also include one or more two-input OR gates.

[0076] For example, when X is 9, according to R = ceiling(log2X), R = 4 is calculated, where ceiling(*) means rounding up. In this case, the switch array will include 4 layers of two-input OR gates. Among them, each first-level logic OR gate can be composed of two layers of two-input OR gates, and each second-level logic OR gate can also be composed of two layers of two-input OR gates.

[0077] For example, referring to Figure 6 , assume that the SPAD array includes 4×4 SPAD sub-pixels, and SPAD1, SPAD2, SPAD3, SPAD5, SPAD6, SPAD7, SPAD9, SPAD10 and SPAD11 form macro pixel 1. In this case, each adjacent two SPAD sub-pixels in the first row of this macro pixel 1 can be connected to a two-input OR gate. In this way, these 2 two-input OR gates are the first layer of two-input OR gates in the first-level logic OR gate connected to the SPAD sub-pixels in the first row of this macro pixel 1. On this basis, an adjacent first-layer input OR gate in the first-level logic OR gate is connected to a two-input OR gate. In this way, this two-input OR gate is the second layer of input OR gates in the first-level logic OR gate connected to the SPAD sub-pixels in the first row. In this way, each first-layer two-input OR gate in the first-level logic OR gate connected to the SPAD sub-pixels in each row of macro pixel 1 receives the sub-pixel data output by the two connected SPAD sub-pixels, and merges the two sub-pixel data and then outputs. Each second-layer two-input OR gate receives the two-way data output by the two connected first-layer input OR gates, and merges the received two-way data to obtain one-way row pixel data.

[0078] After obtaining the row pixel data corresponding to each row of SPAD sub-pixels in the macro pixel through the above method, for these 3 row pixel data, two second-layer two-input OR gates that output the row pixel data of adjacent two rows can be connected to a two-input OR gate. At this time, this connected two-input OR gate is the first layer of two-input OR gates in the second-level logic OR gate. After that, two first-layer two-input OR gates in the second-level logic OR gate are connected to a two-input OR gate again. At this time, this two-input OR gate is the second layer of two-input OR gates in the second-level logic OR gate. In this way, each first-layer two-input OR gate in the second-level logic OR gate can merge the received row pixel data of adjacent two rows and output one-way data. After that, the second-layer two-input OR gate merges the two-way data input by the two first-layer two-input OR gates, so as to obtain the first image data.

[0079] The above is only an exemplary description taking the macro pixel including 9 SPAD sub-pixels as an example. When the macro pixel includes 8, 6 or more SPAD sub-pixels, the above method can be referred to for processing, and the embodiments of the present application will not be elaborated herein.

[0080] In addition, for each of the multiple macro pixels, it can refer to the above first macro pixel and connect multiple first-level logical OR gates and one second-level logical OR gate. In this way, the switch array 3012 will include multiple first-level logical OR gates and multiple second-level logical OR gates.

[0081] Optionally, in another possible implementation manner, still taking the first macro pixel as an example, one column of SPAD sub-pixels in the first macro pixel is connected to one first-level logical OR gate, and multiple first-level logical OR gates connected by multiple columns of SPAD sub-pixels in the first macro pixel are connected to one second-level logical OR gate.

[0082] Among them, each first-level logical OR gate connected to the first macro pixel can be used to receive a path of sub-pixel data output by each SPAD sub-pixel in a column of SPAD sub-pixels connected to itself. After that, the first-level logical OR gate synthesizes the received sub-pixel data to obtain a path of column pixel data and outputs the column pixel data. For example, in a macro pixel composed of (N×M) SPAD sub-pixels, the macro pixel is connected to M first-level logical OR gates, and each first-level logical OR gate will output a column pixel data. In this way, M first-level logical OR gates will output M column pixel data.

[0083] The second-level logical OR gate connected to the first macro pixel is used to receive the column pixel data respectively output by the multiple first-level logical OR gates connected to itself. After that, the second-level logical OR gate synthesizes the received column pixel data to obtain a path of first image data and outputs the first image data.

[0084] It should be noted that when the number of SPAD sub-pixels included in the macro pixel is 4, each first-level logical OR gate and second-level logical OR gate can be implemented by a two-input OR gate. Optionally, when the macro pixel includes more SPAD sub-pixels, the method introduced in the foregoing can be referred to. Each first-level logical OR gate is implemented by one or more two-input OR gates, and each second-level logical OR gate is also implemented by one or more two-input OR gates. The embodiments of the present application will not be elaborated herein.

[0085] After each second-level logical OR gate in the switch array 3012 outputs a path of first image data, the multiplexer 3013 receives a path of first image data respectively output by multiple second-level logical OR gates and sequentially outputs the received multiple paths of first image data to the processing unit 302.

[0086] In an embodiment of the present application, the multiplexer 3013 includes multiple input terminals, one output terminal, and one control terminal. The multiple input terminals of the multiplexer 3013 are connected to the switch array 3012, the control terminal of the multiplexer 3013 is connected to the control terminal of the processing unit 302, and the output terminal of the multiplexer 3013 is connected to the input terminal of the processing unit 302.

[0087] Wherein, each input terminal of the multiplexer 3013 is used to receive a path of first image data output by the switch array 3012; the control terminal of the multiplexer 3013 is used to receive a gating signal output by the control terminal of the processing unit 302 at each measurement moment; the output terminal of the multiplexer 3013 is used to output a path of first image data corresponding to the gating signal received at the corresponding measurement moment at each measurement moment.

[0088] It should be noted that the number of input terminals of the multiplexer 3013 is the same as the number of second-stage logic OR gates included in the switch array 3012. In this way, each input terminal of the multiplexer 3013 is connected to a second-stage logic OR gate in the switch array 3012 to receive the first image data output by the connected second-stage logic OR gate.

[0089] Wherein, in a possible implementation manner, the respective input terminals in the multiplexer 3013 can be sequentially connected to the respective second-stage logic OR gates according to the positions of the macro pixels corresponding to the first image data output by each second-stage logic OR gate in the switch array 3012 in the SPAD array 3011. For example, the second-stage logic OR gate for outputting the first image data corresponding to the macro pixel in the first row and first column of the multiple macro pixels of the SPAD array 3011 can be connected to the first input terminal in the multiplexer 3013, and the second-stage logic OR gate for outputting the first image data corresponding to the macro pixel in the first row and second column of the multiple macro pixels of the SPAD array 3011 can be connected to the second input terminal in the multiplexer 3013, and so on.

[0090] While receiving multiple paths of first image data, the control terminal of the multiplexer 3013 can also receive a gating signal output by the control terminal of the processing unit 302 according to a preset time sequence. Wherein, the processing unit 302 can, according to the positions of the multiple macro pixels in the SPAD array 3011 and the input terminals in the multiplexer 3013 for receiving the first image data corresponding to each macro pixel, sequentially output, through its own control terminal, gating signals for gating different input terminals in the multiplexer at different measurement moments. Correspondingly, the multiplexer 3013 can receive, at each measurement moment, the gating signal output by the control terminal of the processing unit 302 through its own control terminal, and output the first image data input by the corresponding input terminal according to the gating signal.

[0091] For example, the processing unit determines that the first image data corresponding to macro-pixel 1 in the first row and first column of the SPAD array will be input to input terminal 1 of the multiplexer, the first image data corresponding to macro-pixel 2 in the first row and second column will be input to input terminal 2 of the multiplexer, the first image data corresponding to macro-pixel 3 in the second row and first column will be input to input terminal 3 of the multiplexer, and the first image data corresponding to macro-pixel 4 in the second row and second column will be input to input terminal 4 of the multiplexer. On this basis, at the first measurement moment, the control terminal of the processing unit outputs a gating signal 0000 for gating input terminal 1 of the multiplexer. After receiving the gating signal 0000, the control terminal of the multiplexer outputs the first image data of macro-pixel 1 input to input terminal 1 of the multiplexer to the processing unit. At the second measurement moment, the control terminal of the processing unit outputs a gating signal 0001 for gating input terminal 2 of the multiplexer. After receiving the gating signal 0001, the control terminal of the multiplexer outputs the first image data of macro-pixel 2 input to input terminal 2 of the multiplexer to the processing unit. At the third measurement moment, the control terminal of the processing unit outputs a gating signal 0010 for gating input terminal 3 of the multiplexer. After receiving the gating signal 0010, the control terminal of the multiplexer outputs the first image data of macro-pixel 3 input to input terminal 3 of the multiplexer to the processing unit. At the fourth measurement moment, the control terminal of the processing unit outputs a gating signal 0011 for gating input terminal 4 of the multiplexer. After receiving the gating signal 0011, the control terminal of the multiplexer outputs the first image data of macro-pixel 4 input to input terminal 4 of the multiplexer to the processing unit.

[0092] After receiving the first image data corresponding to each gating signal, the processing unit 302 can determine the position of the macro-pixel corresponding to the first image data corresponding to the received gating signal according to the gating signal output at each measurement moment, and use the first image data corresponding to the corresponding gating signal as the pixel data at the position of the determined macro-pixel to generate a fused image.

[0093] It should be noted that a certain time duration can be set between two adjacent measurement moments, and within this time duration, the processing unit 302 can process the received first image data.

[0094] Exemplarily, after the processing unit 302 outputs a gating signal through its control terminal at a certain measurement moment, it can receive the first image data output by the multiplexer 3013 according to the gating signal. As can be seen from the foregoing introduction, when the processing unit 302 sends the gating signal, it is sent according to the position of the macro pixel and the input terminal in the multiplexer 3013 for outputting the image data of the corresponding macro pixel. Based on this, the processing unit 302 can determine which macro pixel the received first image data corresponds to according to the position of the macro pixel corresponding to the gating signal output at the measurement moment, and then use the first image data as the pixel data at the position of the macro pixel. After that, after the next measurement moment arrives, the processing unit 302 can continue to send a gating signal to the multiplexer 3013 through the control terminal and process the first image data corresponding to the received corresponding gating signal. In this way, the processing unit 302 obtains the pixel data at the positions of each macro pixel by receiving and processing the multiplexed first image data sequentially output by the multiplexer, thereby generating a fused image.

[0095] To better understand the device of the embodiment of the present application, an imaging device provided by the embodiment of the present application will be described in detail below by taking a 3×3 SPAD array as an example. Among them, see Figure 7 , the SPAD array includes 9 SPAD sub-pixels, namely SPAD1 to SPAD9. In addition, each macro pixel in the SPAD array includes 2×2 SPAD sub-pixels. Among them, SPAD1, SPAD2, SPAD4, and SPAD5 form macro pixel 1, SPAD2, SPAD3, SPAD5, and SPAD6 form macro pixel 2, SPAD4, SPAD5, SPAD7, and SPAD8 form macro pixel 3, and SPAD5, SPAD6, SPAD8, and SPAD9 form macro pixel 4. The overlapping SPAD sub-pixels in macro pixel 1 and macro pixel 2 are SPAD2 and SPAD5, the overlapping SPAD sub-pixels in macro pixel 3 and macro pixel 4 are SPAD5 and SPAD8, the overlapping SPAD sub-pixels in macro pixel 1 and macro pixel 3 are SPAD4 and SPAD5, and the overlapping SPAD sub-pixels in macro pixel 2 and macro pixel 4 are SPAD5 and SPAD6.

[0096] One row of SPAD sub-pixels in each of the above 4 macro-pixels is connected to a first-level logical OR gate. In this way, two SPAD sub-pixels in one row of SPAD sub-pixels of each macro-pixel will output two sub-pixel data to the connected first-level logical OR gate. For example, the SPAD1 and SPAD2 sub-pixels in the first row of macro-pixel 1 are connected to a first-level logical OR gate. In this way, SPAD1 outputs sub-pixel data 1 to the connected first-level logical OR gate, and SPDA2 outputs sub-pixel data 2 to the connected first-level logical OR gate. After receiving sub-pixel data 1 and 2, this first-level logical OR gate combines the two sub-pixel data into one row of pixel data 1+2 and outputs this row of pixel data 1+2. For the SPAD sub-pixels in each row of other macro-pixels, each row of SPAD sub-pixels is connected to a first-level logical OR gate. In this way, through 6 first-level logical OR gates, 6 row pixel data will be output. In addition, the multiple first-level logical OR gates connected to multiple rows of SPAD sub-pixels in each macro-pixel will be connected to a second-level logical OR gate. For example, the first-level logical OR gate connected to the two sub-pixels SPAD1 and SPAD2 in the first row of macro-pixel 1 and the first-level logical OR gate connected to the two sub-pixels SPAD4 and SPAD5 in the second row will be connected to a second-level logical OR gate. In this way, this second-level logical OR gate will receive row pixel data 1+2 and row pixel data 4+5. After that, this second-level logical OR gate combines row pixel data 1+2 and row pixel data 4+5 into the first image data 1245. For the first-level logical OR gates connected to the SPAD sub-pixels in each row of other macro-pixels, they can also be connected to a second-level logical OR gate. In this way, each second-level logical OR gate can be connected to two first-level logical OR gates corresponding to two rows of SPAD sub-pixels in one macro-pixel and combine the two row pixel data output by the two connected first-level logical OR gates into one path of first image data, thereby obtaining four paths of first image data, namely first image data 1245, first image data 4578, first image data 2356, and first image data 5689.

[0097] Each second-level logical OR gate can output one path of the first image data it obtains to the multiplexer, and the multiplexer can sequentially output each path of the first image data to the processing unit according to the received strobe signal.

[0098] Among them, the second-level logical OR gate corresponding to macro-pixel 1 can be connected to input terminal 1 of the multiplexer, the second-level logical OR gate corresponding to macro-pixel 2 can be connected to input terminal 2 of the multiplexer, the second-level logical OR gate corresponding to macro-pixel 3 is connected to input terminal 3 of the multiplexer, and the second-level logical OR gate corresponding to macro-pixel 4 is connected to input terminal 4 of the multiplexer. Correspondingly, the control terminal of the processing unit can sequentially output strobe signals 00, 01, 10, and 11. When the multiplexer receives the strobe signal 00, it outputs the first image data 1245. After the processing unit receives the first image data 1245, it uses the first image data 1245 as the pixel data at the position where macro-pixel 1 is located. When receiving the strobe signal 01, it outputs the first image data 2356. After the processing unit receives the first image data 2356, it uses the first image data 2356 as the pixel data at the position where macro-pixel 2 is located. And so on, the finally obtained fused image is as Figure 8 shown.

[0099] In the embodiment of the present application, through the switch array and the multiplexer in the imaging unit, one path of first image data corresponding to each macro-pixel among multiple macro-pixels can be sequentially output. The processing unit receives the first image data corresponding to each macro-pixel, and generates a fused image according to the first image data corresponding to each macro-pixel and the position of the corresponding macro-pixel. Since there are overlapping SPAD sub-pixels between every two adjacent macro-pixels in the SPAD array included in the imaging unit, therefore, through the switch array and the multiplexer, the number of image data of the macro-pixels output by the imaging unit is increased, while the TDC and histogram calculation circuits of the SPAD array are not increased. Thus, it can be seen that the image processing method provided by the embodiment of the present application can improve the planar resolution of the output image of the SPAD array without increasing the number of SPAD sub-pixels, subsequent storage, and the area of the main circuit.

[0100] Next, the imaging method provided by the embodiment of the present application will be introduced.

[0101] Figure 9It is a flowchart of an imaging control method provided by an embodiment of the present application. This method is applied to the processing unit of the imaging device introduced in the foregoing embodiment. The imaging device further includes an imaging unit. The imaging unit includes a single-photon avalanche diode (SPAD) array. The SPAD array includes a plurality of macro-pixels. Each macro-pixel in the plurality of macro-pixels includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro-pixels. Among them, the switch array is used to receive the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel among the plurality of macro-pixels, synthesize the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel, obtain a first image data corresponding to the corresponding macro-pixel, and output the first image data corresponding to each macro-pixel to a multiplexer. The method includes the following steps:

[0102] Step 901: The processing unit sequentially outputs different types of gating signals to the multiplexer according to a preset timing sequence, so that when the multiplexer receives each type of gating signal output by the processing unit, it outputs the first image data corresponding to the corresponding gating signal.

[0103] Among them, the implementation process of the processing unit sequentially outputting different types of gating signals according to a preset timing sequence can refer to the implementation manner introduced in the foregoing embodiment, and this embodiment of the present application will not elaborate herein.

[0104] Step 902: The processing unit receives the first image data corresponding to each macro-pixel sequentially output by the multiplexer, and generates a fused image according to the first image data corresponding to each macro-pixel and the position of the corresponding macro-pixel.

[0105] Among them, the process of the multiplexer outputting the corresponding first image data according to the gating signal sent by the processing unit can refer to the implementation manner in the foregoing embodiment. In addition, the process of the processing unit generating the fused image can also refer to the foregoing implementation manner, and this embodiment of the present application will not elaborate herein.

[0106] Optionally, the switch array includes a first-stage logic OR gate and a second-stage logic OR gate. A row of SPAD sub-pixels in the first macro-pixel is connected to a first-stage logic OR gate, and the multiple first-stage logic OR gates connected by multiple rows of SPAD sub-pixels in the first macro-pixel are connected to a second-stage logic OR gate. The first macro-pixel is any one of the plurality of macro-pixels;

[0107] Among them, each first-stage logic OR gate connected to the first macro-pixel receives the sub-pixel data output by each SPAD sub-pixel in a row of SPAD sub-pixels connected thereto, synthesizes the received sub-pixel data into a row of pixel data, and outputs the row of pixel data;

[0108] The second - stage logical OR gate connected to the first macro - pixel receives the row pixel data respectively output by a plurality of first - stage logical OR gates connected thereto, synthesizes the received row pixel data, obtains the first image data corresponding to the first macro - pixel, and outputs the first image data corresponding to the first macro - pixel.

[0109] Optionally, the switch array includes a first - stage logical OR gate and a second - stage logical OR gate. One column of SPAD sub - pixels in the first macro - pixel is connected to one first - stage logical OR gate, and the multiple first - stage logical OR gates connected by multiple columns of SPAD sub - pixels in the first macro - pixel are connected to one second - stage logical OR gate. The first macro - pixel is any one of a plurality of macro - pixels.

[0110] Each first - stage logical OR gate connected to the first macro - pixel is used to receive the sub - pixel data output by each SPAD sub - pixel in a column of SPAD sub - pixels connected thereto, and synthesize the received sub - pixel data into one column of pixel data, and output the column of pixel data.

[0111] The second - stage logical OR gate connected to the first macro - pixel is used to receive the column pixel data respectively output by the multiple first - stage logical OR gates connected thereto, synthesize the received column pixel data, obtain the first image data corresponding to the first macro - pixel, and output the first image data corresponding to the first macro - pixel.

[0112] Optionally, the multiplexer includes a plurality of input terminals, an output terminal, and a control terminal. The plurality of input terminals of the multiplexer are connected to the switch array, the control terminal of the multiplexer is connected to the control terminal of the processing unit, the output terminal of the multiplexer is connected to the input terminal of the processing unit, and each input terminal of the multiplexer receives one path of first image data output by the switch array.

[0113] The processing unit sequentially outputs different types of gating signals to the multiplexer according to a preset timing sequence, including:

[0114] The first gating signal output by the control terminal of the processing unit to the control terminal of the multiplexer at the first measurement moment, so that the output terminal of the multiplexer outputs one path of first image data corresponding to the first gating signal at the first measurement moment. The first measurement moment is any one of a plurality of measurement moments.

[0115] Optionally, the processing unit generates a fused image according to the first image data corresponding to each macro - pixel and the position of the corresponding macro - pixel, including:

[0116] Determine the position of the macro - pixel corresponding to the first image data corresponding to the received corresponding gating signal according to the gating signal output at each measurement moment;

[0117] And use the first image data corresponding to the corresponding gating signal as the pixel value at the position of the macro pixel determined at the corresponding measurement moment to generate a fused image.

[0118] Optionally, every two adjacent macro pixels among the multiple macro pixels have (N - 1) rows of overlapping SPAD sub-pixels, or every two adjacent macro pixels among the multiple macro pixels have (M - 1) columns of overlapping SPAD sub-pixels.

[0119] It should be noted that the implementation manners of the above steps can refer to the implementation manner of the imaging device in the foregoing embodiments, and will not be elaborated herein in the embodiments of the present application.

[0120] In summary, in the embodiments of the present application, the switch array and the multiplexer in the imaging unit can sequentially output the first image data corresponding to each macro pixel among the multiple macro pixels. The processing unit receives the first image data corresponding to each macro pixel and generates a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel. Since there are overlapping SPAD sub-pixels between every two adjacent macro pixels among the multiple macro pixels included in the SPAD array in the imaging unit, the number of the image data of the macro pixels output by the imaging unit is increased through the switch array and the multiplexer, while the TDC and the histogram calculation circuit of the SPAD array are not increased. It can be seen that the image processing method provided by the embodiments of the present application can improve the planar resolution of the output image of the SPAD array without increasing the number of SPAD sub-pixels, subsequent storage, and the main circuit area.

[0121] The embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by the foregoing imaging device, it can implement Figure 9 the imaging control method shown.

[0122] The embodiments of the present application further provide a computer program product containing instructions, and when it runs on the foregoing imaging device, it causes the imaging device to execute the above Figure 9 imaging control method provided by the embodiments shown.

[0123] The above does not serve to limit the embodiments of the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. An imaging device, characterized in that, The imaging device includes: an imaging unit and a processing unit. The imaging unit includes a single-photon avalanche diode (SPAD) array, a switch array, and a multiplexer. The SPAD array includes a plurality of macro-pixels. Each macro-pixel in the plurality of macro-pixels includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro-pixels; The switch array is configured to receive the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel among the plurality of macro-pixels, synthesize the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel, obtain a first image data corresponding to the corresponding macro-pixel, and output the first image data corresponding to each macro-pixel; The multiplexer is configured to receive the multiple paths of first image data output by the switch array and sequentially output the multiple paths of first image data to the processing unit; The processing unit is configured to receive the first image data corresponding to each macro-pixel sequentially output by the multiplexer, and generate a fused image according to the positions of the respective macro-pixels, the corresponding first image data, and the corresponding macro-pixels.

2. The imaging device according to claim 1, wherein The switch array includes a first-stage logical OR gate and a second-stage logical OR gate. One row of SPAD sub-pixels in a first macro-pixel is connected to one first-stage logical OR gate, and the multiple first-stage logical OR gates connected by multiple rows of SPAD sub-pixels in the first macro-pixel are connected to one second-stage logical OR gate. The first macro-pixel is any one of the plurality of macro-pixels; Each first-stage logical OR gate connected to the first macro-pixel is configured to receive the sub-pixel data output by each SPAD sub-pixel in the row of SPAD sub-pixels connected thereto, synthesize the received sub-pixel data into a row of pixel data, and output the row of pixel data; The second-stage logical OR gate connected to the first macro-pixel is configured to receive the row of pixel data respectively output by the multiple first-stage logical OR gates connected thereto, synthesize the received row of pixel data, obtain the first image data corresponding to the first macro-pixel, and output the first image data corresponding to the first macro-pixel.

3. The imaging device according to claim 1, wherein The switch array includes a first-stage logical OR gate and a second-stage logical OR gate. One column of SPAD sub-pixels in a first macro-pixel is connected to one first-stage logical OR gate, and the multiple first-stage logical OR gates connected by multiple columns of SPAD sub-pixels in the first macro-pixel are connected to one second-stage logical OR gate. The first macro-pixel is any one of the plurality of macro-pixels; Each first-stage logical OR gate connected to the first macro-pixel is configured to receive a path of sub-pixel data output by each SPAD sub-pixel in the column of SPAD sub-pixels connected thereto, synthesize the received sub-pixel data into a column of pixel data, and output the column of pixel data; The second-stage logical OR gate connected to the first macro-pixel is configured to receive the column of pixel data respectively output by the multiple first-stage logical OR gates connected thereto, synthesize the received column of pixel data, obtain the first image data corresponding to the first macro-pixel, and output the first image data corresponding to the first macro-pixel.

4. The imaging device according to claim 1, characterized in that, The multiplexer includes multiple input terminals, an output terminal, and a control terminal. The multiple input terminals of the multiplexer are connected to the switch array. The control terminal of the multiplexer is connected to the control terminal of the processing unit. The output terminal of the multiplexer is connected to the input terminal of the processing unit; Each input terminal of the multiplexer is used to receive a path of first image data output by the switch array; The control terminal of the multiplexer is used to receive a strobe signal output by the control terminal of the processing unit at each measurement moment; The output terminal of the multiplexer is used to output a path of first image data corresponding to the strobe signal received at the corresponding measurement moment at each measurement moment.

5. The imaging device according to claim 4, characterized in that, The processing unit is used to determine the position of the macro pixel corresponding to the first image data corresponding to the received corresponding strobe signal according to the strobe signal output at each measurement moment, and use the first image data corresponding to the corresponding strobe signal as the pixel data at the position of the determined macro pixel to generate the fused image.

6. The imaging device according to any one of claims 1-5, characterized in that, Each adjacent two of the multiple macro pixels have (N - 1) rows of overlapping SPAD sub-pixels, or each adjacent two of the multiple macro pixels have (M - 1) columns of overlapping SPAD sub-pixels.

7. An imaging control method, characterized in that, The method is applied to the processing unit of an imaging device. The imaging device further includes an imaging unit. The imaging unit includes a single-photon avalanche diode (SPAD) array, a switch array, and a multiplexer. The SPAD array includes multiple macro pixels. Each macro pixel in the multiple macro pixels includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between each adjacent two macro pixels. Wherein, the switch array is used to receive the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro pixel in the multiple macro pixels, synthesize the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro pixel, obtain a path of first image data corresponding to the corresponding macro pixel, and output a path of first image data corresponding to each macro pixel to the multiplexer; The method includes: The processing unit sequentially outputs different types of strobe signals to the multiplexer according to a preset timing sequence, so that the multiplexer outputs the first image data corresponding to the corresponding strobe signal each time it receives a type of strobe signal output by the processing unit; The processing unit receives the first image data corresponding to each macro pixel sequentially output by the multiplexer, and generates a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel.

8. The method according to claim 7, characterized in that The switch array includes a first-stage logical OR gate and a second-stage logical OR gate. One row of SPAD sub-pixels in the first macro pixel is connected to one first-stage logical OR gate, and the multiple first-stage logical OR gates connected by multiple rows of SPAD sub-pixels in the first macro pixel are connected to one second-stage logical OR gate. The first macro pixel is any one of the multiple macro pixels; Each first - level logical OR gate connected to the first macro - pixel is used to receive the sub - pixel data output by each SPAD sub - pixel in a row of SPAD sub - pixels connected thereto, and synthesize the received sub - pixel data into a single - channel row pixel data, and output the row pixel data; The second - level logical OR gate connected to the first macro - pixel is used to receive the row pixel data respectively output by a plurality of first - level logical OR gates connected thereto, synthesize the received row pixel data, obtain the first image data corresponding to the first macro - pixel, and output the first image data corresponding to the first macro - pixel.

9. The method according to claim 7, characterized in that The switch array includes a first - level logical OR gate and a second - level logical OR gate. One first - level logical OR gate is connected to one column of SPAD sub - pixels in the first macro - pixel, and a plurality of first - level logical OR gates connected to multiple columns of SPAD sub - pixels in the first macro - pixel are connected to one second - level logical OR gate. The first macro - pixel is any one of the multiple macro - pixels; Each first - level logical OR gate connected to the first macro - pixel is used to receive a single - channel sub - pixel data output by each SPAD sub - pixel in a column of SPAD sub - pixels connected thereto, and synthesize the received sub - pixel data into a single - channel column pixel data, and output the column pixel data; The second - level logical OR gate connected to the first macro - pixel is used to receive the column pixel data respectively output by a plurality of first - level logical OR gates connected thereto, synthesize the received column pixel data, obtain the first image data corresponding to the first macro - pixel, and output the first image data corresponding to the first macro - pixel.

10. The method according to claim 7, wherein The multiplexer includes a plurality of input terminals, an output terminal, and a control terminal. The plurality of input terminals of the multiplexer are connected to the switch array, the control terminal of the multiplexer is connected to the control terminal of the processing unit, the output terminal of the multiplexer is connected to the input terminal of the processing unit, and each input terminal of the multiplexer is used to receive a single - channel first image data output by the switch array; The processing unit sequentially outputs different types of gating signals to the multiplexer according to a preset timing sequence, including: The control terminal of the processing unit outputs a first gating signal to the control terminal of the multiplexer at a first measurement moment, so that the output terminal of the multiplexer outputs a single - channel first image data corresponding to the first gating signal at the first measurement moment. The first measurement moment is any one of a plurality of measurement moments.

11. The method according to claim 10, wherein The processing unit generates a fused image according to the first image data corresponding to each macro - pixel and the position of the corresponding macro - pixel, including: Determine the position of the macro - pixel corresponding to the first image data corresponding to the received corresponding gating signal according to the gating signal output at each measurement moment; Use the first image data corresponding to the corresponding gating signal as the pixel data at the position of the macro - pixel determined at the corresponding measurement moment to generate the fused image.

12. The method according to any one of claims 7-11, characterized in that, Each adjacent two of the multiple macro - pixels have (N - 1) rows of overlapping SPAD sub - pixels, or each adjacent two of the multiple macro - pixels have (M - 1) columns of overlapping SPAD sub - pixels.

Images