A receiver system with automatic gain control

Abstract

The invention discloses a receiver system with automatic gain control, comprising an FPGA chip, a detection voltage ADC, a first radio frequency feedforward AGC module, a second radio frequency feedforward AGC module, and an intermediate frequency feedforward AGC module; the first radio frequency feedforward AGC module comprises a first digitally controlled attenuator, a first coupler, a first low noise amplifier, and a first detector; the second radio frequency feedforward AGC module comprises a second digitally controlled attenuator, a second coupler, a second low noise amplifier, and a second detector; the intermediate frequency feedforward AGC module comprises a third digitally controlled attenuator, a third coupler, a first intermediate frequency amplifier, and a third detector; the detector is used to transmit a detected analog voltage signal to the detection voltage ADC, the detection voltage ADC converts the analog voltage signal into a digital voltage signal, and transmits it to the FPGA chip for processing; the FPGA chip generates a gain allocation strategy according to the received digital voltage signal, and simultaneously controls the first digitally controlled attenuator, the second digitally controlled attenuator, and the third digitally controlled attenuator, so as to realize automatic gain control.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communications, and more particularly to a receiver system with automatic gain control. Background Art

[0002] In wireless communication systems, the signal strength received by the receiver fluctuates widely due to the slow fading of electromagnetic waves during propagation and the selective fading in time, space, and frequency. This requires the receiver to use automatic gain control technology (AGC) to automatically compensate for the received electromagnetic signals of different strengths, ensure that the intermediate frequency output signal strength is stable within the target range, and then demodulate it after being converted into a digital signal by ADC. For wide-band frequency hopping communication, since the operating frequency jumps at a high speed, each frequency jump requires re-adjustment of the AGC. This requires the AGC to adjust quickly and spend less time on the AGC for each jump. At the same time, due to the increasing congestion of the spatial electromagnetic spectrum and the harsh electromagnetic environment, each frequency point of wide-band frequency hopping communication is subject to different degrees of out-of-band interference.

[0003] In some public patents or technical literature libraries, there are many methods for automatic gain control of receivers, and these methods have certain limitations or disadvantages. Some methods use a two-way receiving method, which has a complex architecture and high hardware cost, such as: a receiver automatic gain control system and method that takes into account a variety of scenarios (CN107276621B), a high-speed frequency hopping automatic gain control method (CN101883418B); some methods use multiple adjustments, and the AGC adjustment time is long. For example: a large dynamic fast digital AGC control method (CN114204949A). Some methods have a small AGC dynamic range and poor anti-interference ability. For example: a broadband receiver automatic gain control system, method and broadband receiver (CN106160762B). Summary of the invention

[0004] In order to solve the problems of the above-mentioned deficiencies and defects in the prior art, the present invention provides a receiver system with automatic gain control, the purpose of which is to ensure that the receiver AGC has a large dynamic range, covers a wide frequency band and has high adjustment accuracy, while greatly improving the AGC adjustment speed and maximizing the anti-interference ability of the receiver.

[0005] In order to achieve the above-mentioned purpose of the present invention, the technical scheme adopted is as follows:

[0006] A receiver system with automatic gain control, comprising an FPGA chip, a detection voltage ADC, a first radio frequency feedforward AGC module, a second radio frequency feedforward AGC module, and an intermediate frequency feedforward AGC module;

[0007] Wherein, a first RF feedforward AGC module, a second RF feedforward AGC module, and an intermediate frequency feedforward AGC module are connected in sequence;

[0008] The first RF feedforward AGC module comprises a first digitally controlled attenuator, a first coupler, a first low noise amplifier, and a first detector for detecting the RF signal strength of the first coupler, which are connected in sequence;

[0009] The second RF feedforward AGC module comprises a second digitally controlled attenuator, a second coupler, a second low noise amplifier, and a second detector for detecting the RF signal strength of the second coupler, which are connected in sequence;

[0010] The intermediate frequency feedforward AGC module comprises a third digitally controlled attenuator, a third coupler, a first intermediate frequency amplifier, and a third detector for detecting the intermediate frequency signal strength of the third coupler, which are connected in sequence;

[0011] The first detector, the second detector, and the third detector respectively transmit the detected analog voltage signals to the detection voltage ADC, and the detection voltage ADC converts the analog voltage signals into digital voltage signals and transmits them to the FPGA chip for processing;

[0012] The FPGA chip generates a gain allocation strategy based on the received digital voltage signal and simultaneously controls the first digitally controlled attenuator, the second digitally controlled attenuator and the third digitally controlled attenuator to achieve automatic gain control.

[0013] Preferably, it also includes a first tuning filter;

[0014] The input end of the first tuned filter is used to input the received signal;

[0015] The output end of the first tuned filter is electrically connected to the input end of the first digitally controlled attenuator in the first RF feedforward AGC module.

[0016] Preferably, it also includes a second tuning filter;

[0017] The second tuned filter is connected in series between the first RF feedforward AGC module and the first RF feedforward AGC module; that is, the input end of the second tuned filter is electrically connected to the output end of the first low noise amplifier in the first RF feedforward AGC module, and the output end of the second tuned filter is electrically connected to the input end of the second digitally controlled attenuator in the second RF feedforward AGC module.

[0018] Preferably, it also includes a first mixer, a first surface acoustic wave filter, a second intermediate frequency amplifier, and a first variable frequency source;

[0019] The input end of the first mixer is electrically connected to the output end of the second low noise amplifier in the second RF feedforward AGC module;

[0020] The output end of the first mixer is electrically connected to the first surface acoustic wave filter and the second intermediate frequency amplifier in sequence;

[0021] The first variable frequency source is electrically connected to the first mixer.

[0022] Furthermore, it also includes a second mixer, a second surface acoustic wave filter, a third intermediate frequency amplifier, and a second variable frequency source;

[0023] The input end of the second mixer is electrically connected to the output end of the second intermediate frequency amplifier;

[0024] The output end of the second mixer is connected to the second surface acoustic wave filter and the third intermediate frequency amplifier in sequence;

[0025] The output end of the third intermediate frequency amplifier is electrically connected to the input end of the third digitally controlled attenuator in the intermediate frequency feedforward AGC module;

[0026] The second variable frequency source is electrically connected to the second mixer.

[0027] Preferably, it also includes an intermediate frequency ADC;

[0028] The input end of the intermediate frequency ADC is electrically connected to the output end of the first intermediate frequency amplifier in the intermediate frequency feedforward AGC module;

[0029] The output end of the intermediate frequency ADC is used to be electrically connected to the baseband.

[0030] Preferably, it also includes a memory,

[0031] The memory is electrically connected to the FPGA chip.

[0032] Furthermore, the gain allocation strategy follows the following principles:

[0033] a. Based on the capabilities of components, ensure that the components in the first RF feedforward AGC module, the second RF feedforward AGC module, and an intermediate frequency feedforward AGC module operate in a relatively linear state;

[0034] b. The attenuation of the first digitally controlled attenuator, the second digitally controlled attenuator, and the third digitally controlled attenuator is minimized, the receiver system is in a relatively linear working state, and the signal entering the ADC is maximized to reduce the noise coefficient of the RF part of the receiver system;

[0035] c. The peak power of the signal entering the IF ADC is N dB lower than the full-bias power of the IF ADC.

[0036] Furthermore, if the peak-to-average ratio of the useful signal is A, and a safety margin B is reserved, the gain allocation strategies for the two RF feedforward AGC modules and one IF feedforward AGC module are as follows:

[0037] d. For the first RF feedforward AGC module:

[0038] The FPGA chip adjusts the attenuation of the first digitally controlled attenuator according to the signal strength of the first coupler in the first RF feedforward AGC module and the gain of the first low noise amplifier to ensure that the input signal of the first low noise amplifier is (A+B) dB lower than its IP-1;

[0039] e. For the second RF feedforward AGC module:

[0040] The FPGA chip adjusts the attenuation of the second digitally controlled attenuator according to the signal strength of the first coupler and the second coupler, and the channel gain from the first coupler to the first mixer, to ensure that the input signal of the first coupler is (A+B) dB lower than its IP-1;

[0041] f. For the intermediate frequency feedforward AGC module:

[0042] The FPGA chip ensures that the output power of the first intermediate frequency amplifier is (A+B) dB lower than the full-bias power of the intermediate frequency ADC based on the signal strength of the first coupler, the second coupler, the signal strength of the third coupler, and the channel gain between the first coupler and the intermediate frequency ADC.

[0043] Furthermore, all gain allocation strategies are adjusted through the first digitally controlled attenuator, the second digitally controlled attenuator, and the third digitally controlled attenuator to achieve 0.25 dB step adjustment.

[0044] The beneficial effects of the present invention are as follows:

[0045] The present invention innovatively adopts a method in which two RF feedforward AGC modules and one IF feedforward AGC module work in parallel, based on the linearity index of components, and under the premise of ensuring the relatively linear working state of the receiver system, combined with the design of the overall architecture of the receiver system, the performance of components is fully utilized. While ensuring the AGC adjustment accuracy, wide working frequency band and large dynamic range, the AGC adjustment speed is greatly improved, and the anti-interference ability of the receiver is significantly enhanced, which can meet the use of wide-band fast frequency hopping receivers in harsh electromagnetic environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a circuit schematic diagram of a receiver system with automatic gain control according to an embodiment.

[0047] Figure 2 FIG. 4 is a circuit schematic diagram of a receiver system with automatic gain control according to another embodiment.

[0048] Figure 3 This is the workflow of the gain allocation strategy.

[0049] In the figure, 1-first RF feedforward AGC module 1, 101-first digitally controlled attenuator, 102-first coupler, 103-first low noise amplifier, 104-first detector, 2-second RF feedforward AGC module, 202-second coupler, 203-second low noise amplifier, 204-second detector, 3-intermediate frequency feedforward AGC module, 301-third digitally controlled attenuator, 302-third coupler, 303-first intermediate frequency amplifier, 304-third detector, 4-detection voltage ADC, 5-FPGA chip, 6-antenna, 7-first tuned filter, 8-second tuned filter, 9-first mixer, 10-first acoustic surface filter, 11-second intermediate frequency amplifier, 12-second mixer, 13-second acoustic surface filter, 14-third intermediate frequency amplifier, 15-first variable frequency source, 16-second variable frequency source, 17-intermediate frequency ADC, 18-memory. DETAILED DESCRIPTION

[0050] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Example 1

[0052] like Figure 1 As shown, a receiver system with automatic gain control includes an FPGA chip 5, a detection voltage ADC4, a first RF feedforward AGC module 1, a second RF feedforward AGC module 2, and an intermediate frequency feedforward AGC module 3;

[0053] Among them, a first RF feedforward AGC module 1, a second RF feedforward AGC module 2, and an intermediate frequency feedforward AGC module 3 are connected in sequence;

[0054] The first RF feedforward AGC module 1 is connected in sequence to a first digitally controlled attenuator 101, a first coupler 102, a first low noise amplifier 103, and a first detector 104 for detecting the RF signal strength of the first coupler 102;

[0055] The second RF feedforward AGC module 2 includes a second digitally controlled attenuator 201, a second coupler 202, a second low noise amplifier 203, and a second detector 204 for detecting the RF signal strength of the second coupler 202, which are connected in sequence; the intermediate frequency feedforward AGC module 3 includes a third digitally controlled attenuator 301, a third coupler 302, a first intermediate frequency amplifier 303, and a third detector 304 for detecting the intermediate frequency signal strength of the third coupler 302, which are connected in sequence;

[0056] The first detector 104 and the third detector 304 transmit the detected analog voltage signals to the detection voltage ADC4 respectively, and the detection voltage ADC4 converts the analog voltage signals into digital voltage signals and transmits them to the FPGA chip 5 for processing;

[0057] The FPGA chip 5 generates a gain allocation strategy according to the received digital voltage signal and simultaneously controls the first digitally controlled attenuator 101 , the second digitally controlled attenuator 201 , and the third digitally controlled attenuator 301 to achieve automatic gain control.

[0058] The present invention innovatively adopts a method in which two RF feedforward AGC modules and one intermediate frequency feedforward AGC module work in parallel. Based on the linearity index of components, the performance of components is fully utilized in combination with the design of the overall architecture of the receiver system while ensuring the relatively linear working state of the receiver system. While ensuring the AGC adjustment accuracy, wide working frequency band and large dynamic range, the AGC adjustment speed is greatly improved, and the anti-interference ability of the receiver is significantly enhanced, which can meet the use of wide-band fast frequency hopping receivers in harsh electromagnetic environments.

[0059] In this embodiment, the first digitally controlled attenuator 101, the first coupler 102, the first low noise amplifier 103, and the first detector 104 in the first RF feedforward AGC module 1 and the second digitally controlled attenuator 201, the second coupler 202, the second low noise amplifier 203, and the second detector 204 in the second RF feedforward AGC module 2 can select components of different models and have different control strategies.

[0060] Example 2

[0061] like Figure 1 As shown, a receiver system with automatic gain control includes an FPGA chip 5, a detection voltage ADC4, a first RF feedforward AGC module 1, a second RF feedforward AGC module 2, and an intermediate frequency feedforward AGC module 3;

[0062] Among them, a first RF feedforward AGC module 1, a second RF feedforward AGC module 2, and an intermediate frequency feedforward AGC module 3 are connected in sequence;

[0063] The first RF feedforward AGC module 1 is connected in sequence to a first digitally controlled attenuator 101, a first coupler 102, a first low noise amplifier 103, and a first detector 104 for detecting the RF signal strength of the first coupler 102;

[0064] The second RF feedforward AGC module 2 includes a second digitally controlled attenuator 201, a second coupler 202, a second low noise amplifier 203, and a second detector 204 for detecting the RF signal strength of the second coupler 202, which are connected in sequence; the intermediate frequency feedforward AGC module 3 includes a third digitally controlled attenuator 301, a third coupler 302, a first intermediate frequency amplifier 303, and a third detector 304 for detecting the intermediate frequency signal strength of the third coupler 302, which are connected in sequence;

[0065] The first detector 104 and the third detector 304 transmit the detected analog voltage signals to the detection voltage ADC4 respectively, and the detection voltage ADC4 converts the analog voltage signals into digital voltage signals and transmits them to the FPGA chip 5 for processing;

[0066] The FPGA chip 5 generates a gain allocation strategy according to the received digital voltage signal and simultaneously controls the first digitally controlled attenuator 101 , the second digitally controlled attenuator 201 , and the third digitally controlled attenuator 301 to achieve automatic gain control.

[0067] The present invention innovatively adopts a method in which two RF feedforward AGC modules and one intermediate frequency feedforward AGC module work in parallel. Based on the linearity index of components, the performance of components is fully utilized in combination with the design of the overall architecture of the receiver system while ensuring the relatively linear working state of the receiver system. While ensuring the AGC adjustment accuracy, wide working frequency band and large dynamic range, the AGC adjustment speed is greatly improved, and the anti-interference ability of the receiver is significantly enhanced, which can meet the use of wide-band fast frequency hopping receivers in harsh electromagnetic environments.

[0068] In this embodiment, the first digitally controlled attenuator 101, the first coupler 102, the first low noise amplifier 103, and the first detector 104 in the first RF feedforward AGC module 1 and the second digitally controlled attenuator 201, the second coupler 202, the second low noise amplifier 203, and the second detector 204 in the second RF feedforward AGC module 2 can select components of different models and have different control strategies.

[0069] like Figure 2 As shown, it also includes a first tuning filter 7;

[0070] The input end of the first tuned filter 7 is used to input a signal received by the antenna 6;

[0071] The output end of the first tuned filter 7 is electrically connected to the input end of the first digitally controlled attenuator 101 in the first RF feedforward AGC module 1 .

[0072] The first tuning filter 7 is used to filter out interference signals outside the working frequency band.

[0073] In a specific embodiment, it further includes a second tuning filter 8;

[0074] The second tuned filter 8 is connected in series between the first RF feedforward AGC module 1 and the first RF feedforward AGC module 1; that is, the input end of the second tuned filter 8 is electrically connected to the output end of the first low noise amplifier 103 in the first RF feedforward AGC module 1, and the output end of the second tuned filter 8 is electrically connected to the input end of the second digitally controlled attenuator 201 in the second RF feedforward AGC module 2.

[0075] The second tuning filter 8 is used to further filter out interference signals outside the working frequency band.

[0076] In a specific embodiment, it also includes a first mixer 9, a first surface acoustic wave filter 10, a second intermediate frequency amplifier 11, and a first variable frequency source 15;

[0077] The input end of the first mixer 9 is electrically connected to the output end of the second low noise amplifier 203 in the second RF feedforward AGC module 2;

[0078] The output end of the first mixer 9 is electrically connected to the first surface acoustic wave filter 10 and the second intermediate frequency amplifier 11 in sequence;

[0079] The first variable frequency source 15 is electrically connected to the first mixer 9 .

[0080] The first mixer 9, the first SAW filter 10, the second intermediate frequency amplifier 11 and the first variable frequency source 15 are used to convert the received signal to a fixed frequency and further filter out the out-of-band interference signal.

[0081] In a specific embodiment, it also includes a second mixer 12, a second SAW filter 13, a third intermediate frequency amplifier 14, and a second variable frequency source 16;

[0082] The input end of the second mixer 12 is electrically connected to the output end of the second intermediate frequency amplifier 11;

[0083] The output end of the second mixer 12 is connected to the second surface acoustic wave filter 13 and the third intermediate frequency amplifier 14 in sequence;

[0084] The output end of the third intermediate frequency amplifier 14 is electrically connected to the input end of the third digitally controlled attenuator 301 in the intermediate frequency feedforward AGC module 3;

[0085] The second variable frequency source 16 is electrically connected to the second mixer 12 .

[0086] The second mixer 12, the second SAW filter 13, the third intermediate frequency amplifier 14, and the second variable frequency source 16 are used to convert the received signal to a lower frequency to facilitate sampling by the intermediate frequency ADC 17 and further filter out the out-of-band interference signal.

[0087] In a specific embodiment, it also includes an intermediate frequency ADC 17, which is used to convert the radio frequency analog signal into a digital signal and send it to the subsequent baseband unit for digital processing and demodulation.

[0088] The input end of the intermediate frequency ADC 17 is electrically connected to the output end of the first intermediate frequency amplifier 303 in the intermediate frequency feedforward AGC module 3;

[0089] The output end of the intermediate frequency ADC 17 is used to be electrically connected to the baseband.

[0090] The function of the intermediate frequency ADC 17 is to convert the radio frequency analog signal into a digital signal, and then send it to the subsequent baseband unit for digital processing and demodulation.

[0091] In a specific embodiment, it also includes a memory 18,

[0092] The memory 18 is electrically connected to the FPGA chip 5 .

[0093] In a specific embodiment, the gain allocation strategy follows the following principles:

[0094] a. Based on the capabilities of components, ensure that the components in the first RF feedforward AGC module 1, the second RF feedforward AGC module 2, and an intermediate frequency feedforward AGC module 3 operate in a relatively linear state, and minimize the impact of the nonlinear distortion of the receiver on the baseband demodulation;

[0095] b. The attenuation of the first digitally controlled attenuator, the second digitally controlled attenuator, and the third digitally controlled attenuator is minimized, the receiver system is in a relatively linear working state, and the signal entering the ADC is maximized to reduce the noise coefficient of the RF part of the receiver system;

[0096] c. The peak power of the signal entering the intermediate frequency ADC 17 (which may include a large interference signal) is N dB lower than the full-bias power of the intermediate frequency ADC to fully utilize the dynamic range of the intermediate frequency ADC 17. In this embodiment, the peak power of the signal entering the intermediate frequency ADC (which may include a large interference signal) is set to be 1 to 2 dB lower than the full-bias power of the ADC.

[0097] According to the above principles, if the peak-to-average ratio of the useful signal is A, and a safety margin B is reserved, the gain allocation strategies for the two RF feedforward AGC modules and one IF feedforward AGC module 3 are as follows:

[0098] d. For the first RF feedforward AGC module 1:

[0099] The FPGA chip 5 adjusts the attenuation of the first digitally controlled attenuator 101 according to the signal strength of the first coupler 102 in the first RF feedforward AGC module 1 and the gain of the first low noise amplifier 103 to ensure that the input signal of the first low noise amplifier 103 is (A+B) dB lower than its IP-1;

[0100] e. For the second RF feedforward AGC module 2:

[0101] The FPGA chip 5 adjusts the attenuation of the second digitally controlled attenuator 201 in the second RF feedforward AGC module 2 according to the signal strength of the first coupler 102 in the first RF feedforward AGC module 1, the second coupler 202 in the second RF feedforward AGC module 2, and the channel gain between the first coupler 102 in the first RF feedforward AGC module 1 and the first mixer 9, to ensure that the input signal of the first coupler 102 in the first RF feedforward AGC module 1 is (A+B) dB lower than its IP-1;

[0102] f. For IF feedforward AGC module 3:

[0103] The FPGA chip 5 ensures that the output power of the first intermediate frequency amplifier 303 is (A+B) dB lower than the full-bias power of the intermediate frequency ADC17 based on the signal strength of the first coupler 102 in the first RF feedforward AGC module 1, the second coupler 202 in the second RF feedforward AGC module 2, the signal strength of the third coupler 302, and the channel gain between the first coupler 102 in the first RF feedforward AGC module 1 and the intermediate frequency ADC17.

[0104] like Figure 3 As shown, the AGC adjustment is enabled, the detector is controlled to be powered on, the FPGA chip 5 controls the detection voltage ADC4 to read the detection voltage, and at the same time the FPGA chip 5 reads the response data such as the circuit and device frequency and temperature in the storage, and calculates the input power of the three couplers according to the detection voltage, the detector is powered off, and the attenuation values ​​of the three attenuators are calculated according to the gain allocation strategy of the AGC module mentioned above, and the attenuation amount is adjusted according to the attenuation value output control data to complete the adjustment.

[0105] Since the first RF feedforward AGC module 1, the second RF feedforward AGC module 2, and an intermediate frequency feedforward AGC module 3 work simultaneously, the adjustment time of the entire AGC is short, reaching within a few μs. At the same time, through the adjustment allocation strategy of the three feedforward AGC modules and the reasonable design of the receiver receiving link, it can be ensured that the receiver is in a sufficiently linear working state, and the signal with the best signal-to-noise ratio can be output as much as possible to the intermediate frequency ADC17 for sampling and baseband demodulation, so as to achieve the best anti-interference ability under the current hardware.

[0106] Due to the superposition of the adjustment range of the three feedforward AGC modules and the dynamic range of the intermediate frequency ADC17, the receiver system has a large dynamic range, which can reach more than 120dB. All gain controls are adjusted by digitally controlled attenuators to achieve precise adjustment in 0.25dB steps. In addition, through the pre-calibration method, the frequency, temperature and other responses of the circuit and components can be compensated. The receiver system can work with a wide frequency bandwidth and good temperature adaptability.

[0107] Example 3

[0108] This embodiment is based on Embodiment 2. The following is an example. In practice, appropriate components can be selected according to application requirements to implement receiver AGC with different requirements.

[0109] The first detector 104, the second detector 204, and the third detector 304 select ADL5902A, whose power-on time + voltage rise time is about 5μs (filter capacitor 220pF); the first digital controlled attenuator 101, the second digital controlled attenuator 201, and the third digital controlled attenuator 301 select PE43711, which has an adjustment range of 31.75dB and an adjustment accuracy of 0.25dB; the first low noise amplifier 1031 selects MGA30889, with a gain of 15dB and an input 1dB compression point of 5dBm; the first mixer 9 selects ADE-35MH, with an insertion loss of 8dB and an input P -1 9dBm. Assume that the modulation mode of the useful signal is QPSK, the bandwidth is 250kHz, the demodulation threshold is about 4dB, and the PAR is about 5dB. The AGC working frequency band can cover 50~3000MHz, the adjustment time is ≤10μs, the adjustment step is 0.25dB, and the dynamic range is +30~-108dBm.

[0110] Obviously, the above embodiments of the present invention are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A receiver system with automatic gain control, Features: The invention comprises an FPGA chip (5), a detection voltage ADC (4), a first radio frequency feedforward AGC module (1), a second radio frequency feedforward AGC module (2), and an intermediate frequency feedforward AGC module (3); wherein the first radio frequency feedforward AGC module (1), the second radio frequency feedforward AGC module (2), and an intermediate frequency feedforward AGC module (3) are connected in sequence; the first radio frequency feedforward AGC module (1) comprises a first digitally controlled attenuator (101), a first coupler (102), a first low noise amplifier (103), and a first detector (104) for detecting the radio frequency signal strength of the first coupler (102) connected in sequence; the second radio frequency feedforward AGC module (2) comprises a second digitally controlled attenuator (201), a second coupler (202), a second low noise amplifier (203), and a first detector (104) for detecting the radio frequency signal strength of the second coupler (202) connected in sequence; The intermediate frequency feedforward AGC module (3) comprises a third digitally controlled attenuator (301), a third coupler (302), a first intermediate frequency amplifier (303) connected in sequence, and a third detector (304) for detecting the intermediate frequency signal strength of the third coupler (302); the first detector (104), the second detector (204), and the third detector (304) respectively transmit the detected analog voltage signals to the detection voltage ADC (4); the detection voltage ADC (4) converts the analog voltage signals into digital voltage signals and transmits them to the FPGA chip (5) for processing; the FPGA chip (5) generates a gain allocation strategy according to the received digital voltage signals and simultaneously controls the first digitally controlled attenuator (101), the second digitally controlled attenuator (201), and the third digitally controlled attenuator (301) to realize automatic gain control; The gain allocation strategy follows the following principles: a. Based on the component capabilities, ensure that the components in the first RF feedforward AGC module (1), the second RF feedforward AGC module (2), and an intermediate frequency feedforward AGC module (3) operate in a relatively linear state; b. The attenuation of the first digitally controlled attenuator, the second digitally controlled attenuator, and the third digitally controlled attenuator is minimized, the receiver system is in a relatively linear operating state, and the signal entering the ADC is maximized to reduce the noise coefficient of the RF part of the receiver system; c. The peak power of the signal entering the intermediate frequency ADC (17) is N dB lower than the full bias power of the intermediate frequency ADC; and If the peak-to-average ratio of the useful signal is A, and a safety margin B is reserved, the gain allocation strategies for the two RF feedforward AGC modules and one intermediate frequency feedforward AGC module (3) are as follows: d. For the first RF feedforward AGC module (1): the FPGA chip (5) adjusts the attenuation of the first digitally controlled attenuator (101) according to the signal strength of the first coupler (102) in the first RF feedforward AGC module (1) and the gain of the first low noise amplifier (103), so as to ensure that the input signal of the first low noise amplifier (103) is (A+B) dB lower than its IP-1; e. For the second RF feedforward AGC module (2): the FPGA chip (5) adjusts the attenuation of the first digitally controlled attenuator (101) according to the signal strength of the first coupler (102) and the second coupler (202). f. for the intermediate frequency feedforward AGC module (3): the FPGA chip (5) adjusts the attenuation of the third digitally controlled attenuator (301) according to the signal strength of the first coupler (102), the second coupler (202), the signal strength of the third coupler (302), and the channel gain between the first coupler (102) and the intermediate frequency ADC (17), so as to ensure that the output power of the first intermediate frequency amplifier (303) is (A+B) dB lower than the full bias power of the intermediate frequency ADC (17).

2. The receiver system with automatic gain control according to claim 1, Features: It also comprises a first tuned filter (7); the input end of the first tuned filter (7) is used to input a received signal; the output end of the first tuned filter (7) is electrically connected to the input end of the first digitally controlled attenuator (101) in the first radio frequency feedforward AGC module (1).

3. The receiver system with automatic gain control according to claim 1, Features: It also includes a second tuned filter (8); the second tuned filter (8) is connected in series between the first RF feedforward AGC module (1) and the first RF feedforward AGC module (1); that is, the input end of the second tuned filter (8) is electrically connected to the output end of the first low noise amplifier (103) in the first RF feedforward AGC module (1), and the output end of the second tuned filter (8) is electrically connected to the input end of the second digitally controlled attenuator (201) in the second RF feedforward AGC module (2).

4. The receiver system with automatic gain control according to claim 1, Features: The invention also comprises a first mixer (9), a first surface acoustic filter (10), a second intermediate frequency amplifier (11), and a first variable frequency source (15); the input end of the first mixer (9) is electrically connected to the output end of the second low noise amplifier (203) in the second RF feedforward AGC module (2); the output end of the first mixer (9) is electrically connected to the first surface acoustic filter (10) and the second intermediate frequency amplifier (11) in sequence; and the first variable frequency source (15) is electrically connected to the first mixer (9).

5. The receiver system with automatic gain control according to claim 4, Features: The invention also comprises a second mixer (12), a second surface acoustic filter (13), a third intermediate frequency amplifier (14), and a second variable frequency source (16); the input end of the second mixer (12) is electrically connected to the output end of the second intermediate frequency amplifier (11); the output end of the second mixer (12) is connected to the second surface acoustic filter (13) and the third intermediate frequency amplifier (14) in sequence; the output end of the third intermediate frequency amplifier (14) is electrically connected to the input end of the third digitally controlled attenuator (301) in the intermediate frequency feedforward AGC module (3); and the second variable frequency source (16) is electrically connected to the second mixer (12).

6. The receiver system with automatic gain control according to claim 1, Features: It also includes an intermediate frequency ADC (17); the input end of the intermediate frequency ADC (17) is electrically connected to the output end of the first intermediate frequency amplifier (303) in the intermediate frequency feedforward AGC module (3); and the output end of the intermediate frequency ADC (17) is used to be electrically connected to the baseband.

7. The receiver system with automatic gain control according to claim 1, Features: It also includes a memory (18), and the memory (18) is electrically connected to the FPGA chip (5).

8. The receiver system with automatic gain control according to any one of claims 1 to 7, Features: All gain distribution strategies are adjusted through the first digitally controlled attenuator, the second digitally controlled attenuator, and the third digitally controlled attenuator to achieve 0.25dB step adjustment.

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