Differential memory cell array structure for multiple programming non-volatile memory

Abstract

The present invention is a differential memory cell array structure for use in a multi-time programmable non-volatile memory. The array structure is connected to a source line, a word line, a bit line, an inverted bit line, and an erase line. According to embodiments of the present invention, during an erase operation (ERS), the multi-time programmable non-volatile memory does not erase data from all differential memory cells in a selected row of the array structure. Instead, the multi-time programmable non-volatile memory only erases data from a single selected memory cell in the selected row of the array structure.

Description

Technical Field

[0001] This invention relates to an array structure (memory cell array), and more particularly to a differential memory cell array structure used in a repeatedly programmable nonvolatile memory. Background Technology

[0002] As is well known, non-volatile memory retains its data even after power is lost. Taking multi-time programming non-volatile memory (MTP) as an example, users can perform programming operations to store data in the non-volatile memory. Furthermore, users can perform read operations to retrieve the stored data. Of course, users can also perform erase operations to clear the stored data in the non-volatile memory.

[0003] Generally, non-volatile memory consists of an array of memory cells connected to multiple signal lines, such as word lines, bit lines, and erase lines. Furthermore, by providing appropriate bias to these signal lines, users can perform programming, reading, or erasing operations on the memory cells within the array.

[0004] However, due to the known array structure design of non-volatile memory, when an erase operation is performed on the array structure, the data of all memory cells in a single area of ​​the array structure is erased simultaneously, such as chip erase or segment erase. For example, during an erase operation, the data of 256 memory cells in a segment of the array structure will be erased simultaneously. In other words, it is known that non-volatile memory cannot erase a single memory cell in the array structure. Summary of the Invention

[0005] This invention relates to a differential memory cell array structure. The differential memory cell array structure includes: a first differential memory cell. The first differential memory cell includes: a first select transistor, a first drain / source terminal of which is connected to a first source line, a gate terminal of which is connected to a first word line, and a fixed terminal of which receives a first well voltage; a first floating gate transistor, a first drain / source terminal of which is connected to a second drain / source terminal of which is coupled to a first word line, and a fixed terminal of which receives the first well voltage; and a first capacitor, a first terminal of which is connected to a floating gate of which is connected to a first eraser. The first erase line includes: a second select transistor, a first drain / source terminal of which is connected to the first source line, a gate terminal of which is connected to the first word line, and an integral terminal of which receives the first well voltage; a second floating gate transistor, a first drain / source terminal of which is connected to a second drain / source terminal of which is coupled to a first anti-phase line, and an integral terminal of which receives the first well voltage; and a second capacitor, a first terminal of which is connected to a floating gate of the second floating gate transistor, and a second terminal of which is connected to the first erase line.

[0006] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0007] Figures 1A to 1C This is a flowchart illustrating the fabrication process of the differential memory cell according to the first embodiment of the present invention;

[0008] Figure 1D This is the equivalent circuit of the differential memory cell in the first embodiment of the present invention;

[0009] Figure 2A This is a bias gauge used for programming, reading, and erasing operations on differential memory cells according to the first embodiment of the present invention.

[0010] Figures 2B to 2D A schematic diagram of the bias voltage for programming, reading and erasing operations on differential memory cells;

[0011] Figure 3A and Figure 3B This is a top view of the array structure of the MTP non-volatile memory of the present invention, and the equivalent circuit of the array structure.

[0012] Figure 4A A bias meter for programming, reading and erasing operations on the array structure of the present invention;

[0013] Figures 4B to 4D A schematic diagram of the bias voltage for programming, reading, and erasing operations on the array structure;

[0014] Figure 5A This is the equivalent circuit of the differential memory cell in the second embodiment of the present invention;

[0015] Figure 5B The second embodiment is an array structure composed of differential memory cells;

[0016] Figures 6A to 6C This is a flowchart illustrating the fabrication process of the differential memory cell according to the third embodiment of the present invention;

[0017] Figure 6D This is the equivalent circuit of the differential memory cell in the third embodiment of the present invention;

[0018] Figure 7A and Figure 7B This is a top view of the array structure of the MTP non-volatile memory of the present invention, and an equivalent circuit of the array structure.

[0019] Figure 8A A bias gauge for performing various operations on the array structure of the present invention; and

[0020] Figure 8B A schematic diagram of the bias voltage used for erasing the array structure.

[0021] [Symbol Explanation]

[0022] 102, 110, 120, 202, 204, 210, 220, 230, 240, 250, 260, 270, 280, 602, 610, 620, 702, 704, 710, 720, 730, 740, 750, 760, 770, 780: Gate Structure

[0023] 112, 114, 116, 122, 124, 126, 212, 214, 216, 222, 224, 226, 232, 234, 236, 242, 244, 246, 252, 254, 256, 262, 264, 266, 272, 274, 276, 282, 284, 286, 612, 614, 616, 622, 624, 626, 712, 714, 716, 722, 724, 726, 732, 734, 736, 742, 744, 746, 754, 756, 764, 766, 774, 776, 784, 786: p-doped region

[0024] 192, 292, 294, 691, 692, 791, 792, 793, 794, 795, 796: n-doped regions Detailed Implementation

[0025] Please refer to Figures 1A to 1C The diagram shown is a flowchart of the fabrication process of the differential memory cell according to the first embodiment of the present invention. Figure 1D This is the equivalent circuit of the differential memory cell in the first embodiment of the present invention.

[0026] like Figure 1A As shown, an N-well region NW1 and a P-well region PW1 are formed below the surface of the semiconductor substrate Sub.

[0027] like Figure 1B As shown, multiple gate structures 102, 110, and 120 are formed. Gate structure 102 covers the N-type well region NW1. Gate structures 110 and 120 also cover the N-type well region NW1 and extend from the semiconductor substrate Sub to the P-type well region PW1. That is, gate structures 110 and 120 cover both the N-type well region NW1 and the P-type well region PW1. Each gate structure 102, 110, and 120 includes a gate oxide layer and a polysilicon gate layer. The gate oxide layer covers the surface of the semiconductor substrate Sub, and the polysilicon gate layer covers the gate oxide layer.

[0028] A first doping process is performed to form p-doped regions 112, 114, 116, 122, 124, and 126 in the N-type well region NW1. Specifically, p-doped region 112 is located on the first side of gate structure 102, p-doped region 114 is located between the second side of gate structure 102 and the first side of gate structure 110, and p-doped region 116 is located on the second side of gate structure 110. Similarly, p-doped region 122 is located on the first side of gate structure 102, p-doped region 124 is located between the second side of gate structure 102 and the first side of gate structure 120, and p-doped region 126 is located on the second side of gate structure 120.

[0029] Next, a second doping process is performed to form an n-doped region 192 in the P-type well region PW1. For example... Figure 1B As shown, the n-doped region 192 is adjacent to the gate structures 110 and 120 that extend to the P-type well region PW1.

[0030] Of course, the order of the above-mentioned secondary doping processes can be interchanged. That is, the first doping process can form an n-doped region 192 in the P-type well region PW1, and the second doping process can form p-doped regions 112, 114, 116, 122, 124, and 126 in the N-type well region NW1.

[0031] like Figure 1C As shown, an interconnect process is performed to form multiple metal lines. The metal line connected to p-doped regions 112 and 122 serves as the source line SL. The metal line connected to p-doped region 116 serves as the bit line BL1. The metal line connected to p-doped region 126 serves as the anti-phase line BL1'. The metal line connected to gate structure 102 serves as the word line WL1. The metal line connected to n-doped region 192 serves as the erase line EL1. Furthermore, the metal lines are connected to the N-type well region NW1, allowing NW1 to receive the well region voltage V. NW1 .

[0032] like Figure 1D As shown, the differential memory cell c11 includes two sub-cells c1 and c1', and the two sub-cells c1 and c1' have the same structure.

[0033] Sub-memory cell c1 includes two transistors M S1 M F1 A capacitor C1 is used. The N-type well region NW1, p-doped region 112, p-doped region 114, and gate structure 102 form a select transistor M. S1 The N-type well region NW1, p-doped region 114, p-doped region 116, and gate structure 110 form a floating gate transistor M. F1 The gate structure 110 and the n-doped region 192 form a capacitor C1. Therefore, the selection transistor M... S1 The first drain / drain terminal is connected to the source line SL, selecting transistor M. S1 The gate terminal is connected to word line WL1. Floating gate transistor M F1 The first drain / source terminal is connected to the select transistor M. S1 The second drain / source terminal, floating gate transistor M F1 The second drain / source terminal is connected to bit line BL1. The first terminal of capacitor C1 is connected to the floating gate transistor M. F1 The floating gate of the capacitor C1 is connected to the erase line EL1. Furthermore, the select transistor M... S1 With floating gate transistor M F1The body terminal receives the well voltage V. NW1 .

[0034] Similarly, sub-memory cell c1' includes two transistors M. S2 M F2 A capacitor C2 is used. The N-type well region NW1, p-doped region 122, p-doped region 124, and gate structure 102 form a select transistor M. S2 The N-type well region NW1, p-doped region 124, p-doped region 126, and gate structure 120 form a floating gate transistor M. F2 The gate structure 120 and the n-doped region 192 form a capacitor C2. The selection transistor M... S2 The first drain / source terminal is connected to the source line SL, selecting transistor M. S2 The gate terminal is connected to word line WL1. Floating gate transistor M F2 The first drain / source terminal is connected to the select transistor M. S2 The second drain / source terminal, floating gate transistor M F2 The second drain / source terminal is connected to the anti-phase line BL1'. The first terminal of capacitor C2 is connected to the floating gate transistor M. F2 The floating gate of capacitor C2 is connected to the erase line EL1. Furthermore, the selection transistor M... S2 With floating gate transistor M F2 The body extreme receiving well area voltage V NW1 .

[0035] Please refer to Figure 2A The diagram illustrates a bias table for programming, reading, and erasing operations on a differential memory cell according to the first embodiment of the present invention. Furthermore, Figures 2B to 2D A schematic diagram of the bias voltage for programming, reading and erasing operations on differential memory cells.

[0036] Please refer to Figure 2A and Figure 2B During programming (PGM) operation, the source line SL of differential memory cell c11 receives the programming voltage Vpp, the word line WL1 receives half of the programming voltage (Vpp / 2), the erase line EL1 receives half of the programming voltage (Vpp / 2), the bit line BL1 receives the ground voltage (0V), and the anti-phase line BL1' is floating (FLT). Additionally, the well voltage V... NW1 The programming voltage is Vpp. Vpp is approximately 10V.

[0037] In sub-memory cell c1, due to the activation of word line WL1, selection transistor M is activated. S1 When the transistor is turned on, the program current Ip flows from the source line SL through the select transistor M. S1 Floating gate transistor M F1 The current flows to bit line BL1. Therefore, hot carriers, such as electrons, are transported by the floating gate transistor M. F1 Second drain / source injection of floating gate transistor M F1 Floating gate.

[0038] In sub-memory cell c1', although word line WL1 is activated, no programming current can be generated because the anti-phase line BL1' is floating (FLT). Therefore, hot carriers, such as electrons, cannot be injected into the floating gate transistor M. F2 Floating gate.

[0039] In other words, during programming operations (PGM), the floating gate transistor M is controlled. F1 Storage of hot carriers and floating gate transistor M F2 When no hot carriers are stored, the differential memory cell c11 is programmed to the first storage state.

[0040] Of course, during programming operation (PGM), the anti-phase line BL1' can also be controlled to receive ground voltage (0V), while the bit line BL1 is floating (FLT). In this case, the floating gate transistor M... F2 Storage of hot carriers and floating gate transistor M F1 The absence of hot carriers allows the differential memory cell c11 to be programmed into a second storage state.

[0041] As can be seen from the above explanation, during programming operation (PGM), controlling the voltage received by bit line BL1 and anti-phase line BL1' can program the differential memory cell c11 to either the first storage state or the second storage state.

[0042] Please refer to Figure 2A and Figure 2C During a read operation, the source line SL of differential memory cell c11 receives the read voltage Vr, the word line WL1 receives the turn-on voltage Von, the erase line EL1 receives the ground voltage (0V), the bit line BL1 receives the ground voltage (0V), and the inverse phase line BL1' receives the ground voltage (0V). Additionally, the well voltage V... NW1 The reading voltage is Vr. Vr is less than the programming voltage Vpp, and is approximately 3.3V. The turn-on voltage Von is equal to the ground voltage (0V).

[0043] like Figure 2C As shown, during a read operation, word line WL1 is activated, selecting transistor M. S1 M S2 Turn on. Due to the floating gate transistor M of sub-memory cell c1. F1 The floating gate transistor M stores hot carriers and sub-memory cell c1'. F2 No hot carriers are stored. Therefore, sub-memory cell c1 generates a large read current Ir, which flows from the source line SL through the select transistor M. S1 Floating gate transistor M F1 The current flows to bit line BL1, while the sub-memory cell c1' generates a small, almost zero read current Ir'.

[0044] In other words, during a read operation (READ), the storage state of the differential memory cell c11 can be determined by judging the magnitudes of the read currents Ir and Ir' on bit line BL1 and anti-phase line BL1'. Figure 2C In the process, if the read current Ir is greater than the read current Ir', then the differential memory cell c11 is confirmed to be in the first storage state. Conversely, if the read current Ir' is greater than the read current Ir, then the differential memory cell c11 is confirmed to be in the second storage state.

[0045] Please refer to Figure 2A and Figure 2D During the erase operation (ERS), the source line SL of the differential memory cell c11 receives the ground voltage (0V), the word line WL1 receives the ground voltage (0V), the bit line BL1 receives the ground voltage (0V), the anti-phase line BL1' receives the ground voltage (0V), and the erase line EL1 receives the erase voltage Vee. Additionally, the well voltage V... NW1 The ground voltage is 0V. The erase voltage Vee is greater than the programming voltage Vpp, and the erase voltage Vee is approximately 15V.

[0046] like Figure 2D As shown, word line WL1 is activated during the erase operation (ERS). This is because erase line EL1 is connected to the floating gate transistor M. F1 M F2 The body extreme (i.e., the well voltage V) NW1 The voltage difference between the gate transistors is equal to the erase voltage (Vee-0V), causing the floating gate transistor M to... F1 The Fowler-Nordheim (FN) electron tunneling ejection effect occurs, causing hot carriers to be ejected from the floating gate transistor M.F1 The floating gate exits to the floating gate transistor M F1 The body extreme, and complete the erasure operation (ERS).

[0047] Of course, during the erase operation (ERS), if hot carriers are stored in the floating gate transistor M F2 Then the floating gate transistor M F2 The Fowler-Nordheim (FN) electron tunneling ejection effect occurs, causing hot carriers to be ejected from the floating gate transistor M. F2 The floating gate exits to the floating gate transistor M F2 The body extreme is reached, and the erase operation (ERS) is completed. That is, after the erase operation (ERS), the floating gate transistor M in the differential memory cell c11 is... F1 M F2 None of them stored hot carriers.

[0048] Furthermore, multiple differential memory cells from the first embodiment can be combined to form an MTP non-volatile memory. That is, the MTP non-volatile memory of the present invention includes multiple differential memory cells and forms a differential memory cell array structure. According to embodiments of the present invention, in the MTP non-volatile memory, an erase operation can be performed individually on any memory cell in the array structure.

[0049] Please refer to Figure 3A and Figure 3B The diagram shows a top view of the array structure of the MTP non-volatile memory of the present invention, as well as the equivalent circuit of the array structure. The MTP non-volatile memory includes four differential memory cells c11 to c22, forming a 2x2 array structure. Of course, the MTP non-volatile memory of the present invention is not limited to a 2x2 array structure; it can also form an mxn array structure, where m and n are positive integers.

[0050] like Figure 3A As shown, two N-well regions NW1 and NW2, and two P-well regions PW1 and PW2 are formed below the surface of the semiconductor substrate Sub. The two separate N-well regions NW1 and NW2 are formed in the upper and lower regions of the semiconductor substrate Sub, while the two separate P-well regions PW1 and PW2 are formed in the middle region of the semiconductor substrate Sub. Furthermore, the semiconductor substrate Sub can be a P-type semiconductor substrate.

[0051] Next, multiple gate structures 202, 204, 210, 220, 230, 240, 250, 260, 270, and 280 are formed. Gate structure 202 covers the N-type well region NW1, and gate structure 204 covers the N-type well region NW2. Gate structures 210 and 220 cover the N-type well region NW1 and the P-type well region PW1. Gate structures 230 and 240 cover the N-type well region NW1 and the P-type well region PW2. Gate structures 250 and 260 cover the N-type well region NW2 and the P-type well region PW1. Gate structures 270 and 280 cover the N-type well region NW2 and the P-type well region PW2.

[0052] Next, the first doping process is performed to form p-doped regions 212, 214, 216, 222, 224, 226, 232, 234, 236, 242, 244, 246, 252, 254, 256, 262, 264, 266, 272, 274, 276, 282, 284, and 286 in the N-type well regions NW1 and NW2. Taking p-doped regions 212, 214, and 216 as examples, p-doped region 212 is located on the first side of gate structure 202, p-doped region 214 is located between the second side of gate structure 202 and the first side of gate structure 210, and p-doped region 216 is located on the second side of gate structure 210.

[0053] Furthermore, a second doping process is performed to form n-doped regions 292 and 294 in the P-type well regions PW1 and PW2. n-doped region 292 is adjacent to the gate structures 210, 220, 250, and 260 extending into the P-type well region PW1. n-doped region 294 is adjacent to the gate structures 230, 240, 270, and 280 extending into the P-type well region PW2.

[0054] Furthermore, interconnection is performed to form multiple metal lines SL, WL1, WL2, BL1, BL1', BL2, BL2', EL1, and EL2. The source line SL is connected to p-doped regions 212, 222, 232, 242, 252, 262, 272, and 282. The bit line BL1 is connected to p-doped regions 216 and 256. The anti-phase line BL1' is connected to p-doped regions 226 and 266. The bit line BL2 is connected to p-doped regions 236 and 276. The anti-phase line BL2' is connected to p-doped regions 246 and 286. The word line WL1 is connected to gate structure 202. The word line WL2 is connected to gate structure 204. The erase line EL1 is connected to n-doped region 292. The erase line EL2 is connected to n-doped region 294. The well voltage V... NW1 Provided to N-type well area NW1. Well area voltage V NW2 Provided to N-type well area NW2.

[0055] like Figure 3BAs shown, four differential memory cells c11 to c22 form a 2x2 array structure. The equivalent circuit of each differential memory cell c11 to c22 is identical to... Figure 1D The internal connections of differential memory cells c11 to c22 will not be elaborated here. Furthermore, differential memory cell c11 includes two sub-memory cells c1 and c1', differential memory cell c12 includes two sub-memory cells c2 and c2', differential memory cell c21 includes two sub-memory cells c3 and c3', and differential memory cell c22 includes two sub-memory cells c4 and c4'.

[0056] According to an embodiment of the present invention, in Figure 3B In the array structure, the transistors of the differential memory cells in the same row are all designed in the same well region. For example, in the two differential memory cells c11 and c12 in the first row, the selection transistor M... S1 M S2 M S3 M S4 and floating gate transistor M F1 M F2 M F3 M F4 All are designed in an N-type well region NW1. That is, in the two differential memory cells c11 and c12 of the first row, the body terminals of all transistors receive the well region voltage V. NW1 Similarly, in the two differential memory cells c21 and c22 in the second row, transistor M is selected. S5 M S6 M S7 M S8 and floating gate transistor M F5 M F6 M F7 M F8 All are designed in the N-type well region NW2. That is to say, in the two differential memory cells c21 and c22 in the second row, the body terminals of all transistors receive the well region voltage V. NW2 .

[0057] Furthermore, the source line SL is connected to all differential memory cells c11 to c22. That is, the source line SL is connected to the select transistor M. S1 M S2 M S3 M S4 M S5 M S6 M S7 M S8 The first drain / source.

[0058] Word line WL1 is connected to two differential memory cells c11 and c12 in the same row. That is, word line WL1 is connected to the select transistor M. S1 M S2 M S3 M S4 The gate terminal of the [transistor name]. Word line WL2 is connected to two differential memory cells c21 and c22 in the same row. That is, word line WL2 is connected to the select transistor M. S5 M S6 M S7 M S8 The gate terminal.

[0059] Bit line BL1 and anti-phase line BL1' are connected to two differential memory cells c11 and c21 in the same column. That is, bit line BL1 is connected to the floating gate transistor M. F1 M F5 The second drain / source terminal. The anti-phase line BL1' is connected to the floating gate transistor M. F2 M F6 The second drain / source terminal. Bit line BL2 and anti-phase line BL2' are connected to two differential memory cells c12 and c22 in the same column. That is, bit line BL2 is connected to the floating gate transistor M. F3 M F7 The second drain / source terminal. The anti-phase line BL2' is connected to the floating gate transistor M. F4 M F8 The second drain / source.

[0060] According to an embodiment of the present invention, in Figure 3B In the array structure, multiple differential memory cells in the same row are connected to different erase lines. That is, n differential memory cells in the same row will be connected to n different erase lines. Figure 3B In the first row, the two differential memory cells c11 and c12 are connected to erase lines EL1 and EL2, respectively. That is, erase line EL1 is connected to the second terminals of capacitors C1 and C2, and erase line EL2 is connected to the second terminals of capacitors C3 and C4. Similarly, the two differential memory cells c21 and c22 in the second row are connected to erase lines EL1 and EL2, respectively. That is, erase line EL1 is connected to the second terminals of capacitors C5 and C6, and erase line EL2 is connected to the second terminals of capacitors C7 and C8.

[0061] Please refer to Figure 4A The diagram illustrates a bias table used for programming, reading, and erasing operations on the array structure of this invention. Furthermore, Figures 4B to 4DThis diagram illustrates the bias voltage for programming, reading, and erasing operations on an array structure. According to an embodiment of the present invention, in an MTP non-volatile memory, programming, erasing, and reading operations can be performed on a single differential memory cell. The following description uses differential memory cell c11 as the selected memory cell and describes the programming, erasing, and reading operations performed on the selected memory cell.

[0062] Please refer to Figure 4A and Figure 4B During programming (PGM) operation, the source line SL receives the programming voltage Vpp, the word line WL1 receives half of the programming voltage (Vpp / 2), the word line WL2 receives the programming voltage (Vpp), the bit line BL1 receives the ground voltage (0V), the anti-phase line BL1' is floating (FLT), the bit line BL2 is floating (FLT), the anti-phase line BL2' is floating (FLT), the erase line EL1 receives half of the programming voltage (Vpp / 2), the erase line EL2 receives the ground voltage (0V), and the well voltage V... NW1 For programming voltage Vpp, well voltage V NW2 The programming voltage is Vpp.

[0063] In the array structure, word line WL1 is activated because it receives half of the programming voltage (Vpp / 2), and the first row connected to word line WL1 is the selected row. Conversely, word line WL2 receives the programming voltage (Vpp), so it is inactivated, and the second row connected to word line WL2 is the unselected row.

[0064] Since the second row is a non-selected row, the selection transistor M in differential memory cells c21 and c22... S5 M S6 M S7 M S8 When turned off, differential memory cells c21 and c22 cannot generate programming current. In other words, differential memory cells c21 and c22 in non-selected rows are program-inhibited.

[0065] Furthermore, since the first row is a selected row, and bit line BL1 receives ground voltage (0V), the anti-phase line BL1' is floating (FLT), bit line BL2 is floating (FLT), and anti-phase line BL2' is floating (FLT). Therefore, differential memory cell c11 in the first row is a selected memory cell, and differential memory cell c12 is an unselected memory cell. Thus, the selected memory cell (i.e., differential memory cell c11) is programmed into the first memory state; the unselected memory cell c12 is programmed into inhibition.

[0066] Of course, during the above programming operation (PGM), if bit line BL1 is floating (FLT) and antiphase line BL1' receives ground voltage (0V), then differential memory cell c11 is selected memory cell, and the selected memory cell will be programmed to the second storage state.

[0067] Please refer to Figure 4A and Figure 4C During a read operation, the source line SL receives the read voltage Vr, the word line WL1 receives the turn-on voltage (Von), the word line WL2 receives the turn-off voltage (Voff), the bit line BL1 receives the ground voltage (0V), the reverse phase line BL1' receives the ground voltage (0V), the bit line BL2 is floating (FLT), the reverse phase line BL2' is floating (FLT), the erase line EL1 receives the ground voltage (0V), the erase line EL2 receives the ground voltage (0V), and the well voltage V... NW1 To read voltage Vr and well voltage V NW2 To read the voltage Vr. For example, the turn-on voltage Von is equal to the ground voltage (0V), and the turn-off voltage Voff is equal to the read voltage (Vr).

[0068] In the array structure, word line WL1 is activated because it receives an enable voltage (Von), and the first row connected to word line WL1 is the selected row. Conversely, word line WL2 is inactivated because it receives an disable voltage (Voff), and the second row connected to word line WL2 is the non-selected row.

[0069] Since the second row is a non-selected row, the selection transistor M in differential memory cells c21 and c22... S5 M S6 M S7 M S8When turned off, differential memory cells c21 and c22 cannot generate read current. In other words, differential memory cells c21 and c22 that are not in the selected row are read inhibited.

[0070] Furthermore, since the first row is the selected row, and bit line BL1 receives ground voltage (0V), anti-phase line BL1' receives ground voltage (0V), bit line BL2 is floating (FLT), and anti-phase line BL2' is floating (FLT). Therefore, differential memory cell c11 in the first row is the selected memory cell, and differential memory cell c12 is the non-selected memory cell, and the non-selected memory cell is read inhibited. That is to say, during a read operation, bit line BL1 and anti-phase line BL1' of the selected memory cell will generate read current, and the storage state of the selected memory cell (differential memory cell c11) can be determined based on the magnitude of the two read currents.

[0071] Please refer to Figure 4A and Figure 4D During the erase operation (ERS), the source line SL receives the ground voltage (0V), the word line WL1 receives the ground voltage (0V), the word line WL2 receives the programming voltage (Vpp), the bit line BL1 receives the ground voltage (0V), the anti-phase line BL1' receives the ground voltage (0V), the bit line BL2 is floating (FLT), the anti-phase line BL2' is floating (FLT), the erase line EL1 receives the erase voltage (Vee), the erase line EL2 receives the ground voltage (0V), and the well voltage V... NW1 Grounding voltage (0V), well area voltage V NW2 The programming voltage is Vpp.

[0072] In the array structure, word line WL1 is activated because it receives a ground voltage (0V), and the first row connected to word line WL1 is the selected row. Conversely, word line WL2 is inactivated because it receives a programming voltage (Vpp), and the second row connected to word line WL2 is the non-selected row.

[0073] In the differential memory cell c21 of the unselected row, the erase line EL1 and the floating gate transistor M F5 M F6 The body extreme (i.e., the well voltage V) NW2 The voltage difference between them is equal to (Vee - Vpp), so the FN electron tunneling exit effect cannot occur. Additionally, in the differential memory cell c22 of the unselected row, the erase line EL2 and the floating gate transistor M... F7 M F8The body extreme (i.e., the well voltage V) NW2 The voltage difference between them is equal to (0-Vpp), so the FN electron tunneling exit effect cannot occur. In other words, the differential memory cells c21 and c22 of the non-selected rows are erased.

[0074] In the differential memory cell c12 of the selected row, erase line EL2 and floating gate transistor M F3 M F4 The body extreme (i.e., the well voltage V) NW1 The voltage difference between the cells is 0V, so the FN electron tunneling exit effect cannot occur. In other words, the differential memory cell c12 of the selected row is erased.

[0075] Additionally, in the differential memory cell c11 of the selected row, erase line EL1 and floating gate transistor M F1 M F2 The body extreme (i.e., the well voltage V) NW1 The voltage difference between the two is equal to Vee (Vee-0V), so the differential memory cell c11 is the selected memory cell, and the selected memory cell undergoes the FN electron tunneling exit effect, which erases the stored data in the selected memory cell.

[0076] According to an embodiment of the present invention, during an erase operation (ERS), the MTP non-volatile memory does not erase data in all differential memory cells of the selected row. The MTP non-volatile memory erases data only in a single selected memory cell of the selected row.

[0077] Due to variations in semiconductor manufacturing processes, some non-selected memory cells may undergo soft erasure during the erase operation (ERS). For example, Figure 4D In this context, differential memory cell c21, which shares the same column as the selected memory cell (differential memory cell c11), is subject to erase inhibition. However, within differential memory cell c21, erase line EL1 and the floating gate transistor M... F5 M F6 The voltage difference between the second drain / source terminals is Vee (Vee-0V). When the floating gate transistor M... F5 M F6 When the characteristics are poor, the floating gate transistor M F5 M F6Hot carriers in the memory may eject to bit line BL1 and antiphase line BL1', causing the stored data in differential memory cell c21 to gradually leak out.

[0078] To solve the above problems, the differential memory cell of the first embodiment can be modified. Please refer to... Figure 5A The diagram shown is the equivalent circuit of the differential memory cell according to the second embodiment of the present invention. Figure 5B The second embodiment is an array structure composed of differential memory cells.

[0079] like Figure 5A As shown, the differential memory cell c11 includes two sub-memory cells c1 and c1', and the two sub-memory cells c1 and c1' have the same structure. Compared with the differential memory cell of the first embodiment, the differential memory cell c11 of the second embodiment adds two coupling devices 512 and 514. The following only describes the connection relationship and operating principle of the coupling devices 512 and 514.

[0080] The first terminal of coupling element 512 is connected to the floating gate transistor M. F1 The second drain / source terminal of coupling element 512 is connected to bit line BL1, and the third terminal of coupling element 512 is connected to ground. The first terminal of coupling element 514 is connected to the floating gate transistor M. F2 The second drain / source terminal of the coupling element 514 is connected to the anti-phase line BL1', and the third terminal of the coupling element 514 is connected to the ground terminal.

[0081] According to a second embodiment of the present invention, during programming (PGM) and reading (READ) operations, the first end of coupling element 512 is connected to the second end, and the first end of coupling element 514 is connected to the second end. That is, coupling element 512 connects the floating gate transistor M... F1 The second drain / source terminal is coupled to bit line BL1, and coupling element 514 couples the floating gate transistor M F2 The second drain / source terminal is coupled to the anti-phase line BL1'. Therefore, during programming (PGM) and reading (READ) operations, the bias voltage and operating principle of the differential memory cell in the first embodiment and the differential memory cell in the second embodiment are exactly the same.

[0082] Furthermore, during the erase operation (ERS), the coupling elements 512 and 514 of the differential memory cell c11 are switched depending on whether the word line WL1 is activated. For example, during the erase operation (ERS) and when the word line WL1 is not activated, the first terminal of coupling element 512 is connected to the second terminal, and the first terminal of coupling element 514 is connected to the second terminal. That is, coupling element 512 connects the floating gate transistor M...F1 The second drain / source terminal is coupled to bit line BL1, and coupling element 514 couples the floating gate transistor M F2 The second drain / source terminal is coupled to the anti-phase line BL1'.

[0083] Additionally, during the erase operation (ERS) and word line WL1 is activated, the first terminal of coupling element 512 is connected to the third terminal, and the first terminal of coupling element 514 is connected to the third terminal. That is, coupling element 512 connects the floating gate transistor M... F1 The second drain / source terminal is coupled to the ground terminal, and the coupling element 514 couples the floating gate transistor M. F2 The second drain / source terminal is coupled to the ground terminal.

[0084] Please refer to Figure 5B The diagram illustrates the array structure of the differential memory cells in the second embodiment and the bias voltage diagram for the erase operation. Two differential memory cells, c11 to c21, form a 2×1 array structure. Of course, similar to... Figure 3B The connection relationship can also be Figure 5B The array structure is expanded to a 2×2 or m×n array structure. Furthermore, the equivalent circuits of each differential memory cell c11~c21 are identical to... Figure 5A The internal connections of differential memory cells c11 to c21 will not be elaborated here.

[0085] Differential memory cell c11 includes two sub-memory cells c1 and c1', and differential memory cell c21 includes two sub-memory cells c2 and c2'. The source line SL is connected to the select transistor M. S1 M S2 M S3 M S4 The first drain / source terminal. Word line WL1 is connected to the select transistor M. S1 M S2 The gate terminal. Word line WL2 is connected to the select transistor M. S3 M S4 The gate terminal. Bit line BL1 is connected to the second terminal of coupling elements 512 and 516. Anti-phase line BL2' is connected to the second terminal of coupling elements 514 and 518. Erase line EL1 is connected to the second terminal of capacitors C1, C2, C3, and C4.

[0086] During programming operations (PGM) and reading operations (READ), Figure 5B The bias and operating principle of the array structure are similar to Figure 4B and Figure 4C This will not be elaborated upon here.

[0087] Please refer to Figure 5BDuring the erase operation (ERS), the source line SL receives the ground voltage (0V), the word line WL1 receives the ground voltage (0V), the word line WL2 receives the programming voltage (Vpp), and the erase line EL1 receives the erase voltage (Vee) and the well voltage V. NW1 The bit line BL1 and the anti-phase line BL1' simultaneously receive the programming voltage (Vpp) or simultaneously float (FLT).

[0088] In the array structure, word line WL1 is activated because it receives a ground voltage (0V). The first row connected to word line WL1 is the selected row, and the first and third terminals of coupling element 512 and coupling element 514 are connected. Furthermore, word line WL2 receives a programming voltage (Vpp), so it is inactivated. The second row connected to word line WL2 is the non-selected row, and the first and second terminals of coupling element 516 and coupling element 518 are connected.

[0089] In the differential memory cell c11 of the selected row, erase line EL1 and floating gate transistor M F1 M F2 The body extreme (i.e., the well voltage V) NW1 The voltage difference between the two is equal to Vee (Vee-0V), so the differential memory cell c11 is the selected memory cell, and the selected memory cell undergoes the FN electron tunneling exit effect, which erases the stored data in the selected memory cell.

[0090] In the differential memory cell c21 of the unselected row, the erase line EL1 and the floating gate transistor M F3 M F4 The body extreme (i.e., the well voltage V) NW2 The voltage difference between the cells is equal to (Vee - Vpp), so the FN electron tunneling exit effect cannot occur. In other words, the differential memory cell c21 of the non-selected row is erase-inhibited.

[0091] Additionally, in the unselected memory cell (differential memory cell c21), erase line EL1 and floating gate transistor M F3 M F4 The voltage difference between the second drain / source terminals is equal to (Vee-Vpp) or there is no voltage difference, so the differential memory cell c21 will not undergo a soft erase. In other words, during the erase operation (ERS), the floating gate transistor M can be ensured to remain in its normal position.F3 M F4 The hot carriers in the phase line will not eject to the bit line BL1 and the antiphase line BL1'.

[0092] Please refer to Figures 6A to 6C The diagram shown is a flowchart of the fabrication process of the differential memory cell according to the third embodiment of the present invention. Figure 6D This is the equivalent circuit of the differential memory cell in the third embodiment of the present invention.

[0093] like Figure 6A As shown, an N-well NW1 and P-wells PW1 and PW2 are formed below the surface of the semiconductor substrate Sub.

[0094] like Figure 6B As shown, multiple gate structures 602, 610, and 620 are formed. Gate structure 602 covers the substrate Sub and the N-type well region NW1. Gate structures 610 and 620 cover the N-type well region NW1. Gate structure 610 extends from above the semiconductor substrate Sub to the P-type well region PW1, and gate structure 620 extends from above the semiconductor substrate Sub to the P-type well region PW2. That is, gate structure 610 covers both the N-type and P-type well regions NW1 and PW2, and gate structure 620 covers both the N-type and P-type well regions NW1 and PW2. Each of the gate structures 602, 610, and 620 includes a gate oxide layer and a polysilicon gate layer. The gate oxide layer covers the surface of the semiconductor substrate Sub, and the polysilicon gate layer covers the gate oxide layer.

[0095] Next, a first doping process is performed to form p-doped regions 612, 614, 616, 622, 624, and 626 in the N-type well region NW1. Specifically, p-doped region 612 is located on the first side of gate structure 602, p-doped region 614 is located between the second side of gate structure 602 and the first side of gate structure 610, and p-doped region 616 is located on the second side of gate structure 610. Similarly, p-doped region 622 is located on the first side of gate structure 602, p-doped region 624 is located between the second side of gate structure 602 and the first side of gate structure 620, and p-doped region 626 is located on the second side of gate structure 620.

[0096] Next, a second doping process is performed to form n-doped regions 691 and 692 in the P-type well regions PW1 and PW2. Among them, n-doped region 691 is adjacent to the gate structure 610 extending into the P-type well region PW1, and n-doped region 692 is adjacent to the gate structure 620 extending into the P-type well region PW2.

[0097] Of course, the order of the above-mentioned secondary doping processes can be interchanged. That is, the first doping process can form n-doped regions 691 and 692 in the P-type well regions PW1 and PW2, and the second doping process can form p-doped regions 612, 614, 616, 622, 624, and 626 in the N-type well region NW1.

[0098] like Figure 6C As shown, an interconnect process is performed to form multiple metal lines. The metal line connected to p-doped regions 612 and 622 serves as the source line SL1. The metal line connected to p-doped region 616 serves as the bit line BL1. The metal line connected to p-doped region 626 serves as the anti-phase line BL1'. The metal line connected to gate structure 602 serves as the word line WL1. The metal line connected to n-doped region 691 serves as the erase line EL1. The metal line connected to n-doped region 692 serves as the erase line EL1. Furthermore, the metal lines are connected to the N-type well region NW1, allowing NW1 to receive the well region voltage V. NW1 .

[0099] like Figure 6D As shown, the differential memory cell c11 includes two sub-cells c1 and c1', and the two sub-cells c1 and c1' have the same structure.

[0100] Sub-memory cell c1 includes two transistors M S1 M F1 A capacitor C1 is used. The N-type well region NW1, p-doped region 612, p-doped region 614, and gate structure 602 form a select transistor M. S1 The N-type well region NW1, p-doped region 614, p-doped region 616, and gate structure 610 form a floating gate transistor M. F1 The gate structure 610 and the n-doped region 691 form a capacitor C1. Therefore, the selection transistor M... S1 The first drain / drain terminal is connected to the source line SL1, selecting transistor M. S1 The gate terminal is connected to word line WL1. Floating gate transistor M F1 The first drain / source terminal is connected to the select transistor M. S1 The second drain / source terminal, floating gate transistor M F1 The second drain / source terminal is connected to bit line BL1. The first terminal of capacitor C1 is connected to the floating gate transistor M. F1 The floating gate of the capacitor C1 is connected to the erase line EL1. Furthermore, the select transistor M... S1 With floating gate transistor MF1 The body terminal receives the well voltage V. NW1 .

[0101] Similarly, sub-memory cell c1' includes two transistors M. S2 M F2 A capacitor C2 is used. The N-type well region NW1, p-doped region 622, p-doped region 624, and gate structure 602 form a select transistor M. S2 The N-type well region NW1, p-doped region 624, p-doped region 626, and gate structure 620 form a floating gate transistor M. F2 The gate structure 620 and the n-doped region 692 form capacitor C2. Select transistor M... S2 The first drain / source terminal is connected to the source line SL1, selecting transistor M. S2 The gate terminal is connected to word line WL1. Floating gate transistor M F2 The first drain / source terminal is connected to the select transistor M. S2 The second drain / source terminal, floating gate transistor M F2 The second drain / source terminal is connected to the anti-phase line BL1'. The first terminal of capacitor C2 is connected to the floating gate transistor M. F2 The floating gate of capacitor C2 is connected to the erase line EL1. Furthermore, the selection transistor M... S2 With floating gate transistor M F2 The body extreme receiving well area voltage V NW1 .

[0102] basically, Figure 6D Differential memory cell c11 and Figure 1D The differential memory cell c11 in the third embodiment has the same internal connection relationship. Therefore, the bias voltage for programming (PGM), reading (READ), and erasing (RES) operations on the differential memory cell c11 in the third embodiment is the same as that in the first embodiment, and will not be repeated here.

[0103] Although the differential memory cells of the first embodiment and the differential memory cells of the third embodiment have the same internal connection relationship, the array junctions formed by the differential memory cells of the first embodiment and the array structures formed by the differential memory cells of the third embodiment will have different connection relationships.

[0104] Please refer to Figure 7A and Figure 7BThe diagram shows a top view of the array structure of the MTP non-volatile memory of the present invention, as well as the equivalent circuit of the array structure. The MTP non-volatile memory includes four differential memory cells c11 to c22, forming a 2x2 array structure. Of course, the MTP non-volatile memory of the present invention is not limited to a 2x2 array structure; it can also form an mxn array structure, where m and n are positive integers.

[0105] like Figure 7A As shown, two N-well regions NW1 and NW2, and six P-well regions PW1 to PW6 are formed below the surface of the semiconductor substrate Sub. The two N-well regions NW1 and NW2 are separated from each other. Furthermore, the semiconductor substrate Sub can be a P-type semiconductor substrate.

[0106] Next, multiple gate structures 702, 704, 710, 720, 730, 740, 750, 760, 770, and 780 are formed. Gate structures 702 and 704 cover the Sub surface of the semiconductor substrate and two N-type well regions NW1 and NW2. Gate structure 710 covers the N-type well region NW1 and the P-type well region PW1. Gate structure 720 covers the N-type well region NW1 and the P-type well region PW2. Gate structure 730 covers the N-type well region NW2 and the P-type well region PW2. Gate structure 740 covers the N-type well region NW2 and the P-type well region PW3. Gate structure 750 covers the N-type well region NW1 and the P-type well region PW4. Gate structure 760 covers the N-type well region NW1 and the P-type well region PW5. Gate structure 770 covers the N-type well region NW2 and the P-type well region PW5. The gate structure 780 covers the N-type well region NW2 and the P-type well region PW6.

[0107] Next, a first doping process is performed to form p-doped regions 712, 714, 716, 722, 724, 726, 754, 756, 764, and 766 in the N-type well region NW1; and p-doped regions 732, 734, 736, 742, 744, 746, 774, 776, 784, and 786 in the N-type well region NW2. Taking p-doped regions 712, 714, and 716 as examples, p-doped region 712 is located between the first side of gate structure 702 and the first side of gate structure 704, p-doped region 714 is located between the second side of gate structure 702 and the first side of gate structure 710, and p-doped region 716 is located on the second side of gate structure 710.

[0108] Furthermore, a second doping process is performed to form n-doped regions 791 to 796 in the P-type well regions PW1 to PW6. n-doped region 791 is adjacent to the gate structure 710 extending into the P-type well region PW1. n-doped region 792 is adjacent to the gate structures 720 and 730 extending into the P-type well region PW2. n-doped region 793 is adjacent to the gate structure 740 extending into the P-type well region PW3. n-doped region 794 is adjacent to the gate structure 750 extending into the P-type well region PW4. n-doped region 795 is adjacent to the gate structures 760 and 770 extending into the P-type well region PW5. n-doped region 796 is adjacent to the gate structure 780 extending into the P-type well region PW6.

[0109] Furthermore, an interconnect process is performed to form multiple metal contact lines SL1, SL2, WL1, WL2, BL1, BL1', BL2, BL2', EL1, and EL2. Among them, source line SL1 connects to p-doped regions 712 and 722, and source line SL2 connects to p-doped regions 732 and 742. Bit line BL1 connects to p-doped regions 716 and 756. Anti-phase line BL1' connects to p-doped regions 726 and 766. Bit line BL2 connects to p-doped regions 736 and 776. Anti-phase line BL2' connects to p-doped regions 746 and 786. Word line WL1 connects to gate structure 702. Word line WL2 connects to gate structure 704. Erase line EL1 connects to n-doped regions 791-793. Erase line EL2 connects to n-doped regions 294-796. Well voltage V... NW1 Provided to N-type well area NW1. Well area voltage V NW2 Provided to N-type well area NW2.

[0110] like Figure 7B As shown, four differential memory cells c11 to c22 form a 2x2 array structure. The equivalent circuits of each differential memory cell c11 to c12 are identical to... Figure 6D The internal connections will not be elaborated here. Furthermore, differential memory cell c11 includes two sub-memory cells c1 and c1', differential memory cell c12 includes two sub-memory cells c2 and c2', differential memory cell c21 includes two sub-memory cells c3 and c3', and differential memory cell c22 includes two sub-memory cells c4 and c4'.

[0111] According to an embodiment of the present invention, in the array structure, the transistors of the differential memory cells in the same row are designed in different well regions. In the two differential memory cells c11 and c12 of the first row, the selection transistor M of differential memory cell c11... S1 M S2 and floating gate transistor M F1 M F2Designed in an N-type well region NW1. The selection transistor M for differential memory cell c12. S3 M S4 and floating gate transistor M F3 M F4 The design is in the N-type well region NW2. That is, in the differential memory cell c11 of the first row, transistor M is selected. S1 M S2 and floating gate transistor M F1 M F2 The body terminal receives the well voltage V. NW1 In the differential memory cell c12 of the first row, select transistor M. S3 M S4 and floating gate transistor M F3 M F4 The body terminal receives the well voltage V. NW2 .

[0112] Similarly, in the two differential memory cells c21 and c22 in the second row, the selection transistor M of differential memory cell c21... S5 M S6 and floating gate transistor M F5 M F6 Designed in an N-type well region NW1. The selection transistor M for differential memory cell c22. S7 M S8 and floating gate transistor M F7 M F8 The design is in the N-type well region NW2. That is, in the differential memory cell c21 of the second row, transistor M is selected. S5 M S6 and floating gate transistor M F5 M F6 The body terminal receives the well voltage V. NW1 In the differential memory cell c22 in the second row, select transistor M. S7 M S8 and floating gate transistor M F7 M F8 The body terminal receives the well voltage V. NW2 .

[0113] Furthermore, source line SL1 is connected to differential memory cells c11 and c21, and source line SL2 is connected to differential memory cells c12 and c22. That is, source line SL1 is connected to the select transistor M. S1 M S2 M S5 MS6 The first drain / source terminal, source line SL2 is connected to the select transistor M. S3 M S4 M S7 M S8 The first drain / source.

[0114] Word line WL1 is connected to two differential memory cells c11 and c12 in the same row. That is, word line WL1 is connected to the select transistor M. S1 M S2 M S3 M S4 The gate terminal of the [transistor name]. Word line WL2 is connected to two differential memory cells c21 and c22 in the same row. That is, word line WL2 is connected to the select transistor M. S5 M S6 M S7 M S8 The gate terminal.

[0115] Bit line BL1 and anti-phase line BL1' are connected to two differential memory cells c11 and c21 in the same column. That is, bit line BL1 is connected to the floating gate transistor M. F1 M F5 The second drain / source terminal. The anti-phase line BL1' is connected to the floating gate transistor M. F2 M F6 The second drain / source terminal. Bit line BL2 and anti-phase line BL2' are connected to two differential memory cells c12 and c22 in the same column. That is, bit line BL2 is connected to the floating gate transistor M. F3 M F7 The second drain / source terminal. The anti-phase line BL2' is connected to the floating gate transistor M. F4 M F8 The second drain / source.

[0116] Erase line EL1 is connected to two differential memory cells c11 and c12 in the same row. That is, erase line EL1 is connected to the second terminals of capacitors C1, C2, C3, and C4. Erase line EL2 is connected to two differential memory cells c21 and c22 in the same row. That is, erase line EL2 is connected to the second terminals of capacitors C5, C6, C7, and C8.

[0117] Please refer to Figure 8A The diagram illustrates the bias table for various operations of the array structure of this invention. Basically, during programming (PGM) and reading (READ) operations, Figure 8B The bias and operating principle of the array structure are similar to Figure 4B and Figure 4C This will not be elaborated upon here.

[0118] Please refer to Figure 8B The diagram illustrates the bias voltage during an erase operation on the array structure. During the erase operation (ERS), source line SL1 receives ground voltage (0V), source line SL2 receives programming voltage Vpp, word line WL1 receives ground voltage (0V) or programming voltage Vpp, word line WL2 receives programming voltage (Vpp), bit line BL1 receives ground voltage (0V), anti-phase line BL1' receives ground voltage (0V), bit line BL2 receives programming voltage Vpp, anti-phase line BL2' receives programming voltage Vpp, erase line EL1 receives erase voltage (Vee), erase line EL2 receives ground voltage (0V), and the well voltage V... NW1 Grounding voltage (0V), well area voltage V NW2 The programming voltage is Vpp.

[0119] In the array structure, since erase line EL1 receives the erase voltage Vee, the first row connected to erase line EL1 is the selected row. Furthermore, since erase line EL2 receives the ground voltage (0V), the second row connected to erase line EL2 is the non-selected row.

[0120] In the differential memory cell c21 of the unselected row, erase line EL2 and floating gate transistor M F5 M F6 The body extreme (i.e., the well voltage V) NW1 The voltage difference between them is 0V, so the FN electron tunneling exit effect cannot occur. Additionally, in the differential memory cell c22 of the unselected row, the erase line EL2 and the floating gate transistor M... F7 M F8 The body extreme (i.e., the well voltage V) NW2 The voltage difference between them is equal to (0-Vpp), so the FN electron tunneling exit effect cannot occur. In other words, the differential memory cells c21 and c22 of the non-selected rows are erased.

[0121] In the differential memory cell c12 of the selected row, erase line EL1 and floating gate transistor M F3 M F4 The body extreme (i.e., the well voltage V) NW2 The voltage difference between them is equal to (Vee-Vpp), so the FN electron tunneling exit effect cannot occur.

[0122] Additionally, in the differential memory cell c11 of the selected row, erase line EL1 and floating gate transistor M F1 M F2 The body extreme (i.e., the well voltage V)NW1 The voltage difference between the two is equal to Vee (Vee-0V), so the differential memory cell c11 is the selected memory cell, and the selected memory cell undergoes the FN electron tunneling exit effect, which erases the stored data in the selected memory cell.

[0123] According to an embodiment of the present invention, during an erase operation (ERS), the MTP non-volatile memory does not erase data in all differential memory cells of the selected row. The MTP non-volatile memory erases data only in a single selected memory cell of the selected row.

[0124] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A differential memory cell array structure, comprising: a first differential memory cell and a second differential memory cell, and the first differential memory cell comprises: a first select transistor having a first drain / source terminal connected to a first source line, a gate terminal connected to a first word line, and a body terminal receiving a first well voltage; a first floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the first select transistor, a second drain / source terminal coupled to a first bit line, and a body terminal receiving the first well voltage; a first capacitor having a first terminal connected to a floating gate of the first floating gate transistor and a second terminal connected to a first erase line; a second select transistor having a first drain / source terminal connected to the first source line, a gate terminal connected to the first word line, and a body terminal receiving the first well voltage; a second floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the second select transistor, a second drain / source terminal coupled to a first inverted bit line, and a body terminal receiving the first well voltage; and a second capacitor having a first terminal connected to a floating gate of the second floating gate transistor and a second terminal connected to the first erase line; wherein the second differential memory cell comprises: a third select transistor having a first drain / source terminal connected to the first source line, a gate terminal connected to the first word line, and a body terminal receiving the first well voltage; a third floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the third select transistor, a second drain / source terminal coupled to a second bit line, and a body terminal receiving the first well voltage; a third capacitor having a first terminal connected to a floating gate of the third floating gate transistor and a second terminal connected to a second erase line; a fourth select transistor having a first drain / source terminal connected to the first source line, a gate terminal connected to the first word line, and a body terminal receiving the first well voltage; a fourth floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the fourth select transistor, a second drain / source terminal coupled to a second inverted bit line, and a body terminal receiving the first well voltage; and a fourth capacitor having a first terminal connected to a floating gate of the fourth floating gate transistor and a second terminal connected to the second erase line.

2. The differential memory cell array structure of claim 1, wherein the array structure further comprises a third differential memory cell, and the third differential memory cell comprises: a fifth select transistor having a first drain / source terminal coupled to the first source line, a gate terminal coupled to a second word line, and a body terminal receiving a second well voltage; a fifth floating gate transistor having a first drain / source terminal coupled to a second drain / source terminal of the fifth select transistor, a second drain / source terminal coupled to the first bit line, and a body terminal receiving the second well voltage; a fifth capacitor having a first terminal coupled to a floating gate of the fifth floating gate transistor and a second terminal coupled to the first erase line; a sixth select transistor having a first drain / source terminal coupled to the first source line, a gate terminal coupled to the second word line, and a body terminal receiving the second well voltage; a sixth floating gate transistor having a first drain / source terminal coupled to a second drain / source terminal of the sixth select transistor, a second drain / source terminal coupled to the first antiphase line, and a body terminal receiving the second well voltage; and a sixth capacitor having a first terminal coupled to a floating gate of the sixth floating gate transistor and a second terminal coupled to the first erase line.

3. The differential memory cell array structure of claim 2, wherein the array structure further comprises a fourth differential memory cell, and the fourth differential memory cell comprises: a seventh select transistor having a first drain / source terminal coupled to the first source line, a gate terminal coupled to the second word line, and a body terminal receiving the second well voltage; a seventh floating gate transistor having a first drain / source terminal coupled to a second drain / source terminal of the seventh select transistor, a second drain / source terminal coupled to the second bit line, and a body terminal receiving the second well voltage; a seventh capacitor having a first terminal coupled to a floating gate of the seventh floating gate transistor and a second terminal coupled to the second erase line; an eighth select transistor having a first drain / source terminal coupled to the first source line, a gate terminal coupled to the second word line, and a body terminal receiving the second well voltage; an eighth floating gate transistor having a first drain / source terminal coupled to a second drain / source terminal of the eighth select transistor, a second drain / source terminal coupled to the second antiphase line, and a body terminal receiving the second well voltage; and an eighth capacitor having a first terminal coupled to a floating gate of the eighth floating gate transistor and a second terminal coupled to the second erase line.

4. The differential memory cell array structure of claim 3, wherein during a program operation, the first well voltage is equal to a program voltage, the second well voltage is equal to the program voltage, the first source line receives the program voltage, the first word line receives half of the program voltage, the second word line receives the program voltage, the first erase line receives half of the program voltage, the second erase line receives a ground voltage, the first bit line receives the ground voltage, the first complement bit line is floating, the second bit line is floating, the second complement bit line is floating, and the first differential memory cell is programmed to a first storage state.

5. The differential memory cell array structure of claim 3, wherein during a read operation, the first well voltage is equal to a read voltage, the second well voltage is equal to the read voltage, the first source line receives the read voltage, the first word line receives an open voltage, the second word line receives a closed voltage, the first erase line receives a ground voltage, the second erase line receives the ground voltage, the first bit line receives the ground voltage, the first complement bit line receives the ground voltage, the second bit line is floating, the second complement bit line is floating, the first differential memory cell generates a first read current to the first bit line, the first differential memory cell generates a second read current to the first complement bit line, and a storage state of the first differential memory cell is determined based on a magnitude of the first read current and the second read current.

6. The differential memory cell array structure of claim 3, wherein during an erase operation, the first well voltage is equal to a ground voltage, the second well voltage is equal to a program voltage, the first source line receives the ground voltage, the first word line receives the ground voltage, the second word line receives the program voltage, the first erase line receives an erase voltage, the second erase line receives the ground voltage, the first bit line receives the ground voltage, the first complement bit line receives the ground voltage, the second bit line is floating, the second complement bit line is floating, and stored data in the first differential memory cell is erased.

7. A differential memory cell array structure, comprising: a first differential memory cell, and the first differential memory cell comprises: a first select transistor having a first drain / source terminal connected to a first source line, a gate terminal connected to a first word line, and a body terminal receiving a first well voltage; a first floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the first select transistor, a second drain / source terminal coupled to a first bit line, and a body terminal receiving the first well voltage; a first capacitor having a first terminal connected to a floating gate of the first floating gate transistor and a second terminal connected to a first erase line; a second select transistor having a first drain / source terminal connected to the first source line, a gate terminal connected to the first word line, and a body terminal receiving the first well voltage; and a second floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the second select transistor, a second drain / source terminal coupled to a second bit line, and a body terminal receiving the first well voltage. a second floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the second select transistor, a second drain / source terminal coupled to a first anti-phase line, and a body terminal receiving the first well voltage; and a second capacitor having a first terminal connected to a floating gate of the second floating gate transistor and a second terminal connected to the first erase line; wherein the array structure comprises: a semiconductor substrate; a first N-type well formed on a surface of the semiconductor substrate; a first P-type well formed on the surface of the semiconductor substrate; a first gate structure overlying the first N-type well; a second gate structure overlying the first N-type well and the first P-type well; a third gate structure overlying the first N-type well and the first P-type well; a first p-doped region in the first N-type well, on a first side of the first gate structure; a second p-doped region in the first N-type well, between a second side of the first gate structure and a first side of the second gate structure; a third p-doped region in the first N-type well, on a second side of the second gate structure; a fourth p-doped region in the first N-type well, on the first side of the first gate structure; a fifth p-doped region in the first N-type well, between the second side of the first gate structure and a first side of the third gate structure; a sixth p-doped region in the first N-type well, on a second side of the third gate structure; and a first n-doped region in the first P-type well; wherein the first n-doped region is adjacent to the second gate structure extending to the first P-type well, and the first n-doped region is adjacent to the third gate structure extending to the first P-type well; wherein the first N-type well, the first p-doped region, the second p-doped region, the first gate structure form the first select transistor; the first N-type well, the second p-doped region, the third p-doped region, the second gate structure form the first floating gate transistor; the second gate structure and the first n-doped region form the first capacitor; the first N-type well, the fourth p-doped region, the fifth p-doped region, the first gate structure form the second select transistor; the first N-type well, the fifth p-doped region, the sixth p-doped region, the third gate structure form the second floating gate transistor; the third gate structure and the first n-doped region form the second capacitor.

8. A differential memory cell array structure, comprising: a first differential memory cell, and the first differential memory cell comprises: a first select transistor having a first drain / source terminal connected to a first source line, a gate terminal connected to a first word line, and a body terminal receiving a first well voltage; a first floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the first select transistor, a second drain / source terminal coupled to a first bit line, and a body terminal receiving the first well voltage; and a second floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the second select transistor, a second drain / source terminal coupled to a first anti-phase line, and a body terminal receiving the first well voltage; and a second capacitor having a first terminal connected to a floating gate of the second floating gate transistor and a second terminal connected to the first erase line; wherein the array structure comprises: a semiconductor substrate; a first N-type well formed on a surface of the semiconductor substrate; a first P-type well formed on the surface of the semiconductor substrate; a first gate structure overlying the first N-type well; a second gate structure overlying the first N-type well and the first P-type well; a third gate structure overlying the first N-type well and the first P-type well; a first p-doped region in the first N-type well, on a first side of the first gate structure; a second p-doped region in the first N-type well, between a second side of the first gate structure and a first side of the second gate structure; a third p-doped region in the first N-type well, on a second side of the second gate structure; a fourth p-doped region in the first N-type well, on the first side of the first gate structure; a fifth p-doped region in the first N-type well, between the second side of the first gate structure and a first side of the third gate structure; a sixth p-doped region in the first N-type well, on a second side of the third gate structure; and a first n-doped region in the first P-type well; wherein the first n-doped region is adjacent to the second gate structure extending to the first P-type well, and the first n-doped region is adjacent to the third gate structure extending to the first P-type well; wherein the first N-type well, the first p-doped region, the second p-doped region, the first gate structure form the first select transistor; the first N-type well, the second p-doped region, the third p-doped region, the second gate structure form the first floating gate transistor; the second gate structure and the first n-doped region form the first capacitor; the first N-type well, the fourth p-doped region, the fifth p-doped region, the first gate structure form the second select transistor; the first N-type well, the fifth p-doped region, the sixth p-doped region, the third gate structure form the second floating gate transistor; the third gate structure and the first n-doped region form the second capacitor. a first capacitor having a first end connected to a floating gate of the first floating gate transistor and a second end connected to a first erase line; a second select transistor having a first drain / source end connected to the first source line, a gate end connected to the first word line, and a body end receiving the first well voltage; a second floating gate transistor having a first drain / source end connected to a second drain / source end of the second select transistor, a second drain / source end coupled to a first anti-phase line, and a body end receiving the first well voltage; and a second capacitor having a first end connected to a floating gate of the second floating gate transistor and a second end connected to the first erase line. wherein the first differential memory cell comprises: first and second coupling elements, the first coupling element having a first end connected to the second drain / source end of the first floating gate transistor, a second end connected to the first bit line, and a third end connected to a ground, the second coupling element having a first end connected to the second drain / source end of the second floating gate transistor, a second end connected to the first anti-phase line, and a third end connected to the ground.

9. The differential memory cell array structure of claim 8, further comprising a second differential memory cell comprising: a third select transistor having a first drain / source end connected to the first source line, a gate end connected to a second word line, and a body end receiving a second well voltage; a third floating gate transistor having a first drain / source end connected to a second drain / source end of the third select transistor and a body end receiving the second well voltage; a third coupling element having a first end connected to the second drain / source end of the third floating gate transistor, a second end connected to the first bit line, and a third end connected to the ground; a third capacitor having a first end connected to a floating gate of the third floating gate transistor and a second end connected to the first erase line; a fourth select transistor having a first drain / source end connected to the first source line, a gate end connected to the second word line, and a body end receiving the second well voltage; a fourth floating gate transistor having a first drain / source end connected to a second drain / source end of the fourth select transistor and a body end receiving the second well voltage; a fourth coupling element having a first end connected to the second drain / source end of the fourth floating gate transistor, a second end connected to the first anti-phase line, and a third end connected to the ground; and a fourth capacitor having a first end connected to a floating gate of the fourth floating gate transistor and a second end connected to the first erase line. a fourth capacitor having a first end connected to a floating gate of the fourth floating gate transistor and a second end connected to the first erase line.

10. The differential memory cell array structure of claim 9, wherein during a program operation and a read operation, the first end and the second end of the first coupling element are connected, the first end and the second end of the second coupling element are connected, the first end and the second end of the third coupling element are connected, and the first end and the second end of the fourth coupling element are connected.

11. The differential memory cell array structure of claim 9, wherein during an erase operation and when the first word line is active, the first end and the third end of the first coupling element are connected, the first end and the third end of the second coupling element are connected, the first end and the second end of the third coupling element are connected, and the first end and the second end of the fourth coupling element are connected.

12. A differential memory cell array structure, comprising: a first differential memory cell and a second differential memory cell, and the first differential memory cell comprises: a first select transistor having a first drain / source end connected to a first source line, a gate end connected to a first word line, and a body end receiving a first well voltage; a first floating gate transistor having a first drain / source end connected to a second drain / source end of the first select transistor, a second drain / source end coupled to a first bit line, and a body end receiving the first well voltage; a first capacitor having a first end connected to a floating gate of the first floating gate transistor and a second end connected to a first erase line; a second select transistor having a first drain / source end connected to the first source line, a gate end connected to the first word line, and a body end receiving the first well voltage; a second floating gate transistor having a first drain / source end connected to a second drain / source end of the second select transistor, a second drain / source end coupled to a first inverted bit line, and a body end receiving the first well voltage; and a second capacitor having a first end connected to a floating gate of the second floating gate transistor and a second end connected to the first erase line; wherein the second differential memory cell comprises: a third select transistor having a first drain / source end connected to a second source line, a gate end connected to the first word line, and a body end receiving a second well voltage; a third floating gate transistor having a first drain / source end connected to a second drain / source end of the third select transistor, a second drain / source end coupled to a second bit line, and a body end receiving the second well voltage; a third capacitor having a first end connected to a floating gate of the third floating gate transistor and a second end connected to the first erase line; a fourth select transistor having a first drain / source terminal coupled to the second source line, a gate terminal coupled to the first word line, and a body terminal receiving the second well voltage; a fourth floating gate transistor having a first drain / source terminal coupled to a second drain / source terminal of the fourth select transistor, a second drain / source terminal coupled to a second anti-phase line, and a body terminal receiving the second well voltage; and a fourth capacitor having a first terminal coupled to a floating gate of the fourth floating gate transistor and a second terminal coupled to the first erase line.

13. The differential memory cell array structure of claim 12, wherein the array structure further comprises a third differential memory cell, and the third differential memory cell comprises: a fifth select transistor having a first drain / source terminal coupled to the first source line, a gate terminal coupled to a second word line, and a body terminal receiving the first well voltage; a fifth floating gate transistor having a first drain / source terminal coupled to a second drain / source terminal of the fifth select transistor, a second drain / source terminal coupled to the first bit line, and a body terminal receiving the first well voltage; a fifth capacitor having a first terminal coupled to a floating gate of the fifth floating gate transistor and a second terminal coupled to a second erase line; a sixth select transistor having a first drain / source terminal coupled to the first source line, a gate terminal coupled to the second word line, and a body terminal receiving the first well voltage; a sixth floating gate transistor having a first drain / source terminal coupled to a second drain / source terminal of the sixth select transistor, a second drain / source terminal coupled to the first anti-phase line, and a body terminal receiving the first well voltage; and a sixth capacitor having a first terminal coupled to a floating gate of the sixth floating gate transistor and a second terminal coupled to the second erase line.

14. The differential memory cell array structure of claim 13, wherein the array structure further comprises a fourth differential memory cell, and the fourth differential memory cell comprises: a seventh select transistor having a first drain / source terminal coupled to the second source line, a gate terminal coupled to the second word line, and a body terminal receiving the second well voltage; a seventh floating gate transistor having a first drain / source terminal coupled to a second drain / source terminal of the seventh select transistor, a second drain / source terminal coupled to the second bit line, and a body terminal receiving the second well voltage; a seventh capacitor having a first terminal coupled to a floating gate of the seventh floating gate transistor and a second terminal coupled to the second erase line. a seventh capacitor having a first end connected to a floating gate of the seventh floating gate transistor and a second end connected to the second erase line; an eighth select transistor having a first drain / source end connected to the second source line, a gate end connected to the second word line, and a body end receiving the second well voltage; an eighth floating gate transistor having a first drain / source end connected to a second drain / source end of the eighth select transistor, a second drain / source end coupled to the second anti-phase line, and a body end receiving the second well voltage; and an eighth capacitor having a first end connected to a floating gate of the eighth floating gate transistor and a second end connected to the second erase line.

15. The differential memory cell array structure of claim 14, wherein during a program operation, the first well voltage equals a program voltage, the second well voltage equals the program voltage, the first source line receives the program voltage, the second source line receives the program voltage, the first word line receives one-half of the program voltage, the second word line receives the program voltage, the first erase line receives one-half of the program voltage, the second erase line receives a ground voltage, the first bit line receives the ground voltage, the first anti-phase line is floating, the second bit line is floating, the second anti-phase line is floating, and the first differential memory cell is programmed to a first storage state.

16. The differential memory cell array structure of claim 14, wherein during a read operation, the first well voltage equals a read voltage, the second well voltage equals the read voltage, the first source line receives the read voltage, the second source line receives the read voltage, the first word line receives an on voltage, the second word line receives an off voltage, the first erase line receives a ground voltage, the second erase line receives the ground voltage, the first bit line receives the ground voltage, the first anti-phase line receives the ground voltage, the second bit line is floating, the second anti-phase line is floating, the first differential memory cell generates a first read current to the first bit line, the first differential memory cell generates a second read current to the first anti-phase line, and a storage state of the first differential memory cell is determined based on a magnitude of the first read current and the second read current.

17. The differential memory cell array structure of claim 14, wherein during an erase operation, the first well voltage equals a ground voltage, the second well voltage equals a program voltage, the first source line receives the ground voltage, the second source line receives the program voltage, the first word line receives the ground voltage or the program voltage, the second word line receives the program voltage, the first erase line receives an erase voltage, the second erase line receives the ground voltage, the first bit line receives the ground voltage, the first anti-phase line receives the ground voltage, the second bit line receives the program voltage, the second anti-phase line receives the program voltage, and stored data in the first differential memory cell is erased.

18. A differential memory cell array structure, comprising: A first differential memory cell, and the first differential memory cell includes: a first select transistor having a first drain / source terminal connected to a first source line, a gate terminal connected to a first word line, and a body terminal receiving a first well voltage; a first floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the first select transistor, a second drain / source terminal coupled to a first bit line, and a body terminal receiving the first well voltage; a first capacitor having a first terminal connected to a floating gate of the first floating gate transistor and a second terminal connected to a first erase line; a second select transistor having a first drain / source terminal connected to the first source line, a gate terminal connected to the first word line, and a body terminal receiving the first well voltage; a second floating gate transistor having a first drain / source terminal connected to a second drain / source terminal of the second select transistor, a second drain / source terminal coupled to a first inverted bit line, and a body terminal receiving the first well voltage; and a second capacitor having a first terminal connected to a floating gate of the second floating gate transistor and a second terminal connected to the first erase line; wherein the array structure includes: a semiconductor substrate; a first N-type well formed at a surface of the semiconductor substrate; a first P-type well formed at the surface of the semiconductor substrate; a second P-type well formed at the surface of the semiconductor substrate; a first gate structure overlying the first N-type well; a second gate structure overlying the first N-type well and the first P-type well; a third gate structure overlying the first N-type well and the second P-type well; a first p-doped region in the first N-type well, on a first side of the first gate structure; a second p-doped region in the first N-type well, between a second side of the first gate structure and a first side of the second gate structure; a third p-doped region in the first N-type well, on a second side of the second gate structure; a fourth p-doped region in the first N-type well, on the first side of the first gate structure; a fifth p-doped region in the first N-type well, between the second side of the first gate structure and a first side of the third gate structure; a sixth p-doped region in the first N-type well, on a second side of the third gate structure; a first n-doped region in the first P-type well; and a second n-doped region in the second P-type well; wherein the first n-doped region is adjacent to the second gate structure extending to the first P-type well, and the second n-doped region is adjacent to the third gate structure extending to the second P-type well; The first N-type well region, the first p-doped region, the second p-doped region, and the first gate structure form the first select transistor; the first N-type well region, the second p-doped region, the third p-doped region, and the second gate structure form the first floating gate transistor; the second gate structure and the first n-doped region form the first capacitor; the first N-type well region, the fourth p-doped region, the fifth p-doped region, and the first gate structure form the second select transistor; the first N-type well region, the fifth p-doped region, the sixth p-doped region, and the third gate structure form the second floating gate transistor; and the third gate structure and the second n-doped region form the second capacitor.

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