Nanoporous units with seamless working electrodes and their formation methods

Abstract

This invention relates to a nanoporous unit that may include a trap having a seamless porous electrode and hydrophobic sidewalls. The seamless porous electrode can be formed by depositing a porous electrode material on a planar electrode support layer formed of conductive islands and a dielectric layer. The porous electrode material can be formed into uniform seamless pillars and can be protected during manufacturing by depositing a selectively removable protective layer on the seamless pillars. The trap can be formed by forming a hydrophobic cladding over the protective layer and subsequently patterning the hydrophobic cladding. The protective layer can be removed to expose the seamless porous electrode at the bottom of the trap.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 029,936, filed May 26, 2020, the full text of which is incorporated herein by reference.

[0003] Incorporate by reference

[0004] All publications and patent applications mentioned in this specification are incorporated herein by reference to the extent that each individual publication or patent application is specifically and individually indicated to be incorporated herein by reference. Background Technology

[0005] Nanoporous membrane devices with pore sizes on the order of one nanometer have shown promise in rapid nucleotide sequencing. When a voltage potential is applied to a nanopore immersed in a conductive fluid, a small ionic current may be generated due to the conduction of ions across the nanopore. The magnitude of the current is sensitive to the pore size and which molecule is located in the nanopore. The molecule can be the nucleotide itself (e.g., as part of a nucleic acid) or a specific tag attached to a particular nucleotide, allowing the detection of nucleotides at specific locations within the nucleic acid. The voltage in a circuit containing the nanopore (e.g., across an integrated capacitor) can be measured as a way of measuring the resistance of molecules, thus enabling the detection of which molecules are in the nanopore.

[0006] Despite the success of nanopore-based sequencing sensor chips in some applications, improvements are still needed. For example, improved trap structures and methods for nanopores are required. In some cases, it has been found that the working electrodes of nanopore-based sequencing sensor chips are preferably made of porous electrode materials to maximize capacitance and surface area. Since reliable porous working electrodes with desired properties (such as wettability and sufficient capacitance) are crucial for the operation of nanopore-based sequencing devices, methods for protecting the working electrodes during fabrication have been implemented. In particular, the working electrodes must be protected when depositing a hydrophobic cladding and patterning it to form the trap of the nanopore unit. Some methods for protecting the porous working electrodes include applying a protective layer (such as a dielectric layer) to act as a buffer or sacrificial layer to protect the porous working electrodes during subsequent steps. In many cases, it is desirable to easily remove the protective layer by a chemical process to expose the porous working electrode for operation. However, if this is not taken into account in the structure and process of forming the porous electrode and nanopore unit, the chemicals used to remove the protective layer may corrode other layers. Summary of the Invention

[0007] Therefore, nanoporous units and methods for forming nanoporous units are described according to embodiments of this disclosure. The nanoporous units and methods for forming nanoporous units ensure that the working electrode is structurally sound, such that chemical removal of the protective layer does not negatively impact other components of the nanoporous unit. In particular, the nanoporous units and methods for forming nanoporous units ensure that the working electrode is formed from seamless pillars of porous material, which reduces the possibility of chemicals penetrating and damaging other layers of the nanoporous unit.

[0008] The embodiments relate to a method for forming nanoporous units. The method may include providing a device structure including a conductive layer disposed on a top portion of a substrate and an interconnect dielectric layer covering the conductive layer. The method includes removing a portion of the interconnect dielectric layer to form a planar electrode support surface. The planar electrode support surface includes exposed islands of the conductive layer surrounded by the remainder of the interconnect dielectric layer. The method further includes depositing porous electrode material on the planar electrode support surface to form a seamless porous electrode layer. The seamless porous electrode layer includes pillars of porous electrode material. The method further includes depositing a protective layer on the seamless porous electrode layer, patterning the seamless porous electrode layer and the protective layer to form working electrode islands, depositing a hydrophobic cladding on the working electrode islands and patterning the hydrophobic cladding to form sidewalls of a well of the nanoporous unit, and removing at least a portion of the protective layer to expose the porous electrode layer. The exposed porous electrode layer forms at least a portion of the bottom wall of the well of the nanoporous unit.

[0009] Some embodiments may include a nanoporous unit. The nanoporous unit may include a substrate, an electrode support layer covering a top portion of the substrate, and a trap. The electrode support layer may include a conductive layer island surrounded by an interconnect dielectric layer and a planar top surface formed by the conductive layer island and the interconnect dielectric layer. The trap may include a seamless porous working electrode island disposed on the planar top surface of the electrode support layer, a hydrophobic cladding surrounding the seamless porous working electrode island and patterned to form the sidewalls of the trap, and a cavity formed by the hydrophobic cladding and the seamless porous working electrode island. The seamless porous working electrode island may include pillars of porous electrode material. In some embodiments, the seamless working electrode island further includes a protective layer disposed on the pillars of porous electrode material, wherein the protective layer is configured to be selectively removed to expose the porous electrode material to the cavity.

[0010] The nature and advantages of the embodiments of the present invention can be better understood by referring to the following detailed description and accompanying drawings. Attached Figure Description

[0011] Figure 1 This describes the implementation scheme of the unit in a nanopore-based sequencing chip.

[0012] Figure 2This describes the implementation scheme for a unit used in nucleotide sequencing with Nano-SBS technology.

[0013] Figure 3 An embodiment of the electrochemical unit of a nanopore-based sequencing chip is described, which includes a TiN working electrode with increased electrochemical capacitance.

[0014] Figure 4 An embodiment of the circuitry in a cell of a nanopore-based sequencing chip is illustrated, wherein the voltage applied across the nanopore can be configured to vary during a time period in which the nanopore is in a specific detectable state.

[0015] Figure 5 This illustrates the bilayer that forms at any interface between the conductive electrode and the adjacent liquid electrolyte.

[0016] Figure 6 This demonstrates that a pseudocapacitive effect can be formed at the interface between the conductive electrode and the adjacent liquid electrolyte while a bilayer is being formed.

[0017] Figures 7A-7G An implementation scheme for constructing an electrochemical unit of a nanopore-based sequencing chip including a TiN working electrode using chemimechanical planarization is described.

[0018] Figures 8A-8F An implementation scheme for constructing an electrochemical unit of a nanopore-based sequencing chip, including a TiN working electrode, using photolithography and dry etching is described.

[0019] Figure 9 This indicates that it may be used Figures 7A-7G and Figures 8A-8F The seam formed in the working electrode constructed by the process shown.

[0020] Figure 10 This is an instruction on how to use. Figures 7A-7G Micrograph of the TiN electrode layer formed by the process shown.

[0021] Figure 11 This is an instruction on how to use. Figures 8A-8F Micrograph of the TiN electrode layer formed by the process shown.

[0022] Figures 12A-12F An implementation scheme for constructing an electrochemical unit of a nanopore-based sequencing chip including a seamless working electrode is described.

[0023] Figure 13 Instructions on using Figures 12A-12F The process shown constructs a seamless electrode.

[0024] Figure 14A and Figure 14BThrough Figures 12A-12F Micrographs of an example of a seamless electrode array formed by the method.

[0025] Figure 14A and Figure 14B Through Figures 12A-12F Micrographs of an example of a seamless electrode array formed by the method.

[0026] Figure 15 Through Figures 12A-12F Micrographs of an example of a seamless TiN electrode layer formed by the method.

[0027] Figure 16 This is a flowchart illustrating a method for forming nanoporous units with seamless electrodes.

[0028] the term

[0029] "Nanopore" refers to a pore, channel, or pathway formed or otherwise provided in a membrane. The membrane can be an organic membrane, such as a lipid bilayer, or a synthetic membrane, such as a membrane formed from a polymeric material. Nanopores can be positioned adjacent to or coupled to electrodes of a sensing circuit, such as, for example, complementary metal-oxide-semiconductor (CMOS) or field-effect transistor (FET) circuits. In some instances, nanopores have characteristic widths or diameters on the order of 0.1 nanometers (nm) to approximately 1000 nm. Some nanopores are proteins.

[0030] In nanoporous devices, a "trap" refers to a structure formed by an insulating wall and a working electrode that may contain an electrolyte. A "trap profile" is a structural description of the trap and may include measurements of the angles and sharpness of the trap's edges. A "unit" of a nanoporous device may, at different stages of operation, include: a trap, a nanopore (e.g., in a diaphragm across the trap), and a working electrode, as well as other circuitry, such as data acquisition circuitry.

[0031] "Dielectric material" refers to an electrically insulator that can be polarized by an applied electric field. When a dielectric is placed in an electric field, charges do not flow through the material as they would in a conductor; instead, they are slightly deflected from their average equilibrium positions, resulting in dielectric polarization. A "conductive layer" is a layer of material that allows current to flow in one or more directions. Metal wires are common electrical conductors.

[0032] "Porous materials" refer to materials that contain pores or voids on their surface. "Sponge-like materials" refer to materials with open, porous structures. Detailed Implementation

[0033] In nanoporous devices, a diaphragm can be formed on top of a well in a dielectric layer. For example, the diaphragm may comprise a lipid monolayer formed on top of the dielectric layer. When the diaphragm reaches the opening of the well, the lipid monolayer can transform into a lipid bilayer across the opening of the well. The structure of the well and the material forming the well can play important roles in the formation of the diaphragm and the insertion of the nanopore into the diaphragm, and the interactions between the materials forming the well also affect the operation of the nanoporous device.

[0034] The following description includes an overview of the structure and operation of the nanoporous unit. The structure of the traps, the materials forming the traps, and the effects of their interactions are also discussed. Problems arising from the interactions between the chemicals used to remove the protective layer and the porous working electrode are also described, along with proposed solutions.

[0035] I. Overview of Nanoporous Units

[0036] This section introduces the operation, structure, and applications of nanoporous units, as well as signal measurement circuitry. The capacitive effect at the working electrode (referred to as double-layer capacitance) is explained, and an example of constructing a porous working electrode is described.

[0037] A. Unit Operations

[0038] Figure 1 This describes one embodiment of a cell 100 forming a cell array of a nanopore-based sequencing chip. A septum 102 is formed on the surface of the cell. In some embodiments, the septum 102 is a lipid bilayer. A host electrolyte 114 containing a protein nanopore transmembrane molecular complex (PNTMC) and an analyte of interest (e.g., a single polymer molecule, such as DNA) can be directly placed onto the surface of the cell. Individual PNTMCs 104 can be inserted into the septum 102 via electroporation. The individual septa in the array are neither chemically nor electrically connected to each other. Therefore, each cell in the array is an independent sequencer, generating data specific to the individual polymer molecule associated with the PNTMC. The PNTMCs 104 can modulate the ion current through other impermeable bilayers.

[0039] Analog measurement circuitry 112 is connected to a working electrode 110 (e.g., made of metal), which is covered by a volume of electrolyte 108 formed within a trap in an oxide layer 106. This volume of electrolyte 108 is isolated from the host electrolyte 114 by an ion-impermeable membrane 102. The PNTMC 104 passes through the membrane 102 and provides the only path for ion current to flow from the host liquid to the working electrode 110. The unit also includes a counter electrode (CE) 116. The unit also includes a reference electrode 117, which can act as an electrochemical potential sensor.

[0040] Figure 2This describes one embodiment of a unit 200 for performing nucleotide sequencing using nanopore-based sequencing via synthesis (Nano-SBS) technology. In Nano-SBS technology, a template 202 to be sequenced and primers are introduced into unit 200. Four nucleotides 208, A, T, G, and C, tagged in different ways, are added to the template-primer complex and added to the host aqueous phase. When the correctly tagged nucleotides are complexed with polymerase 204, the tail of the tag is positioned within the cylinder of the nanopore 206. The tag held within the cylinder of the nanopore 206 generates a unique ion-blocking signal 210, thereby electronically recognizing the added base due to the different chemical structures of the tag.

[0041] B. Unit structure and application

[0042] Figure 3 An embodiment of an electrochemical unit 300 of a nanopore-based sequencing chip, including a working electrode (e.g., TiN with high electrochemical capacitance), is described. Unit 300 includes a conductive layer or metal layer 301. Metal layer 301 connects unit 300 to the remainder of the nanopore-based sequencing chip. In some embodiments, metal layer 301 is the top metal of a CMOS chip (e.g., a metal 6 layer M6 of the bottom circuitry). Unit 300 also includes a working electrode 302 and a dielectric layer 303 above metal layer 301. In some embodiments, working electrode 302 may be circular or octagonal, and dielectric layer 303 forms a wall surrounding working electrode 302. Unit 300 also includes a dielectric layer 304 above working electrode 302 and dielectric layer 303. Dielectric layer 304 forms an insulating wall surrounding well 305.

[0043] In some embodiments, dielectric layer 303 and dielectric layer 304 together form a monolithic dielectric. Dielectric layer 303 is a portion disposed horizontally adjacent to the working electrode 302, and dielectric layer 304 is a portion disposed above and covering a portion of the working electrode. In some embodiments, dielectric layer 303 and dielectric layer 304 are separate dielectric elements, and they may be formed individually. A well 305 has an opening above the uncovered portion of the working electrode. In some embodiments, the opening above the uncovered portion of the working electrode may be circular or octagonal.

[0044] Inside the trap 305, a certain volume of salt solution / electrolyte 306 is deposited above the working electrode 302. The salt solution 306 may include one of the following: lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KCl), lithium glutamate, monosodium glutamate, potassium glutamate, lithium acetate, sodium acetate, potassium acetate, calcium chloride (CaCl2), strontium chloride (SrCl2), manganese chloride (MnCl2), and magnesium chloride (MgCl2). In some embodiments, the salt solution 306 has a thickness of approximately three micrometers (μm). The thickness of the salt solution 306 can range from 0 micrometers to 5 micrometers.

[0045] The dielectric materials used to form dielectric layers 303 and 304 include glass, oxides, silicon nitride (SiN), etc. The top surface of dielectric layer 304 may be silanized. Silanization forms a hydrophobic layer 320 on the top surface of dielectric layer 304. In some embodiments, the hydrophobic layer 320 has a thickness of about 1.5 nanometers (nm). Alternatively, a hydrophobic dielectric material (such as hafnium oxide) may be used to form dielectric layer 304.

[0046] like Figure 3 As shown, a membrane is formed over a dielectric layer 304 and spans a trap 305. For example, this membrane comprises a lipid monolayer 318 formed over a hydrophobic layer 320, and when the membrane reaches the opening of the trap 305, the lipid monolayer transforms into a lipid bilayer 314 spanning the opening of the trap. The hydrophobic layer 320 facilitates the formation of the lipid monolayer 318 over the dielectric layer 304 and the transformation from a lipid monolayer to a lipid bilayer. A host electrolyte 308 containing a protein nanopore transmembrane molecular complex (PNTMC) and the analyte of interest is placed directly above the trap. A single PNTMC / nanopore 316 is inserted into the lipid bilayer 314 via electroporation. The nanopore 316 permeates the lipid bilayer 314 and provides a single pathway for ion flow from the host electrolyte 308 to the working electrode 302. The main electrolyte 308 may also include one of the following: lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KCl), lithium glutamate, monosodium glutamate, potassium glutamate, lithium acetate, sodium acetate, potassium acetate, calcium chloride (CaCb), strontium chloride (SrCb), manganese chloride (MnCb), and magnesium chloride (MgCb).

[0047] Unit 300 includes a counter electrode (CE) 310. Unit 300 also includes a reference electrode 312, which acts as an electrochemical potential sensor. In some embodiments, the counter electrode 300 may be shared among multiple units and is therefore also referred to as a common electrode. The common electrode may be configured to apply a common potential to the host liquid in contact with the nanopores in the measurement unit. The common potential and the common electrode are shared by all measurement units.

[0048] Working electrode 302 is a titanium nitride (TiN) working electrode with increased electrochemical capacitance. The electrochemical capacitance associated with working electrode 302 can be increased by maximizing the specific surface area of ​​the electrode. The specific surface area of ​​working electrode 302 is the total surface area per unit mass (e.g., m²). 2 / kg) or total surface area per unit volume (e.g., m²) 2 / m 3 m 2 / m 3 or m -1 ) or the total surface area per unit base area (e.g., m²) 2 / m 2 As the surface area increases, the electrochemical capacitance of the working electrode increases, and a greater number of ions can be displaced at the same applied potential before the capacitor is charged. The surface area of ​​the working electrode 302 can be increased by making the TiN electrode “sponge-like” or porous. The TiN sponge absorbs the electrolyte and generates a large effective surface area in contact with the electrolyte. Techniques for manufacturing and using TiN are further described in U.S. Patent No. 10,174,371 to Foster et al.

[0049] Other materials that can be used to form the working electrode include ruthenium, as further described in International Patent Publication WO2020043653A2 granted to Au et al.

[0050] The capacitance (C) related to the diaphragm can be adjusted. 隔膜 ) and capacitance associated with the working electrode (C 电化学 The ratio of C can be adjusted to achieve optimal overall system performance. This can be achieved by reducing C. 隔膜 Simultaneously, the diaphragm will carry C 电化学 Maximize to increase system performance. This can be achieved by adjusting C. 隔膜 This allows for the formation of the required RC time constant without the need for additional on-chip capacitors, thereby significantly reducing cell size and chip size.

[0051] In unit 300, the bottom surface area of ​​the well 305 opening (which is the same as the bottom surface area of ​​the lipid bilayer 314) and the bottom surface area of ​​the working electrode 302 are determined by the dimensions of the dielectric layer 304 and the dielectric layer 303, respectively. The bottom surface area of ​​the working electrode 302 is greater than or equal to the bottom surface area of ​​the well 305 opening. Therefore, these two bottom surface areas can be optimized independently to provide the required C 隔膜 and C 电化学 The ratio between them. For example... Figure 3As shown, a portion of the working electrode 302 is covered by the dielectric 304, and therefore the covered portion does not directly contact the salt solution / electrolyte 306. By using a sponge-like porous TiN working electrode, the electrolyte can diffuse through the spaces between the columnar TiN structures and vertically downwards to the uncovered portion of the working electrode, and then horizontally to the covered portion of the working electrode 302 located below the dielectric layer 304. As a result, the effective surface area of ​​the TiN in contact with the electrolyte is maximized, and C 电化学 Maximized.

[0052] C. Signal Measurement Circuit

[0053] Figure 4 An embodiment of circuitry 400 in a cell of a nanopore-based sequencing chip is illustrated, wherein the voltage or current applied across the nanopore can be configured to vary during a time period in which the nanopore is in a specific detectable state. Figure 4 Instead of showing the nanopores inserted in the diaphragm and the liquid surrounding the nanopores, electrical model 402 represents the electrical properties of the nanopores and the diaphragm, and electrical model 414 represents the electrical properties of the working electrode shown.

[0054] Electrical model 402 includes a capacitor 406 and a resistor 404, the capacitor being related to the capacitance (C) of the diaphragm. 隔膜 The model is used to model the resistance of the nanopore in different states (e.g., open channel state or a state corresponding to different types of tags or molecules within the nanopore). The electrical model 414 includes a capacitor 416 that models the capacitance associated with the working electrode. The capacitance associated with the working electrode is also referred to as electrochemical capacitance (C0). 电化学 Electrochemical capacitance C associated with the working electrode. 电化学 It includes double-layer capacitors and may also include pseudocapacitors.

[0055] Figure 4 It also includes a switch 408 coupled to voltage 410, which can be turned on and off for the purpose of measuring resistance 404. In some embodiments, voltage 410 is applied to an electrical model 402 representing a nanopore. After capacitor 406 is fully charged (this may not be very long, as it is desirable for the membrane to have low capacitance), switch 408 can be turned on, and current can flow from one side of capacitor 406 through resistor 404 to the other side (i.e., the nanopore containing the molecule being detected). Different values ​​of resistor 404 will result in different current flows, and thus different voltage decays. Capacitor 416 can be large enough not to significantly affect the circuit.

[0056] After a specified amount of time, the voltage can be measured at the ADC (Analog-to-Digital Converter) 412. This can be measured by RC...隔膜 The time constant in the circuit is represented because the voltage change after a specified amount of time will be related to the resistance of the orifice (and the molecules therein). The implementation can also measure the amount of time it takes to reach a specific voltage, for example, by using a comparator, as described in U.S. Patent No. 9,377,437.

[0057] D. Capacitive effect at the working electrode (double-layer capacitance)

[0058] It is desirable for the working electrode to have high capacitance, thereby reducing its impedance effect on the circuit, which may cause the voltage level to shift slightly due to charge buildup after multiple measurements involving the opening and closing of switch 408.

[0059] Figure 5 This illustrates the bilayer formed at the interface between the conductive electrode and the adjacent liquid electrolyte. The electrical model of the bilayer is as follows: Figure 4 The electrical model 414 illustrates the modeling of capacitance associated with the working electrode. In the example shown, the electrode surface is negatively charged, causing positively charged material to accumulate in the electrolyte. In another example, the polarity of all charges can be opposite to the example shown. The charge in the electrode is balanced by the reorientation of dipoles and the accumulation of oppositely charged ions in the electrolyte near the interface. Due to the finite size of charged material and solvent molecules in the electrolyte, the accumulation of charge on either side of the interface between the electrode and electrolyte (separated by a small distance) acts as a dielectric in a conventional capacitor. The term "double layer" refers to the combination of the electronic charge distribution and the ionic charge distribution near the interface between the electrode and electrolyte.

[0060] Figure 6 This explains that it is possible to form such as Figure 5 The pseudocapacitive effect is formed at the interface between the conductive electrode and the adjacent liquid electrolyte in the double layer. Figure 6 A bilayer is shown, which adds pseudocapacitance through charge transfer, resulting in adsorption, intercalation, or reduction-oxidation reactions limited by the available surface area (indicated by solid-lined circles).

[0061] E. Example of constructing a porous working electrode

[0062] Figures 7A-7G and Figures 8A-8F An implementation scheme for constructing an electrochemical unit of a nanopore-based sequencing chip including a TiN working electrode is described. For example, a similar process is described in, in whole or in part, U.S. Patent Application Serial No. 15 / 920,158, filed March 18, 2018, the entire contents of which are incorporated herein by reference. In particular, Figures 7A-7G An implementation scheme for constructing an electrochemical unit of a nanopore-based sequencing chip including a TiN working electrode using chemimechanical planarization is described, and Figures 8A-8FOne embodiment of the process for constructing an electrochemical unit of a nanopore-based sequencing chip including a TiN working electrode using photolithography and dry etching is described. As will be described in more detail below, while these processes result in the working electrode having the desired sponge-like and porous properties, both methods can lead to the formation of seams in the working electrode layer, which act as weak points and cause performance problems.

[0063] like Figure 7A As shown, a feed 700 for constructing electrochemical nanopore units can be provided. The feed 700 may include a substrate 701, a conductive layer 702, and a dielectric layer 704 disposed thereon. The substrate 701 may be, for example, a CMOS substrate, which includes circuitry for controlling the operation of the nanopore units. The conductive layer 702 may be part of circuitry that transmits signals from the unit to the rest of the chip. In some cases, the conductive layer 702 may be a top metal layer of the circuitry, such as a sixth metal layer. However, the conductive layer 702 is not limited to a sixth metal layer as a bottom layer of circuitry. In some cases, the conductive layer 702 may be an aluminum layer, such as an aluminum interconnect metal associated with the substrate. Figure 7A As shown, the conductive layer 702 is surrounded in the dielectric layer 704 (e.g., SiO2), which can be the interconnecting dielectric between conductive components of the circuit disposed on the CMOS substrate as described above.

[0064] refer to Figure 7B In the first step of this process, the dielectric layer 704 can be etched to create a via 706. The via 706 provides a cavity for forming the sponge-like porous electrode required to create the nanoporous unit. Figure 7B As shown, the through-hole 706 includes a sidewall 707 formed of dielectric 704, which meets the top surface 709 of the conductive layer 702.

[0065] In the following steps, such as Figure 7C As shown, a sponge-like porous electrode layer 708 is deposited to fill... Figure 7B The porous electrode layer 706 is formed in the process. The sponge-like porous electrode layer 708 can be a TiN layer, which is grown and deposited in a certain way to produce a rough, sparsely spaced TiN columnar structure or pillars of TiN crystals, thereby providing a high specific surface area that can be contacted with the electrolyte. The sponge-like porous TiN layer 708 can be deposited using different deposition techniques, including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering deposition, etc. It should be understood that although TiN is described herein as a preferred electrode material, other suitable porous electrode materials can also be used.

[0066] In further steps, refer to Figure 7DExcess TiN layer 708 can be removed. For example, chemical mechanical planarization (CMP) can be used to remove excess TiN layer. The remaining TiN deposited in the via 706 forms a sponge-like porous working electrode 710.

[0067] As mentioned above, it may be necessary to protect the porous working electrode 710 during further manufacturing steps. Specifically, as will be referred to below. Figure 7F As described, trap formation ultimately requires the formation of a hydrophobic cladding layer on top of a porous electrode. However, if the hydrophobic cladding layer is formed directly on the porous electrode, residues of the hydrophobic cladding layer can become embedded in the gaps or cavities of the porous electrode. Organic residues can make the electrode surface less wettable and prevent fluid contact with the electrode surface. As a result, the effective surface area can be reduced, leading to a significant decrease in the bilayer capacitance at the electrolyte-electrode interface. To mitigate this problem, a thin buffer layer or sacrificial protective layer, such as a SiO2 layer, can be formed on the electrode to protect the electrode surface before subsequent processing, such as depositing a polyimide layer. After trap formation, the thin sacrificial layer can be removed from the top surface of the electrode. The thin buffer layer or sacrificial layer serves to protect the porous electrode layer from the hydrophobic layer during the trap formation process. Therefore, in the steps prior to trap formation, refer to Figure 7E A protective layer 712 may be deposited on top of the working electrode 710. As described above, the protective layer 712 may serve as a buffer layer or sacrificial layer to protect the working electrode 710 during manufacturing, thereby maintaining its required wettability and capacitance for operation. As described in previously incorporated U.S. Patent Application Serial No. 15 / 920,158, the protective layer 712 may be a dielectric material such as silicon oxide or a metallic material such as titanium. In either case, the protective layer may be selected to allow for selective removal.

[0068] exist Figure 7F In the steps shown, a hydrophobic cladding 714 may be formed and patterned to form a well 716 over the working electrode 710 and the protective layer 712. Figure 7F As shown, the presence of the protective layer 712 prevents the formation of a hydrophobic cladding 714 directly on the working electrode 710. Once deposited and patterned, the hydrophobic cladding 714 forms the sidewalls of the trap 716. Figure 7F The bottom of the trap 716 shown initially includes a protective layer 712.

[0069] like Figure 7GAs shown, once the hydrophobic cladding is formed, patterned, and otherwise processed, the protective layer 712 can be chemically removed to expose the working electrode 710 to the well 716. Specifically, the protective layer 712 can be removed by applying a removal agent containing hydrofluoric acid (HF), nitric acid, or any other suitable reagent for removing the protective layer 712. As an example, the protective layer 712 can be removed by a wet etching process using hydrofluoric acid (HF). The resulting nanoporous unit 750 has a well 716 with an exposed working electrode 710 and sidewalls formed by the hydrophobic cladding 714.

[0070] Alternative processes for constructing electrochemical units of nanopore-based sequencing chips are provided. Figures 8A-8F middle. Figures 8A-8F The process described in the text is similar to Figures 7A-7G The process shown, except that it uses photolithography and dry etching instead of... Figures 7A-7G The chemimechanical planarization technique described herein involves patterning the working electrode and the protective layer together. Specifically, Figure 8A This describes the same feed 700, which includes, for example... Figure 7A A substrate 701, a conductive layer 702, and a dielectric layer 704 are disposed thereon, and Figure 8B This illustrates the same etching of dielectric 704 to create via 706 for forming a sponge-like porous TiN electrode. As... Figure 7B The through-hole 706 includes a sidewall 707 formed of dielectric 704 that meets the top surface 709 of the conductive layer 702.

[0071] Next, as Figure 8C As shown, a sponge-like porous TiN layer 708 is deposited to fill... Figure 8B The porous TiN layer 708 produces through-holes 706, and a protective layer 812 is deposited on the porous TiN layer 708. Then, as... Figure 8D As shown, a porous TiN layer 708 and a protective layer 812 are patterned together to produce a working electrode 810 with a patterned protective layer 813. As described above, the patterned protective layer 813 is used for [further details to be provided below]. Figure 8E The working electrode 810 is protected during the subsequent trap formation process.

[0072] refer to Figure 8E A hydrophobic cladding 814 can be formed and patterned to form a trap 816, similar to... Figure 7F The process is shown below. (Refer to previous references.) Figure 7F As described, in Figure 8E In this process, the presence of the protective layer 813 prevents the formation of a hydrophobic cladding 814 directly on the working electrode 810. Once deposited and patterned, the hydrophobic cladding 814 forms the sidewalls of the trap 816 and the bottom of the trap 816 initially includes the protective layer 813.

[0073] like Figure 8F As shown, once the hydrophobic cladding is formed, patterned, and otherwise processed, the protective layer 813 can be chemically removed to expose the working electrode 810 to the trap 816. Specifically, the protective layer 813 can be removed by applying a removal agent containing hydrofluoric acid (HF), nitric acid, or any other suitable reagent for removing the protective layer 813. As an example, the protective layer 813 can be removed by a wet etching process using hydrofluoric acid (HF). The resulting nanoporous unit 850 has a trap 816 with an exposed working electrode 810 and sidewalls formed by the hydrophobic cladding 814.

[0074] Despite the above Figures 7A-7G and Figures 8A-8F The processes described in [the text] typically provide suitable electrochemical units for nanopore-based sequencing, but some drawbacks have been observed related to the growth of porous electrode materials. Specifically, it has been observed that while the deposition of porous electrode materials leads to the growth of columns of electrode material with the desired porous properties, this growth does not occur upwards from the top of the conductive surface as expected (i.e., [the process described in the text]). Figure 7B and Figure 8B The top surface 709 shown in the diagram, but it can also occur perpendicular to the sidewalls of the deposited via (i.e., Figure 7B and Figure 8B This is the expected growth of the sidewall 707 depicted in the diagram. As a result, the pillars growing upward from the top of the conductive surface and the pillars growing laterally from the sidewalls of the deposited via collide with each other and form a joint, which continues to expand until the deposition of TiN is complete.

[0075] Figure 9 This indicates that it may be used Figures 7A-7G and Figures 8A-8F The seam formed in the working electrode constructed by the process shown. For example... Figure 9 As shown, the pillars of TiN 908 grow vertically from the top surface 909 of the conductive layer 902 and horizontally from the sidewalls 907 to form a seam 918. When using similar... Figures 7A-7G and Figures 8A-8F Similar seams have been observed in examples manufactured using this process. For example, seam 1018 can be... Figure 10 As seen in the image, it is used to demonstrate the use of... Figures 7A-7G The image shows a micrograph of the TiN electrode layer formed by the process shown, and the seam 1118 can be... Figure 11 As seen in the image, it is used to demonstrate the use of... Figures 8A-8F Micrograph of the TiN electrode layer formed by the process shown.

[0076] Will understand (and can in) Figure 10 and Figure 11As seen in the diagram, the seams formed in the non-planar vias ultimately lead to undesirable voids, which become weak points in the electrode layer structure. These voids and weak points can allow material to penetrate the electrode layer and interact with or erode other layers of the nanoporous unit, thus significantly affecting the performance of the nanoporous unit. In particular, removal agents used to remove the protective layer as described above (such as HF or nitric acid-containing agents) may penetrate the voids created by the seams. For example, these agents may erode the interconnect dielectric layer (e.g., Figures 7A-7G and Figures 8A-8F Layer 704, as described in the diagram, can be used for conductive interconnects in a separation device. Ultimately, damage to these layers can lead to misalignment of the well structure, electrode short circuits, and crosstalk between electrodes, all of which can severely impact the performance of the nanoporous unit.

[0077] II. Nanoporous units with seamless electrodes

[0078] A. The process for constructing seamless working electrodes

[0079] To avoid the aforementioned seams and related drawbacks, a method for constructing nanoporous units with seamless working electrodes is described. Specifically, Figures 12A-12F An implementation scheme for constructing an electrochemical unit of a nanopore-based sequencing chip including a seamless working electrode is described.

[0080] like Figure 12A As shown, feed 1200 can be similar to the previous description. Figure 7A and Figure 8A The feed 700 described includes a substrate 1201, a conductive layer 1202, and an interconnect dielectric layer 1204 disposed thereon.

[0081] In the next step, such as Figure 12B As shown, a planar electrode support layer 1205 can be formed by removing at least a portion of the interconnect dielectric layer 1204. The planar electrode support layer 1205 includes conductive layer islands 1202 and surrounding interconnect layers 1204, which are retained after the portion is removed. Therefore, the planar electrode support layer 1205 has a planar electrode support surface 1203, which includes the top surface of the conductive layer islands 1202 and the top surface of the surrounding interconnect layers 1204 retained after removal. The removal of the dielectric layer 1204 can be accomplished by patternless etching of the dielectric layer 1204 to expose the islands of the conductive layer 702. Compared to the previously described process, there are no vias with sidewalls in which electrode material is deposited. Instead, electrode material is deposited on a completely planar electrode support surface 1203.

[0082] In the following steps, such as Figure 12CAs shown, a porous electrode material 1208, such as TiN, can be deposited on the planar electrode support surface 1203. Figure 12C As shown, there are no sidewalls for the through-holes used for the vertical columnar growth of the porous electrode material, thus no seams are formed in the porous electrode material. Therefore, the deposited porous electrode material 1208 forms uniform, seamless columns of the porous electrode material. These uniform, seamless columns in Figure 13 The text further explains the use of... Figures 12A-12C The process shown constructs a seamless electrode layer. Once deposited, and also... Figure 12C As seen above, the seamless porous electrode material 1208 can be protected by depositing a protective layer 1212 thereon. As described above, the protective layer 1212 can comprise a dielectric material or a metallic material. Examples of protective dielectrics that can be used include silicon oxide, titanium oxide, hafnium oxide, and zirconium oxide. Other suitable dielectric materials (e.g., protective layer 1212) for embodiments of the present invention include, but are not limited to, oxides, nitrides (e.g., silicon nitride or SiN), silicon oxide, silicon oxynitride, metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium oxide, zirconium silicate, zirconium aluminate, hafnium oxide, titanium oxide, or combinations thereof. Those skilled in the art will understand that other dielectric materials are suitable for the present invention. Examples of other materials that can be used as a protective layer include titanium, aluminum, tantalum, tungsten, or non-porous titanium nitride. Those skilled in the art will understand that other metallic materials are suitable for the present invention.

[0083] Next, as Figure 12D As shown, the porous electrode layer 1208 and the protective layer 1212 are patterned together to produce a patterned working electrode 1210 and a patterned protective layer 1213. The TiN and the protective layer can be patterned together using photolithography and dry etching or other suitable processes for patterning such materials. The resulting working electrode is a uniform pillar island of TiN without the undesirable seams described above, on which the protective layer is disposed.

[0084] In further steps, refer to Figure 12E A hydrophobic cladding 1214 can be formed on the electrode 1210 and the protective layer 1213, and the hydrophobic cladding can be patterned to form a trap 1216, similar to... Figure 7F and Figure 8E The process is shown in the previous reference. Figure 7F and Figure 8EAs described, a patterned hydrophobic cladding 1214 forms the sidewalls of the trap 1216, and the bottom of the trap 1216 initially includes a protective layer 1213 to prevent exposure of the working electrode 1210. Examples of hydrophobic materials that can be used include polyimide, epoxy resin, polybenzoxazole (PBO), and benzocyclobutene (BCB). Other hydrophobic materials suitable for use in this invention will be understood by those skilled in the art.

[0085] Next, refer to Figure 12F Once the manufacturing process is otherwise completed, the protective layer 1213 can be chemically removed using a removal agent, thereby exposing the working electrode 1210 to the trap 1216. As described above, the protective layer 1213 can be chemically removed using a removal agent containing HF, nitric acid, other suitable reagents, and / or combinations thereof, depending on the material chosen for the protective layer 1212 / 1213. For example, if the protective layer 1212 / 1213 contains silicon dioxide, it can be removed using buffered oxide etching (BOE) with a concentration range of 8:1 to 100:1 (NH4F:HF). On the other hand, if the protective layer 1212 / 1213 contains a metallic material, it can be removed using diluted HF / nitric acid mixtures with concentration ranges of 10:1:1 and 500:1:1 (H2O:HF:HNO3). Other reagents suitable for use in this invention will be understood by those skilled in the art. Depending on the protective material and the removal agent, different processes can be used to remove the protective material. In some embodiments, the protective layer 1213 can be removed using any of the reagents described above via a wet etching process; however, those skilled in the art will understand that other processes are suitable for removal in this invention. Compared to the previously described methods, since the electrode 1210 is formed from uniform, seamless pillars of TiN, the likelihood of any removal reagent penetrating and eroding other layers (such as dielectric 1204) is much smaller.

[0086] Figure 16 This is a flowchart illustrating a method for forming nanoporous units with seamless electrodes. Method 1600 includes, at step 1610, providing a device structure including a conductive layer disposed on a top portion of a substrate and an interconnect dielectric layer covering the conductive layer. (The last sentence appears to be incomplete and possibly refers to a technical detail.) Figure 12A More details are provided in the description. At step 1620, a portion of the interconnect dielectric is removed to form a planar electrode support surface, which includes exposed islands of the conductive layer surrounded by the remainder of the interconnect dielectric layer. In combination Figure 12B More details are provided in the description. At step 1630, porous electrode material is deposited on the planar electrode support surface to form a seamless porous electrode layer made of pillars of porous electrode material. In combination Figure 12C and Figure 13More details are provided in the description. At step 1640, a protective layer is deposited on the seamless porous electrode layer. In combination... Figure 12C More details are provided in the description. At step 1650, the seamless porous electrode layer and protective layer are patterned to form the working electrode island. In combination... Figure 12D More details are provided in the description. In step 1660, a hydrophobic cladding is deposited and patterned to form the sidewalls of the trap of the nanoporous unit. In combination Figure 12E More details are provided in the description. At step 1670, a portion of the protective layer is removed to expose the porous electrode layer to the trap of the nanopore units. In combination Figure 12F More details are provided in the description.

[0087] B. Nanoporous unit with seamless working electrode

[0088] Figure 12F A nanoporous unit 1250 is described, comprising a substrate 1201, an electrode support layer 1205 covering a top portion of the substrate 1201, and a well 1216. The electrode support includes a conductive layer island 1202 surrounded by an interconnect dielectric layer 1204, and a planar top surface 1203 formed by the conductive layer island 1202 and the interconnect dielectric layer 1204. The well 1216 includes a seamless porous working electrode island 1210, a hydrophobic cladding layer 1214 surrounding the seamless porous working electrode island 1210 and patterned to form the sidewalls of the well 1216, and a cavity formed by the hydrophobic cladding layer 1214 and the seamless porous working electrode island 1210. The seamless porous working electrode island 1210 is disposed on the planar top surface 1203 of the planar electrode support layer 1205 and is made of pillars of porous electrode material.

[0089] Figure 14A and Figure 14B They are respectively through Figures 12A-12E The method forms an example of a seamless electrode array, shown in top and perspective views. Figure 15 These are SEM (Scanning Electron Microscopy) images, illustrating the presence of... Figures 12A-12E Examples of seamless TiN electrode layers 1510 nanoporous devices formed by this method are shown. As can be seen from each of these figures, the pillars of the electrode material possess the desired porosity and uniformity, without any visible seams that could serve as voids or weak points allowing reagent permeation. Therefore, using... Figures 12A-12E The electrode materials produced by this method can be better configured to prevent damage to other components of the nanopore trap.

[0090] In the foregoing description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments can be practiced without some of these details or with others.

[0091] Where a range of values ​​is provided, it should be understood that, unless the context explicitly indicates otherwise, each intermediate value between the upper and lower limits of the range is also specifically disclosed, accurate to one-tenth of the lower limit unit. This covers every smaller range between any specified value or intermediate value within the specified range and any other specified value or intermediate value within the specified range. The upper and lower limits of these smaller ranges may be independently included or excluded from the range, and each range in which one or both limits are included or neither limit is excluded is also covered by the invention, based on any limit specifically excluded from the specified range. Where the specified range includes one or two limits, ranges excluding one or both of those included limits are also included.

[0092] As used herein and in the appended claims, the singular forms “a,” “an,” “the,” and “the” include plural references unless the context clearly specifies otherwise. Thus, a reference to “a method,” for example, includes multiple such methods. It will also be further understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of the defined features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items and may be abbreviated to “ / ”.

[0093] Several embodiments of the invention have been described above. However, those skilled in the art will recognize that various modifications, alternative architectures, and equivalents can be used without departing from the spirit of the invention. For example, although a polyimide layer is used in the above description as an example of a hydrophobic material for forming a trap, other organic materials with hydrophobic surface properties, such as CYTOP as an amorphous fluoropolymer, can also be used in other embodiments. Furthermore, in addition to silicon oxide, other dielectric materials with suitable etch selectivity and process compatibility can also be used to form the sacrificial layer, such as silicon nitride, zirconium oxide, and hafnium oxide. Moreover, many well-known processes and elements have not been described to avoid unnecessarily obscuring the invention. Additionally, details of any particular embodiment may not always be present in variations of that embodiment or may be added to other embodiments.

[0094] When a feature or element is referred to herein as being “on” another feature or element, it may be directly on the other feature or element, or there may be intermediate features and / or elements present. Conversely, when a feature or element is referred to as being “directly on” another feature or element, there are no intermediate features or elements present. It will also be understood that when a feature or element is referred to as being “connected,” “attached,” or “coupled” to another feature or element, it may be directly connected, attached, or coupled to the other feature or element, or there may be intermediate features or elements present. Conversely, when a feature or element is referred to as being “directly connected,” “directly attached,” or “directly coupled” to another feature or element, there are no intermediate features or elements present. Although one embodiment has been described or shown, the features and elements so described or shown may be applied to other embodiments. Those skilled in the art will also recognize that a structure or feature referred to as being “adjacent” to another feature may have portions that overlap with or are located beneath the adjacent feature.

[0095] For ease of description, spatially relative terms such as “below,” “below,” “lower than,” “above,” “over,” etc., are used herein to describe the relationship of one element or feature to another, as illustrated in the accompanying drawings. It should be understood that, in addition to the orientations depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is inverted, an element described as “below” or “under” other elements or features would then be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both the orientations of “above” and “below.” The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. Similarly, unless otherwise specifically indicated, terms such as “up,” “down,” “vertical,” “horizontal,” etc., are used herein for illustrative purposes only.

[0096] Although the terms “first” and “second” may be used herein to describe various features / elements (including steps), these features / elements should not be limited by these terms unless the context otherwise indicates. These terms can be used to distinguish one feature / element from another. Therefore, without departing from the teachings of the invention, the first feature / element discussed below may be referred to as the second feature / element, and similarly, the second feature / element discussed below may be referred to as the first feature / element.

[0097] Throughout this specification and the following claims, unless the context otherwise requires, the word “comprising” and variations such as “including” and “containing” mean that various components may be used together in methods and articles (e.g., compositions and devices that include means and methods). For example, the term “comprising” will be understood to imply the inclusion of any of the specified elements or steps, but does not exclude any other elements or steps.

[0098] As used herein in the specification and claims, including as in the examples, and unless otherwise expressly specified, all figures may be interpreted as if preceded by the words “about” or “approximately,” even if the term is not explicitly stated. When describing magnitude and / or location, the phrase “about” or “approximately” may be used to indicate that the described value and / or location is within a reasonably expected range of value and / or location. For example, numerical values ​​may have values ​​of + / -0.1% of a specified value (or range of values), + / -1% of a specified value (or range of values), + / -2% of a specified value (or range of values), + / -5% of a specified value (or range of values), + / -10% of a specified value (or range of values), etc. Unless the context otherwise indicates, any numerical value given herein should also be understood to include about or approximately that value. For example, if the value “10” is disclosed, “about 10” is also disclosed. Any numerical ranges described herein are intended to include all subranges contained therein. It should also be understood that, as those skilled in the art would appropriately understand, when a value is disclosed, the terms "less than or equal to" that value, "greater than or equal to" that value, and possible ranges between values ​​are also disclosed. For example, if the value "X" is disclosed, "less than or equal to X" and "greater than or equal to X" are also disclosed (e.g., in the case where X is a numerical value). It should also be understood that throughout this application, data is provided in a variety of different formats, and the data represents a range of endpoints and start points, as well as any combination of data points. For example, if specific data point "10" and specific data point "15" are disclosed, it should be understood that values ​​greater than, greater than or equal to, less than, less than or equal to, equal to 10 and 15, and values ​​between 10 and 15 are considered disclosed. It should also be understood that each unit between two specific units is also disclosed. For example, if 10 and 15 are disclosed, 11, 12, 13, and 14 are also disclosed.

[0099] Although various illustrative embodiments have been described above, any of a variety of changes may be made to the various embodiments without departing from the scope of the invention as set forth in the claims. For example, in alternative embodiments, the order in which the various method steps described are performed may often be changed, while in other alternative embodiments, one or more method steps may be skipped entirely. In some embodiments, optional features of various apparatus and system embodiments may be included, while in others they may not be included. Therefore, the foregoing description is provided primarily for illustrative purposes and should not be construed as limiting the scope of the invention as set forth in the claims.

[0100] The examples and illustrations included herein are shown in an illustrative and not limiting manner, specific embodiments in which the subject matter can be practiced. As mentioned, other embodiments can be utilized and derived from them, allowing for structural and logical substitutions and changes without departing from the scope of this disclosure. These embodiments of the subject matter of the invention may be referred to herein individually or collectively by the term "invention," merely for convenience and not intended to actively limit the scope of this application to any single inventive concept, given that more than one inventive concept has actually been disclosed. Therefore, although specific embodiments have been shown and described herein, any arrangement calculated to achieve the same purpose may replace the specific embodiments shown. This disclosure is intended to cover any and all modifications or variations of the various embodiments. After reviewing the foregoing description, combinations of the above embodiments, as well as other embodiments not explicitly described herein, will be apparent to those skilled in the art.

[0101] All patents, patent applications, publications, and specifications mentioned herein are incorporated herein by reference in their entirety for all purposes. None of them are considered prior art.

Claims

1. A method for forming nanoporous units, the method comprising: A device structure is provided, the device structure comprising: A conductive layer disposed on the top portion of a substrate; and An interconnect dielectric layer, which covers the conductive layer; A portion of the interconnect dielectric layer is removed to form a planar electrode support surface, the planar electrode support surface comprising exposed islands of the conductive layer surrounded by the remainder of the interconnect dielectric layer; A porous electrode material is deposited on the planar electrode support surface to form a seamless porous electrode layer comprising pillars of the porous electrode material; A protective layer is deposited on the seamless porous electrode layer; The seamless porous electrode layer and the protective layer are patterned to form working electrode islands; A hydrophobic cladding is deposited on the working electrode island and patterned to form the sidewalls of the traps of the nanopore units; and At least a portion of the protective layer is removed to expose the porous electrode layer to the trap, wherein the exposed porous electrode layer forms at least a portion of the bottom wall of the trap of the nanopore unit.

2. The method according to claim 1, wherein the porous electrode material comprises porous TiN (titanium nitride).

3. The method according to claim 1, wherein the porous electrode material comprises a ruthenium-containing material.

4. The method of claim 1, wherein removing a portion of the interconnect dielectric comprises performing patternless etching on a portion of the interconnect dielectric.

5. The method of claim 1, wherein the protective layer comprises a dielectric material.

6. The method of claim 1, wherein the protective layer comprises silicon oxide.

7. The method of claim 1, wherein the protective layer comprises a metallic material.

8. The method of claim 1, wherein the protective layer comprises titanium.

9. The method of claim 1, wherein removing at least a portion of the protective layer to expose the porous electrode layer comprises applying a removal agent to the protective layer.

10. The method of claim 9, wherein the removal agent comprises hydrofluoric acid.

11. The method of claim 9, wherein a wet etching process is used to apply the removal agent.

12. The method of claim 9, wherein the removal agent is applied to the protective layer without damaging the interconnect dielectric layer.

13. The method according to any one of claims 1 to 12, wherein the seamless porous electrode layer and the protective layer are patterned using photolithography and dry etching.

14. A nanoporous unit, the nanoporous unit comprising: Substrate; An electrode support layer covering the top portion of the substrate, the electrode support layer comprising: Conductive layer islands; Interconnect dielectric layers, the interconnect dielectric layers surrounding the conductive layer islands; and A planar top surface, the planar top surface being formed by the conductive layer islands and the interconnect dielectric layer; and The trap, comprising: A seamless working electrode island is disposed on the top surface of the plane of the electrode support layer, and the seamless working electrode island comprises pillars of porous electrode material. A hydrophobic cladding surrounds the seamless working electrode island and is patterned to form the sidewalls of the trap; A cavity formed by the hydrophobic cladding and the seamless working electrode island.

15. The nanoporous unit according to claim 14, wherein the porous electrode material comprises porous TiN (titanium nitride).

16. The nanoporous unit of claim 14, wherein the porous electrode material comprises a ruthenium-containing material.

17. The nanoporous unit of claim 14, wherein the seamless working electrode island further comprises a protective layer disposed on a pillar of the porous electrode material, wherein the protective layer is configured to be selectively removable to expose the porous electrode material to the cavity.

18. The nanoporous unit of claim 17, wherein the protective layer is configured to be removed by applying a removal agent.

19. The nanoporous unit of claim 18, wherein the removal reagent comprises hydrofluoric acid.

20. The nanoporous unit of claim 18, wherein the pillars of the porous electrode material are configured to prevent the removal reagent from damaging the electrode support layer.

21. The nanoporous unit of claim 17, wherein the protective layer comprises a dielectric material.

22. The nanoporous unit of claim 21, wherein the protective layer comprises silicon oxide.

23. The nanoporous unit of claim 17, wherein the protective layer comprises a metallic material.

24. The nanoporous unit of claim 23, wherein the protective layer comprises titanium.

25. The nanoporous unit according to any one of claims 14 to 24, wherein the conductive layer island comprises aluminum.

26. The nanoporous unit according to any one of claims 14 to 24, wherein the interconnecting dielectric comprises silicon oxide.

27. The nanoporous unit according to any one of claims 14 to 24, wherein the hydrophobic cladding comprises polyimide.

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