Notifying a memory system of a host event via a modulated reset signal

Abstract

An example memory subsystem includes a memory device; and a processing device operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with a memory system, identify a host event specified by the reset signal by decoding the reset signal, and process the identified host event.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more particularly to informing a memory system of a host event via a modulated reset signal. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at the memory devices and retrieve data from the memory devices. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which:

[0004] Figure 1 An example computing system including a memory sub-system in accordance with some embodiments of the present disclosure is described.

[0005] Figure 2 An example interface between a host system and a memory sub-system implemented in accordance with aspects of the present disclosure is schematically illustrated.

[0006] Figure 3 An example modulated reset signal transmitted by a host system to a memory sub-system operated in accordance with aspects of the present disclosure is schematically illustrated.

[0007] Figure 4 An example reset signal decoder circuit of a memory sub-system operated in accordance with aspects of the present disclosure is schematically illustrated.

[0008] Figure 5 An example signal timing diagram utilized by a memory sub-system operated in accordance with aspects of the present disclosure is schematically illustrated.

[0009] Figure 6 A flowchart of an example method of processing a host event specified by a reset signal implemented by a memory sub-system controller operated in accordance with some embodiments of the present disclosure.

[0010] Figure 7 A flowchart of an example method of performing cache management in response to receiving a notification of a host event via a reset signal implemented by a memory sub-system controller operated in accordance with some embodiments of the present disclosure.

[0011] Figure 8 A block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure relate to informing a memory sub-system of a host event via modulation of a reset signal. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Embodiments are described below in connection with Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0013] The memory sub-system can utilize one or more memory devices, including any combination of different types of non-volatile memory devices and / or volatile memory devices, to store data provided by the host system. In some embodiments, the non-volatile memory devices can be provided by a NAND-type flash memory device. Embodiments are described below in connection with Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a group of physical blocks. Each block is composed of a group of pages. Each page is composed of a group of memory cells (“cells”). The cells are electronic circuits that store information.

[0014] The memory sub-system can perform host-initiated data operations. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory sub-system. The host system can send access requests (e.g., write commands, read commands) to the memory sub-system in order to store data on the memory devices at the memory sub-system and to read data from the memory devices on the memory sub-system. The data to be read or written is referred to hereinafter as “host data” as specified by the host request. The host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is a location associated with the host data by the host system. The logical address information (e.g., LBA, namespace) can be part of metadata for the host data. The metadata can also include error handling data (e.g., ECC codewords, parity codes), data version (e.g., to distinguish an age of written data), valid bitmap (whose LBAs or logical transport units contain valid data), etc.

[0015] The host system can communicate with the memory sub-system by using a specified protocol, which can support a limited set of commands, such as write, read, erase, configure, etc. The communication is performed via a set of interface signals, which are supported by the host system and the memory sub-system.

[0016] Various implementations of the communication interface between the host system and the memory subsystem fail to support certain event notifications from the host to the memory subsystem. For example, if a mobile device acting as the host system would be able to notify the memory subsystem that the mobile device's battery is currently charging, the memory subsystem could perform cache management operations to clear its internal cache under the assumption that the amount of host initiated data operations is minimal and thus unlikely to be utilized by the user while the host system is connected to a charger.

[0017] Accordingly, embodiments of the present disclosure implement event signaling between the host system and the memory subsystem via the memory subsystem's reset signal while supporting the conventional reset signaling on the reset pin, thus significantly improving various operational aspects of the memory subsystem. According to embodiments of the present disclosure, the host system can modulate the memory subsystem reset signal according to a set of predefined patterns, such that each of the predefined patterns will correspond to a certain host event and / or cause the memory subsystem to perform certain actions. Thus, the host system can signal a corresponding host event to the memory subsystem using a certain reset signal pattern, causing the memory subsystem to perform event specific processing.

[0018] For example, the host system can utilize a predefined reset signal pattern (e.g., 10101010 binary) to signal a host battery charging event to the memory subsystem, causing the memory subsystem to perform cache management operations to clear its internal cache.

[0019] In another example, the host system can utilize another predefined reset signal pattern (e.g., 01010101 binary) to signal the expiration of a timeout for waiting for a response from the memory subsystem, causing the memory subsystem to abort current memory access operations and / or save its current state to a non-volatile memory device for debugging. The saved memory subsystem state information can then be retrieved and used by the host system in order to determine the cause of a malfunction that was exhibiting itself as unresponsive in the memory subsystem.

[0020] In yet another example, the host system can utilize yet another predefined reset signal pattern (e.g., 00110011 binary) to signal a programmable predefined event to the memory subsystem, causing the memory subsystem to perform programmable event specific processing by executing event specific code, as described in greater detail herein below.

[0021] As mentioned herein above, embodiments of the disclosure support regular reset signaling on the reset pin, such that the host system drives the reset signal to a predefined state for at least a predefined period of time (which would exceed the characteristic time used in the reset signal pattern described above) to cause the memory sub-system to perform a reset sequence. Thus, legacy host systems that do not support the reset signal pattern described above will still be able to perform regular reset signaling, while host systems that are capable of supporting the reset signal pattern will be able to perform regular reset signaling or utilize the reset pin for enhanced signaling in accordance with embodiments of the disclosure.

[0022] Accordingly, advantages of systems and methods implemented in accordance with some embodiments of the disclosure include, but are not limited to, improving memory sub-system efficiency by signaling host events to the memory sub-system without modifying hardware interfaces, as described in greater detail herein below.

[0023] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the disclosure is illustrated. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such media.

[0024] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, Universal Serial Bus (USB) flash drives, Embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include Dual In-Line Memory Modules (DIMMs), Small Outline Dual Inline Memory Modules (SO-DIMMs), and various types of Non-Volatile Dual In-Line Memory Modules (NVDIMMs).

[0025] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked consumer device), or such computing device including memory and a processing device (e.g., a processor).

[0026] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1An example of a host system 120 coupled to a memory sub-system 110 is illustrated. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0027] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0028] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), double data rate (DDR) memory bus, small computer system interface (SCSI), dual in-line memory module (DIMM) interface (e.g., DIMM socket interface supporting double data rate (DDR)), open NAND flash interface (ONFI), double data rate (DDR), low power double data rate (LPDDR), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface 105, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130). The physical host interface 105 can provide an interface for communicating control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 An example of a memory sub-system 110 is illustrated. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0030] Some examples of non-volatile memory devices (e.g., memory devices 130) include negative-and (NAND)-type flash memory and in-place write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grided data access array. Additionally, in contrast to many flash-based memories, a cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit per cell. Other types of memory cells, for example, multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination of such arrays of memory cells. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device that are used to store data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0032] While non-volatile memory devices are described, such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or negative-or (NOR) flash memory, as well as electrically erasable programmable read-only memory (EEPROM).

[0033] The memory sub-system controller 115 can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, a special- purpose logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory sub-system controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0035] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the local memory 119 is illustrated as being internal to the memory sub-system controller 115, in some embodiments, the local memory 119 can be external to the memory sub-system controller 115. Figure 1 In another embodiment of the disclosure, the memory sub-system 110 does not include a controller 115, and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0036] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., a logical block address (LBA), a namespace) and a physical address (e.g., a physical block address) associated with the memory devices 130. The memory sub-system controller 115 can also include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory devices 130, as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0037] The memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory devices 130.

[0038] In some embodiments, the memory devices 130 include a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory cells of the memory devices 130. An external controller (e.g., the memory sub-system controller 115) can externally manage the memory devices 130 (e.g., perform media management operations on the memory devices 130). In some embodiments, the memory sub-system 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local media controller 135) on-die and a controller (e.g., the memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] The memory sub-system 110 includes a host event notification component 113 that can be used to process host events transmitted via a modulated reset signal, in accordance with embodiments of the present disclosure. In some embodiments, the controller 115 includes at least a portion of the host event notification component 113. For example, the controller 115 can include a processor 117 configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the host event notification component 113 is part of the host system 120, an application, or an operating system. The host event notification component 113 can match a payload carried by a reset signal with one of a predefined sequence of bits that identifies a corresponding host event, and perform event-specific processing, as described in greater detail herein below.

[0040] Figure 2 An example interface 210 between a host system 120 and a memory sub-system 110 implemented in accordance with aspects of the present disclosure is schematically illustrated. As mentioned above herein, the interface 210 can be used to transmit control, address, data, and other signals between the host system 120 and the memory sub-system 110. In the illustrative example, the interface 210 can conform to the Non-Volatile Memory Express (NVMe) interface specification. As indicated by the dashed lines, the interface 210 can be used to transmit a modulated reset signal 212 that carries a payload that identifies a host event, such as a host system reset event, a host system power cycle event, or a host system sleep event. Figure 2Illustratively, interface 210 can include a set of data input signals 220 for transferring data from host system 120 to memory sub-system 110. Interface 210 can further include a set of data output signals 230 for transferring data from memory sub-system 110 to host system 120. Interface 210 can further include a set of power lines and power management signals 240 for transferring power and / or power management commands from host system 120 to memory sub-system 110. Interface 210 can further include a reset signal 250, which can be used to inform memory sub-system 110 of a host event, causing memory sub-system 110 to perform event-specific processing. In some implementations, host system 120 and memory sub-system 110 can synchronize their clocks based on a reset clock signal 260, which is a periodic signal (e.g., toggles between a logic "zero" and a logic "one" state every 100 microseconds). Alternatively, if reset clock signal 260 is not present in interface 210, then memory sub-system can implement a Universal Asynchronous Receiver / Transmitter (UART) in place of a clock signal, which adds start and stop bits to the data packets being transmitted, as described below with reference to Figure 4 described.

[0041] Figure 3 Illustrative examples of modulated reset signals transmitted by a host system to a memory sub-system operating in accordance with aspects of the present disclosure. As illustrated by Figure 3 Illustratively, a reset signal can include a header 310, which can be represented as a predefined bit sequence, followed by a variable bit sequence that serves as a host event identifier 320. Host event identifier 320 can be one of predefined bit sequences 330A-330N, such that each of the predefined bit sequences will correspond to a certain host event and / or cause the memory sub-system to perform certain actions. Thus, a host system can signal a corresponding host event to the memory sub-system with a certain reset signal pattern, causing the memory sub-system to perform event-specific processing.

[0042] For example, a host system can utilize a predefined reset signal pattern 330A (e.g., 10101010 binary) to signal a host battery charging event to the memory sub-system, causing the memory sub-system to perform cache management operations to flush its internal cache. The host battery charging event can be signaled to the memory sub-system in response to detecting an external power connection to the host system.

[0043] In some implementations, the memory sub-system can include one or more non-volatile memory devices, such as NAND flash devices (e.g., devices 130) and one or more volatile memory devices, such as dynamic random access memory (DRAM) devices (e.g., Figure 1 DRAM devices (e.g., devices 130) and one or more volatile memory devices, such as dynamic random access memory (DRAM) devices (e.g.,Figure 1 The volatile memory devices can exhibit access times that are orders of magnitude smaller than access times of the non-volatile memory devices. Thus, the memory sub-system can allocate one or more portions of the volatile memory devices 140 to act as a cache for one or more of the non-volatile memory devices 130. In an illustrative example, portions of host data retrieved from the non-volatile memory devices 130 can be cached on the volatile memory devices 140. In another example, portions of memory sub-system metadata (e.g., including flash translation metadata that includes logical-to-physical (L2P) tables that map host logical addresses to corresponding memory device physical addresses) can be cached on the volatile memory devices 140.

[0044] The memory sub-system can implement different cache policies. Under a write-through policy, all write operations performed with respect to a cache entry are immediately propagated to the non-volatile memory. Conversely, a write-back policy can involve delaying non-volatile memory updates, thereby improving overall memory access efficiency at least for some memory access patterns. Thus, in response to receiving a notification of a host battery charge event, the memory sub-system can perform cache management operations, such as writing contents of modified cache entries back to the non-volatile memory.

[0045] Referring again to Figure 3 In another example, the host system can utilize another predefined reset signal pattern 330B (e.g., 01010101 binary) to signal expiration of a timeout for waiting for a response from the memory sub-system to a host command (e.g., a read or write command). In response to matching the reset signal payload to the reset signal pattern 330B, the memory sub-system can abort a current memory access operation and / or save its current state to the non-volatile memory devices for debugging. The saved memory sub-system state can include contents of registers and memory buffers utilized by the memory sub-system controller 115. The saved memory sub-system state information can then be retrieved and used by the host system in order to determine a cause of a fault that manifested itself as unresponsive in the memory sub-system.

[0046] In yet another example, the host system can utilize yet another predefined reset signal pattern 330N (e.g., 01110001 binary) to signal a programmable predefined event to the memory sub-system, causing the memory sub-system to perform programmable event-specific processing by executing event-specific code. In some implementations, the memory sub-system controller can maintain a memory data structure (e.g., a two-dimensional array) including one or more host event mapping records, such that each host event mapping record maps a host event identifier to a corresponding memory address that serves as an entry point to event processing program code to be executed by the memory sub-system controller in response to determining that the reset signal payload includes a bit sequence that matches the host event identifier.

[0047] Figure 4 An example reset signal decoder circuit of a memory sub-system operating in accordance with aspects of the present disclosure is illustratively shown. As shown by Figure 4 The reset signal decoder circuit 400 can implement a UART interface by employing a latch circuit 410 configured to output a decoded reset signal 430 in response to detecting the input RSTn signal 420 transitioning to a low level (logic "zero"), as shown by Figure 5 The decoded reset signal 430 generated by the latch circuit 410 goes to a logic "one" when the input RSTn signal 420 goes from a logic "one" to a logic "zero," and remains at the logic "one" level until it is reset by the clear signal 450, as illustratively shown. The memory sub-system controller receives the decoded reset signal 430, verifies that the signal header matches a predefined bit pattern of the reset signal, and attempts to match the payload carried by the reset signal to one of the predefined bit sequences that identify a corresponding host event. Upon successfully matching the reset signal payload to a predefined bit sequence, the memory sub-system can perform event-specific processing for the host event referred to by the predefined bit sequence to which the reset signal payload matches, as described herein above with reference to Figures 2 to 3 In more detail.

[0048] Figure 6A flowchart of an example method for processing a host event specified by a reset signal by a memory subsystem controller operating in accordance with some embodiments of the present disclosure. The method 600 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the host event notification component 113 of Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that the illustrated operations can be performed in a different order, or that some operations can be performed in parallel. Additionally, one or more operations can be omitted in some embodiments. Thus, not all of the illustrated operations are required, and other process flows are possible.

[0049] At operation 610, the memory subsystem controller receives a reset signal from the host computer system. In the illustrative example, the reset signal can be generated by a reset signal decoder circuit that generates a reset signal by latching a logic transition on an input RSTn line, as described in greater detail herein above.

[0050] At operation 620, the memory subsystem controller identifies a host event specified by the reset signal. In the illustrative example, the memory subsystem controller verifies that the signal header matches a predefined bit pattern of the reset signal, and attempts to match the payload carried by the reset signal to one of a predefined sequence of bits that identifies a corresponding host event.

[0051] Upon successfully matching the reset signal payload to a predefined sequence of bits, at operation 630, the memory subsystem controller performs event-specific processing for the host event referenced by the predefined sequence of bits to which the reset signal payload matches. In the illustrative example, the memory subsystem controller maintains a memory data structure (e.g., a two-dimensional array) that includes one or more host event mapping records, such that each host event mapping record maps a host event identifier (encoded by the payload of the reset signal) to a corresponding memory address that serves as an entry point to event handler code to be executed by the memory subsystem controller.

[0052] In an illustrative example, the host event code refers to a battery charging event, causing the memory sub-system to perform a cache management operation with respect to the memory sub-system cache. In another illustrative example, the host event code refers to a communication timeout expiration event, causing the memory sub-system to store at least a portion of the memory sub-system state (e.g., contents of registers and memory buffers utilized by the memory sub-system controller) on the memory device. In yet another illustrative example, the host event code refers to a programmable predefined event, causing the memory sub-system to perform event-specific processing by executing event-specific code.

[0053] In response to completing operation 630, the method terminates.

[0054] Figure 7 A flowchart of an example method implemented by a memory sub-system controller for operating in accordance with some embodiments of the disclosure, for performing cache management in response to receiving a host event notification via a reset signal. The method 700 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 700 is performed by the host event notification component 113 of FIG. 1. Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that the illustrated operations can be performed in a different order, or that some operations can be performed in parallel. Additionally, one or more operations can be omitted in some embodiments. Thus, not all of the illustrated operations are required, and other process flows are possible.

[0055] At operation 710, the memory sub-system controller receives a reset signal from the host computer system. In an illustrative example, the reset signal can be generated by a reset signal decoder circuit that generates a reset signal by latching a logic transition on an input RSTn line, as described in greater detail herein above.

[0056] At operation 720, the memory sub-system controller determines that the payload of the reset signal specifies a host battery charging event. In an illustrative example, the memory sub-system controller verifies that a signal header matches a predefined bit pattern of the reset signal, and attempts to match a payload carried by the reset signal to one of predefined bit sequences that identify respective host events, as described in greater detail herein above.

[0057] After successfully matching the reset signal payload to the predefined bit sequence corresponding to the host battery charging event, at operation 730, the memory sub-system controller performs a cache management operation with respect to the memory sub-system cache. In an illustrative example, the memory sub-system controller writes the contents of the modified cache entry to the non-volatile memory device, as described in greater detail herein above.

[0058] In an illustrative example, the reset signal payload further refers to a communication timeout expiration event, causing the memory sub-system to store at least a portion of the memory sub-system state (e.g., contents of registers and memory buffers utilized by the memory sub-system controller) on the memory device. In another illustrative example, the reset signal payload further refers to a programmable predefined event, causing the memory sub-system to perform event-specific processing by executing event-specific code.

[0059] In response to completing operation 730, the method terminates.

[0060] Figure 8 An example machine, the computer system 800, within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed, is illustrated in FIG. 8. In some embodiments, the computer system 800 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to the host event notification component 113 of FIG. 1). Figure 1 Figure 1 Figure 1 In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environments, as a peer machine in peer-to-peer (or distributed) network environments, or as a server or a client machine in a cloud computing infrastructure or environment.

[0061] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0062] ​​The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 808 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0063] Processing device 802 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 802 is configured to execute instructions 828 for performing the operations and steps discussed herein. Computer system 800 may further include a network interface device 838 for communication via network 820.

[0064] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which one or more sets of instructions 828 or software embodying any one or more of the methods or functions described herein are stored. The instructions 828 may also reside wholly or at least partially in main memory 804 and / or processing device 802 during execution by computer system 800, the main memory 804 and processing device 802 also constituting machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or main memory 804 may correspond to... Figure 1 The memory subsystem 18.

[0065] In one embodiment, instruction 828 includes instructions for implementing the corresponding Figure 1 The host event notification component 113 provides functional instructions. Although the machine-readable storage medium 824 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0066] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. The algorithms described herein generally are a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0067] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0068] The disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0069] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as shown in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0070] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0071] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory system comprising: a volatile memory device; a non-volatile memory device; a reset signal decoder circuit that receives a reset signal from a host computer system in communication with the memory system, the reset signal decoder circuit comprising a latch circuit to output a decoded reset signal at a first logic level in response to detecting a transition of the reset signal to a second logic level; a processing device operatively coupled to the volatile memory device and the non-volatile memory device, the processing device to: implement a cache of the non-volatile memory device using at least a portion of the volatile memory device; receive the decoded reset signal from the reset signal decoder circuit; determine that the decoded reset signal comprises a payload specifying a host battery charging event; and perform a cache management operation on the cache.

2. The memory system of claim 1, wherein the decoded reset signal further comprises a host event code referring to a communication timeout expiration event, and wherein the processing device is further to store at least a portion of a state of the memory system on the non-volatile memory device.

3. The memory system of claim 1, wherein the decoded reset signal further comprises a host event code referring to a debug event, and wherein the processing device is further to store at least a portion of a state of the memory system on the non-volatile memory device.

4. The memory system of claim 1, wherein the decoded reset signal includes a predefined header and the payload comprising a sequence of bits identifying the host battery charging event.

5. The memory system of claim 1, wherein receiving the reset signal is performed via a universal asynchronous receiver / transmitter (UART) interface.

6. A memory system comprising: a memory device; a reset signal decoder circuit that receives a reset signal from a host computer system in communication with the memory system, the reset signal decoder circuit comprising a latch circuit to output a decoded reset signal at a first logic level in response to detecting a transition of the reset signal to a second logic level, the latch circuit outputting the decoded reset signal at the second logic level in response to detecting a transition of a clear signal to the first logic level; and a processor operatively coupled to the reset signal decoder, the processor to: receive the decoded reset signal from the reset signal decoder circuit; identify a host event specified by the decoded reset signal; and process the identified host event.

7. The memory system of claim 6, wherein the reset signal decoder circuit further comprises a digital filter to pass reset signal pulses having at least a predetermined width.

8. The memory system of claim 6, wherein the decoded reset signal includes a predefined header and a payload comprising a sequence of bits identifying the host event.

9. The memory system of claim 6, wherein the host event specified by the decoded reset signal refers to a battery charge event, and wherein processing the host event comprises performing a cache management operation with respect to a cache associated with the memory device.

10. The memory system of claim 6, wherein the host event specified by the decoded reset signal refers to a communication timeout expiration event, and wherein processing the host event comprises storing at least a portion of a state of the memory system on the memory device.

11. The memory system of claim 6, wherein the host event specified by the decoded reset signal refers to a debug event, and wherein processing the host event comprises storing at least a portion of a state of the memory system on the memory device.

12. The memory system of claim 6, wherein the reset signal decoder circuit receives the reset signal via a universal asynchronous receiver / transmitter (UART) interface.

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