Quantum devices that facilitate the suppression of ZZ interactions between double-junction superconducting qubits

Abstract

Devices and / or computer-implemented methods are provided for assisting in static ZZ suppression and Purcell loss reduction using mode-selective coupling in a double-junction superconducting qubit. In embodiments, the device may include a superconducting bus resonator. The device may further include a first superconducting qubit. The device may further include a second superconducting qubit, the first and second superconducting qubits each comprising: a first superconducting pad; a second superconducting pad; a third superconducting pad; a first Josephson junction coupled to the first and second superconducting pads; and a second Josephson junction coupled to the second and third superconducting pads. The first and second superconducting pads of the first and second superconducting qubits are coupled to the superconducting bus resonator. The superconducting bus resonator winds the first and second superconducting qubits together based on a received control signal.

Description

Technical Field

[0001] The present invention relates to a quantum device, and more specifically, to a quantum device that facilitates the suppression of ZZ interactions between double-junction superconducting qubits (qubits). Background Technology

[0002] Even without external drivers (e.g., external microwave pulses, magnetic fields, etc.), qubits coupled via a bus exhibit residual interactions with each other. These residual interactions (called ZZ interactions) can cause the frequency of a qubit to depend on the state of its neighboring regions and can suppress the fidelity of quantum operations. Furthermore, coupling qubits to the bus via internal losses in the bus (e.g., surface losses or two-stage systems) or via external energy losses to the outside world through the bus's drive ports can contribute to energy loss and decoherence.

[0003] Some existing techniques use double-junction qubits to enable tunable coupling to the readout resonator and as a method of encoding multiple qubits in a single circuit. The problem with these existing techniques is that they do not use mode-selective coupling in multi-mode qubits to suppress static ZZ interactions between data modes, while achieving pure longitudinal coupling to the bus resonator. Summary of the Invention

[0004] The following overview is presented to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, devices, computer implementations, and / or computer program products are described that utilize mode-selective coupling in double-junction superconducting qubits to assist in static ZZ suppression and Purcell loss reduction.

[0005] According to an embodiment, a device may include a superconducting bus resonator. The device may further include a first superconducting qubit. The device may further include a second superconducting qubit, wherein the first and second superconducting qubits each include: a first superconducting pad; a second superconducting pad; a third superconducting pad; a first Josephson junction coupled to the first and second superconducting pads; and a second Josephson junction coupled to the second and third superconducting pads. The first and second superconducting pads of the first and second superconducting qubits are coupled to the superconducting bus resonator. The superconducting bus resonator causes the first and second superconducting qubits to become entangled based on a received control signal. An advantage of such a device is that it can suppress ZZ interactions between the first and second superconducting qubits in their first oscillation modes and / or increase the speed of quantum gates (e.g., entangled quantum gates) including such qubits.

[0006] In some embodiments, the first and second superconducting pads of the first and second superconducting qubits are coupled to the superconducting bus resonator to suppress ZZ interactions between the first and second superconducting qubits and to reduce energy losses associated with the superconducting bus resonator, thereby promoting at least one of the following: reduced quantum gate errors associated with at least one of the first or second superconducting qubits; increased speed of quantum gates including the first and second superconducting qubits; or at least one of improved fidelity, improved accuracy, or improved performance of the quantum processor of the device. An advantage of such a device is that it enables the development of logic qubits and / or scalable quantum computers.

[0007] According to another embodiment, a computer implementation method may include encoding quantum information in a first oscillation mode of a first superconducting qubit and a second superconducting qubit via a system operatively connected to a processor. The computer implementation method may further include coupling a superconducting bus resonator by the system to an oscillation mode structure corresponding to a second oscillation mode of the first and second superconducting qubits. An advantage of such a computer implementation method is that it can be implemented to suppress ZZ interactions between the first oscillation modes of both the first and second superconducting qubits and / or increase the speed of quantum gates (e.g., entangled quantum gates) including such qubits.

[0008] In some embodiments, the above computer implementation method may further include encoding the quantum information by the system in the first oscillation mode of the first superconducting qubit and the second superconducting qubit; and coupling the superconducting bus resonator to an oscillation mode structure corresponding to the second oscillation mode of the first superconducting qubit and the second superconducting qubit via the system to suppress ZZ interactions between the first superconducting qubit and the second superconducting qubit and to reduce energy losses associated with the superconducting bus resonator, thereby contributing to at least one of the following: reduced quantum gate errors associated with at least one of the first superconducting qubit or the second superconducting qubit; increased speed of quantum gates including the first superconducting qubit and the second superconducting qubit; or at least one of improved fidelity, improved accuracy, or improved performance of a quantum processor including the first superconducting qubit, the second superconducting qubit, and the superconducting bus resonator. An advantage of such a computer implementation method is that it can be implemented to enable the development of logical qubits and / or scalable quantum computers.

[0009] According to another embodiment, the device may include a superconducting bus resonator. The device may further include a first superconducting qubit. The device may further include a second superconducting qubit, the first and second superconducting qubits each comprising: a first superconducting pad; a second superconducting pad; a third superconducting pad; a first Josephson junction coupled to the first and second superconducting pads; and a second Josephson junction coupled to the second and third superconducting pads. The second superconducting pads of the first and second superconducting qubits are coupled to the superconducting bus resonator. The superconducting bus resonator entangles the first and second superconducting qubits based on a received control signal. An advantage of such a device is that it can suppress ZZ interactions between the first and second superconducting qubits in their first oscillation modes and / or increase the speed of quantum gates (e.g., entangled quantum gates) including such qubits.

[0010] In some embodiments, the second superconducting pads of the first and second superconducting qubits are coupled to the superconducting bus resonator to suppress ZZ interactions between the first and second superconducting qubits and to reduce energy losses associated with the superconducting bus resonator, thereby promoting at least one of the following: reduced quantum gate errors associated with at least one of the first or second superconducting qubits; increased speed of quantum gates including the first and second superconducting qubits; or improved fidelity, improved accuracy, or improved performance of the quantum processor of the device. An advantage of such a device is that it enables the development of logic qubits and / or scalable quantum computers.

[0011] According to another embodiment, a computer implementation method may include encoding quantum information in data modes of a first superconducting qubit and a second superconducting qubit via a system operatively coupled to a processor. The computer implementation method may further include coupling a superconducting bus resonator via the system to a coupling mode structure corresponding to the coupling modes of the first and second superconducting qubits. An advantage of such a computer implementation method is that it can be implemented to suppress ZZ interactions between first oscillation modes of both the first and second superconducting qubits and / or increase the speed of quantum gates (e.g., entangled quantum gates) including such qubits.

[0012] In some embodiments, the above computer implementation method may further include encoding the quantum information in data patterns of the first superconducting qubit and the second superconducting qubit by the system; and coupling the superconducting bus resonator to a coupling mode structure corresponding to the coupling modes of the first and second superconducting qubits by the system, in order to suppress ZZ interactions between the first and second superconducting qubits and to reduce energy losses associated with the superconducting bus resonator, thereby contributing to at least one of the following: reduced quantum gate errors associated with at least one of the first or second superconducting qubits; increased speed of quantum gates of the first and second superconducting qubits; or improved fidelity, improved accuracy, or improved performance of a quantum processor comprising the first superconducting qubit, the second superconducting qubit, and the superconducting bus resonator. An advantage of such a computer implementation method is that it can be implemented to enable the development of logical qubits and / or scalable quantum computers.

[0013] According to another embodiment, a device may include a first superconducting qubit and a second superconducting qubit operating in a first oscillation mode. The device may further include a superconducting bus resonator coupled to an oscillation mode structure corresponding to a second oscillation mode of the first and second superconducting qubits. An advantage of such a device is that it can suppress ZZ interactions between the first and second superconducting qubits in their first oscillation modes and / or increase the speed of quantum gates (e.g., entangled quantum gates) including such qubits.

[0014] In some embodiments, the first and second superconducting qubits operate in the first oscillation mode, and the superconducting bus resonator is coupled to an oscillation mode structure corresponding to the second oscillation mode to suppress ZZ interactions between the first and second superconducting qubits and reduce energy losses associated with the superconducting bus resonator, thereby promoting at least one of the following: reduced quantum gate errors associated with at least one of the first or second superconducting qubits; increased speed of quantum gates including the first and second superconducting qubits; or at least one of improved fidelity, improved accuracy, or improved performance of the quantum processor comprising the device. An advantage of such a device is that it enables the development of logic qubits and / or scalable quantum computers. Attached Figure Description

[0015] Figure 1A A top view of an example, non-limiting device is shown according to one or more embodiments described herein, which can assist in static ZZ suppression and Purcell loss reduction using mode-selective coupling in double-junction superconducting qubits. Figure 1B It shows Figure 1A An exemplary, non-limiting circuit diagram of the device.

[0016] Figure 2A A top view of an example, non-limiting device is shown according to one or more embodiments described herein, which can assist in static ZZ suppression and Purcell loss reduction using mode-selective coupling in double-junction superconducting qubits. Figure 2B It shows Figure 2A Example non-limiting circuit diagram of the device.

[0017] Figure 3 A top view of an exemplary, non-limiting device according to one or more embodiments described herein is shown, which can use mode-selective coupling in a double-junction superconducting qubit to facilitate static ZZ suppression and Purcell loss reduction.

[0018] Figure 4 , Figure 5 ,and Figure 6 Examples, non-limiting figures, of how mode-selective coupling in a double-junction superconducting qubit can be used to promote static ZZ suppression and Purcell loss reduction are illustrated by one or more embodiments described herein.

[0019] Figure 7 , 8 9 illustrates, according to one or more embodiments described herein, instances of non-limiting computer-implemented methods for promoting static ZZ suppression and Purcell loss reduction using mode-selective coupling in double-junction superconducting qubits.

[0020] Figure 10 A block diagram is shown that illustrates an example non-limiting operating environment that can facilitate one or more embodiments described herein. Detailed Implementation

[0021] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being limited by any express or implied information presented in the preceding background or overview or detailed description sections.

[0022] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances.

[0023] Quantum computing, for the purpose of performing computational and information processing functions, typically utilizes quantum-mechanical phenomena. It can be viewed in contrast to classical computing, which typically uses transistors to manipulate binary values. That is, while classical computers operate on bit values ​​of 0 or 1, quantum computers operate on qubits (quantum bits) that include both 0 and 1, can entangle multiple qubits, and can use interference.

[0024] In view of the problems described above using the prior art, this disclosure can be implemented to produce solutions to these problems in the form of devices and / or computer-implemented methods by using a device including a superconducting bus resonator, a first superconducting qubit, and a second superconducting qubit, which can assist in static ZZ suppression and Purcell loss reduction using mode-selective coupling in a double-junction superconducting qubit, the first superconducting qubit and the second superconducting qubit respectively including: a first superconducting pad; a second superconducting pad; a third superconducting pad; a first Josephson junction coupled to the first superconducting pad and the second superconducting pad; and a second Josephson junction coupled to the second superconducting pad and the third superconducting pad, wherein the first superconducting pad and the second superconducting qubit of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator, and wherein the superconducting bus resonator winds the first superconducting qubit and the second superconducting qubit based on a received control signal. The advantage of such devices and / or computer implementations is that they can be implemented to suppress the ZZ interaction between the first oscillation modes of the first superconducting qubit and the second superconducting qubit and / or increase the speed of quantum gates (e.g., entangled quantum gates) that include such qubits.

[0025] In some embodiments, this disclosure can be implemented as a solution to the above-described problems in the form of multiple device and / or computer implementations, wherein the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator to suppress ZZ interactions between the first and second superconducting qubits and reduce energy losses associated with the superconducting bus resonator, thereby contributing to at least one of the following: reduced quantum gate errors associated with at least one of the first or second superconducting qubits; increased speed of quantum gates including the first and second superconducting qubits; or at least one of improved fidelity, improved accuracy, or improved performance of the quantum processor including the device. An advantage of such device and / or computer implementations is that they can be implemented to enable the development of logic qubits and / or scalable quantum computers.

[0026] It will be understood that when a component is referred to as being "coupled" to another component, it can describe one or more different types of coupling, including but not limited to chemical coupling, communication coupling, electrical coupling, electromagnetic coupling, operational coupling, optical coupling, physical coupling, thermal coupling, and / or another type of coupling. It will also be understood that the following terms mentioned herein are defined as follows:

[0027] Figure 1AA top view of an example, non-limiting device 100a is shown according to one or more embodiments described herein, which can use mode-selective coupling in a double-junction superconducting qubit to promote static ZZ suppression and Purcell loss reduction. Figure 1B An example of device 100a and a non-limiting circuit diagram 100b are shown.

[0028] Device 100a may include semiconductor and / or superconducting devices that can be implemented in a quantum device. For example, device 100a may include integrated semiconductor and / or superconducting circuits (e.g., quantum circuits) that can be implemented in a quantum device, such as quantum hardware, a quantum processor, a quantum computer, and / or another quantum device. Device 100a may include semiconductor and / or superconducting devices, such as quantum coupler devices that can be implemented in such quantum devices as defined above.

[0029] like Figure 1A and 1B As illustrated in the example embodiments depicted, device 100a may include a superconducting bus resonator 102 (in... Figure 1A and 1B (represented as a resonator in the image), this superconducting bus resonator can be coupled to the first superconducting quantum bit 104a (in... Figure 1A and 1B The second superconducting quantum bit 104b is represented as the tunable coupler quantum bit (TCQ1) and the second superconducting quantum bit 104b. Figure 1A and 1B The qubit is represented as a tunable coupler (TCQ2). Figure 1A and 1B The superconducting bus resonator 102 shown in the exemplary embodiments depicted may include a coplanar waveguide resonator. Figure 1A and 1B The first superconducting quantum bit 104a and / or the second superconducting quantum bit 104b shown in the exemplary embodiments depicted may each include at least one of a tunable coupler quantum bit, a double-junction quantum bit, a multimode quantum bit, a multimode double-junction quantum bit, or a tunable quantum bit.

[0030] Figure 1A and 1BThe superconducting bus resonator 102 shown in the exemplary embodiment depicted herein may include a first superconducting pad 102a, a second superconducting pad 102b, a third superconducting pad 102c, and / or a fourth superconducting pad 102d, wherein each such superconducting pad may include an electrode. In this exemplary embodiment, each of the first superconducting pad 102a, the second superconducting pad 102b, the third superconducting pad 102c, and / or the fourth superconducting pad 102d may include a superconducting film (e.g., a superconducting metal film) formed on a substrate (e.g., a silicon (Si) substrate, etc.) using one or more semiconductor and / or superconductor device fabrication techniques described below. Figure 1B As illustrated in the exemplary embodiments depicted, the superconducting bus resonator 102 may further include an inductor 132 (in... Figure 1B The middle is represented as L R ), capacitor 134 (in Figure 1B This is represented as CR), and / or ground 136. For example... Figure 1B As shown in the exemplary embodiments depicted, the superconducting bus resonator 102 may have a resonant frequency (fr) of 6 GHz.

[0031] Figure 1A and 1B The exemplary embodiment depicted in the illustration shows a first superconducting qubit 104a that may include a first superconducting pad 106a, a second superconducting pad 108a, and / or a third superconducting pad 110a, wherein each such superconducting pad may include an electrode. In this exemplary embodiment, the first superconducting pad 106a, the second superconducting pad 108a, and / or the third superconducting pad 110a may each include a superconducting film (e.g., a superconducting metal film) formed on a substrate (e.g., a silicon (Si) substrate, etc.) using one or more semiconductor and / or superconductor device fabrication techniques described below. Figure 1A and 1B The first superconducting qubit 104a shown in the exemplary embodiment depicted may further include a first Josephson junction 112a (in Figure 1B The middle is represented as E J1 The first Josephson junction is coupled to the first superconducting pad 106a and the second superconducting pad 108a. Figure 1A and 1B The first superconducting qubit 104a shown in the exemplary embodiment depicted may further include a second Josephson junction 114a (in Figure 1B The middle is represented as E J2The second Josephson junction is coupled to the second superconducting pad 108a and the third superconducting pad 110a. In this exemplary embodiment, the first Josephson junction 112a and / or the second Josephson junction 114a may comprise one or more superconducting films (e.g., one or more superconducting metal films) and / or one or more non-superconducting films (e.g., one or more ordinary metal films) formed on a substrate (e.g., a silicon (Si) substrate, etc.).

[0032] like Figure 1A and 1B As shown in the exemplary embodiment, the first superconducting pad 106a and the second superconducting pad 108a of the first superconducting quantum bit 104a can be capacitively coupled to each other, wherein such capacitive coupling is Figure 1B The first capacitor 116a is in Figure 1B In this case, it is represented as C1). Figure 1A and 1B As shown in the exemplary embodiments depicted, the second superconducting pad 108a and the third superconducting pad 110a of the first superconducting quantum bit 104a can be capacitively coupled to each other, wherein such capacitive coupling is Figure 1B The second capacitor 118a is in Figure 1B This is represented as C2). Figure 1B In the exemplary embodiment shown, the first capacitor 116a and the second capacitor 118a represent direct capacitive shunts across the first Josephson junction 112a and the second Josephson junction 114a, respectively. In this exemplary embodiment, as Figure 1A and 1B As shown, the first superconducting quantum bit 104a may include two capacitive shunt Josephson junctions connected in series, namely the first Josephson junction 112a and the second Josephson junction 114a.

[0033] Figure 1A and 1B The second superconducting qubit 104b shown in the exemplary embodiment depicted may include a first superconducting pad 106b, a second superconducting pad 108b, and / or a third superconducting pad 110b, wherein each such superconducting pad may include an electrode. In this exemplary embodiment, each of the first superconducting pad 106b, the second superconducting pad 108b, and / or the third superconducting pad 110b may include a superconducting film (e.g., a superconducting metal film) formed on a substrate (e.g., a silicon (Si) substrate, etc.) using one or more semiconductor and / or superconductor device fabrication techniques described below. Figure 1A and 1B The second superconducting qubit 104b shown in the exemplary embodiment depicted may further include a first Josephson junction 112b (in Figure 1B The middle is represented as EJ3 The first Josephson junction is coupled to the first superconducting pad 106b and the second superconducting pad 108b. Figure 1A and 1B The second superconducting qubit 104b shown in the exemplary embodiment depicted may further include a second Josephson junction 114b (in Figure 1B The middle is represented as E J4 The second Josephson junction is coupled to the second superconducting pad 108b and the third superconducting pad 110b. In this exemplary embodiment, the first Josephson junction 112b and / or the second Josephson junction 114b may include one or more superconducting films (e.g., one or more superconducting metal films) and / or one or more non-superconducting films (e.g., one or more ordinary metal films) formed on a substrate (e.g., a silicon (Si) substrate, etc.).

[0034] like Figure 1A and 1B As illustrated in the exemplary embodiments depicted, the first superconducting pad 106b and the second superconducting pad 108b of the second superconducting quantum bit 104b can be capacitively coupled to each other, wherein such capacitive coupling occurs in… Figure 1B The middle is composed of a first capacitor 116b (in Figure 1B The Chinese character is represented as C3). For example... Figure 1A and 1B As illustrated in the exemplary embodiments depicted, the second superconducting pad 108b and the third superconducting pad 110b of the second superconducting quantum bit 104b can be capacitively coupled to each other, wherein such capacitive coupling occurs in... Figure 1B The middle is composed of a second capacitor 118b (in Figure 1B (represented as C4) Figure 1B In the exemplary embodiment shown, the first capacitor 116b and the second capacitor 118b represent direct capacitive shunts across the first Josephson junction 112b and the second Josephson junction 114b, respectively. In this exemplary embodiment, as Figure 1A and 1B As shown, the second superconducting quantum bit 104b may include two capacitive shunt Josephson junctions connected in series, a first Josephson junction 112b and a second Josephson junction 114b.

[0035] Figure 1A and 1BThe first superconducting quantum bit 104a and the second superconducting quantum bit 104b shown in the exemplary embodiments depicted herein can each operate in a first oscillation mode and a second oscillation mode (not shown). In some embodiments of the subject matter described herein, the first oscillation mode and the second oscillation mode may correspond to different (e.g., different) frequencies and / or different spatial symmetries relative to each other. In these embodiments, the first oscillation mode and the second oscillation mode may indicate a symmetric and antisymmetric combination of excitations associated with the first Josephson junction 112a and the second Josephson junction 114a of the first superconducting quantum bit 104a; and / or the first Josephson junction 112b and the second Josephson junction 114b of the second superconducting quantum bit 104b. In these embodiments, such a symmetric and antisymmetric combination of excitations associated with the first Josephson junction 112a and the second Josephson junction 114a of the first superconducting quantum bit 104a can be generated by the capacitive coupling of the first superconducting pad 106a and the third superconducting pad 110a of the first superconducting quantum bit 104a, wherein such capacitive coupling is achieved by... Figure 1B The third capacitor is represented as 120A (in Figure 1B The middle is represented as C S1 In these embodiments, this symmetric and antisymmetric combination of excitations associated with the first Josephson junction 112b and the second Josephson junction 114b of the second superconducting qubit 104b can be generated by the capacitive coupling of the first superconducting pad 106b and the third superconducting pad 110b of the second superconducting qubit 104b, wherein such capacitive coupling is in Figure 1B The third capacitor 120b is represented in the middle. Figure 1B The middle is represented as C S2 ).

[0036] exist Figure 1A and 1B In the exemplary embodiment shown, the third capacitor 120a represents the capacitive coupling between the first superconducting pad 106a and the third superconducting pad 110a of the first superconducting quantum bit 104a, wherein this capacitive coupling enables the generation of a first oscillation mode and a second oscillation mode that have different frequencies and different spatial symmetries relative to each other, as described above. In this exemplary embodiment, in Figure 1BThis capacitive coupling, denoted as the third capacitor 120a, allows the first oscillation mode and the second oscillation mode to interact with each other, wherein such modes would otherwise be isolated across the first Josephson junction 112a and the second Josephson junction 114a of the first superconducting quantum bit 104a. In this exemplary embodiment, such interaction between the first oscillation mode and the second oscillation mode can enable the generation of extended states (e.g., hybrid quantum states, hybrid oscillation modes, etc.) of the first superconducting quantum bit 104a (e.g., hybrid quantum states and / or hybrid oscillation modes corresponding to different frequencies and different spatial symmetries). In this exemplary embodiment, Figure 1B This capacitive coupling, denoted as the third capacitor 120a, allows the fundamental mode of the first superconducting qubit 104a to extend symmetrically or antisymmetrically across the first Josephson junction 112a and the second Josephson junction 114a.

[0037] exist Figure 1A and 1B In the exemplary embodiment shown, the third capacitor 120b represents the capacitive coupling between the first superconducting pad 106b and the third superconducting pad 110b of the second superconducting qubit 104b, wherein this capacitive coupling enables the generation of a first oscillation mode and a second oscillation mode that have different frequencies and different spatial symmetries relative to each other, as described above. In this exemplary embodiment, in Figure 1B This capacitive coupling, denoted as the third capacitor 120b, allows the first oscillation mode and the second oscillation mode to interact with each other, wherein such modes would otherwise be isolated across the first Josephson junction 112b and the second Josephson junction 114b of the second superconducting quantum bit 104b. In this exemplary embodiment, such interaction between the first oscillation mode and the second oscillation mode enables the creation of extended states (e.g., hybrid quantum states, hybrid oscillation modes, etc.) of the second superconducting quantum bit 104b (e.g., hybrid quantum states and / or hybrid oscillation modes corresponding to different frequencies and different spatial symmetries). In this exemplary embodiment, Figure 1B This capacitive coupling, denoted as the third capacitor 120b, allows the fundamental mode of the second superconducting qubit 104b to extend symmetrically or antisymmetrically across the first Josephson junction 112b and the second Josephson junction 114b.

[0038] The first oscillation mode and the second oscillation mode can respectively correspond to the first oscillation mode structure 124a (in... Figure 1A (represented as mode A) and the second oscillation mode structure 124b (in Figure 1A (represented as Mode B in Chinese). Figure 1A and 1BIn the exemplary embodiment shown, the first oscillation mode structure 124a and the second oscillation mode structure 124b can each define a specific coupling technique (e.g., coupling scheme, coupling arrangement, coupling pattern, etc.) that can be used to encode and / or store quantum information in the first oscillation mode of the first superconducting qubit 104a and / or the second superconducting qubit 104b. As a result, in this exemplary embodiment, the first and / or second oscillation modes of the first and / or second superconducting qubit 104a and / or the second superconducting qubit 104b can include encoded quantum information (e.g., qubit information, quantum state information, etc.). In this exemplary embodiment, the first and / or second oscillation mode structures 124a and / or 124b can be used to couple the superconducting bus resonator 102 to the first and / or second oscillation modes, such that the superconducting bus resonator 102 operates according to the first and / or second oscillation modes of the first and / or second superconducting qubit 104a and / or the second superconducting qubit 104b.

[0039] Figure 1A and 1B The exemplary embodiment depicted in the diagram shows a first superconducting quantum bit 104a and / or a second superconducting quantum bit 104b that can be capacitively coupled to a superconducting bus resonator 102. Figure 1A and 1B In the exemplary embodiment shown, the first superconducting pad 102a of the superconducting bus resonator 102 can be capacitively coupled to the first superconducting pad 106a of the first superconducting quantum bit 104a, wherein this capacitive coupling is Figure 1B The capacitor is 126a (in Figure 1B The middle is represented as C c1 (This is indicated by the symbol )). In this exemplary embodiment, the second superconducting pad 102b of the superconducting bus resonator 102 can be capacitively coupled to the second superconducting pad 108a of the first superconducting quantum bit 104a, wherein this capacitive coupling is... Figure 1B The capacitor is 128A (in Figure 1B The middle is represented as C c2 (This is indicated by the symbol )). In this exemplary embodiment, the third superconducting pad 102c of the superconducting bus resonator 102 can be capacitively coupled to the first superconducting pad 106b of the second superconducting qubit 104b, wherein this capacitive coupling is... Figure 1B The capacitor 126b is in Figure 1B The middle is represented as C c3 (This is indicated by the symbol )). In this exemplary embodiment, the fourth superconducting pad 102d of the superconducting bus resonator 102 can be capacitively coupled to the second superconducting pad 108a of the second superconducting quantum bit 104b, wherein this capacitive coupling is... Figure 1B The capacitor 128b is in Figure 1BThe middle is represented as C c4 ) is used to represent this.

[0040] In some embodiments, the superconducting bus resonator 102 may be coupled to the first superconducting qubit 104a and the second superconducting qubit 104b based on a first oscillation mode structure 124a corresponding to a first oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b (e.g., according to this first oscillation mode structure), wherein the first oscillation mode may include a coupling mode. In these embodiments, the second oscillation mode structure 124b corresponding to a second oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b may enable the encoding and / or storage of quantum information (e.g., qubit information, quantum state information, etc.) in the second oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b, wherein the second oscillation mode may include a data mode. In other embodiments, the superconducting bus resonator 102 may be coupled to the first superconducting qubit 104a and the second superconducting qubit 104b based on a second oscillation mode structure 124b (e.g., according to this second oscillation mode structure) corresponding to a second oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b, wherein the second oscillation mode may include a coupling mode. In these embodiments, the first oscillation mode structure 124a corresponding to the first oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b enables the encoding and / or storage of quantum information (e.g., qubit information, quantum state information, etc.) in the first oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b, wherein the first oscillation mode may include a data mode. As mentioned herein, such pattern coupling schemes described in the above embodiments can constitute pattern-selective coupling schemes that can be implemented by entities (e.g., humans, computing devices, software applications, agents, machine learning models, artificial intelligence models, etc.) that implement one or more embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.).

[0041] exist Figure 1A and 1B In the exemplary embodiment depicted, the superconducting bus resonator 102 can be coupled to the first superconducting quantum bit 104a and the second superconducting quantum bit 104b based on (e.g., according to) a second oscillation mode structure 124b corresponding to a second oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, wherein the second oscillation mode may include a coupling mode. Figure 1A and 1BIn this exemplary embodiment depicted, the first oscillation mode structure 124a corresponding to the first oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b enables the encoding and / or storage of quantum information (e.g., qubit information, quantum state information, etc.) in the first oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b, wherein the first oscillation mode may include a data mode.

[0042] exist Figure 1A and 1B In the exemplary embodiment shown, by encoding and / or storing quantum information in the first oscillation modes of the first and second superconducting qubits 104a and 104b simultaneously with the superconducting bus resonator 102 coupled to the first superconducting qubit 104a and 104b, based on (e.g., according to) a second oscillation mode structure 124b corresponding to the second oscillation mode, the device 100a can thereby help suppress (e.g., cancel, reduce, etc.) the direct interaction between the first oscillation modes of the first superconducting qubit 104a and the second superconducting qubit 104b. For example, in this exemplary embodiment, the device 100a can thereby help suppress (e.g., cancel, reduce, etc.) direct interactions, such as exchange interactions and / or static ZZ interactions between the first superconducting qubit 104a and the second superconducting qubit 104b (e.g., between the first oscillation modes of the first superconducting qubit 104a and the first oscillation modes of the second superconducting qubit 104b). In this exemplary embodiment, device 100a can assist in suppressing the static ZZ interaction between the first oscillation mode of the first superconducting qubit 104a and the first oscillation mode of the second superconducting qubit 104b, because a higher-order interaction exists (e.g., data mode 1 → coupling mode 1 → bus resonator → coupling mode 2 → data mode 2). For example, it can be expressed as a higher-order interaction: data mode 1 (e.g., the first oscillation mode of the first superconducting qubit 104a) → coupling mode 1 (e.g., the second oscillation mode of the first superconducting qubit 104a) → bus resonator (e.g., superconducting bus resonator 102) → coupling mode 2 (e.g., the second oscillation mode of the second superconducting qubit 104b) → data mode 2 (the first oscillation mode of the second superconducting qubit 104b).

[0043] exist Figure 1A and 1BIn the exemplary embodiment shown, by encoding and / or storing quantum information in the first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b while coupling the superconducting bus resonator 102 to the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, the device 100a can thereby further promote a strong (e.g., relatively strong) longitudinal coupling between the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (e.g., between the first oscillation mode structure 124a and the second oscillation mode structure 124b) and the second oscillation mode. In this exemplary embodiment, such strong (e.g., relatively strong) longitudinal coupling between the first superconducting quantum bit 104a and the second superconducting quantum bit 104b in the first oscillation mode and the second oscillation mode (e.g., between the first oscillation mode structure 124a and the second oscillation mode structure 124b) can achieve net longitudinal coupling between the superconducting bus resonator 102 and the first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b. In this exemplary embodiment, such net longitudinal coupling between the superconducting bus resonator 102 and the first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (also referred to as chi shift (chi_01 shift)) can enable the generation and / or performance of the dual quantum bit winding gate by driving (e.g., via microwave pulses) the superconducting bus resonator 102 detuned from its resonant frequency (e.g., 6 GHz).

[0044] Alternatively or alternatively, in Figure 1A and 1B In the exemplary embodiment shown, device 100a can further prevent exchange coupling between these data modes and superconducting bus resonator 102, which can protect such data modes from energy losses (e.g., Purcell losses) associated with superconducting bus resonator 102 (e.g., internal energy dissipation or loss to the environment outside device 100a through drive ports near superconducting bus resonator 102). For example, in Figure 1A and 1BIn the exemplary embodiment shown, device 100a can prevent: exchange coupling between the superconducting bus resonator 102 and the first oscillation mode of the first superconducting qubit 104a; and / or exchange coupling between the superconducting bus resonator 102 and the first oscillation mode of the second superconducting qubit 104b. In this exemplary embodiment, by preventing such exchange coupling between this data mode and the superconducting bus resonator 102 as described above, device 100a can thereby help reduce Purcell losses and / or reduce decoupling associated with device 100a and / or one or more of its components (e.g., superconducting bus resonator 102, first superconducting qubit 104a, second superconducting qubit 104b, etc.).

[0045] The various embodiments of this disclosure described herein and / or shown in the accompanying drawings (e.g., device 100a, device 200a, device 300, etc.) can be coupled to one or more external devices. Figure 1A or Figure 1B (Not shown in the image) to facilitate the operation of these implementations. For example, see... Figure 1A and 1B In the exemplary embodiment shown, device 100a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b can be coupled to one or more external devices that may be outside device 100a, such as pulse generator devices, power supplies, and / or magnetic field generators.

[0046] In the exemplary embodiment, although in Figure 1A Or, as not depicted in 1B, device 100a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b may be coupled to a pulse generator device, which includes, but is not limited to, an arbitrary waveform generator (AWG), a vector network analyzer (VNA), and / or another pulse generator device that may be external to device 100a and may send pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to and / or receive pulses (e.g., microwave pulses, microwave signals, control signals, etc.) from device 100a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b. In another exemplary embodiment (although in...), the superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b may be coupled to a pulse generator device that may send pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to and / or receive ... Figure 1A In (or not depicted in 1B), device 100a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b can be coupled to a power supply and / or magnetic field generator, which can be external to device 100a and can provide current, potential, and / or magnetic field to device 100a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b.

[0047] In the above example embodiments, one or more such external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), power supplies and / or magnetic field generators) may also be coupled to a computer (e.g., hereinafter referred to as...). Figure 10 The computer 1012 described includes a memory (e.g., hereinafter referred to as memory) on which instructions (e.g., software, routines, processing threads, etc.) can be stored. Figure 10 The system memory 1016 described herein and the processor capable of executing such instructions that can be stored in the memory (e.g., the following reference) Figure 10 The processing unit 1014 described herein. In these exemplary embodiments, such a computer can be used to operate and / or control (e.g., by executing instructions stored in system memory 1016 by the processing unit 1014) one or more external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), power supplies, and / or magnetic field generators). For example, in these exemplary embodiments, such a computer can be used to enable one or more external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), power supplies, and / or magnetic field generators) to: a) transmit and / or receive pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to and / or from device 100a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b); and / or b) provide current, potential, and / or magnetic field to device 100a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b.

[0048] In various embodiments, the entity implementing device 100a (e.g., an entity such as a human, computing device, software application, agent, machine learning model, artificial intelligence model, etc.) may implement one or more mode-selective coupling schemes described herein according to one or more embodiments of this disclosure (e.g., Figure 1A , 1B(The mode-selective coupling schemes described and illustrated in 2A, 2B and / or 3). In these embodiments, such an entity can implement one or more such mode-selective schemes by setting and / or adjusting one or more coupling capacitors between the superconducting bus resonator 102 and one or more superconducting pads of the first superconducting qubit 104a and / or the second superconducting qubit 104b. In these embodiments, such an entity can set and / or adjust one or more coupling capacitors (e.g., the coupling capacitances of capacitors 126a, 126b, 128a and / or 128b) by applying and / or adjusting (e.g., via one or more of the external devices defined above and / or the computer 1012 as described above) applied to device 100a and / or one or more of its components (e.g., the superconducting bus resonator 102, the first superconducting qubit 104a, the second superconducting qubit 104b, etc.)

[0049] exist Figure 1A and 1B In the exemplary embodiments shown, such entities as defined above can be set and / or adjusted to represent capacitors 126a, 126b, 128a, and / or Figure 1B The coupling capacitance of capacitor 128b in the device is applied and / or adjusted (e.g., via one or more of the external devices defined above and / or the computer 1012 as described above) to the device 100a and / or one or more of its components (e.g., superconducting bus resonator 102, first superconducting quantum bit 104a, second superconducting quantum bit 104b, etc.) by applying and / or adjusting (e.g., via one or more of the external devices defined above and / or the computer 1012 as described above). In this exemplary embodiment, based on setting and / or adjusting the coupling capacitance described above, an entity as defined herein can thereby implement the mode-selective coupling scheme described above, wherein: the superconducting bus resonator 102 can be coupled to the first superconducting quantum bit 104a and the second superconducting quantum bit 104b based on a second oscillation mode structure 124b corresponding to a second oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (e.g., according to the second oscillation mode structure), wherein the second oscillation mode includes a coupling mode; and / or quantum information (e.g., quantum bit information, quantum state information, etc.) can be encoded and / or stored based on (e.g., according to) the first oscillation mode structure 124a in a first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, wherein the first oscillation mode can include a data mode.

[0050] In this exemplary embodiment, to achieve net exchange coupling of the superconducting bus resonator 102 only with the second oscillation modes of the first superconducting qubit 104a and the second superconducting qubit 104b (e.g., net exchange coupling of the superconducting bus resonator 102 only with the second oscillation mode structure 124b corresponding to the second oscillation modes of the first superconducting qubit 104a and the second superconducting qubit 104b), such entities as defined herein may be configured and / or adjusted with such coupling capacitance as follows: capacitor 126a = 2 * capacitor 128a (e.g., C c1 =2*C c2 ) and capacitor 126b = 2 * capacitor 128b (e.g., C c3 =2*C c4 ).

[0051] In the above embodiments, based on implementing the mode-selective coupling scheme described above, the entity implementing device 100a can thereby assist in: a) suppressing (e.g., canceling, reducing, etc.) direct interactions, such as exchange interactions and / or static ZZ interactions (e.g., canceling, reducing, etc.) between the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (between the first oscillation mode of the first superconducting quantum bit 104a and the first oscillation mode of the second superconducting quantum bit 104b, wherein the first oscillation mode and the second oscillation mode may include the data modes of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b). a) strong (e.g., relatively strong) longitudinal coupling of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b between the first oscillation mode and the second oscillation mode (e.g., between the first oscillation mode structure 124a and the second oscillation mode structure 124b); and / or c) preventing exchange coupling between these data modes (e.g., between the first oscillation mode and the second oscillation mode) and the superconducting bus resonator 102, which can reduce energy losses (e.g., Purcell losses) and / or decoherence associated with device 100a and / or superconducting bus resonator 102. In this embodiment, based on such suppression of such static ZZ interactions, reduced energy loss associated with the superconducting bus resonator 102, and / or reduced decoupling, device 100a can thereby assist in: reduced quantum gate errors associated with the first superconducting quantum bit 104a and / or the second superconducting quantum bit 104b; increased speed of quantum gates including the first superconducting quantum bit 104a and the second superconducting quantum bit 104b; and / or at least one of improved fidelity, improved accuracy, or improved performance of the quantum processor including device 100a.

[0052] In the above embodiments, the entity of the implementation device 100a as defined herein can further drive (e.g., via microwave pulses using one or more of the external devices and / or computer 1012 as defined above) a superconducting bus resonator 102 detuned from its resonant frequency (e.g., 6 GHz) to generate and / or execute a two-qubit entangled gate via a RIP gate. For example, in this embodiment, by driving the superconducting bus resonator 102 detuned from its resonant frequency (as described above), such an entity can entangle the first superconducting qubit 104a with the second superconducting qubit 104b (e.g., to generate an entangled quantum gate between the first superconducting qubit 104a and the second superconducting qubit 104b). In this embodiment, such entanglement of the first superconducting qubit 104a with the second superconducting qubit 104b enables quantum gate operations to be performed between the first superconducting qubit 104a and the second superconducting qubit 104b. For example, in this embodiment, based on a superconducting bus resonator 102 driven to detune from its resonant frequency, device 100a and / or superconducting bus resonator 102 can operate as a RIP gate that can generate ZZ interactions between a first qubit (e.g., a first superconducting qubit 104a) and a second qubit (e.g., a second superconducting qubit 104b), which are present when there is microwave drive (e.g., microwave pulse, microwave signal, control signal, etc.) at the superconducting bus resonator 102 (e.g., when there is a microwave signal applied to the superconducting bus resonator 102).

[0053] Fabrication of the various embodiments disclosed herein and / or in the accompanying drawings (e.g., device 100a, device 200a, device 300, etc.) may include a multi-step sequence of steps, such as photolithography and / or chemical processing steps, which facilitate the stepwise creation of electronic-based systems, devices, components, and / or circuits in semiconductor and / or superconducting devices (e.g., integrated circuits). For example, various embodiments of the present disclosure described herein and / or shown in the accompanying drawings (e.g., device 100a, device 200a, device 300, etc.) can be fabricated on a substrate (e.g., a silicon (Si) substrate, etc.) by employing techniques including, but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomask technology, patterning technology, photoresist technology (e.g., positive photoresist, negative photoresist, hybrid photoresist, etc.), etching technology (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), evaporation technology, sputtering technology, plasma ashing technology, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), back polishing technology and / or another technology for fabricating integrated circuits.

[0054] Various materials can be used to manufacture the various embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., device 100a, device 200a, device 300, etc.). For example, the various embodiments of this disclosure described herein and / or illustrated in the figures (e.g., device 100a, device 200a, device 300, etc.) can be manufactured using one or more different material classes, including but not limited to: conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, non-conductive materials, and / or another material that can be used in conjunction with one or more of the techniques described above for manufacturing integrated circuits.

[0055] Figure 2A A top view of an example, non-limiting device 200a is shown according to one or more embodiments described herein, which can assist in static ZZ suppression and Purcell loss reduction using mode-selective coupling in a double-junction superconducting qubit. Figure 2B An example non-limiting circuit diagram 200b of device 200a is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes used in the corresponding embodiments are omitted.

[0056] Device 200a may include the above-mentioned references. Figure 1A and 1BExamples and non-limiting alternative embodiments of the described device 100a. For example, such as... Figure 2A and 2B The exemplary embodiment shown illustrates that device 200a may include an exemplary, non-limiting alternative embodiment of device 100a, wherein only the second superconducting pad 108a of the first superconducting quantum bit 104a and the second superconducting pad 108b of the second superconducting quantum bit 104b are coupled to the third superconducting pad 102c and the fourth superconducting pad 102d of the superconducting bus resonator 102. Alternatively or alternatively, such as Figure 2B As shown in the exemplary embodiments depicted herein, the superconducting bus resonator 102 of device 200a can have a resonant frequency (fr) of 4 GHz.

[0057] like Figure 2A and 2B As shown in the exemplary embodiment, the second superconducting pad 108a of the first superconducting quantum bit 104a can be capacitively coupled to the third superconducting pad 102c of the superconducting bus resonator 102, wherein this capacitive coupling is Figure 2B The first capacitor 228a is in Figure 2B The middle is represented as C c1 (This is indicated by the symbol )). In this exemplary embodiment, the second superconducting pad 108b of the second superconducting quantum bit 104b can be capacitively coupled to the fourth superconducting pad 102d of the superconducting bus resonator 102, wherein such capacitive coupling is... Figure 2B The second capacitor 228b is in Figure 2B The middle is represented as C c2 )express.

[0058] See above. Figure 1A and 1B As described, in some embodiments, the superconducting bus resonator 102 may be coupled to the first superconducting qubit 104a and the second superconducting qubit 104b based on (e.g., according to) a first oscillation mode structure 124a corresponding to a first oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b, wherein the first oscillation mode may include a coupling mode. In these embodiments, the second oscillation mode structure 124b corresponding to a second oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b may enable the encoding and / or storage of quantum information (e.g., qubit information, quantum state information, etc.) in the second oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b, wherein the second oscillation mode may include a data mode.

[0059] exist Figure 2A and 2BIn the exemplary embodiment shown, the superconducting bus resonator 102 can be coupled to the first superconducting quantum bit 104a and the second superconducting quantum bit 104b based on (e.g., according to) a first oscillation mode structure 124a corresponding to a first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, wherein the first oscillation mode may include a coupling mode. Figure 2A and 2B In this exemplary embodiment shown, the second oscillation mode structure 124b corresponding to the second oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b enables the encoding and / or storage of quantum information (e.g., qubit information, quantum state information, etc.) in the second oscillation mode of the first superconducting qubit 104a and the second superconducting qubit 104b, wherein the second oscillation mode may include a data mode.

[0060] exist Figure 2A and 2B In the exemplary embodiment shown, by coupling the superconducting bus resonator 102 to the first superconducting qubit 104a and the second superconducting qubit 104b based on (e.g., according to) a first oscillation mode structure 124a corresponding to the first oscillation mode, while encoding and / or storing quantum information in the second oscillation modes of the first superconducting qubit 104a and the second superconducting qubit 104b, the device 200a can thereby assist in suppressing (e.g., canceling, reducing, etc.) the direct interaction between the second oscillation modes of the first superconducting qubit 104a and the second superconducting qubit 104b. For example, in this exemplary embodiment, the device 200a can thereby assist in suppressing (e.g., canceling, reducing, etc.) direct interactions, such as exchange interactions and / or static ZZ interactions between the first superconducting qubit 104a and the second superconducting qubit 104b (e.g., between the second oscillation modes of the first superconducting qubit 104a and the second superconducting qubit 104b). In this exemplary embodiment, device 200a can help suppress the static ZZ interaction between the second oscillation mode of the first superconducting qubit 104a and the second oscillation mode of the second superconducting qubit 104b, because there is a higher-order interaction (e.g., data mode 1 → coupling mode 1 → bus resonator → coupling mode 2 → data mode 2). For example, it can be expressed as a higher-order interaction: data mode 1 (e.g., the second oscillation mode of the first superconducting qubit 104a) → coupling mode 1 (e.g., the first oscillation mode of the first superconducting qubit 104a) → bus resonator (e.g., superconducting bus resonator 102) → coupling mode 2 (e.g., the first oscillation mode of the second superconducting qubit 104b) → data mode 2 (the second oscillation mode of the second superconducting qubit 104b).

[0061] exist Figure 2Aand 2B In the exemplary embodiment shown, by coupling the superconducting bus resonator 102 to the first superconducting quantum bit 104a and the second superconducting quantum bit 104b based on (e.g., according to) a first oscillation mode structure 124a corresponding to the first oscillation mode, while encoding and / or storing quantum information in the second oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, the device 200a can thereby further assist in the strong (e.g., relatively strong) longitudinal coupling between the first superconducting quantum bit 104a and the second superconducting quantum bit 104b between the first oscillation mode and the second oscillation mode (e.g., between the first oscillation mode structure 124a and the second oscillation mode structure 124b). In this exemplary embodiment, the strong (e.g., relatively strong) longitudinal coupling between the first superconducting quantum bit 104a and the second superconducting quantum bit 104b in the first oscillation mode and the second oscillation mode (e.g., between the first oscillation mode structure 124a and the second oscillation mode structure 124b) can achieve a net longitudinal coupling between the superconducting bus resonator 102 and the second oscillation modes of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b. In this exemplary embodiment, this net longitudinal coupling (also referred to as chi-shift (chi_01 shift)) between the superconducting bus resonator 102 and the second oscillation modes of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b can be achieved by driving (e.g., via microwave pulses) the superconducting bus resonator 102 detuned from its resonant frequency (e.g., 4 GHz) to achieve the generation and / or performance of a two-qubit winding gate via a RIP gate.

[0062] Alternatively or alternatively, in Figure 2A and 2B In the exemplary embodiment shown, device 200a can further prevent exchange coupling between the data mode and the superconducting bus resonator 102, which can protect such data modes from energy losses (e.g., Purcell losses) associated with the superconducting bus resonator 102 (e.g., internal energy dissipation or energy loss to the environment outside device 200a via the drive port near the superconducting bus resonator 102). For example, in Figure 2A and 2BIn the exemplary embodiment shown, device 200a can prevent: exchange coupling between the second oscillation mode of the superconducting bus resonator 102 and the first superconducting qubit 104a; and / or exchange coupling between the second oscillation mode of the superconducting bus resonator 102 and the second superconducting qubit 104b. In this exemplary embodiment, by preventing such exchange coupling between this data mode and the superconducting bus resonator 102 as described above, device 200a can thereby help reduce Purcell losses and / or reduce decoupling associated with device 200a and / or one or more of its components (e.g., the superconducting bus resonator 102, the first superconducting qubit 104a, the second superconducting qubit 104b, etc.).

[0063] See above. Figure 1A and 1B The various embodiments described herein and / or shown in the accompanying drawings (e.g., device 100a, device 200a, device 300, etc.) can be coupled to one or more external devices. Figure 2A (or not shown in 2B) to facilitate the operation of such embodiments. For example, see Figure 2A and 2B In the exemplary embodiment shown, device 200a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b can be coupled to one or more external devices that can be outside device 100a, such as pulse generator devices, power supplies, and / or magnetic field generators.

[0064] In exemplary embodiments, although in Figure 2A As not depicted in 2B, device 200a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b may be coupled to a pulse generator device (e.g., AWG, VNA, etc.) that is external to device 200a and can transmit pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to and / or receive pulses (e.g., microwave pulses, microwave signals, control signals, etc.) from and from device 200a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b. In another example embodiment, although in Figure 2AAs not depicted in 2B, device 200a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b may be coupled to a power supply and / or magnetic field generator, which may be external to device 200a and may provide current, potential, and / or magnetic field to device 200a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b.

[0065] In the above example embodiments, one or more such external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), power supplies and / or magnetic field generators) may also be coupled to a computer (e.g., hereinafter referred to as...). Figure 10 The computer 1012 described includes a memory (e.g., hereinafter referred to as memory) on which instructions (e.g., software, routines, processing threads, etc.) can be stored. Figure 10 The system memory 1016 described herein and the processor capable of executing such instructions that can be stored in the memory (e.g., the following reference) Figure 10 The processing unit 1014 described. In these exemplary embodiments, such a computer can be used to operate and / or control (e.g., by executing instructions stored in system memory 1016 by the processing unit 1014) one or more external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), power supplies and / or magnetic field generators). For example, in these exemplary embodiments, such a computer can be used to enable one or more external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), power supplies and / or magnetic field generators) to: a) send and / or receive pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to and / or from device 200a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b; and / or b) provide current, potential, and / or magnetic field to device 200a, superconducting bus resonator 102, first superconducting quantum bit 104a, and / or second superconducting quantum bit 104b).

[0066] In different embodiments, the implementation device 200a is as described above. Figure 1A and 1B The defined entities can implement one or more mode-selective coupling schemes described herein according to one or more embodiments of this disclosure (e.g., in...). Figure 1A , 1B(The mode-selective coupling schemes described and illustrated in 2A, 2B and / or 3). In these embodiments, such an entity can implement one or more such mode-selective schemes by setting and / or adjusting one or more coupling capacitors between the superconducting bus resonator 102 and one or more superconducting pads of the first superconducting qubit 104a and / or the second superconducting qubit 104b. In these embodiments, such an entity can set and / or adjust one or more coupling capacitors (e.g., via one or more external devices and / or computer 1012 as defined above) applied to the device 200a and / or one or more of its components (e.g., superconducting bus resonator 102, first superconducting qubit 104a, second superconducting qubit 104b, etc.) by applying and / or adjusting magnetic fields, currents, potentials, and / or microwave pulses applied to the device 200a and / or one or more of its components (e.g., superconducting bus resonator 102, first superconducting qubit 104a, second superconducting qubit 104b, etc.). Figure 1B The coupling capacitance of capacitor 228a and / or capacitor 228b of device 200a shown.

[0067] exist Figure 2A and 2B In the exemplary embodiment shown, such an entity as defined herein can be set and / or adjusted by applying and / or adjusting (e.g., via one or more of the external devices defined above and / or computer 1012) magnetic fields, currents, potentials, and / or microwave pulses applied to device 200a and / or one or more of its components (e.g., superconducting bus resonator 102, first superconducting quantum bit 104a, second superconducting quantum bit 104b, etc.) to form a magnetic field, current, potential, and / or microwave pulse. Figure 2B The coupling capacitance of capacitors 228a and / or 228b in the example embodiment. Based on setting and / or adjusting such coupling capacitance, an entity as defined herein can thereby implement the above-described mode-selective coupling scheme, wherein: the superconducting bus resonator 102 can be coupled to the first superconducting quantum bit 104a and the second superconducting quantum bit 104b based on (e.g., according to) a first oscillation mode structure 124a corresponding to a first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, wherein the first oscillation mode includes a coupling mode; and / or quantum information (e.g., quantum bit information, quantum state information, etc.) can be encoded and / or stored in a second oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b based on (e.g., according to) a second oscillation mode structure 124b, wherein the second oscillation mode can include a data mode.

[0068] In the above embodiments, based on implementing the mode-selective coupling scheme described above, the entity implementing device 200a can thereby assist in: a) suppressing (e.g., canceling, reducing, etc.) direct interactions, such as exchange interactions and / or static ZZ phases between the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (e.g., between the second oscillation mode of the first superconducting quantum bit 104a and the second oscillation mode of the second superconducting quantum bit 104b, wherein the first oscillation mode and the second oscillation mode may include the data modes of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b). The interaction; b) strong (e.g., relatively strong) longitudinal coupling of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b between the first oscillation mode and the second oscillation mode (e.g., between the first oscillation mode structure 124a and the second oscillation mode structure 124b); and / or c) preventing exchange coupling between these data modes (e.g., between the first oscillation mode and the second oscillation mode) and the superconducting bus resonator 102, which can reduce energy losses (e.g., Purcell losses) and / or de-dissociation associated with device 200a and / or superconducting bus resonator 102. In this embodiment, based on such suppression of such static ZZ interactions, reduced energy loss associated with the superconducting bus resonator 102, and / or reduced decoupling, device 200a may thereby facilitate: reduced quantum gate errors associated with the first superconducting quantum bit 104a and / or the second superconducting quantum bit 104b; increased speed of the quantum gate including the first superconducting quantum bit 104a and the second superconducting quantum bit 104b; and / or at least one of improved fidelity, improved accuracy, or improved performance of the quantum processor including device 200a.

[0069] In the above embodiments, the entity of the implementation device 200a as defined herein can further drive (e.g., using one or more of the external devices and / or computer 1012 as defined above, via microwave pulses) a superconducting bus resonator 102 detuned from its resonant frequency (e.g., 4 GHz) to generate and / or execute a two-qubit entangled gate via a RIP gate. For example, in this embodiment, by driving the superconducting bus resonator 102 detuned from its resonant frequency (as described above), such an entity can entangle the first superconducting qubit 104a with the second superconducting qubit 104b (e.g., to generate an entangled quantum gate between the first superconducting qubit 104a and the second superconducting qubit 104b). In this embodiment, such entanglement of the first superconducting qubit 104a with the second superconducting qubit 104b enables quantum gate operations to be performed between the first superconducting qubit 104a and the second superconducting qubit 104b. For example, in this embodiment, based on a superconducting bus resonator 102 driven to detune from its resonant frequency, device 200a and / or superconducting bus resonator 102 can operate as a RIP gate that can generate ZZ interaction between a first qubit (e.g., a first superconducting qubit 104a) and a second qubit (e.g., a second superconducting qubit 104b) when microwave drive (e.g., microwave pulse, microwave signal, control signal, etc.) is present at the superconducting bus resonator 102 (e.g., when a microwave signal is applied to the superconducting bus resonator 102).

[0070] Figure 3 A top view of an exemplary, non-limiting device 300 according to one or more embodiments described herein is shown, which can use mode-selective coupling in a double-junction superconducting qubit to facilitate static ZZ suppression and Purcell loss reduction. For brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0071] Device 300 may include the above-mentioned components. Figure 2A and 2B Examples and non-limiting alternative embodiments of the device 200a described herein, wherein the first readout resonator 302a (in) Figure 3 (represented as R) can be coupled to the first superconducting quantum bit 104a and the second readout resonator 302b (in Figure 3 The qubit (denoted as R) can be coupled to the second superconducting qubit 104b. For example, as shown in the figure... Figure 3As shown in the exemplary embodiments, the first readout resonator 302a can be coupled (e.g., capacitively coupled) to the first superconducting pad 106a of the first superconducting quantum bit 104a via the first coupling pad 304a of the device 300, and the second readout resonator 302b can be coupled (e.g., capacitively coupled) to the first superconducting pad 106b of the second superconducting quantum bit 104b via the second coupling pad 304b of the device 300. Figure 3 In the exemplary embodiment shown, the first sense resonator 302a and / or the second sense resonator 302b can facilitate (e.g., via the above reference) Figure 1A-2B One or more external devices and / or computer 1012 as defined above may read one or more types of information (e.g., quantum information, qubit information, quantum state information, etc.) from device 300.

[0072] As in Figure 3 As shown in the exemplary embodiments depicted, device 300 may further include a third coupling pad 304c and / or a fourth coupling pad 304d, which can assist in the coupling (e.g., capacitive coupling) of one or more devices (not shown) to device 300 (e.g., coupling of one or more devices to the second superconducting pad 108a of the first superconducting quantum bit 104a and / or the second superconducting pad 108b of the second superconducting quantum bit 104b). In different embodiments, the first coupling pad 304a, the second coupling pad 304b, the third coupling pad 304c, and / or the fourth coupling pad 304d may include a superconducting film (e.g., a superconducting metal film), which may use the methods described above. Figure 1A and 1B The semiconductor and / or superconductor device is formed on a substrate (e.g., a silicon (Si) substrate, etc.) using one or more semiconductor and / or superconductor device fabrication techniques as described.

[0073] Figure 4 An example non-limiting pattern 400 according to one or more embodiments described herein is shown, which can be used with mode-selective coupling in a double-junction superconducting qubit to facilitate static ZZ suppression and Purcell loss reduction. For brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0074] Figure 400 may include resulting data from one or more embodiments implementing the subject matter described herein. For example, Figure 400 may include device 200a and / or device 300 (e.g., referred to below) according to one or more embodiments of the subject matter disclosed herein, based on implementations (e.g., simulation, quantization, etc.). Figure 7 , Figure 8 and Figure 9The resulting data generated by the computer implementation methods 700, 800 and / or 900, respectively.

[0075] exist Figure 4 In the exemplary embodiment shown, pattern 400 may include a second oscillation mode of the first superconducting quantum bit 104a (in the first superconducting quantum bit 104a) as a function of the frequencies of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b. Figure 4 The second oscillation mode of the second superconducting quantum bit 104b (represented as TCQ1) and the second superconducting quantum bit 104b (in) Figure 4 The ZZ interactions between (represented as TCQ2) are (e.g., the static ZZ interactions of ZZ:TCQ-TCQ). Figure 4 Numerical simulations of the ZZ interaction (B mode) as described above. In this exemplary embodiment, graph 400 may include numerical simulations of the ZZ interaction as described above, wherein quantum information (e.g., qubit information, quantum state information, etc.) may be encoded and / or stored as described above. Figure 2A and 2B The second oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b is described (e.g., where the second oscillation mode includes the data modes of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b). In this exemplary embodiment, the figure 400 may include a numerical simulation of the ZZ interaction described above, wherein the superconducting bus resonator 102 may be coupled only to the first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (e.g., coupled only to the first oscillation mode structure 124a corresponding to the first oscillation modes of both the first superconducting quantum bit 104a and the second superconducting quantum bit 104b).

[0076] As in Figure 4 As shown in the exemplary embodiment of the figure 400 depicted: the frequency of the second oscillation mode of the first superconducting qubit 104a is expressed in gigahertz (GHz), and along the X-axis of the figure 400 (in Figure 4 The frequency of the second oscillation mode of the second superconducting quantum bit 104b is expressed in GHz and extended along the Y-axis of Figure 400 (in... Figure 4 The frequency is represented as TCQ2fB (GHz); and the ZZ interaction frequency is expressed in kilohertz (kHz). Figure 4 This is represented as Log10(ZZ(kHz)), and is derived from... Figure 4 The frequency represented in the ZZ legend shown is indicated by shading in the Z-axis of Figure 400 (e.g., the axis of Figure 400 extending inside and outside the page).

[0077] exist Figure 4In the exemplary embodiment shown, pattern 400 may include a numerical simulation of the ZZ interaction described above, wherein the capacitance of capacitor 228a = the capacitance of capacitor 228b = 10 femtofarads (fF), and the resonant frequency (fr) of superconducting bus resonator 102 is 4 GHz. In this exemplary embodiment, pattern 400 may include a numerical simulation of the ZZ interaction described above, which can be achieved by changing the critical current of the first superconducting qubit 104a and the second superconducting qubit 104b from approximately 20 nanoamperes (nA) (e.g., via the above-mentioned reference). Figure 1A and 1B (and / or one or more of these external devices as defined by computer 1012) to obtain approximately 30 nA, wherein for each of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, there is a 5 percentage point (%) asymmetry between current I1 and current I2. Figure 4 As shown in Figure 400, when device 200a and / or device 300 are implemented according to the parameters defined above, the ZZ interaction (e.g., static ZZ interaction) between the second oscillation mode of the first superconducting quantum bit 104a and the second oscillation mode of the second superconducting quantum bit 104b is less than 1 kHz, and therefore it should be understood that such ZZ interaction is suppressed, canceled and / or effectively absent under such conditions.

[0078] Figure 5 An example non-limiting pattern 500 according to one or more embodiments described herein is shown, which can use mode-selective coupling in a double-junction superconducting qubit to facilitate static ZZ suppression and Purcell loss reduction. For brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0079] Graph 500 may include result data generated from implementing one or more embodiments of the present disclosure described herein. For example, Graph 500 may include device 200a and / or device 300 (e.g., referred to below respectively) from implementing (e.g., simulation, quantization, etc.) one or more embodiments of the subject matter disclosed herein. Figure 7 , 8 The resulting data generated by the computer implementation methods 700, 800 and / or 900 described in 9.

[0080] exist Figure 5 In the exemplary embodiment shown, graph 500 may include a numerical simulation of the aforementioned net longitudinal coupling between the superconducting bus resonator 102 and the second oscillation mode of the first superconducting quantum bit 104a, as a function of the frequencies of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, referred to as chi-shift (in Figure 5(represented as chi01). In this exemplary embodiment, graph 500 may include a numerical simulation of the net longitudinal coupling (chi shift) described above, wherein quantum information (e.g., qubit information, quantum state information, etc.) may be encoded and / or stored as described above. Figure 2A and 2B The second oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b is described (e.g., where the second oscillation mode includes the data modes of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b). In this exemplary embodiment, the figure 500 may include a numerical simulation of the net longitudinal coupling (chi shift) described above, wherein the superconducting bus resonator 102 may be coupled only to the first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (e.g., coupled only to the first oscillation mode structure 124a corresponding to the first oscillation modes of both the first superconducting quantum bit 104a and the second superconducting quantum bit 104b).

[0081] As in Figure 5 As shown in the exemplary embodiment of the figure 500 depicted: the frequency of the second oscillation mode of the first superconducting quantum bit 104a is expressed in GHz and extends along the X-axis of the figure 500 (in Figure 5 The frequency of the second oscillation mode of the second superconducting quantum bit 104b is expressed in GHz and extended along the Y-axis of Figure 500 (in Figure 5 The TCQ2fB (GHz) is used in this context; and the net longitudinal coupling (chi-shift) frequency is expressed in megahertz (MHz). Figure 5 The value is represented as chi01 (MHz), and is derived from... Figure 5 The frequency represented in the chi01 legend is indicated by shading in the Z-axis of graph 500 (e.g., the axis of graph 500 extending into and from the page).

[0082] exist Figure 5 In the exemplary embodiment shown, pattern 500 may include a numerical simulation of the net longitudinal coupling (chi shift) described above, wherein the capacitance of capacitor 228a = the capacitance of capacitor 228b = 10 fF, and the resonant frequency (fr) of superconducting bus resonator 102 is 4 GHz. In this exemplary embodiment, pattern 500 may include a numerical simulation of the net longitudinal coupling (chi shift) described above, which can be achieved by varying the critical currents of the first superconducting qubit 104a and the second superconducting qubit 104b from approximately 20 nA (e.g., via the above-mentioned reference). Figure 1A and 1BThe current is obtained by using one or more external devices and / or a computer (1012) to a current of approximately 30 nA, wherein for each of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, there is a 5 percentage point (%) asymmetry between current I1 and current I2. (See above) Figure 2A and 2B As described and as Figure 5 As shown in Figure 500, although devices 200a and / or 300 can prevent exchange coupling between the second oscillation modes of the superconducting bus resonator 102 and the first superconducting qubit 104a and the second superconducting qubit 104b, devices 200a and / or 300 can enable a large (e.g., relatively large) net longitudinal coupling (chi shift) between the second oscillation modes of the superconducting bus resonator 102 and the first superconducting qubit 104a.

[0083] Figure 6 An example non-limiting pattern 600 according to one or more embodiments described herein is shown, which can be used with mode-selective coupling in a double-junction superconducting qubit to facilitate static ZZ suppression and Purcell loss reduction. For brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0084] Graph 600 may include result data generated from implementing one or more embodiments of the present disclosure described herein. For example, Graph 600 may include device 200a and / or device 300 (e.g., referred to below respectively) from implementing (e.g., simulation, quantization, etc.) one or more embodiments of the subject matter disclosed herein. Figure 7 , 8 The resulting data generated by the computer implementation methods 700, 800 and / or 900 described in 9.

[0085] exist Figure 6 In the exemplary embodiment shown, graph 600 may include a numerical simulation based on the frequencies of the first superconducting qubit 104a and the second superconducting qubit 104b, the net longitudinal coupling referred to as the chi-shift of the aforementioned net longitudinal coupling between the superconducting bus resonator 102 and the second oscillation mode of the second superconducting qubit 104b (in Figure 6 (represented as chi01). In this exemplary embodiment, graph 600 may include a numerical simulation of the net longitudinal coupling (chi shift) described above, wherein quantum information (e.g., qubit information, quantum state information, etc.) may be encoded and / or stored as described above. Figure 2A and 2BThe second oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b is described (e.g., where the second oscillation mode includes the data modes of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b). In this exemplary embodiment, Figure 600 may include the above-described numerical simulation of net longitudinal coupling (chi shift), wherein the superconducting bus resonator 102 may be coupled only to the first oscillation mode of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (e.g., coupled only to the first oscillation mode structure 124a corresponding to the first oscillation modes of both the first superconducting quantum bit 104a and the second superconducting quantum bit 104b).

[0086] As in Figure 6 The exemplary embodiment of the figure 600 depicted shows that the frequency of the second oscillation mode of the first superconducting quantum bit 104a is expressed in GHz and extends along the X-axis of the figure 600 (in... Figure 6 The frequency of the second oscillation mode of the second superconducting quantum bit 104b is expressed in GHz and extended along the Y-axis of graph 600 (in Figure 6 The TCQ2fB (GHz) is used in this context; and the net longitudinal coupling (chi-shift) frequency is expressed in megahertz (MHz). Figure 6 The value is represented as chi01 (MHz), and is derived from... Figure 6 The frequency represented in the chi01 legend is indicated by shading in the Z-axis of graph 600 (e.g., the axis of graph 600 extending into and from the page).

[0087] exist Figure 6 In the exemplary embodiment shown, pattern 600 may include the numerical simulation of the net longitudinal coupling (chi shift) described above, wherein the capacitance of capacitor 228a = the capacitance of capacitor 228b = 10 fF, and the resonant frequency (fr) of superconducting bus resonator 102 is 4 GHz. In this exemplary embodiment, pattern 600 may include the numerical simulation of the net longitudinal coupling (chi shift) described above, which can be achieved by varying the critical currents of the first superconducting qubit 104a and the second superconducting qubit 104b from approximately 20 nA (e.g., via the above-mentioned reference). Figure 1A and 1B The current is obtained by using one or more external devices and / or a computer (1012) to a current of approximately 30 nA, wherein for each of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b, there is a 5 percentage point (%) asymmetry between current I1 and current I2. (See above) Figure 2A and 2B As described and as Figure 6As shown in Figure 600, although devices 200a and / or 300 can prevent exchange coupling between the second oscillation modes of the superconducting bus resonator 102 and the first superconducting qubit 104a and the second superconducting qubit 104b, devices 200a and / or 300 can enable a large (e.g., relatively large) net longitudinal coupling (chi shift) between the second oscillation modes of the superconducting bus resonator 102 and the second superconducting qubit 104b.

[0088] The various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) can be associated with various technologies. For example, the different embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) can be associated with quantum computing technology, quantum gate technology, quantum coupler technology, quantum hardware and / or software technology, quantum circuit technology, superconducting circuit technology, machine learning technology, artificial intelligence technology, cloud computing technology, and / or other technologies.

[0089] The various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) can provide technical improvements to systems, apparatuses, components, operating steps, and / or processing steps associated with the various techniques identified above. For example, the different embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) are capable of encoding quantum information in a first oscillation mode of a first superconducting qubit and a second superconducting qubit; and / or coupling a superconducting bus resonator to an oscillation mode structure corresponding to a second oscillation mode of the first superconducting qubit and the second superconducting qubit.

[0090] In the above examples and referring to the above description, and Figure 1A and Figure 1BThe exemplary embodiments shown herein, based on the mode-selective coupling scheme described above, enable the device 100a of this disclosure to assist in the suppression (e.g., cancellation, reduction, etc.) of direct interactions between the first superconducting quantum bit 104a and the second superconducting quantum bit 104b (e.g., between a first oscillation mode of the first superconducting quantum bit 104a and a first oscillation mode of the second superconducting quantum bit 104b, wherein the first oscillation mode and the second oscillation mode may include data modes of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b), such as exchange interactions and / or static ZZ interactions. In this example, based on the mode-selective coupling scheme described above, the device 100a can also assist in strong (e.g., relatively strong) longitudinal coupling between the first superconducting quantum bit 104a and the second superconducting quantum bit 104b between the first oscillation mode and the second oscillation mode (e.g., between the first oscillation mode structure 124a and the second oscillation mode structure 124b). In this example, based on implementing the mode-selective coupling scheme described above, device 100a can further assist in preventing exchange coupling between these data modes (e.g., between the first oscillation mode and the second oscillation mode) and the superconducting bus resonator 102, which can reduce energy losses (e.g., Purcell losses) and / or decoupling associated with device 100a and / or the superconducting bus resonator 102. In this example, based on such suppression of such static ZZ interactions, the reduced energy losses associated with the superconducting bus resonator 102, and / or the reduced decoupling, device 100a can thereby assist in: reduced quantum gate errors associated with the first superconducting qubit 104a and / or the second superconducting qubit 104b; increased speed of quantum gates including the first superconducting qubit 104a and the second superconducting qubit 104b; and / or at least one of improved fidelity, improved accuracy, or improved performance of the quantum processor including device 100a.

[0091] The various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) can provide technical improvements to processing units (e.g., quantum processors including device 100a, device 200a, or device 300, processing unit 1014, etc.) that may be associated with one or more associated classical computing devices and / or quantum computing devices (e.g., quantum processors, quantum hardware, superconducting circuits, etc.) of the various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.). For example, by implementing the mode-selective coupling scheme described above, device 100a can assist in the suppression of such static ZZ interactions, reduced energy loss, and / or reduced decoupling associated with superconducting bus resonator 102. In this example, by suppressing the ZZ interaction associated with the superconducting bus resonator 102, reducing the energy loss, and / or reducing the decoupling, device 100a can thereby assist in: reducing quantum gate errors associated with the first superconducting qubit 104a and / or the second superconducting qubit 104b; and / or increasing the speed of quantum gates (e.g., entangled quantum gates) including the first superconducting qubit 104a and the second superconducting qubit 104b. In this example, by reducing such quantum gate errors and / or increasing the speed of such quantum gates, device 100a can promote improved fidelity, improved accuracy, and / or improved performance of the quantum processor including device 100a.

[0092] Based on this suppression of the ZZ interaction between the first oscillation mode of the first superconducting qubit 104a and the first oscillation mode of the second superconducting qubit 104b as described above, the practical application of one or more embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) is that they can be implemented in quantum devices (e.g., quantum processors, quantum computers, etc.) for faster and more efficient computation, utilizing improved fidelity and / or accuracy, for one or more solutions (e.g., heuristics, etc.) to a wide range of problems (e.g., estimation problems, optimization problems, etc.) in various fields (e.g., finance, chemistry, medicine, etc.) with a range of complexity. For example, based on this suppression of the ZZ interaction between the first oscillation mode of the first superconducting quantum bit 104a and the first oscillation mode of the second superconducting quantum bit 104b as described above, the practical application of one or more embodiments of this disclosure described herein (e.g., device 100a, etc.) is that they can be implemented in, for example, a quantum processor (e.g., a quantum processor including device 100a) for computation to improve fidelity and / or accuracy. One or more solutions (e.g., heuristics, etc.) to optimization problems in the chemical, medical, and / or financial fields can be used to design such solutions, for example, new compounds, new drugs, and / or new option pricing systems and / or methods.

[0093] It should be understood that the various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) provide a novel approach driven by relatively new quantum computing techniques. For example, one or more embodiments disclosed in this subject matter (e.g., device 100a, etc.) provide a novel method to suppress ZZ interactions between a first oscillation mode of a first superconducting qubit 104a and a first oscillation mode of a second superconducting qubit 104b, which, as described above, cause quantum gate errors during quantum computing. In this example, this novel method of suppressing ZZ interactions can be used with one or more quantum processors (e.g., device 100a, etc.) including those in the various embodiments of this disclosure described herein to achieve faster and more efficient quantum computing with improved fidelity and / or accuracy.

[0094] The various embodiments of this disclosure described herein (e.g., apparatus 100a, apparatus 200a, apparatus 300, etc.) can employ hardware or software to solve problems that are inherently highly technical, non-abstract, and cannot be performed by humans as a set of mental actions. In some embodiments, one or more methods in the processes described herein can be executed by one or more dedicated computers (e.g., dedicated processing units, dedicated classical computers, dedicated quantum computers, etc.) to perform tasks defined in relation to the different technologies identified above. The various embodiments of this disclosure described herein (e.g., apparatus 100a, apparatus 200a, apparatus 300, etc.) can be used to solve new problems arising from advancements in the technologies described above, quantum computing systems, cloud computing systems, computer architectures, and / or other technologies.

[0095] It should be understood that, because the various operations that can be performed by the various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) are operations beyond the capabilities of the human mind, the various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) can utilize various combinations of electrical components, mechanical components, and circuits that cannot be copied in the human mind or performed by a human. For example, the amount of data processed, the speed at which such data is processed, or the type of data processed by the various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) within a certain time period may be greater than, faster than, or different from the amount, speed, or type of data that can be processed by the human mind within the same time period.

[0096] According to several embodiments, the different embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) are also fully operable to perform one or more other functions (e.g., full power-on, full execution, etc.) while simultaneously performing the different operations described herein. It should be understood that such simultaneous multi-operation execution is beyond the capabilities of the human mind. It should also be understood that the various embodiments of this disclosure described herein (e.g., device 100a, device 200a, device 300, etc.) may include information that is not manually obtainable by an entity (such as a human user). For example, the type, amount, and / or variety of information included in device 100a, device 200a, and / or device 300 may be more complex than information manually obtainable by a human user.

[0097] Figure 7 A flowchart illustrating an example, non-limiting computer implementation of method 700 according to one or more embodiments described herein, is shown, which can use mode-selective coupling in a double-junction superconducting qubit to promote static ZZ suppression and Purcell loss reduction. For brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0098] At 702, the computer implementation method 700 may include a system (e.g., including device 100a, computer 1012 and / or the above-mentioned device 100a, computer 1012 and / or the above-mentioned device 1012) operably coupled to a processor (e.g., processing unit 1014, etc.). Figure 1A and Figure 1B A system of one or more types of external devices (defined) for a first oscillation mode of a first superconducting qubit (e.g., first superconducting qubit 104a) and a second superconducting qubit (e.g., second superconducting qubit 104b) (e.g., see above). Figure 1A and 1B The quantum information (e.g., qubit information, quantum state information, etc.) in the first oscillation mode described is encoded.

[0099] At 704, the computer implementation method 700 may include the use of a system (e.g., including device 100a, computer 1012, and / or see above) Figure 1A and 1B The system of one or more types of external devices (as defined) couples a superconducting bus resonator (e.g., superconducting bus resonator 102) to a second oscillation mode of the first superconducting qubit and the second superconducting qubit (e.g., see above). Figure 1A and 1B The oscillation mode structure corresponding to the described second oscillation mode (e.g., second oscillation mode structure 124b).

[0100] Figure 8A flowchart illustrating an example, non-limiting computer implementation of method 800 according to one or more embodiments described herein, is shown, which can use mode-selective coupling in a double-junction superconducting qubit to promote static ZZ suppression and Purcell loss reduction. For brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0101] At 802, the computer-implemented method 800 may include a system (e.g., including device 100a, computer 1012 and / or the above-mentioned device 100a, computer 1012 and / or the above-mentioned device 1012) operably coupled to a processor (e.g., processing unit 1014, etc.). Figure 1A and Figure 1B A system of one or more types of external devices (defined) uses a data mode of a first superconducting quantum bit (e.g., first superconducting quantum bit 104a) and a second superconducting quantum bit (e.g., second superconducting quantum bit 104b) (e.g., see above). Figure 1A and 1B The first oscillation mode described encodes quantum information (e.g., qubit information, quantum state information, etc.).

[0102] At 804, the computer implementation method 800 may include implementation via a system (e.g., including device 100a, computer 1012, and / or see above). Figure 1A and 1B A system of one or more types of external devices (as defined) couples a superconducting bus resonator (e.g., superconducting bus resonator 102) to a coupling mode structure (e.g., a second oscillation mode structure 124b) that corresponds to the coupling mode of the first superconducting qubit and the second superconducting qubit (e.g., see above). Figure 1A and 1B The second oscillation mode described.

[0103] Figure 9 A flowchart of an example, non-limiting computer implementation of method 900 according to one or more embodiments described herein is shown, which can use mode-selective coupling in a double-junction superconducting qubit to promote static ZZ suppression and Purcell loss reduction. For brevity, repeated descriptions of similar elements and / or processes employed in the corresponding embodiments are omitted.

[0104] At 902, the computer implementation of method 900 may include a first oscillation mode of a first superconducting qubit (e.g., first superconducting qubit 104a) and a second superconducting qubit (e.g., second superconducting qubit 104b) (e.g., see above). Figure 1A and 1BThe first oscillation mode described encodes quantum information (e.g., qubit information, quantum state information, etc.) (e.g., through a system including device 200a or device 300, computer 1012, and / or see above). Figure 1A and 1B (One or more types of external devices as defined).

[0105] At 904, the computer-implemented method 900 may include coupling a superconducting bus resonator (e.g., superconducting bus resonator 102) to (e.g., a communication system, the system including device 200a or device 300, computer 1012, and / or see above) a system including device 200a or device 300, computer 1012, and / or see above. Figure 1A and 1B The external device (one or more types as defined) is applied to an oscillation mode structure (e.g., a second oscillation mode structure 124b) corresponding to the second oscillation modes of the first superconducting qubit and the second superconducting qubit (e.g., see above). Figure 1A and 1B The second oscillation mode described.

[0106] At 906, the computer implementation method 900 may include adjustments (e.g., through a system including device 200a or device 300, computer 1012, and / or see above). Figure 1A and 1B (One or more types of external devices as defined) the critical currents of the first superconducting qubit and the second superconducting qubit. For example, see above. Figure 1A , 1B As described in 2A, 2B, and 4, the entities of implementing device 200a and / or device 300 as defined herein can be configured such that the capacitance of capacitor 228a = the capacitance of capacitor 228b = 10 femtofarads (fF), wherein the resonant frequency (fr) of superconducting bus resonator 102 is 4 GHz. In this example, such an entity can adjust and / or change the critical current of the first superconducting quantum bit 104a and the second superconducting quantum bit 104b from approximately 20 nA (e.g., by referring above). Figure 1A and 1B One or more external devices and / or computers 1012 as defined are available in the range of approximately 30 nA, wherein for each of the first superconducting quantum bits 104a and the second superconducting quantum bits 104b, there is a 5 percent (%) asymmetry between currents I1 and I2.

[0107] At 908, the computer-implemented method 900 may include determining (e.g., through a system including entities as defined herein, device 200a or device 300, computer 1012, and / or see above) Figure 1A and 1BThe ZZ interaction (e.g., static ZZ interaction) between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit (defined by one or more types of external devices) is suppressed. For example, referring to the example described above at operation 906, such an entity implementing device 200a and / or device 300 according to the parameters defined above can use graph 400 to determine whether the ZZ interaction (e.g., static ZZ interaction) between the second oscillation mode of the first superconducting qubit 104a and the second oscillation mode of the second superconducting qubit 104b is suppressed. In this example, when device 200a and / or device 300 are implemented according to the parameters defined above, such an entity can use graph 400 to determine whether the ZZ interaction (e.g., static ZZ interaction) between the second oscillation mode of the first superconducting qubit 104a and the second oscillation mode of the second superconducting qubit 104b is less than 1 kHz. In this example, it should be appreciated that when device 200a and / or device 300 are implemented according to such parameters as defined above, such ZZ interactions with frequency values ​​less than 1 kHz are suppressed, eliminated, and / or effectively absent.

[0108] If at 908 it is determined that the ZZ interaction (e.g., static ZZ interaction) between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit is suppressed, at 910, the computer-implemented method 900 may include execution between the first and second superconducting qubits (e.g., through a system including device 200a or device 300, computer 1012, and / or see above). Figure 1A and 1B Entangled quantum gates (of one or more types of external devices as defined). For example, see above. Figure 2A and 2B The entity described herein, such as implementation device 200a, can drive (e.g., using one or more external devices defined herein and / or computer 1012 as described above via microwave pulses) a superconducting bus resonator 102 detuned from its resonant frequency (e.g., 4 GHz) to generate and / or execute a two-qubit entangled gate (e.g., a two-qubit entangled quantum gate) via a RIP gate. In this example, by driving the superconducting bus resonator 102 detuned from its resonant frequency (as described above), such an entity can entangle a first superconducting qubit 104a with a second superconducting qubit 104b (e.g., to generate an entangled quantum gate between the first superconducting qubit 104a and the second superconducting qubit 104b). In this example, such entanglement of the first superconducting qubit 104a with the second superconducting qubit 104b enables entangled quantum gate operations to be performed between the first superconducting qubit 104a and the second superconducting qubit 104b.

[0109] If it is determined at 908 that the ZZ interaction (e.g., static ZZ interaction) between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit is suppressed, the computer implementation method 900 may include returning to operation 906 to adjust the critical currents of the first and second superconducting qubits. In different embodiments, operations 906 and 908 of the computer implementation method 900 may be repeated until the ZZ interaction between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit is suppressed (e.g., less than 1 kHz). In these embodiments, based on the repetition of operations 906 and 906 until the ZZ interaction between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit is suppressed, the computer implementation method 900 may proceed to operation 910.

[0110] In order to provide context for the various aspects of the disclosed subject, Figure 10 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 10 A block diagram is shown illustrating an example non-limiting operating environment that can facilitate one or more embodiments described herein. For example, operating environment 1000 can be used to implement the above-described references, as described below. Figure 1A and 1B The described example, non-limiting multi-step manufacturing sequence, can be implemented to manufacture devices 100a, 200a, and / or 300 according to one or more embodiments of the subject matter disclosed herein. In another example, as described below, operating environment 1000 can be used to implement the above-described embodiments respectively. Figure 7 , Figure 8 and Figure 9 One or more examples, non-limiting computer implementations of methods 700, 800, and / or 900 are described herein. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0111] It can be done through a computing system (e.g., Figure 10 The operating environment 1000 shown and described below and / or computing device (e.g., Figure 10 The computer 1012 shown in the figure and described below implements the above. Figure 1A and 1BThe described example is a non-limiting multi-step manufacturing sequence that can be implemented as manufacturing apparatus 100a, 200a, and / or 300. In a non-limiting exemplary embodiment, such a computing system (e.g., operating environment 1000) and / or such a computing device (e.g., computer 1012) may include one or more processors and one or more memory devices on which executable instructions are stored, which, when executed by the one or more processors, facilitate the above description. Figure 1A and 1B The described example is the execution of a non-limiting multi-step manufacturing sequence. As a non-limiting example, the one or more processors may facilitate the above-mentioned process by guiding and / or controlling one or more systems and / or devices for performing the fabrication of semiconductor and / or superconductor devices. Figure 1A and 1B The described example is the execution of a non-restrictive multi-step manufacturing sequence.

[0112] In another example, the above refer to... Figure 7 , Figure 8 and Figure 9 The one or more examples, non-limiting computer implementations of methods 700, 800, and / or 900 described may also be implemented (e.g., executed) by the operating environment 1000. As a non-limiting example, one or more processors of such a computing device (e.g., computer 1012) may boot and / or control one or more systems and / or devices operable to perform operations and / or routines of such computer-implemented methods(e.g., see above). Figure 1A and 1B One or more of the defined external devices (e.g.) facilitate the above, see below for details. Figure 7 , 8 The execution of one or more examples of the non-limiting computer implementation methods 700, 800 and / or 900 described in 9.

[0113] For simplicity of explanation, the computer-implemented method is depicted and described as a series of actions. It should be understood and recognized that the subject matter innovation is not limited to the actions shown and / or the order of the actions; for example, actions may occur in different orders and / or simultaneously, and may occur with other actions not presented and described herein. Furthermore, not all actions shown are necessary to implement the computer-implemented method according to the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that the computer-implemented method may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the computer-implemented methods disclosed below and throughout this specification can be stored on an article of art to facilitate the transfer and assignment of such computer-implemented methods to a computer. As used herein, the term article of art is intended to cover a computer program accessible from any computer-readable device or storage medium.

[0114] refer to Figure 10 The suitable operating environment 1000 for implementing various aspects of this disclosure may also include a computer 1012. The computer 1012 may further include a processing unit 1014, system memory 1016, and a system bus 1018. The system bus 1018 couples system components, including but not limited to system memory 1016, to the processing unit 1014. The processing unit 1014 may be any of the various available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1014. The system bus 1018 may be any of several types of bus architectures, including memory buses or memory controllers, peripheral buses or external buses, and / or local buses using any of the various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0115] System memory 1016 may also include volatile memory 1020 and non-volatile memory 1022. The Basic Input / Output System (BIOS) is stored in the non-volatile memory 1022, and the BIOS contains basic routines for transferring information between components within the computer 1012, such as during startup. The computer 1012 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 10Disk storage 1024 is illustrated, for example. Disk storage 1024 may also include, but is not limited to, devices such as disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Disk storage 1024 may also include storage media, either alone or in combination with other storage media. To facilitate connection of disk storage 1024 to system bus 1018, a removable or non-removable interface, such as interface 1026, is typically used. Figure 10 Software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 1000 is also described. Such software may also include, for example, an operating system 1028. The operating system 1028, which may be stored on a disk storage device 1024, is used to control and allocate the resources of the computer 1012.

[0116] System application 1030 utilizes resource management by operating system 1028 through program modules 1032 and program data 1034 stored, for example, in system memory 1016 or disk storage 1024. It should be understood that this disclosure can be implemented using different operating systems or combinations of operating systems. Users input commands or information into computer 1012 via input device 1036. Input device 1036 includes, but is not limited to, pointing devices such as a mouse, trackball, pen, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, TV tuner card, digital camera, digital camcorder, and webcam. These and other input devices are connected to processing unit 1014 via system bus 1018 through one or more interface ports 1038. Interface ports 1038 include, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 1040 uses some of the same type of ports as input device 1036. Thus, for example, a USB port can be used to provide input to computer 1012 and to output information from computer 1012 to output device 1040. Output adapter 1042 is provided to illustrate that, in addition to other output devices 1040 that require special adapters, there are other output devices 1040, such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 1042 includes video and sound cards that provide a connection between output device 1040 and system bus 1018. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 1044.

[0117] Computer 1012 can operate in a networked environment using a logical connection to one or more remote computers (such as remote computers 1044). Remote computer 1044 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other public network node, and typically may also include many or all of the elements described relative to computer 1012. For simplicity, only remote computer 1044 and memory storage device 1046 are shown. Remote computer 1044 is logically connected to computer 1012 via network interface 1048 and then physically connected via communication connection 1050. Network interface 1048 includes wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and its variants, packet-switched networks, and Digital Subscriber Line (DSL). Communication connection 1050 refers to the hardware / software used to connect network interface 1048 to system bus 1018. Although communication connection 1050 is shown inside computer 1012 for clarity, it may also be outside computer 1012. For illustrative purposes only, the hardware / software used to connect to network interface 1048 may also include internal and external technologies such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters and Ethernet cards.

[0118] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. The computer-readable storage medium may be a tangible means capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards, or protrusions in slots having instructions recorded thereon, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0119] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or downloaded to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may be personalized to execute computer-readable program instructions by utilizing state information of the computer-readable program instructions in order to perform aspects of the present invention.

[0120] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other apparatus to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operations to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0121] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0122] While the subject matter has been described above in the general context of computer-executable instructions running on a computer program product on a computer and / or a computer, those skilled in the art will recognize that this disclosure may also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the computer implementation methods of the present invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be implemented in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the present invention can be practiced on a standalone computer. In a distributed computing environment, program modules may reside in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from memory that may include or consist of one or more distributed memory cells. As used herein, the terms “memory” and “memory cell” are interchangeable. Furthermore, one or more embodiments described herein are capable of executing the code of a computer executable component in a distributed manner, for example, multiple processors combined or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" may include a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

[0123] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, processor, object, executable file, execution thread, program, and / or computer running on a processor. For illustration, both an application running on a server and the server itself can be components. One or more components may reside within a process and / or an execution thread, and components may reside on one computer and / or be distributed across two or more computers. In another instance, a corresponding component may be executed from a different computer-readable medium having different data structures stored thereon. Components may communicate via local and / or remote processes, such as according to a signal having one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or data from a component interacting with other systems across a network such as the Internet via that signal). As another example, a component may be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, the component can be a device that provides a specific function through electronic components without mechanical parts, wherein the electronic components can include a processor or other means for performing software or firmware that at least partially endows the electronic components with the functions. In one aspect, the component can be emulated via a virtual machine, for example, within a cloud computing system.

[0124] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing cases. Additionally, the articles "a" and "an" as used in the subject matter specification and figures should generally be interpreted as meaning "one or more," unless otherwise specified or clearly indicated from the context to the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an instance, example, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as an "example" and / or "exemplary" is not necessarily to be construed as superior to or better than other aspects or designs, nor does it imply the exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0125] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, "processor" can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user equipment. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage," "memory," "data storage," "data memory," "database," and substantially any other information storage component, as used in relation to the operation and function of a component, are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein can be volatile or non-volatile memory, or may include both. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM that can serve as an external cache memory. By way of illustration and not limitation, RAM can be obtained in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components of the systems or computer implementation methods disclosed herein inherently include (but are not limited to) these and any other suitable types of memory.

[0126] The above description includes only examples of systems and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components or computer-implemented method; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, the use of terms such as “comprising,” “having,” “possessing,” etc., in the detailed description, claims, appendices, and drawings, and the interpretation of “comprising” as inclusive when used as a transitional word in the claims, are intended to be interpreted in a manner similar to the interpretation of the term “comprising.”

[0127] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device comprising: Superconducting bus resonator; First superconducting quantum bit; as well as The second superconducting quantum bit, wherein the first superconducting quantum bit and the second superconducting quantum bit each include: First superconducting liner; Second superconducting liner; Third superconducting liner; A first Josephson junction, the first Josephson junction being coupled to the first superconducting pad and the second superconducting pad; and A second Josephson junction is coupled to a second superconducting pad and a third superconducting pad, wherein the first superconducting pad and the second superconducting pad of the first superconducting quantum bit and the second superconducting quantum bit are coupled to the superconducting bus resonator, and wherein the superconducting bus resonator winds the first superconducting quantum bit and the second superconducting quantum bit based on a received control signal.

2. The device according to claim 1, wherein, The first superconducting quantum bit operates in a first oscillation mode and a second oscillation mode.

3. The device according to claim 1, wherein, The second superconducting quantum bit operates in a first oscillation mode and a second oscillation mode.

4. The device according to any one of claims 1-3, wherein at least one of the first superconducting quantum bit or the second superconducting quantum bit includes at least one of a tunable coupler quantum bit, a double-junction quantum bit, a multimode quantum bit, a multimode double-junction quantum bit, or a tunable quantum bit.

5. The device according to any one of claims 1-3, wherein the first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator to suppress ZZ interaction between the first superconducting qubit and the second superconducting qubit and reduce energy loss associated with the superconducting bus resonator, thereby promoting at least one of the following: reduced quantum gate error associated with at least one of the first superconducting qubit or the second superconducting qubit; increased speed of quantum gates including the first superconducting qubit and the second superconducting qubit; or improved fidelity, improved accuracy, or improved performance of the quantum processor of the device.

6. A computer-implemented method, comprising: Quantum information is encoded in a first oscillation mode of a first superconducting qubit and a second superconducting qubit by a system operatively coupled to a processor; and The system couples the superconducting bus resonator to an oscillation mode structure corresponding to the second oscillation mode of the first superconducting quantum bit and the second superconducting quantum bit. The superconducting bus resonator winds the first superconducting quantum bit and the second superconducting quantum bit based on the received control signal.

7. The computer implementation method according to claim 6, wherein the first superconducting quantum bit operates in the first oscillation mode and the second oscillation mode.

8. The computer implementation method according to claim 6, wherein, The second superconducting quantum bit operates in both the first oscillation mode and the second oscillation mode.

9. The computer implementation method according to any one of claims 6 to 8, wherein at least one of the first superconducting quantum bit or the second superconducting quantum bit includes at least one of a tunable coupler quantum bit, a double-junction quantum bit, a multimode quantum bit, a multimode double-junction quantum bit, or a tunable quantum bit.

10. The computer-implemented method according to any one of claims 6 to 8, further comprising: The quantum information is encoded by the system using the first oscillation mode of the first superconducting quantum bit and the second superconducting quantum bit; and The system couples the superconducting bus resonator to an oscillation mode structure corresponding to a second oscillation mode of the first and second superconducting qubits to suppress ZZ interactions between the first and second superconducting qubits and to reduce energy losses associated with the superconducting bus resonator, thereby contributing to at least one of the following: reduced quantum gate errors associated with at least one of the first or second superconducting qubits; increased speed of quantum gates including the first and second superconducting qubits; or at least one of improved fidelity, improved accuracy, or improved performance of a quantum processor including the first superconducting qubit, the second superconducting qubit, and the superconducting bus resonator.

11. A device comprising: Superconducting bus resonator; First superconducting quantum bit; as well as The second superconducting quantum bit, wherein the first superconducting quantum bit and the second superconducting quantum bit each include: First superconducting liner; Second superconducting liner; Third superconducting liner; A first Josephson junction, the first Josephson junction being coupled to the first superconducting pad and the second superconducting pad; and A second Josephson junction is coupled to a second superconducting pad and a third superconducting pad, wherein the second superconducting pad of the first superconducting qubit and the second superconducting qubit is coupled to the superconducting bus resonator, and wherein the superconducting bus resonator is wound around the first superconducting qubit and the second superconducting qubit based on a received control signal.

12. The device according to claim 11, wherein, The first superconducting quantum bit operates in a first oscillation mode and a second oscillation mode.

13. The device according to claim 11, wherein, The second superconducting quantum bit operates in a first oscillation mode and a second oscillation mode.

14. The device according to any one of claims 11 to 13, wherein, At least one of the first superconducting quantum bit or the second superconducting quantum bit includes at least one of a tunable coupler quantum bit, a double-junction quantum bit, a multimode quantum bit, a multimode double-junction quantum bit, or a tunable quantum bit.

15. The device according to any one of claims 11 to 13, wherein, The second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator to suppress ZZ interactions between the first and second superconducting qubits and reduce energy losses associated with the superconducting bus resonator, thereby contributing to at least one of the following: reduced quantum gate error associated with at least one of the first or second superconducting qubits; increased speed of quantum gates including the first and second superconducting qubits; or improved fidelity, improved accuracy, or improved performance of the quantum processor of the device.

16. A computer-implemented method, comprising: Quantum information is encoded in a data mode of a first superconducting qubit and a second superconducting qubit by a system operatively coupled to a processor; and The system couples the superconducting bus resonator to a coupling mode structure corresponding to the coupling mode between the first superconducting qubit and the second superconducting qubit. The superconducting bus resonator winds the first superconducting quantum bit and the second superconducting quantum bit based on the received control signal.

17. The computer implementation method of claim 16, wherein the first superconducting quantum bit operates in the data mode and the coupling mode.

18. The computer-implemented method according to claim 16, wherein, The second superconducting quantum bit operates in the data mode and the coupling mode.

19. The computer implementation method according to any one of claims 16 to 18, wherein at least one of the first superconducting quantum bit or the second superconducting quantum bit includes at least one of a tunable coupler quantum bit, a double-junction quantum bit, a multimode quantum bit, a multimode double-junction quantum bit, or a tunable quantum bit.

20. The computer-implemented method according to any one of claims 16 to 18, further comprising: The system encodes the quantum information using the data patterns of the first superconducting qubit and the second superconducting qubit; and The system couples the superconducting bus resonator to a coupling mode structure corresponding to the coupling modes of the first and second superconducting qubits to suppress ZZ interactions between the first and second superconducting qubits and reduce energy losses associated with the superconducting bus resonator, thereby contributing to at least one of the following: reduced quantum gate errors associated with at least one of the first or second superconducting qubits; increased speed of quantum gates including the first and second superconducting qubits; or at least one of improved fidelity, improved accuracy, or improved performance of a quantum processor including the first superconducting qubit, the second superconducting qubit, and the superconducting bus resonator.

21. A device comprising: The first and second superconducting qubits operate in the first oscillation mode; as well as A superconducting bus resonator, wherein the superconducting bus resonator is coupled to an oscillation mode structure corresponding to a second oscillation mode of the first superconducting qubit and the second superconducting qubit; The superconducting bus resonator winds the first superconducting quantum bit and the second superconducting quantum bit based on the received control signal.

22. The device of claim 21, wherein at least one of the first superconducting quantum bit or the second superconducting quantum bit includes at least one of a tunable coupler quantum bit, a double-junction quantum bit, a multimode quantum bit, a multimode double-junction quantum bit, or a tunable quantum bit.

23. The device according to any one of claims 21 to 22, wherein, The first oscillation mode and the second oscillation mode represent a combination of symmetric and antisymmetric excitations associated with the first Josephson junction and the second Josephson junction of the first superconducting qubit and the second superconducting qubit.

24. The device according to any one of claims 21 to 22, wherein, At least one of the first oscillation mode or the second oscillation mode includes at least one of the data mode or the coupling mode.

25. The device according to any one of claims 21 to 22, wherein, The first superconducting qubit and the second superconducting qubit operate in the first oscillation mode, and the superconducting bus resonator is coupled to the oscillation mode structure corresponding to the second oscillation mode to suppress ZZ interactions between the first and second superconducting qubits and reduce energy losses associated with the superconducting bus resonator, thereby promoting at least one of the following: reduced quantum gate error associated with at least one of the first or second superconducting qubits; increased speed of quantum gates including the first and second superconducting qubits; or improved fidelity, improved accuracy, or improved performance of the quantum processor of the device.

Images