Semiconductor device, semiconductor module, and method for manufacturing semiconductor device

Abstract

A semiconductor device comprising: a semiconductor element (11) having a first electrode pad (111) and a plurality of second electrode pads (112) on a surface (11a) and generating current in a direction connecting the surface and the back surface (11b); a seal (12) made of an insulating resin material covering a portion of the surface and the side surface (11c) of the semiconductor element; and an extended wiring (152) disposed on the semiconductor element inside or on the seal, electrically connected to the second electrode pads and extending from the inside of the outer contour of the semiconductor element to the outside.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-98220, filed on June 5, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device with a fan-out package structure, a semiconductor module using the same, and a method for manufacturing the semiconductor device. Background Technology

[0004] Conventionally, semiconductor devices having power semiconductor elements and semiconductor modules utilizing their two-sided heat dissipation structures are exemplified by, for example, the structure described in Patent Document 1. The semiconductor module described in Patent Document 1 includes a semiconductor device serving as a power semiconductor element, two heat sinks disposed on both sides sandwiching the semiconductor device, lead terminals, and wires connecting the semiconductor device and the lead terminals. Furthermore, to prevent short circuits caused by contact between the wires and the heat sinks, a heat sink made of a material with high thermal conductivity is disposed between the side of the semiconductor device where the wires are connected and the heat sink facing that side.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2001-156225

[0008] However, the aforementioned semiconductor module is constructed such that the gap between the semiconductor device and the heat sink is set to a predetermined value or higher via a heat sink to prevent the wiring from contacting the heat sink. Therefore, the heat sink becomes a major obstacle to thinning. Furthermore, because a heat sink is placed between the semiconductor device and the heat sink, the thermal resistance increases accordingly, resulting in a decrease in the heat dissipation performance of the semiconductor module. Summary of the Invention

[0009] Therefore, the inventors of this invention carefully studied the structure of the semiconductor device and the semiconductor module in order to achieve both thinness and high heat dissipation in this semiconductor module. As a result, they conceived of a semiconductor module with a fan-out package structure in which the semiconductor device is formed with a redistribution layer, heat sinks are bonded to both sides of the semiconductor device without heat sinks, and lead terminals are connected to the redistribution layer without wires. Thus, a semiconductor module with a two-sided heat dissipation structure that achieves both thinness and high heat dissipation, without heat sinks and wires, is achieved.

[0010] The inventors of this invention, through further careful study, discovered that in the conceived fan-out packaged semiconductor device, the insulation of the semiconductor device may be insufficient due to the step difference between the side of the semiconductor element and the seal covering it. Specifically, in this semiconductor device, if a step difference occurs between the side of the semiconductor element and the seal covering it, cracks caused by this step difference may occur in the area of ​​the insulating film constituting the redistribution layer covering the step difference. If such cracks occur in the insulating film, the insulation between the wiring formed on the step difference portion and the end of the semiconductor element can no longer be guaranteed.

[0011] This disclosure relates to a technique for improving insulation in a fan-out packaged semiconductor device by suppressing short circuits between extended wiring disposed on a semiconductor element and the semiconductor element. Furthermore, it relates to a semiconductor module employing a semiconductor device with improved insulation, high reliability, and a two-sided heat dissipation structure that achieves thinness and high heat dissipation.

[0012] A semiconductor device according to one aspect of this disclosure includes: a semiconductor element having a first electrode pad and a plurality of second electrode pads on its surface, generating current in a direction connecting the surface and the back side; a seal made of an insulating resin material, covering a portion of the surface and the side of the semiconductor element; and an extended wiring disposed on the semiconductor element, disposed inside or on the seal, electrically connected to the second electrode pads, and extending from the inner side of the outer contour of the semiconductor element to the outer side.

[0013] Therefore, a portion of the side surface and surface of the semiconductor element is covered by a seal made of insulating resin material, resulting in a structure that eliminates the step difference between the side surface of the semiconductor element and the seal covering it. Consequently, the extended wiring formed at the boundary between the side surface of the semiconductor element and the seal is unaffected by this step difference. Thus, insulation failures caused by this step difference are suppressed, short circuits between the extended wiring and the semiconductor element are suppressed, and insulation performance is improved.

[0014] A semiconductor module according to one aspect of this disclosure includes: a semiconductor device; a semiconductor element having at least one first electrode pad and at least one second electrode pad on its surface, generating current in a direction connecting the surface and the back side; a first seal made of an insulating resin material, covering the area around the semiconductor element, including a portion of the surface; and an extended wiring disposed on the semiconductor element inside or on the first seal, electrically connected to the second electrode pad and extending from the inner side of the outer contour of the semiconductor element to the outer side; a first heat dissipation member connected to the back side of the semiconductor device exposed from the first seal via a bonding member; a second heat dissipation member electrically connected to the first electrode pad in the semiconductor device via a bonding member; a lead frame electrically connected to the extended wiring in the semiconductor device via a bonding member; and a second seal covering the semiconductor device, a portion of the first heat dissipation member, a portion of the second heat dissipation member, and a portion of the lead frame.

[0015] Therefore, a semiconductor device incorporating one aspect of this disclosure, with a first heat dissipation component and a second heat dissipation component arranged opposite each other, becomes a semiconductor module in which the lead frame is connected to the extended wiring of the semiconductor device via a bonding member. The semiconductor device and the lead frame are bonded via the bonding member, resulting in a structure that achieves thinness and high heat dissipation without a heat sink between the second heat dissipation component and the semiconductor device to ensure a gap. Furthermore, short circuits between the extended wiring and semiconductor elements in the semiconductor device are suppressed, thereby further improving reliability. Additionally, the extended wiring can also be connected to the lead frame via the bonding member in an exposed area of ​​the semiconductor device that is further outward from the outer contour of the second heat dissipation component. In this case, it also becomes a semiconductor module with a simpler structure and achieves thinness and high heat dissipation.

[0016] One aspect of the semiconductor device manufacturing method disclosed herein is a method for manufacturing a semiconductor device with a fan-out package structure, comprising the following steps: preparing a semiconductor element having at least one first electrode pad and at least one second electrode pad on its surface; preparing a conductive component, the conductive component having a thick-walled portion, a first thin-walled portion extending outward from the upper end of the thick-walled portion and having a thickness smaller than the thick-walled portion, a medium-thickness wall portion disposed at the front end of the first thin-walled portion and having a thickness smaller than and larger than the thick-walled portion, and a second thin-walled portion extending from the medium-thickness wall portion toward the lower end of the thick-walled portion and having a thickness smaller than the thick-walled portion; and placing the back side of the semiconductor element towards the surface of the semiconductor device. The process involves: attaching a support substrate; connecting the lower end face of the thick-walled portion of the conductive component to the first electrode pad of the semiconductor element, and connecting the front end of the second thin-walled portion of the conductive component to the second electrode pad of the semiconductor element; forming a seal that covers the semiconductor element, which is connected to the conductive component and attached to the support substrate, together with the conductive component; removing the seal from the side of the seal that covers the conductive component, thereby exposing the thick-walled portion and the medium-thickness wall portion of the conductive component; using an insulating resin material in forming the seal; and removing the seal by removing the first thin-walled portion of the conductive component, thereby separating the thick-walled portion from the medium-thickness wall portion and the second thin-walled portion.

[0017] Therefore, after bonding the conductive component to the first electrode pad and the second electrode pad of the semiconductor element, a seal is formed. The seal and the first thin-walled portion are then removed, separating the thick-walled portion, the medium-thickness wall portion, and the second thin-walled portion of the conductive component. Thus, a portion connecting to the first electrode pad and an extended wiring connection connecting to the second electrode pad are formed from a single conductive component, manufacturing a semiconductor device with a fan-out package structure. Therefore, the conductive component, including the extended wiring, is pre-connected to the second electrode pad before the seal is formed. Furthermore, a seal is formed that covers the surface and sides of the semiconductor element together with the conductive component, thus preventing a step difference at the boundary between the side of the semiconductor element and the seal. Therefore, no step difference between the side of the semiconductor element and the seal, and no short circuit between the extended wiring and the semiconductor element caused by it, are generated, enabling the manufacture of a semiconductor device with improved insulation.

[0018] In addition, the parenthesized markings assigned to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent elements described in the embodiments described later. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0020] Figure 2 It means to Figure 1 A three-dimensional view of the morphology of a semiconductor device as seen from the surface side.

[0021] Figure 3A This is a cross-sectional view showing the temporary fixing process of the semiconductor substrate in the manufacturing process of the semiconductor device according to the first embodiment.

[0022] Figure 3B It means to continue Figure 3A A cross-sectional view of the manufacturing process.

[0023] Figure 3C It means to continue Figure 3B A cross-sectional view of the manufacturing process.

[0024] Figure 3D It means to continue Figure 3C A cross-sectional view of the manufacturing process.

[0025] Figure 3E It means to continue Figure 3D A cross-sectional view of the manufacturing process.

[0026] Figure 3F It means to continue Figure 3E A cross-sectional view of the manufacturing process.

[0027] Figure 3G It means to continue Figure 3F A cross-sectional view of the manufacturing process.

[0028] Figure 3H It means to continue Figure 3G A cross-sectional view of the manufacturing process.

[0029] Figure 3I It means to continue Figure 3H A cross-sectional view of the manufacturing process.

[0030] Figure 3J It means to continue Figure 3I A cross-sectional view of the manufacturing process.

[0031] Figure 4A This diagram illustrates an example of another manufacturing method for the redistribution layer of the semiconductor device according to the first embodiment. It shows the following... Figure 3D A cross-sectional view of the manufacturing process.

[0032] Figure 4B express Figure 4A A variation of the manufacturing process is used to represent the following... Figure 3D A diagram of the manufacturing process.

[0033] Figure 5 It is a cross-sectional view showing the structure of a conventional semiconductor device.

[0034] Figure 6 It means Figure 5 Enlarged cross-sectional view of region VI in the image.

[0035] Figure 7 This is a cross-sectional view showing an example of a semiconductor module using the semiconductor device of the first embodiment.

[0036] Figure 8 This is a cross-sectional view showing another example of a semiconductor module employing the semiconductor device of the first embodiment.

[0037] Figure 9 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0038] Figure 10A This is a cross-sectional view showing the temporary fixing process of a semiconductor substrate with a surface protector in the manufacturing process of the semiconductor device according to the second embodiment.

[0039] Figure 10B It means to continue Figure 10A A cross-sectional view of the manufacturing process.

[0040] Figure 10C It means to continue Figure 10B A cross-sectional view of the manufacturing process.

[0041] Figure 10D It means to continue Figure 10C A cross-sectional view of the manufacturing process.

[0042] Figure 10E It means to continue Figure 10D A cross-sectional view of the manufacturing process.

[0043] Figure 10F It means to continue Figure 10E A cross-sectional view of the manufacturing process.

[0044] Figure 10G It means to continue Figure 10F A cross-sectional view of the manufacturing process.

[0045] Figure 10H It means to continue Figure 10G A cross-sectional view of the manufacturing process.

[0046] Figure 10I It means to continue Figure 10H A cross-sectional view of the manufacturing process.

[0047] Figure 10J It means to continue Figure 10I A cross-sectional view of the manufacturing process.

[0048] Figure 10K It means to continue Figure 10J A cross-sectional view of the manufacturing process.

[0049] Figure 11This is an explanatory diagram illustrating the stepped cutting of the insulation layer when the upper cross-sectional shape of the inner wall surface in the seal is a right angle.

[0050] Figure 12 It means Figure 11 Enlarged cross-sectional view of region XII in the image.

[0051] Figure 13 This is an enlarged cross-sectional view showing an example of making the inner wall surface of the seal into a different cross-sectional shape.

[0052] Figure 14 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

[0053] Figure 15A It is a top view of the conductive components bonded to the semiconductor substrate as seen from the top surface.

[0054] Figure 15B From Figure 15A The XVB direction view in the view.

[0055] Figure 16A This is a cross-sectional view showing the temporary fixing process of the semiconductor substrate to which the conductive component is bonded in the manufacturing process of the semiconductor device according to the third embodiment.

[0056] Figure 16B It means to continue Figure 16A A cross-sectional view of the manufacturing process.

[0057] Figure 17 This is a cross-sectional view illustrating an example of a semiconductor module in another implementation. Detailed Implementation

[0058] Hereinafter, embodiments of the present disclosure will be described based on the accompanying drawings. Furthermore, in each of the following embodiments, the same or equivalent parts will be described with the same reference numerals.

[0059] (First Embodiment)

[0060] Reference Figure 1 , Figure 2 The semiconductor device 1 of the first embodiment will be described. Figure 1 It means Figure 2 A cross-sectional view of the structure between II and III.

[0061] 〔structure〕

[0062] For example, the semiconductor device 1 in this embodiment is as follows: Figure 1As shown, the device includes a semiconductor element 11, a seal 12, a first conductor portion 13, a second conductor portion 14, and a rewiring layer 15 having extended wiring 152 extending from the inner side of the outer contour of the semiconductor element 11 to the outer side. The semiconductor element 11 has a first electrode pad 111, a plurality of second electrode pads 112, an electric field mitigation layer 113, and an insulating film 114 on its surface 11a. The first electrode pads 111 are connected to the first conductor portion 13, and the second electrode pads 112 are connected to the second conductor portion 14. The extended wiring 152 extends from the second conductor portion 14 to the outer side of the outer contour of the semiconductor element 11, and a portion of its front end is exposed from the seal 12. This semiconductor device 1 is a fan-out package structure (hereinafter referred to as "FOP structure") in which a portion of the surface 11a of the semiconductor element 11 is covered by the seal 12, and a rewiring layer 15 including the extended wiring 152 is formed on one side 12a of the seal 12.

[0063] Semiconductor element 11, for example, has a first electrode pad 111 and a plurality of second electrode pads 112 made of a metal material such as Cu (copper), an electric field mitigation layer 113, and an upper insulating film 114 covering the electric field mitigation layer 113 and a portion of the surface 11a on its surface 11a. Semiconductor element 11 is, for example, a power semiconductor element such as an IGBT, manufactured using conventional semiconductor processes. Semiconductor element 11 has, for example, a third electrode pad (not shown) formed on its back surface 11b, which is a structure capable of being connected to other components. The first electrode pad 111 and the third electrode pad (not shown) are, for example, a pair of electrodes constituting an emitter electrode and a collector electrode, forming a current path connecting the surface 11a and the back surface 11b of semiconductor element 11. At least one of the plurality of second electrode pads 112 serves as a gate electrode for controlling the on / off state of the current between the first electrode pad 111 and the third electrode pad. The first electrode pad 111 is as follows: Figure 1 It is connected to the first conductor portion 13 as shown. Multiple second electrode pads 112 are respectively connected to the second conductor portion 14. The portion of the semiconductor element 11 other than the back surface 11b is covered by the sealant 12. Furthermore, the electric field mitigation layer 113 is, for example, made into a protective ring, but is not limited thereto.

[0064] Seal 12 Figure 1As shown, the component covering the portion of the semiconductor element 11 other than the back surface 11b is made of an insulating resin material, such as epoxy resin or any other resin material. Specifically, the seal 12 covers a portion of the surface 11a of the semiconductor element 11, including the insulating film 114 on the element, and the side surface 11c, i.e., the surrounding area, between the surface 11a and the back surface 11b. Viewed from the normal direction of the surface 11a of the semiconductor element 11, the seal 12 covers a portion of the surface 11a across the side surface 11c of the semiconductor element 11, and its outer contour is further outward than the outer contour of the semiconductor element 11. In other words, the shape of the seal 12 is larger than the shape of the semiconductor element 11. One side 12a of the seal 12 that covers the surface 11a of the semiconductor element 11 is positioned higher than the surface 11a. The other side 12b of the seal 12, which is the opposite side to the side 12a, together with the back surface 11b of the semiconductor element 11, constitutes the back surface 1b of the semiconductor device 1.

[0065] The first conductor portion 13 and the second conductor portion 14 are, for example, made of a conductive material such as Cu, and formed by electroplating or the like. The first conductor portion 13 and the second conductor portion 14 are, for example, made of a conductive material such as Cu, and formed by electroplating or the like. Figure 1 As shown, the material extends in the normal direction toward the upper part (e.g., directly above) of the semiconductor element 11, i.e., the surface 11a. In this embodiment, the thickness is set to be greater than or equal to the height of the surface 12a of the seal 12. The first conductor portion 13 and the second conductor portion 14 are partially disposed inside the redistribution layer 15.

[0066] One end of the first conductor portion 13 is connected to the first electrode pad 111, and the other end on the opposite side of the first conductor portion 13 is exposed from the seal 12. The other end of the first conductor portion 13 is covered, for example, by a cover portion 161 made of Cu or the like and a metal thin film 153 made of Ni (nickel), Au (gold), or the like.

[0067] One end of the second conductor portion 14 is connected to the second electrode pad 112, and the other end, on the opposite side, protrudes from the seal 12. The other end of the second conductor portion 14 is as follows... Figure 1 As shown, an extension wiring 152 is provided connecting the inner side of the outer contour of the semiconductor element 11 to the outer side. The second conductor portion 14 is formed in the same number as the plurality of second electrode pads 112.

[0068] The rewiring layer 15 has an insulating layer 151, extended wiring 152, and a cover portion 161, and is formed to cover one side 12a of the seal 12. The rewiring layer 15 is formed, for example, by a known rewiring forming technique. Furthermore, the rewiring layer 15 is not limited to... Figure 1 The wiring example shown can also be a structure with multiple layers of insulating films and internal wiring.

[0069] The insulating layer 151 is made of an insulating material such as polyimide and is formed through any coating process. The insulating layer 151 is formed through multiple film-forming processes and a photolithography-based patterning process, resulting in a predetermined pattern shape that exposes a portion of the first conductor portion 13 and a portion of the extended wiring 152 extending from the second conductor portion 14. The insulating layer 151 is formed on one side 12a of the seal 12, which covers the insulating film 114 on the component and is a flat surface, and is shaped without any step difference caused by the interface between the side surface 11c of the semiconductor component 11 and the seal 12 (hereinafter referred to as the "side interface"). In other words, the insulating layer 151 is a shape that ensures the insulation between the semiconductor component 11 and the extended wiring 152 without producing cracks caused by the side interface. Details will be described later.

[0070] Furthermore, regarding the portion of the insulating layer 151 that is closer to the side 12a than the extended wiring 152 (the first layer 1511 described later), from the viewpoint of ensuring insulation, it is preferable to make its thickness greater than the portion that is closer to the extended wiring 152 (the second layer 1512 described later).

[0071] The extended wiring 152 is made of a conductive metallic material, for example, with Cu, Au, Ni, Al (aluminum), Ti (titanium), Ag (silver), Pd (palladium), W (tungsten), Zn (zinc), and Pb (lead) as its main components. The extended wiring 152 extends from the second conductor portion 14, for example, and is formed by electroplating or electroless plating. The extended wiring 152 is disposed on the semiconductor element 11 and on one side 12a of the seal member 12, separated by a portion of the insulating layer 151, and has a wiring length spanning the inner and outer sides of the outer contour of the semiconductor element 11. The extended wiring 152 is formed in the same number as the second conductor portion 14, and extends from the second conductor portion 14 inside the outer contour of the semiconductor element 11 to the outer side of that outer contour. A predetermined area of ​​each extended wiring 152, located on the outer side of the outer contour of the semiconductor element 11 and situated near the front end opposite to the second conductor portion 14, is exposed from the insulating layer 151 and covered by a metal thin film 154 made of Au or the like. Furthermore, from the viewpoint of reducing impedance, it is preferable that the thickness of the extended wiring 152 is greater than that of the second electrode pad 112.

[0072] Metal thin films 153, 154, etc. Figure 2As shown, the metal films 153 and 154 function as external electrodes exposed from the insulating layer 151, capable of connecting externally to the first electrode pad 111 and the second electrode pad 112. The metal films 153 and 154 are electrode portions exposed externally on opposite sides of the first electrode pad 111 or the second electrode pad 112, and can be referred to as the "first external electrode" and "second external electrode," respectively. The metal films 153 and 154 are spaced apart, and the metal film 153 has a larger external shape and planar dimensions than the metal film 154. Figure 2 In the example, multiple metal films 154 have the same shape and planar dimensions and are evenly arranged, but this is not a limitation. They can also be set with different shapes and planar dimensions, or they can be arranged unevenly. In addition, the metal films 153 and 154 can be structures that are exposed to the outside of the redistribution layer 15 and can be used for external connection. They can be platings made of Ni, Au, etc., or bumps made of solder, etc.

[0073] The above describes the basic structure of the semiconductor device 1 according to this embodiment. The semiconductor device 1 has an FOP (Flexible Open-Place) structure with a redistribution layer 15 formed between a seal 12 covering the surface 11a of the semiconductor element 11. This structure prevents a step difference caused by the boundary between the side surface 11c of the semiconductor element 11 and the seal 12 within the redistribution layer 15. As a result, short circuits between the semiconductor element 11 and the extended wiring 152 are suppressed. Therefore, compared to conventional FOP-structured semiconductor devices, the semiconductor device 11 exhibits improved insulation between the semiconductor element 11 and the extended wiring 152, leading to improved reliability.

[0074] [Manufacturing Method]

[0075] Next, regarding an example of the manufacturing method of the semiconductor device 1 of this embodiment, refer to... Figures 3A to 3J Please provide an explanation.

[0076] First, a semiconductor substrate 10 is prepared, having a first electrode pad 111, a second electrode pad 112, an electric field mitigation layer 113, and an insulating film 114 covering the electric field mitigation layer 113 on the surface 11a of the semiconductor element 11. Next, for example, by electroplating, a first conductor portion 13 is formed on the first electrode pad 111 of the semiconductor substrate 10, and a second conductor portion 14 is formed on the second electrode pad 112. Furthermore, as... Figure 3A As shown, the back surface 11b of the semiconductor element 11 in the semiconductor substrate 10, where conductor portions 13 and 14 are formed, is temporarily fixed by attaching it to the support substrate 200. As the support substrate 200, any substrate (not shown) with an adhesive sheet (with high adhesion to Si) on its surface can be used, for example.

[0077] Next, a mold (not shown) is prepared, and the semiconductor substrate 10 held on the support substrate 200 is covered with a resin material such as epoxy resin by compression molding, etc., and then hardened by heating, etc., so as... Figure 3B The seal 12 is formed as shown. This forms a seal 12 that, together with the conductor portions 13 and 14, covers the surface 11a and sides of the semiconductor element 11. Then, the semiconductor substrate 10 covered by the seal 12 is peeled from the support substrate 200, for example, by heat treatment.

[0078] Next, as Figure 3C As shown, the surface covering the surface 11a of the semiconductor element 11 in the seal 12 is removed, exposing the first conductor portion 13 and the second conductor portion 14 from the seal 12. Thus, the seal 12 forms a flat surface 12a covering the insulating film 114 on the element and a portion of the surface 11a, resulting in a shape without any step difference caused by the insulating film 114 on the element. Furthermore, the removal of the seal 12 can be performed, for example, by grinding with a grinding tool such as a grinding machine (not shown), or by any other method such as cutting, etching, or polishing; there is no particular limitation.

[0079] Furthermore, for example, a solution containing resin materials such as polyimide is coated and dried using methods such as spin coating. Figure 3D As shown, a first layer 1511 is formed that constitutes part of the insulating layer 151. The first layer 1511 is patterned, for example by photolithography, to form a predetermined pattern shape that exposes at least a portion of the first conductor portion 13 and the second conductor portion 14 in the semiconductor substrate 10 and covers one side 12a of the seal 12.

[0080] Furthermore, the first layer 1511 formed on the flat side 12a, even the portion above the insulating film 114 on the element, has a shape without an interface step difference across the side of the semiconductor element 11 and the seal 12, and will not adversely affect the extended wiring 152 formed thereafter.

[0081] Then, for example, Figure 3E As shown, a seed layer 16 covering the first layer 1511 and the exposed portion of the semiconductor substrate 10 is formed, for example, by vacuum deposition such as sputtering. The seed layer 16 is made of a conductive material such as Cu. Then, for example, as... Figure 3F As shown, an insulating resist layer 16r, with a predetermined pattern shape that partially covers a portion of the substrate, is formed through the same process as the first layer 1511. Then, as... Figure 3GAs shown, for example, by electroplating, a cover portion 161 covering at least a portion of the first conductor portion 13 and an extended wiring 152 covering a portion of the first layer 1511 and at least a portion connected to the second conductor portion 14 are formed. The cover portion 161 and the extended wiring 152 are made of a conductive metal material such as Cu, for example, in the case of electroplating.

[0082] Next, for example, the resist layer 16r is removed using a stripping solution or the like, exposing the seed layer 16 from the resist layer 16r. Then, for example, an etching solution or the like is used to remove the portion of the seed layer 16 that was covered by the resist layer 16r. Thus, as... Figure 3H As shown, a covering portion 161 is formed that covers the first conductor portion 13, and an extension wiring 152 is formed that covers the second conductor portion 14 and extends from the inside to the outside of the outer contour of the semiconductor element 11.

[0083] Next, for example, Figure 3I As shown, the remaining portion of the insulating layer 151, namely the second layer 1512, is formed by spin coating using an insulating resin material similar to the first layer 1511.

[0084] Furthermore, the layout of the second layer 1512 is performed using photolithography, such as... Figure 3J As shown, unwanted portions of the second layer 1512 are removed, and a predetermined pattern shape is formed. Specifically, a portion of the second layer 1512 is removed, covering a predetermined area of ​​the cover portion 161 above the first conductor portion 13 and a portion of the extended wiring 152 near the front end opposite to the second conductor portion 14, exposing the cover portion 161 and a portion of the extended wiring 152 to the outside. This forms the insulating layer 151 constituting the rewiring layer 15.

[0085] Finally, for example, by electroless plating or the like, a metal film 153, 154 is formed to cover the cover portion 161 and the portion of the wiring 152 exposed from the second layer 1512.

[0086] For example, the semiconductor device 1 of this embodiment can be manufactured through the above-described process.

[0087] [Example of a variation of the manufacturing method]

[0088] The manufacturing method described above is merely one example and is not limited thereto. For instance, the covering portion 161 and the extended wiring 152 can also be formed by screen printing instead of electroplating.

[0089] For example, it can also be like Figure 4A As shown, in Figure 3DFollowing the steps shown, a printed layer 171 is formed by screen printing using a screen mask (not shown) and a conductive paste material, and then fired to form the cover portion 161 and the extended wiring 152. For example, sintered Ag, Cu paste, or Ag paste material can be used as the conductive paste material.

[0090] Alternatively, the cover 161 and the extended wiring 152 can be made of different materials. This is possible, for example, as... Figure 4B As shown, after the first printed layer 171 covering the first conductor portion 13 is formed by screen printing, the second printed layer 172 covering the second conductor portion 14 and extending to the outer side of the outer contour of the semiconductor element 11 is formed. Then, by performing a firing process, a cover portion 161 made of different conductive materials and an extended wiring 152 can be formed.

[0091] For example, the cover portion 161, which is connected to the first electrode pad 111 serving as the emitter electrode, can be constructed using a sintered Cu paste material. On the other hand, the extended wiring 152, which is connected to the second electrode pad 112 serving as the gate electrode and other signal terminals and has an increased wiring length, can be constructed using a conductive paste material with lower stress than the cover portion 161. When the cover portion 161 and the extended wiring 152 are formed by screen printing, the number of steps is reduced compared to rewiring formation technology, and compared to electroplating, the cover portion 161 and the extended wiring 152 can be made into thicker films (not limited, for example, 20 μm or more). Furthermore, in the case of screen printing, it is also possible to easily form multiple wirings with different characteristics depending on the formation location, wiring length, etc.

[0092] The semiconductor device 1 of this embodiment can be manufactured by forming the cover portion 161 and extending the wiring 152 through the above-described modification.

[0093] 〔Effect〕

[0094] Here, in the semiconductor device 1 of this embodiment, the reason for suppressing the short circuit between the extended wiring 152 and the semiconductor element 11 is explained by referring to a semiconductor device 300 (hereinafter referred to as "semiconductor device 300") whose surface is not covered by the seal 302. Figure 5 , Figure 6 Please provide an explanation.

[0095] First, let me briefly explain the structure of the semiconductor device 300.

[0096] Semiconductor device 300, for example Figure 5As shown, the semiconductor device 300 includes a semiconductor element 301 having a first electrode 303, a second electrode 304, an electric field mitigation layer 305, and an insulating film 306 covering the semiconductor element 301 on its surface 301a, and a sealant 302 covering its sides. Furthermore, the semiconductor device 300 includes an insulating layer 309 covering a portion of the surface 301a of the semiconductor element 301 and one side 302a of the sealant 302, a cover portion 311 covering the first electrode 303, an extending wiring 310 extending from the second electrode 304, and a metal thin film 312 partially covering the second electrode 304. The semiconductor device 300 is configured as an open-circuit device (FOP) and can transmit electrical signals to the second electrode 304 via the metal thin film 312 exposed to the outside of the outer contour of the semiconductor element 301.

[0097] In the semiconductor device 300, the portion of the insulating layer 309 on the side of the extended wiring 310 closest to the semiconductor element 301 or the seal 302 is designated as a first layer 307, and the remaining portion is designated as a second layer 308. This first layer 307 has a structure that may create a step difference at the interface between the semiconductor element 301 and the seal 302. When such a step difference occurs, the portion of the first layer 307 covering this step difference becomes thinner than other portions. In this case, the thinning at the interface step difference between the semiconductor element 301 and the seal 302, compared to the seal 302 and the insulating film 306 on the element, may cause a short circuit between the extended wiring 310 and the semiconductor element 301.

[0098] Specifically, for example Figure 6 As shown, the portion of the first layer 307 covered by the step difference between the side surface 301c of the semiconductor element 301 and the seal 302 is locally thinner compared to other portions. Due to factors such as thermal stress, cracks may form at the interface between the side surface 301c of the semiconductor element 301 and the seal 12 in the locally thinned portion of the first layer 307.

[0099] For ease of explanation, the cracks in the insulating layer that form the substrate for extending wiring are sometimes referred to as “step cuts” due to the step difference between the side of the semiconductor element and the seal covering it.

[0100] If generated in layer 1, 307 Figure 6 Cracks like those shown, i.e. stepped cuts, cannot ensure the insulation of the stepped cut portion, and may cause a short circuit between the extended wiring 310 and the semiconductor element 301, thus reducing reliability.

[0101] Furthermore, after the semiconductor device 300 is temporarily fixed by attaching the surface 301a to a support substrate (not shown) and forming a seal 302 covering the back surface 301b and the sides, the back surface 301b is exposed by removing the seal 302. Subsequently, the semiconductor device 300 can be obtained by forming a rewiring layer on the surface 301a using a known rewiring formation technique, which includes an insulating layer 309 and extended wiring 310. In this case, if the seal 302 is made of an insulating resin material containing particles such as heat dissipation filler, if these particles enter between the surface 301a and the support substrate (not shown), the surface 301a may contain particles during the formation of the rewiring layer. This results in a step difference caused by particles such as heat dissipation filler at the side interface between the side surface 301c of the semiconductor element 301 and the seal 302, potentially causing a stepped cut in the first layer 307 due to the step difference of the heat dissipation filler.

[0102] In contrast, the semiconductor device 1 of this embodiment is constructed such that the seal 12 covers the insulating film 114 on the element and has a flat side 12a located at a position higher than the surface 11a of the semiconductor element 11. An insulating layer 151 and extended wiring 152 are formed on this side 12a. Therefore, the first layer 1511, which serves as the substrate for the extended wiring 152, does not produce locally thinner areas due to the step difference at the side interface between the side surface 11c of the semiconductor element 11 and the seal 12. Step cutting is suppressed, thereby ensuring insulation.

[0103] Furthermore, regarding the semiconductor device 1, the back side 11b of the semiconductor element 11, on which the conductor portions 13 and 14 are formed, is temporarily fixed to the side support substrate 200. After the sealing member 12 covering the surface 11a and the side is formed, one side 12a of the sealing member 12 is formed by grinding the sealing member 12. Therefore, even when using an insulating resin material containing particles such as heat dissipation filler as the sealing member 12, no step difference caused by particles is generated in one side 12a, nor is a stepped cut caused by particles in the sealing member 12 generated.

[0104] Thus, the semiconductor device 1 ensures the insulation of the insulating layer 151 that forms part of the substrate of the extended wiring 152, suppresses short circuits between the extended wiring 152 and the semiconductor element 11, thereby creating a structure with improved reliability.

[0105] [Example of a semiconductor module]

[0106] Next, refer to Figure 7 This section describes an example of a semiconductor module using the semiconductor device 1 of this embodiment. Figure 7In the second heat sink 3 described later, the wiring portion that connects to the outside in other cross sections is indicated by dashed lines.

[0107] Semiconductor device 1 in, for example, Figure 7 When applied to a semiconductor module with a two-sided heat dissipation structure as shown, it is preferable to achieve both a thinner semiconductor module and high heat dissipation. Furthermore, this specification describes the application of semiconductor device 1 to a semiconductor module with a two-sided heat dissipation structure as a representative example, but is not limited to this application example.

[0108] like Figure 7 As shown, a semiconductor module is constituted by a semiconductor device 1, a first heat sink 2, a second heat sink 3, a lead frame 4, a connector 5, and a seal 6. The semiconductor module is a two-sided heat dissipation structure in which the semiconductor device 1 is sandwiched between two heat sinks 2 and 3 and is arranged opposite each other, and the heat generated by the semiconductor device 1 is released to the outside from both sides through these heat sinks 2 and 3.

[0109] Semiconductor device 1, for example, Figure 7 As shown, the back side 1b is connected to the first heat sink 2 via a bonding member 5, and the metal film 153 covering the first conductor portion 13 on the surface 1a side is connected to the second heat sink 3 via the bonding member 5. The semiconductor device 1 is configured such that the entire area of ​​the back side 1b is contained within the outer contour of the upper surface 2a of the first heat sink 2. In the second heat sink 3, one side 3a is exposed to the outside, and the other side 3b is facing the semiconductor device 1. In the semiconductor device 1, for example, the portion of the extended wiring 152 covered by at least the metal film 154 is positioned outside the outer contour of the other side 3b of the second heat sink 3. The extended wiring 152 of the semiconductor device 1 is electrically connected to the lead frame 4 via the bonding member 5 in the region outside the outer contour of the second heat sink 3.

[0110] First heat sink 2 Figure 7 As shown, the device is plate-shaped, having an upper surface 2a and a lower surface 2b in a surface-to-back relationship, and is made of a metallic material such as Cu or Fe. The first heat sink 2 mounts the semiconductor device 1 on its upper surface via a solder joint 5, and its lower surface 2b is exposed from the seal 6. The first heat sink 2 serves as a current path for the semiconductor device 1 during power-on, and a portion of its upper surface 2a extends to the outside of the seal 6. In this embodiment, the first heat sink 2 serves as both a heat dissipation component and a wiring component. Alternatively, the first heat sink 2 can also be referred to as a "first heat dissipation component".

[0111] 2nd heat sink 3rd Figure 7As shown, the second heat sink 3 is plate-shaped, having one side 3a and another side 3b in a surface-to-back relationship, and is made of the same material as the first heat sink 2. In the second heat sink 3, the other side 3b is positioned opposite a portion of the upper surface 2a of the semiconductor device 1, while one side 3a protrudes from the seal 6. The second heat sink 3 is electrically connected to the first conductor portion 13 via the connector 5, and like the first heat sink 2, serves as a current path for the semiconductor element 11. Furthermore, the second heat sink 3, in relation to... Figure 7 In different cross-sections, a portion of the other side 3b extends to the outside of the seal 6, serving as both a heat dissipation component and an electrical wiring component. Additionally, the second heat sink 3 can also be referred to as the "second heat dissipation component".

[0112] The lead frame 4 is made of metal materials such as Cu and Fe, for example. Figure 7 As shown, in the semiconductor device 1, in an exposed area outside the outer contour of the second heat sink 3, a portion of the extended wiring 152 is electrically connected via a bonding member 5 to a metal thin film 154 covering the extended wiring 152. The lead frame 4, for example, has a plurality of leads equal in number to the second electrode pads 112, each of which is electrically connected to the extended wiring 152.

[0113] Furthermore, these leads are connected to adjacent leads via tie rods (not shown) before the seal 6 is formed, and are separated after the seal 6 is formed by removing the tie rods through punching or the like. Alternatively, the lead frame 4 may be constructed as the same component as the first heat sink 2 or the second heat sink 3, connected by tie rods (not shown) until the seal 6 is formed. In this case, the lead frame 4 is also separated from the first heat sink 2 or the second heat sink 3 by removing the tie rods through punching or the like after the seal 6 is formed.

[0114] The bonding component 5 is a bonding component that joins the components of the semiconductor module together. It is made of a conductive material, such as solder, for electrical connection. In addition, the bonding component 5 is not limited to solder, and is made of a material that is at least different from the wire.

[0115] The seal 6 is made of, for example, a thermosetting resin such as epoxy resin, such as... Figure 7 As shown, the semiconductor device 1, a portion of the heat sinks 2 and 3, a portion of the lead frame 4, and the connector 5 are covered. When the seal 12, which constitutes a part of the semiconductor device 1, is designated as the "first seal", the seal 6 can be referred to as the "second seal" that covers the semiconductor device 1.

[0116] This semiconductor module has a structure in which the extended wiring 152 of the semiconductor device 1 is joined to the lead frame 4 via a connector 5 in a region outside the outer contour of the second heat sink 3. Therefore, it is not necessary to connect the semiconductor device 1 and the lead frame 4 with wires as described in conventional semiconductor modules disclosed in Japanese Patent Application Publication No. 2001-156225. Furthermore, by eliminating the use of wires, it is also unnecessary to place a heat sink between the semiconductor device 1 and the second heat sink 3 to prevent contact between the wires and the second heat sink 3. Consequently, the thickness of the semiconductor module can be made thinner accordingly, eliminating the thermal resistance of the heat sink and thus reducing the thermal resistance from the semiconductor device 1 to the second heat sink 3.

[0117] In this way, the semiconductor module using semiconductor device 1 does not require heat sinks or wiring connections between components, resulting in a thinner and lower thermal resistance structure compared to the past. In addition, short circuits between the extended wiring 152 of semiconductor device 1 and semiconductor element 11 are suppressed, thereby improving the reliability of the semiconductor module.

[0118] Furthermore, in the above example, both the first and second heat dissipation components are made of heat sinks, but are not limited to this. For example, the first and second heat dissipation components can also be as follows: Figure 8 As shown, it is composed of a heat transfer insulating substrate 7 and heat sinks 2 and 3, and the heat transfer insulating substrate 7 is bonded to the semiconductor device 1.

[0119] The structure of the heat transfer insulating substrate 7 includes a conductive portion 71, an insulating portion 72, and a heat conduction portion 73, which are stacked sequentially. The conductive portion 71 and the heat conduction portion 73 are separated by the insulating portion 72, thus being electrically independent. Regarding the heat transfer insulating substrate 7, for example, the conductive portion 71 is mainly made of a metallic material such as Cu, the insulating portion 72 is mainly made of an insulating material such as Al2O3 (alumina) or AlN (aluminum nitride), and the heat conduction portion 73 is mainly made of a metallic material such as Cu. The heat conduction portion 73 of the heat transfer insulating substrate 7 is bonded to the first heat sink 2 or the second heat sink 3 via a solder or other bonding member (not shown). For example, a DBC (Direct Bonded Copper) substrate is used as the heat transfer insulating substrate 7. Regarding the conductive portion 71 in the heat transfer insulating substrate 7, for example, a portion is used as wiring for connection to an external power source, or connected to other wiring such as the lead frame 4, enabling electrical exchange with the semiconductor element 11.

[0120] In this case, the semiconductor module is constructed as follows: the heat-conducting insulating substrate 7 insulates the semiconductor device 1 from the heat sinks 2 and 3. When the heat sinks 2 and 3 are connected to external coolers, etc., no additional insulating layer is required between the cooler and the semiconductor module. Therefore, Figure 8The semiconductor module shown also improves reliability when connected to external coolers, etc. Furthermore, the first and second heat dissipation components can be constructed with a portion of the heat-conducting insulating substrate 7 connected to the semiconductor device 1, as described above, or they can be entirely constructed with the heat-conducting insulating substrate 7.

[0121] According to this embodiment, the semiconductor device 1 is configured such that a redistribution layer 15, including extended wiring 152, is formed on a flat surface 12a of a seal 12 covering an insulating film 114 on the semiconductor element 11. After forming a first layer 1511, which is part of an insulating layer 151, on the flat surface 12a, the extended wiring 152 is formed on the first layer 1511 without step difference at the boundary between the side surface 11c of the semiconductor element 11 and the seal 12, thereby obtaining the redistribution layer 15. Therefore, the first layer 1511 does not experience step cutting due to the step difference at the boundary between the side surface 11c of the semiconductor element 11 and the seal 12, thus ensuring insulation. As a result, the insulation of the redistribution layer 15 is ensured, short circuits between the semiconductor element 11 and the extended wiring 152 are suppressed, resulting in a semiconductor device 1 with an improved FOP structure and enhanced reliability.

[0122] Furthermore, the semiconductor device 1 is an FOP (Fold-on-Plug) structure that connects heat dissipation components such as heat sinks to the first electrode pad 111, and allows the exposed portion of the extended wiring 152 electrically connected to the second electrode pad 112 to be joined to other components such as lead frames on the outer side of the outer contour of the heat dissipation component. Therefore, by using the semiconductor device 1 in the semiconductor module, heat sinks and wire connections between components are no longer required, and the semiconductor device 1 can be said to be a structure suitable for the thinning and high heat dissipation of semiconductor modules.

[0123] (Second Implementation)

[0124] Reference Figure 9 The semiconductor device 1 of the second embodiment will be described.

[0125] The semiconductor device 1 in this embodiment, such as Figure 9 As shown, the surface of the seal 12 located on the surface 11a of the semiconductor element 11 and connected to the surface 12a is referred to as the "inner wall surface 12c". The inner wall surface 12c is a curved surface shape in cross-section. In this respect, the first conductor portion differs from the first embodiment described above. In this embodiment, this difference will be mainly explained.

[0126] The inner wall surface 12c of the seal 12 is, for example, Figure 9As shown in the cross-section, the boundary between surface 12a and inner wall surface 12c is a curved surface shape without forming an angle. In other words, the seal 12 has an opening that exposes the surface 11a side of the semiconductor element 11, and the inner wall surface 12c constituting the opening is made into a curved cross-sectional shape. This is to use the portion of the insulating layer 151 that covers the step difference between surface 12a of the seal 12 and the surface 11a of the semiconductor element 11 as a "step difference coverage portion," suppressing the generation of cracks in the step difference coverage portion and ensuring insulation. Details will be described later through the manufacturing method of the semiconductor device 1 of this embodiment.

[0127] (Manufacturing method)

[0128] Next, refer to Figures 10A to 10K An example of the manufacturing method of the semiconductor device 1 according to this embodiment will be described. Here, the differences from the manufacturing process of the semiconductor device 1 of the first embodiment described above will be mainly explained.

[0129] First, a semiconductor substrate 10 is prepared, on the surface 11a of the semiconductor element 11, having a first electrode pad 111, a second electrode pad 112, an electric field mitigation layer 113, and an insulating film 114 covering the electric field mitigation layer 113. Then, a temporary protective member 210 is formed covering the first electrode pad 111 and the second electrode pad 112 of the semiconductor element 11. As the temporary protective member 210, for example, an adhesive material, a photosensitive resin material, etc., can be used. Figure 10A As shown, the back side 11b of the semiconductor element 11 in the semiconductor substrate 10, which forms the temporary protective element 210, is temporarily fixed by attaching it to the support substrate 200.

[0130] Next, using the same method as in the first embodiment described above, such as... Figure 10B As shown, a seal 12 is formed to cover the semiconductor substrate 10 together with a temporary protective member 210. Then, the semiconductor substrate 10 covered by the seal 12 is peeled off from the support substrate 200, for example by heat treatment.

[0131] Next, using the same method as in the first embodiment described above, such as... Figure 10C As shown, the surface of the seal 12 covering the surface 11a of the semiconductor element 11 is ground using a grinding tool such as a grinding machine (not shown), exposing the temporary protective member 210 from the seal 12. Thus, the seal 12 forms a flat surface 12a covering the insulating film 114 on the element and a portion of the surface 11a. Grinding is cited as an example of removing the seal 12 to expose the temporary protective member 210, but it is not limited to this method; other arbitrary methods such as cutting, etching, and polishing can also be used.

[0132] Subsequently, for example, by any method such as peeling with a cutting strip or etching, a predetermined area in the semiconductor substrate 10, including the first electrode pad 111 and the second electrode pad 112, is exposed to the outside. During this stage, the inner wall surface 12c of the seal 12 is as follows... Figure 10D As shown, in cross-section, the boundary between surface 12a and inner wall surface 12c has a corner shape.

[0133] Furthermore, isotropic etching, such as oxygen ashing, is performed to remove the surface portion of the seal 12, including the inner wall surface 12c, from the resin material. Thus, the seal 12, for example... Figure 10E As shown, the inner wall surface 12c becomes a curved shape that is bent in cross-section, and becomes a shape without corners in the boundary portion between the surface 12a and the inner wall surface 12c.

[0134] Next, for example, similar to the first embodiment described above, a solution containing a resin material such as polyimide is coated by spin coating, and a pattern is formed by photolithography, such as... Figure 10F As shown, a first layer 1511 is formed. In this embodiment, the first layer 1511 is formed into a predetermined pattern shape that exposes the first conductor portion 13 and the second conductor portion 14 in the semiconductor substrate 10 and covers one side 12a and the inner wall surface 12c of the seal 12.

[0135] Furthermore, by making the inner wall surface 12c into a curved shape that bends in cross-section, the portion of the first layer 1511 covering the inner wall surface 12c and the surface 12a is prevented from becoming locally thinner due to the boundary between the inner wall surface 12c and the surface 12a. Specifically, the area from the surface 12a of the seal 12 toward the inner wall surface 12c is made into a gentle slope, so that the shape of the portion of the first layer 1511 covering this area is more stable compared to the case where this area has, for example, a right-angled isoangular portion.

[0136] For example, in such Figure 11 As shown, when the cross-sectional shape of the inner wall surface 12c is a corner that is approximately right-angled with the boundary portion between it and the surface 12a, the first layer 1511 covers this corner at the step portion of the seal 12. In this case, the height of the step portion between the surface 12a of the seal 12 and the exposed portion of the semiconductor element 11 changes drastically, and the first layer 1511 covering it may produce locally thinned areas. Specifically, in the redistribution layer 15, the portion covered by the step formed by the seal 12, particularly the portion covering the approximately right-angled corner in the cross-section of the seal 12, such as... Figure 12As shown, step cuts may occur in the first layer 1511 and the extended wiring 152 formed thereon. If a step cut occurs in the first layer 1511, a short circuit may occur between the extended wiring 152 and the semiconductor element 11, causing a power failure. This step cut in the extended wiring 152 may also occur if the first layer 1511 fails to follow the corner of the seal 12 or does not completely cover the corner.

[0137] In addition, in this embodiment, the situation in which cracks are generated in the first layer 1511 and other components disposed thereon due to the step difference between the surface 12a and the portion of the semiconductor element 11 exposed from the seal 12 or the seal 12 is called "step cutting".

[0138] In contrast, such as Figure 10E As shown, when the inner wall surface 12c is made into a curved cross-sectional shape, the height difference between one side 12a and the exposed portion of the semiconductor element 11 becomes gradual, suppressing the possibility of locally thinner areas in the first layer 1511 covering it. Therefore, the first layer 1511 becomes a shape that suppresses stepped cutting and ensures insulation. Furthermore, the extended wiring 152 formed thereon suppresses the generation of cracks caused by stepped cutting in the first layer 1511.

[0139] Next, for example, Figure 10G As shown, a seed layer 16 covering the first layer 1511 and electrode pads 111 and 112 is formed using the same method as in the first embodiment described above. Then, for example, as... Figure 10H As shown, an insulating resist layer 16r with a predetermined pattern shape, covering a portion of the seed layer 16, is formed through the same process as the first layer 1511. Then, for example, as... Figure 10I As shown, by electroplating, a cover portion 161 covering the first electrode pad 111 and an extended wiring 152 covering a portion of the first layer 1511 and the second electrode pad 112 are formed.

[0140] Furthermore, for example, after removing the resist layer 16r with a stripping solution or the like, the portion of the seed layer 16 exposed by the removal of the resist layer 16r is removed with an etching solution or the like. Thus, as... Figure 10J As shown, a cover portion 161 that covers the first electrode pad 111 and an extension wiring 152 that covers the second electrode pad 112 and extends outward beyond the outer contour of the semiconductor element 11 are formed.

[0141] Then, for example, after forming the second layer 1512 using the same process as forming the first layer 1511, the pattern is created using photolithography, such as... Figure 10K As shown, a portion of the cover 161 and the extended wiring 152 are exposed to the outside.

[0142] Finally, for example, by the same process as forming the cover portion 161 and the extended wiring 152, metal films 153 and 154 are formed to cover the portions of the cover portion 161 and the extended wiring 152 that are exposed from the second layer 1512.

[0143] For example, the semiconductor device 1 of this embodiment can be manufactured through the above-described process.

[0144] According to this embodiment, the inner wall surface 12c has a curved cross-sectional shape, which suppresses the stepped cut in the first layer 1511, the substrate of the extended wiring 152, thus creating a semiconductor device 1 with a structure that suppresses short circuits between the extended wiring 152 and the semiconductor element 11. Furthermore, similar to the first embodiment described above, the semiconductor device 1 is constructed such that the first layer 1511 and a portion of the extended wiring 152 are formed on a flat surface 12a of the sealant 12, which covers a portion of the side surface 11c and surface 11a of the semiconductor element 11. Therefore, in this embodiment, compared to the case where the redistribution layer 15 is directly formed on the boundary step between the side surface 11c of the semiconductor element 11 and the sealant 12, short circuits between the extended wiring 152 and the semiconductor element 11 are also suppressed, improving reliability.

[0145] (A variation of the second embodiment)

[0146] The above description illustrates an example where the cross-sectional shape of the inner wall surface 12c is curved, but it is not limited to this. The inner wall surface 12c can simply be a shape where the step difference between one surface 12a and the exposed portion of the semiconductor element 11 changes gently; for example, it could also be as follows: Figure 13 As shown, the inner wall surface 12c forms a cone shape with an obtuse angle θ at the intersection of the surface 12a and the inner wall surface 12c. That is, when the inner wall surface 12c is shaped such that its upper end, which intersects with the surface 12a of the seal 12, is divided into a corner with an obtuse angle, stepped cutting of the insulating layer 151 can be suppressed. In this case, the first layer 1511 of the insulating layer 151 can also follow the corner of the seal 12, suppressing the situation where the corner of the seal 12 becomes locally thinner and the corner is exposed from the first layer 1511, and also suppressing stepped cutting of the extended wiring 152.

[0147] According to this modified example, it also becomes a semiconductor device that can achieve the same effect as the second embodiment described above.

[0148] (Third Implementation)

[0149] Reference Figures 14-16B The semiconductor device 1 of the third embodiment is described.

[0150] The semiconductor device 1 in this embodiment is, for example, such as Figure 14 As shown, the structure does not have a redistribution layer 15, and the first electrode pad 111 is connected to the first conductive portion 181 and the second electrode pad 112 is connected to the second conductive portion 182, which differs from the first embodiment described above. In this embodiment, this difference will be mainly explained.

[0151] In this embodiment, the seal 12 covers the surface 11a and side surface of the semiconductor element 11, and exposes the side 12a covered on the surface 11a to the outside. In other words, a portion of the seal 12 in this embodiment covers the first conductive portion 181 and the second conductive portion 182, serving as an insulating layer 151 equivalent to the redistribution layer 15.

[0152] First conductive section 181 Figure 14 As shown, the end face opposite to the first electrode pad 111 is exposed from the seal 12 in a region that is inside the outer contour of the semiconductor element 11. The first conductive portion 181 is a component corresponding to the first conductor portion 13 in the first embodiment described above.

[0153] Second conductive section 182 Figure 14 As shown, the end face opposite to the second electrode pad 112 is exposed from the seal 12 in a region outside the outer contour of the semiconductor element 11. The second conductive portion 182 is a component corresponding to the second conductor portion 14 and the extension wiring 152 in the first embodiment described above. During the manufacturing process of the semiconductor device 1 in this embodiment, the second conductive portion 182 is formed as a single component together with the first conductive portion 181, and is separated from the first conductive portion 181 during the removal process of the seal 12, thus becoming separate from the first conductive portion 181. Therefore, the second conductive portion 182, from the portion connected to the second electrode pad 112 to the portion exposed from the seal 12, is formed by a single component made of the same material as the first conductive portion 181.

[0154] Specifically, the first conductive part 181 and the second conductive part 182 are configured as follows: Figure 15A , Figure 15B The conductive components 19 shown are separate components, with the portions connecting them removed midway through the manufacturing process of the semiconductor device 1.

[0155] For example, Figure 15A or Figure 15BAs shown, the conductive member 19 comprises a thick-walled portion 191, a plurality of first thin-walled portions 192, a plurality of medium-thickness wall portions 193, and a plurality of second thin-walled portions 194. The conductive member 19, as... Figure 15B As shown, a plurality of first thin-walled portions 192 are provided extending outward from the upper end surface 19a of the thick-walled portion 191, such as... Figure 15A As shown, the plurality of first thin-walled portions 192 are arranged in parallel with their extension directions aligned and separated from each other. Among the conductive members 19, the thick-walled portion 191 has the largest thickness, and the medium-thickness wall portion 193 has a thickness that is slightly less than that of the thick-walled portion 191 and is also relatively large. Furthermore, the conductive member 19 includes first thin-walled portions 192 and second thin-walled portions 194, which are thinner than the medium-thickness wall portions 193, and extend from each of the medium-thickness wall portions 193 and the second thin-walled portions 194 toward the lower end face of the thick-walled portion 191.

[0156] For example, after preparing a metal plate such as Cu, and forming portions corresponding to the first thin-walled portion 192, the medium-thickness wall portion 193, and the second thin-walled portion 194 by locally thinning the wall through etching, the conductive component 19 can be manufactured by methods such as stamping and bending. In this case, for example, by stamping, gaps are formed between the extended portions formed by the first thin-walled portion 192, the medium-thickness wall portion 193, and the second thin-walled portion 194, creating a state where they are separated into multiple extended portions. Then, by bending, the multiple second thin-walled portions 194 are bent toward the lower end side of the thick-walled portion 191, thereby obtaining... Figure 15A or Figure 15B The conductive component 19 is shown.

[0157] Furthermore, the bending direction of the plurality of second thin-walled portions 194 is appropriately determined according to the arrangement of the second electrode pads 112 of the semiconductor element 11. The front ends of the plurality of second thin-walled portions 194 opposite to the medium-thickness wall portions 193 are, for example, as shown in... Figure 15A As shown, they are set to face different directions.

[0158] [Manufacturing Method]

[0159] Next, refer to Figure 16A , Figure 16B Here is an example of a method for manufacturing the semiconductor device 1 according to this embodiment. Here, we will mainly describe manufacturing processes that differ from those described in the first embodiment.

[0160] First, a semiconductor substrate 10 and a conductive component 19 are prepared, having a first electrode pad 111, a second electrode pad 112, an electric field mitigation layer 113, and an insulating film 114 covering the electric field mitigation layer 113 on the surface 11a of the semiconductor element 11. Then, a thick-walled portion 191 is connected to the first electrode pad 111 of the semiconductor element 11, and a second thin-walled portion 194 is connected to the second electrode pad 112, respectively, using solder or other bonding members (not shown). Then, as... Figure 16A As shown, the back side 11b of the semiconductor element 11 in the semiconductor substrate 10, which is connected to the conductive component 19, is temporarily fixed to the support substrate 200 by pasting it.

[0161] Next, similar to the first embodiment described above, a mold (not shown) is used, and compression molding or the like is employed. Figure 16B As shown, a seal 12 is formed that covers the semiconductor substrate 10 together with the conductive component 19.

[0162] Next, the sealing member 12 is ground from the side covering the conductive member 19 using a grinding tool such as a grinding machine (not shown), so that the conductive member 19 is exposed from the sealing member 12. In this grinding process of the sealing member 12, the first thin-walled portion 192 is completely removed, leaving a portion of the medium-thickness wall portion 193. Thus, the thick-walled portion 191, the medium-thickness wall portion 193, and the second thin-walled portion 194 are separated, forming the first conductive portion 181 and the second conductive portion 182. Furthermore, while grinding using a grinding tool such as a grinding machine (not shown) is used as an example of removing a portion of the sealing member 12 and the conductive member 19, it is not limited to this method; for example, it can be performed by any other method such as cutting, etching, or grinding.

[0163] For example, the semiconductor device 1 of this embodiment can be manufactured using the manufacturing method described above.

[0164] According to this embodiment, the conductive member 19, which has a second conductive portion 182 that functions as an extension of the wiring 152, is formed before the sealing member 12. Therefore, this manufacturing method ensures that the second conductive portion 182 is not affected by the boundary between the side 11c of the semiconductor element 11 and the sealing member 12, thus suppressing insulation failures and preventing short circuits between the second conductive portion 182 and the semiconductor element 11. Furthermore, the formation of a rewiring layer 15 is unnecessary, and compared to the first embodiment described above, the number of manufacturing steps is reduced, resulting in a structure that lowers manufacturing costs.

[0165] (Other implementation methods)

[0166] This disclosure is based on embodiments, but it should be understood that this disclosure is not limited to these embodiments and constructions. This disclosure also includes various modifications and variations within the same range. In addition, various combinations and forms, including only one element thereof, and other combinations and forms above or below thereof also fall within the scope and spirit of this disclosure.

[0167] For example, in the first embodiment described above, as an example of a semiconductor module, a configuration is illustrated where the second external electrode in the semiconductor device 1 is disposed in an exposed area outside the outer contour of the second heat sink 3, and the lead frame 4 is connected to the second external electrode in the exposed area, but this is not limited to this. When the second heat dissipation component has a structure with a heat-conducting insulating substrate 7, for example, as shown... Figure 17 As shown, a semiconductor module can also be formed where the second external electrode of the semiconductor device 1 and the lead frame 4 are connected via a heat-conducting insulating substrate 7. In this case, the conductive portion 71 in the heat-conducting insulating substrate 7 is made into an arbitrary pattern shape that is electrically independent of the portion connected to the first external electrode of the semiconductor device 1 and the portion connected to the second external electrode. Furthermore, a portion of the lead frame 4 is disposed inside the outer contour of the second heat dissipation member and is connected to the portion of the conductive portion 71 connected to the second external electrode via a connector 5, thereby being electrically connected to the second external electrode. In this way, the structure of the semiconductor module using the semiconductor device 1 can be appropriately modified according to the heat dissipation member. This is the same not only for the case of using the semiconductor device 1 of the first embodiment described above, but also for the case of using the semiconductor device 1 of the other embodiments described above.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor device having a first electrode pad and a plurality of second electrode pads on its surface generates current in the direction connecting the aforementioned surface and back surface. A seal, made of an insulating resin material, covers a portion of the aforementioned surface and sidewalls of the semiconductor element; as well as The wiring is extended and disposed on the semiconductor element, inside the seal or on the seal, electrically connected to the second electrode pad, and extends from the inside to the outside of the outer contour of the semiconductor element. The surface of the aforementioned seal that covers one side of the aforementioned semiconductor element is designated as one side, and this side is covered by an insulating layer made of a resin material with a different insulating property than the aforementioned seal. The aforementioned semiconductor device has an electric field mitigation layer on its surface that is closer to the outer contour of the semiconductor device than the second electrode pad, and an insulating film on the device that covers the electric field mitigation layer and a portion of the surface. The aforementioned seal covers the insulating film on the aforementioned component.

2. The semiconductor device as claimed in claim 1, characterized in that, It also has: The first conductor portion is connected to the first electrode pad and extends directly above the first electrode pad, protruding from the seal; and The second conductor portion is connected to the second electrode pad and extends towards the upper part of the second electrode pad, protruding from the seal. The aforementioned extended wiring is connected to the aforementioned second conductor portion.

3. The semiconductor device as claimed in claim 2, characterized in that, The first conductor portion is composed of a single component, with the side opposite to the side connected to the first electrode pad exposed to the outside. The second conductor portion described above is partly an extension wiring portion, which is made of a single component of the same material as the first conductor portion described above, and the side opposite to the side connected to the second electrode pad described above is exposed to the outside.

4. The semiconductor device as claimed in claim 1, characterized in that, The portion of the electrode electrically connected to the first electrode pad and exposed to the outside on the opposite side of the first electrode pad is designated as the first external electrode, and the portion electrically connected to the second electrode pad and exposed to the outside on the opposite side of the second electrode pad is designated as the second external electrode. The first external electrode and the second external electrode are arranged at a distance from each other, and the planar dimension of the first external electrode is larger than that of the second external electrode.

5. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned extended wiring is made of a conductive material whose main component is one of Cu, Al, Ti, Au, Ag, Pd, W, Ni, Zn, or Pb.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The portion of the above-mentioned insulating layer that is closer to the side of the extended wiring than described above is designated as the first layer. The thickness of the first layer is greater than the thickness of the portion of the insulation layer that is above the extended wiring.

7. The semiconductor device as claimed in claim 2, characterized in that, The second conductor portion described above is partly an extension wiring provided above, and is made of a different conductive material than the first conductor portion described above.

8. The semiconductor device as claimed in claim 1, characterized in that, The surface of the seal that is located above the surface of the semiconductor element and connected to the aforementioned surface is designated as the inner wall surface. The cross-sectional shape of the upper portion of the inner wall surface that intersects with the aforementioned surface is a curved surface shape.

9. The semiconductor device as claimed in claim 1, characterized in that, The surface of the seal member located above the surface of the semiconductor element and connected to the aforementioned surface is designated as the inner wall surface, and the angle of the upper portion where the inner wall surface intersects with the aforementioned surface is designated as the intersection angle. The cross-sectional shape of the aforementioned inner wall surface is a shape with an obtuse angle at the aforementioned intersection angle.

10. A semiconductor device, characterized in that, have: A semiconductor device having a first electrode pad and a plurality of second electrode pads on its surface generates current in the direction connecting the aforementioned surface and back surface. A seal, made of an insulating resin material, covers a portion of the aforementioned surface and sidewalls of the semiconductor element; The wiring is extended and disposed on the semiconductor element, inside the seal or on the seal, electrically connected to the second electrode pad, and extends from the inside of the outer contour of the semiconductor element to the outside. The first conductor portion is connected to the first electrode pad and extends directly above the first electrode pad, protruding from the seal; and The second conductor portion is connected to the second electrode pad and extends towards the upper part of the second electrode pad, protruding from the seal. The aforementioned extended wiring is connected to the aforementioned second conductor portion. The second conductor portion described above, partly consisting of the extended wiring, is made of a different conductive material than the first conductor portion. The aforementioned semiconductor device has an electric field mitigation layer on its surface that is closer to the outer contour of the semiconductor device than the second electrode pad, and an insulating film on the device that covers the electric field mitigation layer and a portion of the surface. The aforementioned seal covers the insulating film on the aforementioned component.

11. A semiconductor device, characterized in that, have: A semiconductor device having a first electrode pad and a plurality of second electrode pads on its surface generates current in the direction connecting the aforementioned surface and back surface. A seal, made of an insulating resin material, covers a portion of the aforementioned surface and sidewalls of the semiconductor element; as well as The wiring is extended and disposed on the semiconductor element, inside the seal or on the seal, electrically connected to the second electrode pad, and extends from the inside to the outside of the outer contour of the semiconductor element. The surface of the sealing member that covers one side of the surface of the semiconductor element is designated as a surface, and the surface located above the surface of the semiconductor element and connected to the surface is designated as an inner wall surface. The cross-sectional shape of the upper portion of the inner wall surface that intersects with the aforementioned surface is a curved surface shape. The aforementioned semiconductor device has an electric field mitigation layer on its surface that is closer to the outer contour of the semiconductor device than the second electrode pad, and an insulating film on the device that covers the electric field mitigation layer and a portion of the surface. The aforementioned seal covers the insulating film on the aforementioned component.

12. A semiconductor device, characterized in that, have: A semiconductor device having a first electrode pad and a plurality of second electrode pads on its surface generates current in the direction connecting the aforementioned surface and back surface. A seal, made of an insulating resin material, covers a portion of the aforementioned surface and sidewalls of the semiconductor element; as well as The wiring is extended and disposed on the semiconductor element, inside the seal or on the seal, electrically connected to the second electrode pad, and extends from the inside to the outside of the outer contour of the semiconductor element. The surface of the sealing member that covers one side of the surface of the semiconductor element is designated as a surface, the surface located above the surface of the semiconductor element and connected to the surface is designated as an inner wall surface, and the angle of the upper portion where the inner wall surface intersects with the surface is designated as the intersection angle. The cross-sectional shape of the aforementioned inner wall surface is a shape with an obtuse angle at the aforementioned intersection angle. The aforementioned semiconductor device has an electric field mitigation layer on its surface that is closer to the outer contour of the semiconductor device than the second electrode pad, and an insulating film on the device that covers the electric field mitigation layer and a portion of the surface. The aforementioned seal covers the insulating film on the aforementioned component.

13. A semiconductor module, characterized in that, have: A semiconductor device comprising: a semiconductor element having at least one first electrode pad and at least one second electrode pad on its surface, generating current in a direction connecting the surface and the back side; a first seal made of an insulating resin material covering the area around the semiconductor element, including a portion of the surface; and an extending wiring disposed on the semiconductor element, either inside or on the first seal, electrically connected to the second electrode pad, and extending from the inside to the outside of the outer contour of the semiconductor element. The first heat dissipation component is connected to the back side of the semiconductor device exposed from the first seal via a connector; The second heat dissipation component is electrically connected to the first electrode pad in the semiconductor device via the aforementioned bonding member. The lead frame is electrically connected to the extended wiring in the semiconductor device via the aforementioned connector; and The second seal covers the semiconductor device, a portion of the first heat dissipation component, a portion of the second heat dissipation component, and a portion of the lead frame. The aforementioned semiconductor device has an electric field mitigation layer on its surface that is closer to the outer contour of the semiconductor device than the second electrode pad, and an insulating film on the device that covers the electric field mitigation layer and a portion of the surface. The first seal covers the insulating film on the aforementioned component.

14. The semiconductor module as described in claim 13, characterized in that, A portion of the aforementioned semiconductor device is an exposed area located outside the outer contour of the aforementioned second heat dissipation component; The aforementioned lead frame is electrically connected to the aforementioned extended wiring via the aforementioned connector in the aforementioned exposed area.

15. The semiconductor module as described in claim 13, characterized in that, The upper surface of the first heat dissipation component, which is opposite to the surface facing the semiconductor device, is exposed from the second seal. The lower surface of the second heat dissipation component, which is opposite to the surface facing the semiconductor device, is exposed from the second seal.

16. The semiconductor module as described in any one of claims 13 to 15, characterized in that, The first heat dissipation component and part or all of the second heat dissipation component are heat-transfer insulating substrates in which conductive parts, insulating parts and heat-conducting parts are stacked in sequence, and the conductive parts are connected to the semiconductor device.

17. A method for manufacturing a semiconductor device with a fan-out package structure, characterized in that, Includes the following steps: A semiconductor device is prepared having at least one first electrode pad and at least one second electrode pad on its surface. The prepared semiconductor device has an electric field mitigation layer on the surface that is closer to the outer contour of the semiconductor device than the second electrode pad, and an insulating film on the device that covers the electric field mitigation layer and a portion of the surface. Prepare a conductive component, which includes a thick-walled portion, a first thin-walled portion extending outward from the upper end of the thick-walled portion and having a thickness smaller than that of the thick-walled portion, a medium-thickness wall portion disposed at the front end of the first thin-walled portion and having a thickness smaller than that of the thick-walled portion and larger than that of the first thin-walled portion, and a second thin-walled portion extending from the medium-thickness wall portion toward the lower end of the thick-walled portion and having a thickness smaller than that of the thick-walled portion. The back side of the aforementioned semiconductor element is attached to the support substrate; The lower end side of the thick-walled portion in the conductive component is connected to the first electrode pad of the semiconductor element, and the front end of the second thin-walled portion in the conductive component is connected to the second electrode pad of the semiconductor element. A seal is formed that includes the insulating film on the aforementioned element, together with the aforementioned conductive component, covering the aforementioned semiconductor element which is connected to the aforementioned conductive component and is adhered to the aforementioned support substrate; and Remove the seal from the side of the seal that covers the conductive component, so that the thick-walled portion and the medium-thickness wall portion of the conductive component are exposed from the seal. In the formation of the above-mentioned seal, an insulating resin material is used; In the removal of the aforementioned seal, the first thin-walled portion of the aforementioned conductive component is removed, thereby separating the aforementioned thick-walled portion from the aforementioned medium-thickness wall portion and the aforementioned second thin-walled portion.

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